JP2016082012A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing concentration of an electric field in the vicinity of a drain region.SOLUTION: A semiconductor device comprises: an Ntype drain region 19 formed on an N type well 13; a P type body region 15 formed on the N type well; an Ntype source region 18 formed in the body region 15; a field insulating film 14 located between the drain region 19 and the body region 15; a gate insulating film 16 located between the drain region 19 and the source region 18; a gate electrode 17 formed on the field insulating film 14 and the gate insulating film 16; and an N type embedded diffusion layer 21 formed on the N type well 13. Relations of a<b and a<c are satisfied.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

FIG. 5 is a cross-sectional view for explaining a conventional N-channel LDMOS (Lateral Diffused MOS).
The N-channel LDMOS has a P-type silicon substrate 101, and an N-type buried diffusion layer 102 is formed on the P-type silicon substrate 101.

An epitaxial layer is formed on the N-type buried diffusion layer 102, and an N-type well 103 is formed in the epitaxial layer. A field insulating film 104 as an offset insulating film is formed on the N-type well 103. A P-type body region diffusion layer 105 is formed in the N-type well 103, and a P ⁺ -type body contact region diffusion layer 105 a is formed in the P-type body region diffusion layer 105. A gate insulating film 106 is formed on the N-type well 103 and the P-type body region diffusion layer 105, and a gate electrode 107 is formed on the field insulating film 104 and the gate insulating film 106.

An N ⁺ -type drain region diffusion layer 109 is formed in the N-type well 103 in a self-aligned manner with respect to the field insulating film 104. An N ⁺ type source region diffusion layer 108 is formed in the P type body region diffusion layer 105 in a self-aligned manner with respect to the gate electrode 107. An LDMOS similar to the above-described LDMOS is disclosed in Patent Document 1.

  In an LDMOS with high breakdown voltage and high capability, the electric field tends to concentrate near the drain region diffusion layer 109. This will be described in detail below.

  The potential of the N-type buried diffusion layer 102 is a potential between the potential of the drain region diffusion layer 109 and the potential of the source region diffusion layer 108. The potential of the N-type buried diffusion layer 102 is divided by the parasitic resistance between the source region diffusion layer 108 and the N-type buried diffusion layer 102 and between the drain region diffusion layer 109 and the N-type buried diffusion layer 102. It becomes the electric potential. Therefore, the potential of the N-type buried diffusion layer 102 largely depends on the layout and may become unstable. Therefore, when the potential of the N-type buried diffusion layer 102 is close to the potential of the source region diffusion layer 108, the electric field tends to concentrate near the drain region diffusion layer 109. In general, the body region diffusion layer 105 is larger than the drain region diffusion layer 109, and the gate electrode 107 serves as a field plate. Therefore, it can be said that the source region diffusion layer 108 is less likely to concentrate an electric field.

  Further, in an LDMOS having the N-type buried diffusion layer 102, the potential of the buried diffusion layer 102 is often fixed to the potential of the drain region diffusion layer 109 in many cases. In this case, the drain current flows through the buried diffusion layer 102, the potential of the buried diffusion layer 102 becomes unstable, and the electric field concentration in the drain region diffusion layer 109 becomes significant.

In order to suppress the electric field concentration in the drain region diffusion layer 109, the following method can be considered.
A low-resistance N-type diffusion layer (plug) is provided in the epitaxial layer, and the N-type diffusion layer is positioned on the outer periphery of the N-type buried diffusion layer 102 like a guard ring. Then, a drain potential is applied to the buried diffusion layer 102 through the N-type diffusion layer to fix the potential of the buried diffusion layer 102 to the drain potential. Thereby, electric field concentration in the drain region diffusion layer 109 can be suppressed.

  However, in the above method, it is necessary to form a large-area N-type diffusion layer in order to reduce the resistance of the N-type diffusion layer provided like a guard ring. Specifically, in order to bring the N-type diffusion layer into contact with the diffusion layer 102 with a low resistance, it is necessary to diffuse the impurity ions up to the thickness of the epitaxial layer. As a result, the impurity ions spread in a high concentration in the lateral direction, so that a large-area N-type diffusion layer is formed and occupies the chip area. Therefore, there is a drawback that the area where elements cannot be arranged increases.

  In addition, in a large-area LDMOS, the following problem may occur even when the above-described method of fixing the potential of the buried diffusion layer 102 to the drain potential is used. In a large area LDMOS, the buried diffusion layer 102 also has a large area, so that the drain potential is not stabilized by the parasitic resistance of the buried diffusion layer 102. That is, in a large area LDMOS, the number of parallel transistors is large and the gate width of the transistors is large, so that the drain current increases. In the center of the buried diffusion layer, the parasitic resistance increases because the distance to the N-type diffusion layer provided like a guard ring increases. A part of the drain current flows in the buried diffusion layer. Therefore, the drain current drops due to the parasitic resistance of the buried diffusion layer, and the central potential of the buried diffusion layer becomes close to the potential of the source region diffusion layer. As a result, the electric field tends to concentrate near the drain region diffusion layer.

JP2010-16155

  Some embodiments of the present invention relate to a semiconductor device that suppresses concentration of an electric field in the vicinity of a drain region and a manufacturing method thereof.

  One embodiment of the present invention includes a first semiconductor layer of a first conductivity type, a drain region of a first conductivity type formed in the first semiconductor layer, and a second layer formed in the first semiconductor layer. A conductive type body region; a first conductive type source region formed in the body region; and a field insulating film formed on the first semiconductor layer and positioned between the drain region and the body region. A gate insulating film formed on the first semiconductor layer and the body region and positioned between the drain region and the source region; and a gate formed on the field insulating film and the gate insulating film. An electrode and a first impurity region of a first conductivity type formed in the first semiconductor layer, wherein the first impurity region at least partially overlaps the drain region in plan view, The field The second distance between the end of the field insulating film on the source region side and the first impurity region is larger than the first distance between the end of the film on the source region side and the drain region, A semiconductor device, wherein a third distance between the body region and the first impurity region is larger than a first distance between an end of the field insulating film on the source region side and the drain region. It is.

  According to one embodiment of the present invention, the voltage from the first impurity region to the drain region can be obtained by setting the positional relationship among the first impurity region, the drain region, the field insulating film, and the body region as described above. The descent is reduced. Thereby, the voltage of the first impurity region is stabilized, and the concentration of the electric field in the vicinity of the drain region can be suppressed.

  Note that the first semiconductor layer includes various semiconductor substrates and epitaxial layers, and also includes a well or an impurity diffusion layer formed in the semiconductor substrate or the epitaxial layer.

  Further, in one embodiment of the present invention, the first impurity region has a second impurity region in contact with the first impurity region, and the second impurity region includes the drain region and the source region in plan view. , Overlapping the body region and the gate electrode. As a result, the drain current from the source region via the first and second impurity regions can be increased by the first impurity region and the second impurity region.

  In the above embodiment of the present invention, the second impurity region is formed in a second semiconductor layer located below the first semiconductor layer. Note that the second semiconductor layer includes various semiconductor substrates and epitaxial layers, and also includes wells or impurity diffusion layers formed in the semiconductor substrate or epitaxial layers.

  In the embodiment of the present invention, the first impurity region is in contact with the drain region. Thereby, the electric field concentration in the drain region can be more effectively suppressed.

  According to one embodiment of the present invention, a second impurity region of a first conductivity type is formed in a semiconductor substrate, a first impurity region of the first conductivity type is formed in the second impurity region, and the first impurity Forming an epitaxial layer on the semiconductor substrate including the region and the second impurity region, forming a first conductivity type well in the epitaxial layer, and thermally diffusing the impurity of the first impurity region in the well; Forming a field insulating film on the well; forming a second conductivity type body region on the well; forming a gate insulating film on the well and the body region; and the field insulating film and the gate insulating film. A gate electrode is formed thereon, a drain region of the first conductivity type is formed in the well in a self-aligned manner with respect to the field insulating film, and a source region of the first conductivity type is formed in the body region. The field insulating film is positioned between the drain region and the body region, and at least a part of the first impurity region is planarly viewed from the drain region. And the end of the field insulating film on the source region side and the first impurity region are larger than the first distance between the end of the field insulating film on the source region side and the drain region. 2 is large, and the third distance between the body region and the first impurity region is larger than the first distance between the end of the field insulating film on the source region side and the drain region. A method for manufacturing a semiconductor device.

  According to one embodiment of the present invention, the voltage from the first impurity region to the drain region can be obtained by setting the positional relationship among the first impurity region, the drain region, the field insulating film, and the body region as described above. The descent is reduced. Thereby, the voltage of the first impurity region is stabilized, and the concentration of the electric field in the vicinity of the drain region can be suppressed.

  In the above embodiment of the present invention, the second impurity region overlaps the drain region, the source region, the body region, and the gate electrode in plan view. As a result, the drain current from the source region via the first and second impurity regions can be increased by the first impurity region and the second impurity region.

(A) is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention, (B) is a plan view of a region obtained by cutting the cross section of (A) with an arrow on the A plane, and (C) is a cross section of (A). The top view of the area | region cut | disconnected by the arrow of B plane. 2A to 2D are cross-sectional views illustrating a method for manufacturing the semiconductor device illustrated in FIG. 2A and 2B are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG. The figure which shows the simulation result of the electric potential distribution at the time of an on-break of N channel LDMOS shown to FIG. 3 (B) and FIG. Sectional drawing for demonstrating the conventional N channel LDMOS.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

[Embodiment 1]
FIG. 1A is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 1B is a plan view of a region obtained by cutting the cross section of FIG. 1A with an A-plane arrow, and FIG. 1C is a cross-sectional view of FIG. 1A cut with a B-plane arrow. FIG. This semiconductor device is an N-channel LDMOS.

  As shown in FIG. 1A, a first N-type buried diffusion layer (also referred to as a second impurity region) 12 is formed on the surface of a P-type silicon substrate (also referred to as a second semiconductor layer) 11. Yes. An epitaxial layer (also referred to as a first semiconductor layer) is formed on the first N-type buried diffusion layer 12, and an N-type well 13 is formed in the epitaxial layer. A field insulating film 14 as an offset insulating film is formed on the N-type well 13. The field insulating film 14 is formed by the LOCOS method.

A P-type body region diffusion layer 15 is formed in the N-type well 13, and an N ⁺ -type source region diffusion layer 18 is formed in the P-type body region diffusion layer 15. An N ⁺ type drain region diffusion layer 19 is formed in the N type well 13. A P ⁺ type body contact region 15 a for partially connecting to the P type body region diffusion layer 15 is formed in the N ⁺ type source region diffusion layer 18.

  A gate insulating film 16 is formed on the N-type well 13 and the P-type body region diffusion layer 15, and a gate electrode 17 is formed on the field insulating film 14 and the gate insulating film 16.

An N ⁺ type drain region diffusion layer 19 is formed in the N type well 13 in a self-aligned manner with respect to the field insulating film 14. An N ⁺ type source region diffusion layer 18 is formed in the P type body region diffusion layer 15 in a self-aligned manner with respect to the gate electrode 17. The gate insulating film 16 is located between the drain region diffusion layer 19 and the source region diffusion layer 18.

  A second N-type buried diffusion layer (also referred to as a first impurity region) 21 is formed in the N-type well 13, and the second N-type buried diffusion layer 21 is connected to the first N-type buried diffusion layer 12. It touches. The impurity concentration of the second N-type buried diffusion layer 21 is higher than the impurity concentration of the N-type well 13.

  The positional relationship among the second N-type buried diffusion layer 21, the drain region diffusion layer 19, the field insulating film 14, and the P-type body region diffusion layer 15 is as follows. The second N-type buried diffusion layer 21 is located below the drain region diffusion layer 19 and is disposed so as to at least partially overlap the drain region diffusion layer 19 in plan view. The distance between the end of the field insulating film 14 on the source region side and the second N-type buried diffusion layer 21 is larger than the first distance a between the end of the field insulating film 14 on the source region side and the drain region diffusion layer 19. The second distance b is large (a <b). A third distance between the P-type body region diffusion layer 15 and the second N-type buried diffusion layer 21 rather than a first distance a between the end of the field insulating film 14 on the source region side and the drain region diffusion layer 19. c is large (a <c) (see FIGS. 1A, 1B, and 1C).

  1B and 1C is different from the above relationship in the first distance a, the second distance b, and the third distance c. This is because C) is drawn in a plan view. Accordingly, the actual distance relationship is as shown in FIG.

  The first N type buried diffusion layer 12 is disposed so as to overlap the drain region diffusion layer 19, the source region diffusion layer 18, the P type body region diffusion layer 15, and the gate electrode 17 in plan view.

  According to the present embodiment, the positional relationship among the second N-type buried diffusion layer 21, the drain region diffusion layer 19, the field insulating film 14, and the P-type body region diffusion layer 15 is expressed as a <b and Let a <c. Thereby, the voltage drop from the second N-type buried diffusion layer 21 to the drain region diffusion layer 19 is reduced, and the voltage of the second N-type buried diffusion layer 21 can be stabilized. It is possible to suppress the electric field concentration that the electric field is biased near the drain region diffusion layer 15 when the LDMOS is on, and the on-breakdown voltage is improved.

In the present embodiment, the first N-type buried diffusion layer 12 is disposed so as to overlap the drain region diffusion layer 19, the source region diffusion layer 18, the P-type body region diffusion layer 15, and the gate electrode 17 in plan view. To do. Thereby, the first N-type buried diffusion layer 12 can be isolated from other elements, and the influence of noise on the P-type silicon substrate 11 can be reduced. Further, the first N-type buried diffusion layer 12 and the second N-type buried diffusion layer 21 increase the drain current from the source region diffusion layer 18 via the first and second N-type buried diffusion layers 12, 21. be able to. Therefore, the on-resistance of the LDMOS can be reduced. In the present specification, “overlap” means that the upper layer pattern and the lower layer pattern overlap in a plan view.
Further, the leakage between the P-type body region diffusion layer 15 and the P-type substrate 11 can be suppressed by the first N-type buried diffusion layer 12.

  In addition, the second N-type buried diffusion layer 21 can suppress the potential of the first N-type buried diffusion layer 12 from approaching the potential of the source region diffusion layer 18, and the electric field concentration near the drain region diffusion layer 19 can be reduced. Can be suppressed. In particular, when the LDMOS is used by fixing the potential of the first N-type buried diffusion layer 12 to the potential of the drain region diffusion layer 19, even if a drain current flows through the first N-type buried diffusion layer 12, It is possible to suppress the potential of the N-type buried diffusion layer 12 of 1 from becoming unstable, and to suppress electric field concentration in the drain region diffusion layer 19.

  In this embodiment, the N-channel LDMOS has been described. However, the present invention is not limited to the N-channel, and the P-channel LDMOS can also be implemented by reversing the conductivity type.

Further, in the present embodiment, the second N-type buried diffusion layer 21 is arranged so as not to contact the N ⁺ -type drain region diffusion layer 19, but may be modified as follows. The second N type buried diffusion layer 21 is disposed so as to be in contact with the N ⁺ type drain region diffusion layer 19. However, the second N-type buried diffusion layer 21 is preferably arranged so as not to exceed the dotted line shown in FIG. By doing so, electric field concentration in the drain region diffusion layer 19 can be more effectively suppressed.

[Embodiment 2]
A method for manufacturing a semiconductor device according to one embodiment of the present invention is described below with reference to FIGS. 2 and 3 are cross-sectional views illustrating a method for manufacturing the semiconductor device shown in FIG.

  As shown in FIG. 2A, by introducing N-type impurity ions into the P-type silicon substrate 11, the first N-type buried diffusion layer 12 is formed on the surface of the P-type silicon substrate 11.

  Next, as shown in FIG. 2B, by introducing N-type impurity ions into the first N-type buried diffusion layer 12, the second N-type buried diffusion is introduced into the first N-type buried diffusion layer 12. Layer 21 is formed. The impurity of the second N-type buried diffusion layer 21 is preferably an impurity having a higher concentration than the impurity of the first N-type buried diffusion layer 12 and easily diffused, for example, As and P.

  Thereafter, as shown in FIG. 2C, a P-type epitaxial layer 13a is formed on the first and second N-type buried diffusion layers 12 and 21. In the present embodiment, the P-type epitaxial layer 13a is formed, but an N-type epitaxial layer may be formed.

  Next, as shown in FIG. 2D, N-type impurity ions are introduced into the P-type epitaxial layer 13a and heat treatment is performed, thereby forming the N-type well 13 in the P-type epitaxial layer 13a. By this heat treatment, impurity ions in the first and second N type buried diffusion layers 12 and 21 are diffused into the N type well 13. Since the impurity in the second N-type buried diffusion layer 21 has a higher concentration than the impurity in the first N-type buried diffusion layer 12 and is easily diffused, the second N-type buried diffusion layer 21 has the first N-type buried diffusion layer. The layer 12 spreads from the layer 12 to the surface side of the N-type well 13 and is diffused.

  Thereafter, as shown in FIG. 3A, a field insulating film 14 as an offset insulating film is formed in the N-type well 13 by the LOCOS method.

  Next, as shown in FIG. 3B, a gate insulating film 16 is formed by thermal oxidation on the surface of the N-type well 13 where the field insulating film 14 is not formed. Next, a P-type impurity is introduced into the N-type well 13 to form a P-type body region diffusion layer 15 in the N-type well 13. Next, a polysilicon film is formed on the entire surface including the field insulating film 14 and the gate insulating film 16, and the polysilicon film is processed to form a gate electrode 17 on the field insulating film 14 and the gate insulating film 16. .

Next, an N ⁺ type drain region diffusion layer 19 is formed in the N type well 13 in a self-aligned manner with respect to the field insulating film 14, and an N ⁺ type source region diffusion layer 18 is formed on the P type body region diffusion layer 15 as a gate electrode. 17 in a self-aligned manner. Next, a P ⁺ type body contact region 15 a for partially connecting to the P type body diffusion layer 15 is formed in the N ⁺ type source region diffusion layer 18.

  The left side of FIG. 4 is a diagram showing the simulation result of the potential distribution during the on-break of the N-channel LDMOS shown in FIG. The potential distribution at the time of on-break is a potential distribution just before the LDMOS is broken. In this simulation, the voltage distribution is increased from 0V and shows a potential distribution just before it breaks, and is a potential distribution when the drain voltage Vd is 55.2V and the drain current Id is 2 mA / μm.

  On the other hand, the right side of FIG. 4 is a diagram showing a simulation result of the potential distribution during the on-break of the N-channel LDMOS shown in FIG. 5 as a comparative example. This simulation shows the potential distribution when the drain voltage Vd is 17.1 V and the drain current Id is 0.5 mA / μm.

  In the left side of FIG. 4, the number of equipotential lines in the drain region is reduced compared to the right side, the electric field concentration in the drain region is reduced, and the LDMOS of this embodiment is less likely to break than the comparative example. You can see that

  In the present invention, when a specific B (hereinafter referred to as “B”) is formed above (or below) a specific A (hereinafter referred to as “A”) (when B is formed), Or, it is not limited to the case where B is directly formed (below). It includes the case where B is formed (otherwise B) is formed on the upper side (or the lower side) of A through other things as long as the effects of the present invention are not inhibited.

DESCRIPTION OF SYMBOLS 11 ... P-type silicon substrate, 12 ... 1st N-type buried diffusion layer, 13 ... N-type well, 13a ... P-type epitaxial layer, 14 ... Field insulating film, 15 ... P-type body region diffusion layer, 15a ... P ⁺ Type body contact region, 16 ... gate insulating film, 17 ... gate electrode, 18 ... N ⁺ type source region diffusion layer, 19 ... N ⁺ type drain region diffusion layer, 21 ... second N type buried diffusion layer.

Claims (6)

A first semiconductor layer of a first conductivity type;
A drain region of a first conductivity type formed in the first semiconductor layer;
A second conductivity type body region formed in the first semiconductor layer;
A first conductivity type source region formed in the body region;
A field insulating film formed on the first semiconductor layer and positioned between the drain region and the body region;
A gate insulating film formed on the first semiconductor layer and the body region and positioned between the drain region and the source region;
A gate electrode formed on the field insulating film and the gate insulating film;
A first impurity region of a first conductivity type formed in the first semiconductor layer;
Comprising
At least a portion of the first impurity region overlaps the drain region in plan view,
A second distance between the end of the field insulating film on the source region side and the first impurity region, rather than a first distance between the end of the field insulating film on the source region side and the drain region. Is big,
A semiconductor device, wherein a third distance between the body region and the first impurity region is larger than a first distance between an end of the field insulating film on the source region side and the drain region. . In claim 1,
A second impurity region of a first conductivity type in contact with the first impurity region;
The semiconductor device, wherein the second impurity region overlaps the drain region, the source region, the body region, and the gate electrode in plan view. In claim 2,
The semiconductor device, wherein the second impurity region is formed in a second semiconductor layer located below the first semiconductor layer. In any one of Claims 1 thru | or 3,
The semiconductor device, wherein the first impurity region is in contact with the drain region. Forming a second impurity region of the first conductivity type in the semiconductor substrate;
Forming a first impurity region of a first conductivity type in the second impurity region;
Forming an epitaxial layer on the semiconductor substrate including the first impurity region and the second impurity region;
Forming a first conductivity type well in the epitaxial layer, thermally diffusing the impurity in the first impurity region in the well;
Forming a field insulating film on the well;
Forming a gate insulating film on the well;
Forming a second conductivity type body region in the well;
Forming a gate electrode on the field insulating film and the gate insulating film;
Forming a drain region of a first conductivity type in the well in a self-aligned manner with respect to the field insulating film, and forming a source region of a first conductivity type in the body region in a self-aligned manner with respect to a gate electrode;
The field insulating film is located between the drain region and the body region,
At least a portion of the first impurity region overlaps the drain region in plan view,
A second distance between the end of the field insulating film on the source region side and the first impurity region, rather than a first distance between the end of the field insulating film on the source region side and the drain region. Is big,
A semiconductor device, wherein a third distance between the body region and the first impurity region is larger than a first distance between an end of the field insulating film on the source region side and the drain region. Manufacturing method. In claim 5,
The method of manufacturing a semiconductor device, wherein the second impurity region overlaps the drain region, the source region, the body region, and the gate electrode in plan view.