JP2016080822A - Manufacturing method of organic el display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform open/short-circuit inspection of a data line of an organic EL display panel comprising a TFT including a channel made of an amorphous oxide semiconductor (AOS).SOLUTION: A manufacturing method of an organic EL display panel 100 comprising a selection transistor 121 including a channel 114 made of amorphous oxide semiconductor includes the steps of: forming a gate electrode 125; forming a scan line 122; forming a gate common wiring 123; forming a source electrode 126; forming a drain electrode 127; forming a plurality of data lines 124 connected to the source electrode 126; applying a negative potential to gate common wiring 123 on a stage 200 on which a substrate 110 is mounted; and performing open/short-circuit inspection of the data line 124.SELECTED DRAWING: Figure 14

Description

  The present disclosure relates to a method of manufacturing an organic EL display panel that displays an image by causing an organic EL (Electro Luminescence) to emit light by a transistor or the like formed in a matrix on a substrate.

  Conventionally, a display panel using an organic EL emits light by passing a current through each of the organic ELs (pixels) arranged in a matrix. A color image (moving image) is controlled by controlling the emission color and luminance of the pixels. ) Is displayed. The organic EL that emits red light, the organic EL that emits green light, and the organic EL that emits blue light, which constitute the pixel, are referred to as sub-pixels, and the sub-pixels are connected to a plurality of thin film transistors (TFTs). The drive is controlled based on this.

  As described above, in order to drive each sub-pixel, a large number of TFTs are arranged in a matrix (referred to as a TFT array), and the TFT array is, for example, a low-temperature polysilicon or a- A semiconductor made of Si (amorphous silicon), a wiring material, and an insulator for separating each layer are formed.

  In manufacturing the TFT array, each layer is laminated and etching is performed. However, a defect of the TFT array may be detected by using an inspection device or the like during the manufacturing process. For example, Patent Document 1 describes a method of performing a function inspection of a TFT array before the organic EL forming step. Specifically, Patent Document 1 discloses a method for detecting an open-short defect of a driving TFT with respect to a TFT array before mounting an organic EL.

JP 2004-347749 A

  In recent years, the display panel has been improved in definition, and the wiring material stretched in a striped pattern on the entire display panel is also formed in a thin and high density, so that not only the defect of the TFT itself but also the disconnection of the wiring It is also preferable to detect defects such as short circuits between adjacent wires.

  Therefore, conventionally, a TFT array is placed on a stage, and a predetermined voltage is applied to the entire stage (including grounding) to perform an open short inspection of wiring.

  However, when a TFT having a desired performance is formed by using, for example, TAOS (Transparent Amorphous Oxide Semiconductor) as a semiconductor constituting the TFT, the conventional method, that is, the TFT array is set to a stage of a predetermined voltage. Each TFT is turned on (a state in which current flows between the source and drain) in a state where it is mounted on the substrate, and is in a conductive state with other wiring, so that it is impossible to effectively perform an open short inspection of the wiring. Found.

  The present disclosure is based on the knowledge of the inventor described above, and manufactures an organic EL display panel by performing an effective open-short inspection of a wiring even for a display panel including a TFT using an amorphous oxide semiconductor. The purpose is to provide a method capable of

  In order to achieve the above object, a method for manufacturing an organic EL display panel according to the present disclosure is a method for manufacturing an organic EL display panel including a selection transistor having a channel made of an amorphous oxide semiconductor, and the method is provided on an insulating substrate. Forming a gate electrode of the selection transistor, forming a scan line connected to the plurality of gate electrodes, forming a common gate wiring connected to the plurality of scan lines, and forming a source electrode of the selection transistor Forming a drain electrode of the selection transistor, forming a data line connected to the plurality of source electrodes, and applying a negative potential to close the channel of the selection transistor to the stage on which the substrate is placed An open short inspection is performed on the data line while applying to the common gate wiring. .

  In order to achieve the above object, a method for manufacturing an organic EL display panel according to the present disclosure is a method for manufacturing an organic EL display panel including a selection transistor having a channel made of an amorphous oxide semiconductor, and includes an insulating substrate. Forming a gate electrode of the selection transistor; forming a scan line connected to the plurality of gate electrodes; forming a source electrode of the selection transistor; forming a drain electrode of the selection transistor; A data line connected to the source electrode is formed, and a potential head arranged along a sequence of the plurality of selection transistors commonly connected to any of the data lines is used, and the stage on which the substrate is mounted Applying a negative potential to the potential head and generating an electric field that closes the channel of the selection transistor Which comprises carrying out the open short inspection for over data lines.

  According to the present disclosure, it is possible to effectively perform an open short inspection of a data line in a manufacturing process of an organic EL display panel.

FIG. 1 is a circuit diagram showing a part of a TFT array according to an embodiment. FIG. 2 is a cross-sectional view showing the structure of the selection transistor. FIG. 3 is a plan view showing a pattern obtained by the GM process. FIG. 4 is a cross-sectional view showing one process included in the GM process of the first embodiment. FIG. 5 is a cross-sectional view showing the next step included in the GM step of the first embodiment. FIG. 6 is a cross-sectional view showing the next step included in the GM step of the first embodiment. FIG. 7 is a plan view showing a pattern obtained by the SC process. FIG. 8 is a cross-sectional view showing one process included in the SC process of the first embodiment. FIG. 9 is a cross-sectional view showing the next step included in the SC step in the first embodiment. FIG. 10 is a plan view showing a pattern of openings obtained by the ES process. FIG. 11 is a cross-sectional view showing the selection transistor after completion of the ES process of the first embodiment. FIG. 12 is a plan view showing a pattern of openings obtained by the SD process. FIG. 13 is a cross-sectional view showing the selection transistor after completion of the SD process of the first embodiment. FIG. 14 is a perspective view showing a state of the open short inspection of the data line according to the first embodiment. FIG. 15 is a circuit diagram showing a part of the TFT array according to the second embodiment. FIG. 16 is a perspective view showing a state of an open short inspection of a data line according to the third embodiment.

  Next, an embodiment of a method for manufacturing an organic EL display panel according to the present disclosure will be described with reference to the drawings. The following embodiments are merely examples of a method for manufacturing an organic EL display panel according to the present disclosure. Accordingly, the scope of the present disclosure is defined by the wording of the claims with reference to the following embodiments, and is not limited to the following embodiments. Therefore, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept of the present disclosure are not necessarily required to achieve the object of the present disclosure. It will be described as constituting a preferred form.

  Each figure is a schematic diagram and is not necessarily illustrated strictly.

(Embodiment 1)
Hereinafter, a method for manufacturing an organic EL display panel according to an embodiment will be described with reference to the drawings.

[Configuration of TFT array]
First, the structure of the TFT array 101 which is a part of the organic EL display panel 100 manufactured by the manufacturing method according to the embodiment will be described.

  FIG. 1 is a circuit diagram showing a part of a TFT array according to an embodiment.

  FIG. 2 is a cross-sectional view showing the structure of the selection transistor. Note that other transistors may have a similar structure.

  As shown in FIG. 1, the TFT array 101 has thin film transistors provided in a matrix.

  The TFT array 101 includes one selection transistor 121 for each subpixel 102, and further includes a scan line 122, a gate common wiring 123, and a data line 124 that are wired across the plurality of subpixels 102. Yes. As shown in FIG. 2, the selection transistor 121 is a thin film transistor formed on the substrate 110, and includes a gate electrode 125, a source electrode 126, a drain electrode 127, a gate insulating film 113, a channel 114, and channel protection. And a film 115.

  The selection transistor 121 is a thin film transistor in which the gate electrode 125 is connected to the scan line 122 and the source electrode 126 is connected to the data line 124, and determines whether to supply an image signal transmitted to the data line 124 to the capacitor. This is a transistor for selecting based on the scanning signal transmitted to the scanning line 122. In this embodiment, the selection transistor 121 is a bottom gate type.

  The material of the substrate 110 is not particularly limited as long as it has insulating properties. For example, the substrate 110 is made of a glass material such as quartz glass, non-alkali glass, or high heat resistance glass, polyethylene, polypropylene, In some cases, the resin material is made of a resin material such as polyimide. Further, the substrate 110 may be a flexible substrate having flexibility as well as a rigid substrate having relatively high rigidity.

  The gate electrode 125 is an electrode having a single layer structure or a multilayer structure of a conductive film made of a conductive material, and is formed in a predetermined shape above the substrate 110. The material of the gate electrode 125 is not specifically limited. For example, a metal or an alloy made of a plurality of types of metals (for example, molybdenum tungsten), indium tin oxide (ITO), aluminum-doped zinc oxide ( Examples thereof include conductive metal oxides such as AZO) and gallium-doped zinc oxide (GZO), or conductive polymer materials such as polythiophene and polyacetylene.

  The gate insulating film 113 is a member that is disposed between the gate electrode 125 and the channel 114 and insulates the gate electrode 125 and the channel 114. The gate insulating film 113 is not particularly limited as long as it is made of an electrically insulating material. For example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, or a tantalum oxide is used. Examples thereof include a single layer film such as a film or a hafnium oxide film, or a stacked film in which a plurality of these films are stacked.

  The channel 114 is a portion made of an amorphous oxide semiconductor and is formed in a predetermined shape on the gate insulating film 113 above the gate electrode 125. In this embodiment mode, a transparent amorphous oxide semiconductor (TAOS) is used as a material of the channel 114, and metal elements included in the channel 114 are indium (In), tungsten (W), and gallium (Ga). Zinc (Zn) and the like.

  The channel protective film 115 is a film that is disposed on the channel 114 so as to cover the channel 114 and protects the channel 114. In this embodiment mode, the channel protective film 115 is an interlayer insulating layer formed over the entire surface of the substrate 110.

  The channel protective film 115 is not particularly limited as long as it is an electrically insulating material. For example, a single layer film such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an aluminum oxide film, or these Examples of such laminated films can be given.

  In addition, an opening (contact hole) is formed in the channel protective film 115 so as to penetrate a part of the channel protective film 115. The channel 114 is connected to the source electrode 126 and the drain electrode 127 through the opening of the channel protective film 115.

  The source electrode 126 and the drain electrode 127 are electrodes formed above the channel protective film 115. Specifically, the source electrode 126 and the drain electrode 127 are disposed on the channel protective film 115 so as to be spaced apart from each other in a direction parallel to the substrate 110 (substrate horizontal direction) and to face each other. It is connected to the channel 114 through an opening formed in the channel.

  The source electrode 126 and the drain electrode 127 are not particularly limited as long as they are conductive materials. For example, aluminum, tantalum, molybdenum, tungsten, silver, copper, titanium, or chromium is used. Further, the source electrode 126 and the drain electrode 127 may be electrodes having a multilayer structure as well as a single layer structure.

  The scan line 122 is a wiring connected to the gate electrode 125 of the selection transistor 121, and is a wiring through which a scanning signal for displaying an image is transmitted. When the scan signal is supplied to the scan line 122, the source electrode 126 and the drain electrode 127 of the selection transistor 121 are brought into conduction, that is, the selection transistor 121 is turned on. The scan line 122 is connected to the gate electrode 125 of the selection transistor 121. A plurality of scan lines 122 are wired side by side so as to intersect with the data lines 124.

  The gate common wiring 123 is a wiring connected to the ends of the plurality of scan lines 122. The gate common wiring 123 is a wiring called a short bar (ESC element) provided to protect the selection transistor 121 and the like from static electricity and the like in the process of manufacturing the TFT array 101. Wired. When displaying an image, it is necessary to transmit a scanning signal to each of the scanning lines 122 independently. Therefore, when the organic EL display panel 100 is completed, the electrical connection between the gate common wiring 123 and each scanning line 122 is not performed. Blocked. In this embodiment, since the gate common wiring 123 and the scan line 122 are directly connected via a contact hole, the gate common wiring 123 and the scan line 122 are subjected to an open short inspection of the data line 124. Is disconnected by breaking the wiring together with the substrate 110.

  In the case of the present embodiment, a contact pad 131 that is a portion that contacts a contact pin 132 (see FIG. 14) for applying a potential is provided at the end of the gate common wiring 123. Note that the contact pad 131 may be used for other purposes in the manufacturing process of the organic EL display panel 100, for example, for grounding the gate common wiring 123 in order to release static electricity.

  The data line 124 is a wiring connected to each of the source electrodes 126 of the plurality of selection transistors 121 arranged in a line, and is a wiring through which an image signal is transmitted. A plurality of data lines 124 are arranged so as to intersect the scan lines 122, and are wired extending from one end of the TFT array 101 to the other end. Note that the open short inspection of the present disclosure inspects whether the data line 124 is short-circuited or disconnected from another wiring (for example, a wiring used for an adjacent subpixel).

[TFT array manufacturing process]
Next, the manufacturing process of the TFT array 101 will be described with reference to the drawings.

  First, the GM process will be described. The GM process is a process of forming the selection transistor 121, the gate electrode 125 of other transistors, wirings connected to the gate electrodes, other wirings, and the like.

  FIG. 3 is a plan view showing a pattern obtained by the GM process.

  4-6 is sectional drawing which shows each process included in the GM process of embodiment.

  First, as shown in FIG. 4, a metal film 111 is formed on the entire upper surface of the substrate 110 using a sputtering method or the like. The metal film may have a multilayer structure of copper and molybdenum.

  Next, a pattern of a photoresist 112 is formed on the surface of the metal film 111 using photolithography or the like. The pattern of the photoresist 112 is the same as the pattern of the metal film 111 that is desired to remain in the next etching process.

  Next, the portion of the metal film 111 where the photoresist 112 is not formed is etched using a wet etching method or the like.

  As a result, a pattern as shown in FIG. 3 including the gate electrode 125 of the selection transistor 121 and the scan line 122 connected to the gate electrode 125 is formed. In the case of this embodiment, the gate electrode 125 and the scan line 122 are integrally formed.

  Next, the SC process will be described. The SC process is a process for forming the channel 114.

  FIG. 7 is a plan view showing a pattern obtained by the SC process.

  8 and 9 are cross-sectional views showing each process included in the SC process of the embodiment.

  First, as shown in FIG. 8, a gate insulating film 113 is formed on a pattern such as the gate electrode 125 formed by the GM process. Next, an amorphous oxide semiconductor film 119 which is a channel formation layer is formed over the gate insulating film 113. In this embodiment, TAOS is formed as the amorphous oxide semiconductor film 119 by a sputtering method or the like.

  Next, similarly to the case where the pattern of the gate electrode 125 or the like is formed, a photoresist pattern is formed on the surface of the amorphous oxide semiconductor film 119 using photolithography or the like, and unnecessary using a wet etching method or the like. Etch the part.

  As a result, as shown in FIG. 9, a channel 114 is formed at a position facing the gate electrode 125 with the gate insulating film 113 interposed therebetween.

  Next, the ES process will be described. The ES step is a step of forming the channel protective film 115 and forming an opening reaching the channel 114 or the gate electrode 125.

  FIG. 10 is a plan view showing a pattern of openings obtained by the ES process.

  FIG. 11 is a cross-sectional view illustrating the select transistor after completion of the ES process according to the embodiment.

  First, similarly to the case where the gate insulating film 113 is formed, a channel protective film 115 is formed on the gate insulating film 113 so as to cover the channel 114.

  Next, similarly to the case where the pattern of the gate electrode 125 or the like is formed, a photoresist pattern is formed on the surface of the channel protective film 115 using photolithography or the like, and the opening 118 is formed using a dry etching method or the like. Form.

  As a result, as shown in FIG. 11, a channel protective film 115 and an opening 118 are formed.

  Next, the SD process will be described. The SD process is a process of forming the selection transistor 121 and the source electrode 126, drain electrode 127, and other wirings of other transistors.

  FIG. 12 is a plan view showing a wiring pattern obtained by the SD process.

  FIG. 13 is a cross-sectional view illustrating the select transistor after the SD process according to the embodiment.

  As in the case of forming the gate electrode 125 and the like, a metal film is formed on the entire surface of the channel protective film 115 by sputtering or the like. As a result, a metal film is also formed on the inner peripheral surface of the opening 118. Next, a photoresist pattern is formed on the surface of the metal film using photolithography or the like. Next, unnecessary portions of the metal film are etched using a wet etching method or the like.

  As a result, a wiring pattern as shown in FIG. 12 including the source electrode 126, the drain electrode 127 of the selection transistor 121, and the data line 124 connected to the source electrode 126 is formed.

  In the present embodiment, the gate common wiring 123 is also formed in the SD process. Note that the gate common line 123 and the scan line 122 are connected via the opening 118.

  Through the above steps, the data line 124 to be subjected to the open short inspection is formed, and the gate common wiring 123 connected to the gate electrodes 125 of all the selection transistors 121 of the TFT array 101 is formed. Further, immediately after the data line 124 and the gate common wiring 123 are formed or after that, the open short inspection of the data line 124 is performed.

[Open short inspection]
Next, the open short inspection of the data line 124 will be described.

  FIG. 14 is a perspective view showing a state of an open short inspection of a data line.

  As shown in the drawing, a data line 124 and a common gate wiring 123 are formed on a substrate 110 through an SD process, and a TFT array 101 on which a selection transistor 121, other transistors, wirings, and the like are formed is placed below the substrate 110. Then, it is placed on the stage 200.

  A negative potential that closes the channel 114 of the selection transistor 121 is applied to the gate common wiring 123 with respect to the stage 200 on which the TFT array 101 is mounted.

  Here, the state in which the channel 114 of the selection transistor 121 is closed indicates a state in which the selection transistor 121 is turned off, that is, a state in which no current flows between the source electrode 126 and the drain electrode 127 of the selection transistor 121. Yes.

  The negative potential for closing the channel 114 is not specifically limited, but is a potential equal to or lower than the threshold voltage of the selection transistor 121. For example, when the TFT array 101 is mounted on the grounded stage 200, the voltage applied to the gate electrode 125 via the gate common wiring 123 and the scan line 122 is lower than the ground potential (0 potential) ( Apply a potential below the (negative) threshold voltage. This is because when the channel 114 formed of an amorphous oxide semiconductor has a desired characteristic (for example, high mobility), the threshold voltage of the selection transistor 121 may be negative and grounded. This is based on the knowledge that the channel 114 is opened, that is, the selection transistor 121 is kept on only by placing the TFT array 101 on the stage 200.

  Next, with the selection transistors 121 directly connected to the data line 124 to be inspected turned off as described above (in the present embodiment, all the selection transistors 121 are turned off), the data lines 124 are opened. Conduct a short inspection.

  The open short inspection method is not particularly limited, and open only inspection and short only inspection are also included in the open short inspection. In the case of the present embodiment, the inspection apparatus for performing the open short inspection has a power supply terminal 133 to which an alternating voltage of a predetermined frequency can be applied by contact and a change in the potential of the wiring in a contactless manner (with capacitive coupling). And a power receiving sensor 134 capable of measuring.

  The open short inspection using the inspection apparatus is as follows. The power supply terminal 133 is brought into contact with one end portion of the data line 124, and the power receiving sensor 134 is disposed in the vicinity of the other end portion of the data line 124 (a distance that allows capacitive coupling). An AC voltage having a predetermined frequency is applied to one end of the data line 124 through the power supply terminal 133. If the data line 124 is not broken or short-circuited, a change in voltage corresponding to the applied AC voltage can be acquired based on the power receiving sensor 134. On the other hand, when the wire is disconnected or short-circuited, the voltage change state acquired by the power receiving sensor 134 is a voltage change state different from that in a favorable case. As described above, the open / short inspection of the data line 124 can be performed by observing the voltage change state.

  The above open short inspection is performed on each data line 124. For example, by fixing the stage 200 and the TFT array 101 placed on the stage 200 and moving the power supply terminal 133 and the power receiving sensor 134 relative to the stage 200 (in the direction indicated by the arrow in FIG. 14), The open short inspection may be performed on the data lines 124 arranged in stripes in order.

  Note that whether the power supply terminal 133 is in contact with or non-contact with the data line 124 is not particularly limited, and whether the power receiving sensor 134 is in contact with the data line 124 or not is not particularly limited. Moreover, these combinations are also arbitrary.

  The TFT array 101 in which a defect is found by the above open short inspection is repaired.

  The TFT array 101 in which no defect is found or the repaired TFT array 101 is further subjected to other film forming process, etching process, etc., and the electrical connection between the scan line 122 and the gate common wiring 123 is cut off. The organic EL display panel 100 is manufactured by performing the cleaving process.

  According to the manufacturing method as described above, even when an amorphous oxide semiconductor having a negative threshold voltage is used for the channel 114, the individual data lines 124 are electrically disconnected from each other to perform an open short test. It can be performed. Therefore, the organic EL display panel 100 can be manufactured using the TFT array 101 provided with the data line 124 without disconnection or short circuit, and the yield of the organic EL display panel 100 can be improved.

(Embodiment 2)
Subsequently, Embodiment 2 of the present disclosure will be described. Note that parts corresponding to those in the first embodiment may be denoted by the same reference numerals and description thereof may be omitted, and description will be made focusing on differences from the first embodiment.

  FIG. 15 is a circuit diagram showing a part of the TFT array according to the second embodiment.

  As shown in the figure, a diode 103 is connected between the gate common line 123 and each scan line 122.

  The semiconductor used for the diode 103 is preferably the same as the amorphous oxide semiconductor film constituting the channel 114. In the present embodiment, the diode 103 is a bidirectional diode.

  The diode 103 has a low resistance until the open / short inspection of the data line 124 is completed, that is, the diode 103 is manufactured to have a low resistance. Here, the low resistance is a resistance that allows the selection transistor 121 to be turned off by a negative DC voltage applied to the gate common wiring 123.

  The diode 103 is increased in resistance after the open short inspection of the data line 124. A method for changing the diode 103 from a low resistance to a high resistance is not particularly limited. For example, when the entire TFT array 101 is annealed, the diode 103 has a high resistance. Here, the high resistance is a resistance that prevents the scanning signal from being transmitted to the other scanning line 122 via the gate common wiring 123 when the scanning signal is transmitted to one scanning line 122.

  According to the present embodiment, as in the first embodiment, even when an amorphous oxide semiconductor is used for the channel 114, the individual data lines 124 are electrically disconnected from the other and the open short inspection is performed. be able to. Therefore, the organic EL display panel 100 can be manufactured using the TFT array 101 provided with the data line 124 without disconnection or short circuit, and the yield of the organic EL display panel 100 can be improved.

  Further, since the scan line 122 and the gate common wiring 123 can be disconnected only by increasing the resistance of the diode 103 (for example, annealing the TFT array 101), each of the scan line 122 and the gate common wiring 123 It becomes possible to manufacture the organic EL display panel 100 without performing a cleaving step for physically dividing the layer.

(Embodiment 3)
Subsequently, Embodiment 3 of the present disclosure will be described. Note that portions corresponding to those in the first and second embodiments may be denoted by the same reference numerals and description thereof may be omitted, and description will be made focusing on differences from the first embodiment.

  FIG. 16 is a perspective view illustrating a state of an open short test of a data line according to the third embodiment.

  As shown in the figure, the TFT array 101 placed on the stage 200 is the same as the TFT array 101 described in the first embodiment. In the case of this embodiment, the gate common wiring 123 may not be provided. Further, the diode 103 may be interposed between the gate common line 123 and each scan line 122, and the diode 103 may be in a high resistance state or a low resistance state.

  In the case of the present embodiment, the inspection device for performing the open short inspection includes a power supply terminal 133 and a power reception sensor 134, and further includes a potential head 135.

  The potential head 135 is a conductive member arranged along a line of a plurality of selection transistors 121 connected in common to the data line 124 to be subjected to the open short test. The potential head 135 is arranged along the data line 124 to be inspected in a state slightly separated from the TFT array 101 placed on the stage 200. In the potential head 135, a negative potential is applied to the stage 200 on which the substrate 110 of the TFT array 101 is placed, so that an electric field generated between the stage 200 and the potential head 135 causes a channel 114 of the selection transistor 121. Can be closed.

  By using the above inspection apparatus, it is possible to perform an open / short inspection of the data line 124 after turning off only the selection transistor 121 directly connected to the data line 124 to be inspected.

  The open short inspection using the inspection apparatus is as follows. A potential (negative potential) is applied to the potential head 135 to turn off the selection transistor 121 directly connected to the data line 124. Next, as in the first embodiment, the power supply terminal 133 is brought into contact with one end portion of the data line 124, the power receiving sensor 134 is disposed at the other end portion of the data line 124, and the AC voltage supplied from the power supply terminal 133 is used. Is detected by the power receiving sensor 134, and disconnection or short circuit of the data line 124 is detected.

  When performing an open short inspection on the next data line 124, for example, the TFT array 101 placed on the stage 200 is fixed, and the power supply terminal 133, the power receiving sensor 134, and The potential head 135 may be moved.

  According to the present embodiment, as in the first and second embodiments, even when an amorphous oxide semiconductor is used for the channel 114, the channel 114 is connected to the desired data line 124 regardless of the presence or absence of the gate common wiring 123. Only the select transistor to be turned off can be turned off, and the data line 124 can be electrically disconnected from the other to perform an open short test. Therefore, the organic EL display panel 100 can be manufactured using the TFT array 101 provided with the data line 124 without disconnection or short circuit, and the yield of the organic EL display panel 100 can be improved.

  Further, it is not necessary to contact the contact pin 132 in order to apply a predetermined potential to all the scan lines 122, and the open / short of the data line 124 can be easily performed regardless of whether or not the gate common wiring 123 is formed. An inspection can be performed.

  In addition, this indication is not limited to the said embodiment. For example, another embodiment realized by arbitrarily combining the components described in this specification and excluding some of the components may be used as an embodiment of the present disclosure. Further, the present disclosure also includes modifications obtained by making various modifications conceivable by those skilled in the art without departing from the gist of the present disclosure, that is, the meanings of the words described in the claims. It is.

  For example, in the present embodiment, the potential head 135 has been described as having a shape extending along the data line 124, but the shape and the like are not particularly limited. For example, the potential head 135 may be configured by arranging a plurality of pin-shaped electrodes corresponding to the position where the selection transistor 121 is disposed. The potential head 135 may include one or a plurality of pins and can individually turn on / off individual thin film transistors.

  The technique disclosed here can be widely used in the manufacture of an organic EL display panel including a thin film transistor using an amorphous oxide semiconductor.

100 Organic EL Display Panel 101 TFT Array 102 Subpixel 103 Diode 110 Substrate 111 Metal Film 112 Photoresist 113 Gate Insulating Film 114 Channel 115 Channel Protection Film 118 Opening 119 Amorphous Oxide Semiconductor Film 121 Select Transistor 122 Scan Line 123 Gate Common Wiring 124 data line 125 gate electrode 126 source electrode 127 drain electrode 131 contact pad 132 contact pin 133 power supply terminal 134 power receiving sensor 135 potential head 200 stage

Claims (4)

A method of manufacturing an organic EL display panel including a selection transistor having a channel made of an amorphous oxide semiconductor,
Insulating substrate
Forming a gate electrode of the selection transistor;
Forming a scan line connected to the plurality of gate electrodes;
Forming a gate common line connected to the plurality of scan lines;
Forming a source electrode of the selection transistor;
Forming a drain electrode of the selection transistor;
Forming data lines connected to the plurality of source electrodes;
While applying a negative potential to close the channel of the selection transistor to the gate common wiring with respect to the stage on which the substrate is placed,
An organic EL display panel manufacturing method for performing an open short inspection on the data line. Forming a diode between the gate common line and each of the scan lines;
The method for manufacturing an organic EL display panel according to claim 1, wherein the resistance of the diode is increased after the open short inspection. The method of manufacturing an organic EL display panel according to claim 1, wherein the gate common line and each of the scan lines are cleaved after the open short inspection. A method of manufacturing an organic EL display panel including a selection transistor having a channel made of an amorphous oxide semiconductor,
Insulating substrate
Forming a gate electrode of the selection transistor;
Forming a scan line connected to the plurality of gate electrodes;
Forming a source electrode of the selection transistor;
Forming a drain electrode of the selection transistor;
Forming data lines connected to the plurality of source electrodes;
Using a potential head arranged along a sequence of the plurality of selection transistors commonly connected to any of the data lines, a negative potential is applied to the potential head with respect to the stage on which the substrate is placed, A method of manufacturing an organic EL display panel, wherein an open-short inspection is performed on the data line while generating an electric field that closes a channel of a selection transistor.

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