JP2016076249A - Image processing device, control method thereof, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute hibernation transition processing safely and suitably shorten the time needed for the supply of power to stop, even when it is so configured that the power source is always turned off a certain time later by turning a power switch off.SOLUTION: An image processing device executes hibernation processing which, when a first time elapses after a power switch is manipulated by an operator so as to stop the supply of power, a stored content of a main storage memory used as a work area by a CPU is saved to a secondary storage device. Furthermore, when the hibernation processing is completed within a target time that is necessary for the hibernation processing and termination processing of the image processing device to complete before the first time elapses, the image processing device executes the termination processing after the hibernation processing is completed and stops the supply of power; when the hibernation processing is not completed within the target time, the image processing device suspends the hibernation processing and executes the termination processing and then stops the supply of power.SELECTED DRAWING: Figure 11

Description

  The present invention relates to an image processing apparatus, a control method thereof, and a program.

  With the increase in functionality of current image processing apparatuses, the startup time from when the user turns on the power switch until it can be operated tends to increase. On the other hand, there is a method for speeding up the startup time by a suspend method in which the main memory is energized when the user performs a power OFF operation. However, the suspend method has a problem that energization needs to be continued when the main memory is a general DRAM or the like, and standby power is increased. The technology for reducing the standby power to zero is a hibernation method, which is a technology adopted when it is desired to improve the power saving performance, although it takes longer time to recover than the suspend method. For example, Patent Document 1 discloses a technique in which a physical power switch (toggle type switch) having an OFF / ON state is assigned as a hibernation function. Patent Document 2 discloses a technique for performing a hibernation operation when the remaining battery level is low, and avoiding the occurrence of power interruption during hibernation transition when the battery runs out at that time.

JP 2002-73220 A Japanese Patent Laid-Open No. 11-3151

  However, the above prior art has the following problems. For example, in Patent Document 1, since the power switch of the image processing apparatus is a (toggle type) switch having a physical OFF / ON state, the switch OFF / ON state and the power supply OFF / ON state of the main body are matched. There is a need. That is, a state where the main body power is not turned off even when the switch is OFF should not occur. In order to avoid this, when the power switch is turned off, it is necessary to set a protection timer in the power supply device separately from the software control to ensure that the power is always turned off after a certain time. However, when the power switch is assigned as the hibernation function and the hibernation transition process is not in time, there is a failure that the power is forcibly turned off by the protection timer during the hibernation transition.

  The present invention has been made in view of the above-described problem, and even when the power switch is always turned off after a certain time from turning off the power switch, the hibernation transition process is executed safely. An object of the present invention is to provide a mechanism that suitably shortens the time required until the power supply is stopped.

  The present invention, for example, is an image processing apparatus that forcibly stops power supply when a first time elapses after an operator operates a power switch so that power supply is stopped. Processing means for executing hibernation processing for saving the storage contents of the main memory used by the CPU of the image processing apparatus as a work area to a secondary storage device when the power supply of the image processing apparatus is stopped, and the first time has elapsed Determining means for determining whether or not the hibernation process by the processing means is completed within a target time required for completing the hibernation process and the termination process of the image processing apparatus before If it is determined that the hibernation process is completed within a time period, after the hibernation process is completed by the processing means, An image processing device termination process is executed to stop power supply. When it is determined that the hibernation process is not completed within the target time, the hibernation process by the processing unit is interrupted, and the image processing apparatus And power supply control means for stopping the power supply by executing a termination process.

  Even if the present invention has a configuration in which the power is always turned off after a certain time from turning off the power switch, the hibernation transition process is executed safely and the time required to stop the power supply is suitably reduced. A mechanism to do this can be provided.

1 is a diagram illustrating a configuration example of an image processing system according to an embodiment. The block diagram which shows the structural example of the controller part which concerns on this embodiment. The figure which shows an example of the power supply structure which concerns on this embodiment. The flowchart which shows the processing flow at the time of the shutdown which concerns on this embodiment. The figure explaining the hibernation which concerns on this embodiment. The flowchart which shows the processing flow at the time of the system interruption which concerns on this embodiment. The figure which shows the secondary storage device which concerns on this embodiment. The timing chart which shows the case where a malfunction occurs when it is normal. The timing chart which concerns on this embodiment. The timing chart which shows the system protection timer which concerns on this embodiment. The flowchart which shows the processing flow which concerns on this embodiment.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. The following embodiments do not limit the invention according to the claims, and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention.

<Configuration of image processing apparatus>
First, the configuration of the image processing system in the present embodiment will be described with reference to FIG. As shown in FIG. 1, the image processing system includes an image processing apparatus 100 and a computer 109 connected to the image processing apparatus 100 via a LAN 108. This system configuration is an example and is not intended to limit the present invention. For example, another image processing apparatus or another computer may be included.

  The image processing apparatus 100 includes a scanner device 102, a controller 103, a printer device 104, an operation unit 105, a hard disk 106, and a FAX device 107. The scanner device 102 optically reads an image from a document and converts it into a digital image. The printer device 104 outputs a digital image to a paper medium. The operation unit 105 is an interface for operating the image processing apparatus 100 by the user. The hard disk 106 stores a digital image, a control program, and the like. The FAX apparatus 107 transmits a digital image to a telephone line or the like, or receives a digital image from the telephone line or the like. The controller 103 is connected to each of the modules described above, and executes a job on the image processing apparatus 100 by giving an instruction to each module.

  The image processing apparatus 100 can perform input / output of digital images, job issuance, device instructions, and the like from the computer 109 via the LAN 108. The scanner apparatus 102 includes a document feeding unit 121 that can automatically and sequentially replace a bundle of documents, and a scanner unit 122 that can optically scan a document and convert it into a digital image. The converted image data is transmitted to the controller 103. The printer device 104 includes a paper feed unit 142 that can sequentially feed a paper bundle one by one, a marking unit 141 for printing image data on the fed paper, and a paper discharge unit for discharging the printed paper. 143.

The image processing apparatus 100 can execute various jobs. An example is described below.
Copying function The image read from the scanner device 102 is recorded on the hard disk 106 and simultaneously printed using the printer device 104.
Image transmission function The image read from the scanner apparatus 102 is transmitted to the computer 109 via the LAN 108.
Image storage function The image read from the scanner device 102 is recorded on the hard disk 106, and image transmission and image printing are performed as necessary.
Image printing function Analyzes, for example, a page description language transmitted from the computer 109 and prints it by the printer device 104.

<Configuration of controller>
Next, a configuration example of the controller 103 will be described with reference to FIG. The controller 103 includes a main board 200 and a sub board 220. The main board 200 is a so-called general-purpose CPU system, and includes a CPU 201, a boot ROM 202, a memory 203, a bus controller 204, a nonvolatile memory 205, a disk controller 206, a flash disk 207, a USB controller 208, and a timer 210. The CPU 201 comprehensively controls the entire board. The boot ROM 202 stores a boot program that is a program at the time of initial startup. A memory 203 is a main memory used as a work area by the CPU 201. The bus controller 204 has a bridge function with an external bus. The nonvolatile memory 205 is a memory whose stored contents do not disappear even when the power is turned off. The disk controller 206 controls the storage device. A flash disk (SSD or the like) 207 is a relatively small-capacity storage device configured with semiconductor devices. The USB controller 208 controls the USB device (here, the USB memory 209). The timer 210 is a system protection timer that functions as a time measuring means. In addition, a USB memory 209, an operation unit 105, a hard disk 106, and the like are connected to the main board 200 to the outside.

  The sub board 220 includes a relatively small general-purpose CPU system and image processing hardware. The sub board 220 includes a CPU 221, a memory 223, a bus controller 224, a nonvolatile memory 225, an image processing unit 227, and device controllers 226 and 228. The CPU 221 comprehensively controls the entire board. The memory 223 is used as a work memory by the CPU 221. The bus controller 224 has a bridge function with an external bus. The nonvolatile memory 225 does not erase the stored contents even when the power is turned off. The image processing unit 227 performs real-time digital image processing. The device controllers 228 and 226 exchange digital image data with the external scanner device 102 and the printer device 104, respectively. Note that the CPU 221 directly controls the FAX apparatus 107.

  FIG. 2 is a block diagram and is simplified. For example, the CPU 201, the CPU 221 and the like include a large number of CPU peripheral hardware such as a chip set, a bus bridge, and a clock generator. However, the CPU 201 and the CPU 221 are simplified for ease of explanation, and this block configuration limits the present invention. Please understand that it is not.

  Here, the operation of the controller 103 will be described by taking an image copy using a paper medium as an example. When the user instructs image copying from the operation unit 105, the CPU 201 sends a document image reading command to the scanner device 102 via the CPU 221. The scanner device 102 optically scans a paper document, converts it into digital image data, and inputs the digital image data to the image processing unit 227 via the device controller 228. The image processing unit 227 performs DMA transfer to the memory 223 via the CPU 221 and temporarily stores digital image data.

  When the CPU 201 can confirm that a certain amount or all of the digital image data has entered the memory 223, it issues an image output instruction to the printer device 104 via the CPU 221. The CPU 221 tells the image processing unit 227 the position (address) of the image data stored in the memory 223. The image data on the memory 223 is transmitted to the printer device 104 via the image processing unit 227 and the device controller 226 in accordance with the synchronization signal from the printer device 104, and the digital image data is printed on a paper medium in the printer device 104. When printing a plurality of copies, the CPU 201 stores the image data in the memory 223 in the hard disk 106. Therefore, the second and subsequent copies can be sent to the printer device 104 without receiving an image from the scanner device 102.

<Configuration of power switch>
Next, the configuration of the power switch in the image processing apparatus 100 according to the present embodiment will be described with reference to FIG. Reference numeral 301 shown in FIG. 3 denotes a toggle type power switch. Reference numeral 302 denotes a power supply unit. 303 is an AC-DC converter. Reference numeral 304 denotes an AC power input unit. A power cable 305 supplies DC power to the printer device 104. A power cable 306 supplies power to the controller 103. A line 307 notifies the controller of the state of the toggle switch 301. Reference numeral 308 denotes a power supply remote signal capable of controlling the output of the AC-DC converter. Reference numeral 309 denotes a power protection timer for ensuring that the power supply is stopped until a predetermined time elapses after the toggle switch 301 is operated to stop the power supply. A remote line 310 is capable of controlling the output of the AC-DC converter.

  The operator can turn on / off the image processing apparatus 100 by operating the toggle switch 301. The toggle type switch 301 is connected to the AC-DC converter when ON, and can control the energization state of the power source. When the power is OFF, the power supply of 306 must not be stopped until the controller 103 completes the system shutdown (end processing of the image processing apparatus 100). That is, the state of the toggle switch 301 is notified via the line 307, and the DC power supply 306 is turned off using the power remote signal 308 after the shutdown is completed. As described above, the power supply configuration of the image processing apparatus 100 is the same as the power supply configuration of a general device that needs to be shut down.

  The toggle type switch 301 is a switch that keeps mechanically holding either one of the ON / OFF states. The operator can input the power supply state by tilting the switch to either side of ON / OFF. The timer 309 measures the time in conjunction with the OFF of the toggle switch 301, changes the remote signal 310 after a certain time, and can forcibly turn off the output of the AC-DC converter 303. In other words, by measuring the time when the toggle switch 301 is turned off and turning off the AC-DC converter 303 after a certain time, the power supply has a function of completely turning off the apparatus power after a certain time.

  Further, the controller 103 can turn off its own power by using the power remote signal 308. In that case, in order to prevent inconsistency with the physical OFF / ON state of the toggle type switch 301, the controller 103, when notified of power OFF by 307, uses a solenoid or the like using an electromagnet. 301 can be automatically turned OFF.

That is, there are the following two methods for stopping the power supply to the “controller 103, printer device 104, and scanner device 102” that supply power from the power source shown in FIG.
(1) A method in which the controller 103 receives OFF of the switch 301 via 307, and powers down the “controller 103, printer device 104, scanner device 102” using the power remote signal 308 after shutdown.
(2) The timer 309 measures the OFF state of the switch 301 for a fixed time (120 s). A method of turning off the power of the “controller 103, printer device 104, scanner device 102” when the remote control signal 310 changes when the power supply remote signal 308 does not turn OFF during a predetermined time (120 s).
The above (2) is a power supply protection circuit for preventing the “controller 103, printer device 104, scanner device 102” from being turned off even when the toggle switch 301 is turned off.

<Processing flow at shutdown>
Next, a processing flow when the toggle switch 301 is turned off will be described with reference to FIG. Here, the operation when the operator ends the main body will be described. When detecting that the toggle switch 301 corresponding to the main body power switch is turned off, the CPU 201 executes the following processing. At this time, the timer 309 starts time measurement for the power protection circuit. The processing described below is realized by the CPU 201 reading out and executing a control program stored in the nonvolatile memory 205, the HDD 106, or the like into the memory 203.

  In step S <b> 401, when the toggle switch 301 is turned off, the CPU 201 displays a screen indicating that the system is being terminated on the operation unit 105. In step S <b> 402, the CPU 201 performs interruption / termination processing for the service currently being performed. Since the end processing is executed in parallel by a plurality of processes, the CPU 201 determines in step S403 whether the end processing has been completed. If completed, the process proceeds to S404, and if not completed, the determination of S403 is periodically repeated.

  In S404, the CPU 201 syncs the value of the memory to the storage (SYNC). Here, “sink (SYNC)” indicates a process of storing the contents of the buffer in the storage in order to synchronize the contents of the storage buffer cached on the DRAM with the storage, for example. In step S <b> 405, the CPU 201 calls a kernel shutdown I / F and performs a kernel software final termination process. Thereafter, in S406, the CPU 201 turns off the AC-DC converter 303 through the power remote signal 308 path, and the power of the entire apparatus is turned off. When the power supply of the entire apparatus is turned off, the power supply of the timer 309 itself is also turned off, and the power protection timer stops functioning.

  If the processing stops in any of the flowcharts shown in FIG. 4 due to some trouble, the controller 103 does not change the power remote signal 308. However, in that case, the power is forcibly turned off by the timer 309 using the remote control signal 310 to reduce the output of the AC-DC converter 303.

<Hibernation>
Next, the hibernation method used in the present embodiment will be described with reference to FIG. Hibernation refers to a function of storing the state immediately before turning off the power of the apparatus and restarting the operation from the state immediately before turning off the power when the power is turned on next time. Therefore, in order to use hibernation when the power is turned off, it is necessary to maintain a predetermined memory state (contents) when the power is turned off. A general kernel operating on the CPU 201 manages the memory 203 in “pages” for each fixed size. The page contains
A. Memory that can be discarded (memory that is not valid)
B. Memory that must not be discarded (effective memory)
There are two states.

  A is, for example, a page whose contents are known to be synchronized with an external disk while operating as a disk cache, or an unused memory. B is, for example, a cached change request to the external disk by the user but not yet synchronized, or the memory of the kernel itself. Since the memory of A may be discarded, only B must be stored as a hibernation target. In addition, some kernels may delete the memory in which zero is stored in all areas even if it is an effective memory. The effective memory determination unit 510 functions as a selection unit and determines such effective memory, but the determination conditions differ depending on the type and method of the kernel.

  In this embodiment, among 501-509, 501-503 and 505-506 are effective memories of B, and only the effective memory is stored in the disk using the hibernation method, and the image processing apparatus 100 is made the same by returning it. It can be returned to the state. There are two types of hibernation: those performed by BIOS and those controlled by software. In the former method, there is no means for limiting the effective memory, so it is necessary to save and restore the entire memory area. In recent years, the latter method is becoming mainstream, and since it operates inside the kernel, the hibernation process can be completed in a short time if only a necessary part of the memory is saved and restored. In recent years, the latter soft hibernation method (hereinafter referred to as soft hibernation in this embodiment) is often handled. Although the present embodiment will be described with a soft hibernation method, the present invention does not limit the hibernation method.

<Hibernation transfer process>
Next, with reference to FIG. 6, a description will be given of the transition process when the hibernation ends. Here, a description will be given using the example shown in FIG. The processing described below is realized by the CPU 201 reading out and executing a control program stored in the nonvolatile memory 205, the HDD 106, or the like into the memory 203.

  In step S <b> 601, when starting the hibernation transition process, the CPU 201 outputs a message indicating “system termination process in progress” to the operation unit 105. In step S <b> 602, the CPU 201 interrupts the hardware device driver that is currently operating in order to turn off the power to the board so that the board does not operate.

  In step S <b> 603, the CPU 201 sequentially reads 501 to 509 of the memory 203, and the effective memory determination unit 510 determines only the necessary memory. The effective memories in FIG. 5 are 501-503 and 505-506. In step S604, the CPU 201 generates valid memory page management information. In this embodiment, as indicated by reference numeral 511, the valid memory page management information includes information on the first block where valid memory is started and information on the number of blocks in which valid memory blocks are continuous. In addition to these two pieces of information, this management information may additionally include necessary information such as physical memory address, virtual memory address, memory usage, storage location, etc. as necessary. . As described above, the effective memory page management information in the present embodiment means management information for referring to the memory block saved in the storage in order to restore it to the main memory.

  In step S <b> 605, the CPU 201 stores the memory of 501 to 3 blocks in the flash disk 207 via the disk controller 206 according to the information indicated by 512, which is an element of the valid memory page management information. In step S606, the CPU 201 loops until all memory blocks listed in the valid memory page management information that need to be saved are saved. Data transfer such as 513 occurs in accordance with the memories 203 to 511.

  When the process of saving all the valid memories to the flash disk 207 is completed, the CPU 201 saves the valid memory page management information 511 itself in S607, and syncs all the memory values to the storage (flash disk 207) in S608. . Thereafter, the CPU 201 uses the power remote signal 308 to turn off the system.

<Secondary storage device>
Next, a memory map on the flash disk 207 as a secondary storage device will be described with reference to FIG. Reference numeral 701 denotes an MBR (Master Boot Record). Reference numeral 702 denotes a system loader. Reference numeral 703 denotes a logical partition group. Reference numeral 704 denotes an area created for hibernation, and includes a hibernation header 705, a data area 706, and valid memory page management information 707. Information included in the memories 501 to 503 and 505 to 506 is stored in the data area 706. Such a memory map is an example and is not intended to limit the present invention.

<Timing chart>
Hereinafter, a case 820 in which the hibernation transition process is normally performed and a case 810 in which the forced power cut-off of the CPU 201 occurs will be described with reference to FIG. First, the case 810 will be described. Reference numeral 801 denotes a count-up state of the power protection timer 309 in FIG. Reference numeral 802 denotes a voltage output of the AC-DC converter 303. Reference numeral 803 denotes the processing contents executed by the CPU 201 of FIG. The horizontal axis represents time, and the operation statuses 801 to 803 are described from the timing when the toggle switch 301 shown in 800 is turned off.

  When the operator turns off the toggle switch 301 at 800 points, the power protection timer 309 starts counting up for the purpose of protecting the power. In this embodiment, the measurement time of the power protection timer 309 is 120 seconds. That is, in the case of this embodiment, power off is guaranteed after 120 seconds.

  As indicated by reference numeral 803, the CPU 201 executes the system interruption process (hibernation transition process) described with reference to FIG. The power protection timer 309 measures 120 seconds for protecting the power. As shown in 803, when the system interruption process of the CPU 201 (Case 1) requires 120 seconds or more, the remote control signal 310 is turned OFF at the timing of 804, and the power supply to the AC-DC converter 303 of 802 is turned off. Stopped. As a result, the power of the controller 103 is turned off, and the power is forcibly turned off even though the CPU 201 is executing the hibernation process. Since hibernation writes the value of the memory to the storage and is turned off during storage access, there is a possibility of data corruption in the storage.

  The case 820 will be described. When the system interruption process of the CPU 201 (Case 2) is completed within 120 seconds, the shutdown 807 is executed, and after the hibernation process is completed as indicated by 806, the AC-DC converter 303 can be turned off spontaneously. The system ends normally.

The time required for the hibernation transition process includes a plurality of factors that fluctuate, and the fluctuation range is large. For example,
The amount of data subject to hibernation has increased significantly due to dirty memory 203. Temporary decrease in storage access speed when writing to data area 706.
Etc. are considered. Also, when the delay is an external device factor, the time required until actual access is not known, so it cannot be calculated in advance.

<Processing flow>
The present invention proposes a method of hibernation transition processing in a situation where the apparatus needs to be terminated within a certain period of time as described above. The processing flow and timing when the toggle switch 301 according to the present invention is turned off will be described below with reference to FIGS. 9 to 11. FIG. 9 shows a timing chart when executing the hibernation transition process in the present embodiment, and FIG. 11 shows a process flow of the hibernation transition process in the present embodiment. The processing described below is realized by the CPU 201 reading out and executing a control program stored in the nonvolatile memory 205, the HDD 106, or the like into the memory 203.

  Reference numeral 901 in FIG. 9 indicates the count-up state of the power protection timer 309. The vertical axis 902 is obtained by normalizing the progress of the total number of pages that need to be written to the data area 706 to 100 while the CPU 201 executes the processing of S606 to S607. That is, a graph is formed to show the progress of the storage process of data to be written in the data area 706.

  When the operator turns off the toggle switch 301, according to the present embodiment, the flowchart of 1101 in FIG. 11 is executed. In S1102, the CPU 201 activates a hibernation transition processing task (task for executing the flowchart of FIG. 6), and activates a system protection timer task (task for executing the flowchart 1121 of FIG. 11) in S1103. In step S1104, the CPU 201 activates a hibernation progress management task (task for executing the flowchart 1111 in FIG. 11) and ends the process. These three flowcharts are executed in parallel virtually on the CPU 201 by independent threads.

  As described above, the flowchart of FIG. 6 calculates all memory pages to be hibernated and sequentially writes them in the data area 706. When the writing is completed, a hibernation transition process for performing a shutdown is executed. The flowchart 1111 is executed by a task for managing the progress of hibernation that operates in parallel even during execution of the hibernation process. Specifically, it is monitored whether or not the flowchart of FIG. 6 is completed by the target time 909.

  First, a normal end case when the hibernation storing process (hibernation process) executed in the flowchart of FIG. 6 operates as indicated by the solid line 910 in FIG. 9 will be described with reference to the flowchart 1111. In step S <b> 1112, the CPU 201 waits for a certain period of time 903. Subsequently, in S1113, the CPU 201 acquires the elapsed time t (point on the horizontal axis in the graph 902) up to the present. In step S1114, the CPU 201 acquires the total number of pages in the memory page and the number of pages that have been completed.

In step S <b> 1115, the CPU 201 determines whether the memory page saving process for the current hibernation is completed by the target time 909. There are various calculation methods. For example, the calculation can be performed using the following expression.
(Expression 1) Progress = number of memory pages that have been written / number of memory pages that need to be written * 100
By the above equation 1, the vertical axis 902, that is, the progress [%] at the current time t with the completion of the writing process as 100% can be obtained.

Next, in S1116, whether or not the current progress is in time for the target time 909 is determined using the following conditional expression, for example.
(Formula 2) (Progress * Target time 909) / t> 100
By evaluating Equation 2, it is possible to determine whether or not the hibernation storage process is completed within the target time 909.

  In the case of the solid line 910, since it can be predicted that the progress will be made as indicated by the broken line 912, it is determined that the storage process for all pages can be completed by the target time 909, and the process returns to the wait process of S1112. The same evaluation is performed again after waiting in S1112. If such a loop process is repeated several times, if there is no problem, the progress state of the broken line 912 is changed, the storage is synced by the process of S608, the AC-DC converter 303 is turned off, and the board power is turned off. This is the normal case processing flow.

  Next, an end case of hibernation interruption in which the hibernation storing process of the flowchart of FIG. 6 operates as indicated by a solid line 911 will be described. S1112 to S1116 are executed as in the case of the solid line 910. As a result of the calculation of S1116, it can be predicted that the processing will not be completed by the target time 909 with the current progress rate. In step S1117, the CPU 201 interrupts the hibernation process in the flowchart of FIG. 6 and cares for information in the hibernation area 705 to 707 (for example, discards intermediate data). In step S1118, the CPU 201 functions as a power control unit, shuts down the system, and turns off the power. This is a shutdown operation 907 in FIG. 9, and the board power is turned off after the shutdown is completed, as indicated by 908.

  By implementing the present invention in this way, if the hibernation storing process is not completed within a predetermined time, the system can be terminated in a short time without waiting for the target time 909. Further, by appropriately setting the target time 909, even if the power supply source has a timer device configured to forcibly turn off the power outside, the risk of power being turned off during the hibernation operation is avoided. It becomes possible.

  However, this is a method that is effective when the process of the CPU 201 that performs the hibernation process is operating normally. On the other hand, there may be a case where the flowchart 1111 does not operate normally, or a case where a process executing hibernation is fixed at the timing 1003 shown in FIG. In such a case, the processing from S1116 to S1118 cannot be judged / executed and the power is forcibly turned off. Therefore, according to the present embodiment, a system is provided for causing the system protection timer task to end normally even in these abnormal states. Specific processing will be described with reference to the timing chart of FIG. 10 and the flowchart 1121 of FIG.

First, in step S <b> 1122, the CPU 201 sets the system protection timer 210. The time to set is
(Formula 3) Timer 210 hours <(Timer 309 hours-Shutdown 1005 hours)
And timer 210 hours> (target time 909 + shutdown 1005 hours)
And That is, the time (second time) set in the timer 210 is shorter than the time obtained by subtracting the time required for the shutdown process from the time (first time) set in the timer 309, and the time required for the shutdown process is the target time. It is set to be longer than the time added to 909. By setting in this way, even if an event is issued to the CPU 201 before the time of the timer 309 elapses and the shutdown process 1005 is performed after receiving the event, the control can be performed in time for the time of the power protection timer 309. It becomes. As described above, the set time of the timer 210 obtained by the condition of the above expression 3 is set in S1122.

  In step S1123, the CPU 201 determines whether an interrupt of the timer 210 has occurred. If not, the determination in S1123 is repeated periodically. On the other hand, if an interrupt occurs, the process proceeds to S1124. When the timer 210 expires at the timing of 1004 in FIG. 10, the process proceeds to S1124, where the CPU 201 functions as a forced termination means, performs a shutdown process 1005, and then powers down the board before the time of the power protection timer 309 expires. . By constructing this control in a system that operates in a privileged mode such as kernel mode or a process that is different from the process (software resource) that is executing hibernation, the normal termination processing of the system is executed with a stronger force. Is possible.

  According to the present embodiment, if hibernation is not performed, the system is cold booted at the next power-on. Therefore, it is not possible to return to the previous pre-end state, and it is possible to control the apparatus normally although the start-up time is reduced.

  As described above, according to the present embodiment, in an image processing apparatus having a timed timer that forcibly stops power supply from the outside when the toggle switch 301 is turned off, data storage of hibernation having a large time variation factor is stored. Processing can be performed safely. Further, when the data storage process is not in time, it is possible to give up in a minimum time, and it is possible to shorten the time (system end time) from the switch OFF until the power is actually turned off.

<Other embodiments>
The present invention can also be realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed.

  DESCRIPTION OF SYMBOLS 100: Image processing apparatus, 102: Scanner apparatus, 103: Controller, 104: Printer apparatus, 105: Operation part, 106: Hard disk, 107: FAX apparatus, 108: LAN, 109: Computer

The present invention relates to, for example, an image processing apparatus, a switch for inputting an instruction to turn on or off the state of the image processing apparatus, and an operation for turning off the state of the image processing apparatus to the switch. And processing means for performing processing for shifting to the OFF state in which the image processing apparatus keeps the information stored in the memory before turning OFF, and outputs power to the processing means. And forcibly stopping the output of power to the processing means after a first time has elapsed since an operation for turning off the state of the image processing apparatus is performed on the switch. And a stop unit that causes the image processing apparatus to be turned off until the second time shorter than the first time elapses after the operation for turning off the image processing apparatus is performed on the switch. If the sense is not completed, by generating an interrupt to the processing unit, and a interruption control means for starting the shutdown processing to suspend the processing to the processing unit.

Claims (8)

An image processing apparatus that forcibly stops power supply when a first time has elapsed after an operator operates the power switch to stop power supply,
Processing means for executing hibernation processing for saving the storage contents of the main memory used by the CPU of the image processing apparatus as a work area to the secondary storage device when the power supply to the image processing apparatus is stopped;
It is determined whether or not the hibernation process by the processing means is completed within a target time required to complete the hibernation process and the end process of the image processing apparatus before the first time elapses. A determination means;
When it is determined that the hibernation process is completed within the target time, after the hibernation process by the processing unit is completed, an end process of the image processing apparatus is executed to stop power supply, and the power supply is stopped within the target time. A power control unit configured to interrupt the hibernation process performed by the processing unit when the hibernation process is not completed, and to terminate the image processing apparatus and stop the power supply. Image processing device. The processing means includes
Selecting means for selecting a memory block for saving stored contents to the secondary storage device among a plurality of memory blocks of the main memory;
Generating means for generating management information indicating information of the memory block selected by the selecting means;
The image according to claim 1, further comprising: a saving unit that stores the storage contents of the memory block selected by the selection unit and the management information generated by the generation unit in the secondary storage device. Processing equipment.   The determination unit refers to the management information generated by the generation unit, and determines whether or not the hibernation process by the processing unit is completed within the target time. An image processing apparatus according to 1. A time measuring means for measuring an elapsed time after the power switch is operated by the operator so that the power supply is stopped;
When the second time shorter than the first time is timed by the time measuring means, the image processing apparatus further includes a forcible end means for forcibly stopping the power supply by executing a termination process of the image processing apparatus. The image processing apparatus according to any one of claims 1 to 3.   The second time is shorter than the time obtained by subtracting the time required for the end processing of the image processing device from the first time, and is longer than the time required for adding the time required for the end processing of the image processing device to the target time. The image processing apparatus according to claim 4, wherein the image processing apparatus is long.   The software resource for executing the processing of the time measuring means and the forced termination means is different from the software resource for executing the processing of the processing means, the determination means, and the power control means. The image processing apparatus according to 4 or 5. An image processing apparatus control method for forcibly stopping power supply when a first time has elapsed after an operator operates a power switch to stop power supply,
When the processing means stops supplying power to the image processing apparatus, a process of executing hibernation processing for saving the storage contents of the main storage memory used as a work area by the CPU of the image processing apparatus to a secondary storage device Steps,
Whether the determination unit completes the hibernation process in the processing step within a target time required to complete the hibernation process and the end process of the image processing apparatus before the first time elapses. A determination step for determining whether or not
When it is determined that the hibernation process is completed within the target time, the power control unit executes an end process of the image processing apparatus after the hibernation process in the processing step is completed to stop power supply, and When it is determined that the hibernation process is not completed within a target time, the hibernation process in the processing step is interrupted, and a power control step is executed to stop the power supply by executing an end process of the image processing apparatus A control method for an image processing apparatus.   The program for making a computer perform each step in the control method of the image processing apparatus of Claim 7.

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