JP2016072402A

JP2016072402A - Semiconductor device

Info

Publication number: JP2016072402A
Application number: JP2014199510A
Authority: JP
Inventors: 俊介福永; Shunsuke Fukunaga
Original assignee: Sanken Electric Co Ltd
Current assignee: Sanken Electric Co Ltd
Priority date: 2014-09-30
Filing date: 2014-09-30
Publication date: 2016-05-09

Abstract

PROBLEM TO BE SOLVED: To achieve a trench gate MOS in which electrodes have favorable connectivity inside a trench, and which does not cause deterioration in voltage withstanding and gains stable and favorable electrical characteristics.SOLUTION: In a trench gate MOS, by eliminating trench grooves arranged in a T-shape and performing layout of the trench grooves only by an L-shape and a straight line, an etching gas of silicon is prevented from locally remaining thereby to achieve a uniform silicon etching rate and a uniform depth of the trench groove. As a result, a trench gate MOS in which deterioration in voltage withstanding caused by a local increase in depth of the groove does not occur, and which has stable electrical characteristics owing to favorable connection of electrodes inside the trench.SELECTED DRAWING: Figure 4

Description

本発明は、トレンチ内部における電極の接続性が良く、安定して良好な電気特性が得られるトレンチゲート型ＭＯＳに関する。 The present invention relates to a trench gate type MOS having good electrode connectivity in a trench and stable and good electrical characteristics.

トレンチゲート型ＭＯＳはトレンチ内部にポリシリコンなどの材料で形成されたゲート電極、シールド電極などを有するが、トレンチ内部での電極の接続が悪いとエレクトロマイグレーションなどによる断線が生じ、安定して良好な電気特性が得られないといった問題があった。 A trench gate type MOS has a gate electrode, a shield electrode, etc. formed of a material such as polysilicon inside the trench, but if the connection of the electrode inside the trench is poor, disconnection due to electromigration or the like occurs, and it is stable and good. There was a problem that electrical characteristics could not be obtained.

特開２００２−８３９６３号公報JP 2002-83963 A

先行文献では、複数のストライプ形のトレンチ溝の中に、埋め込み電極およびゲート電極が埋め込まれ、トレンチ溝が端部でＴ字型になる構造の半導体素子が示されている。しかし、プラズマエッチング等でＴ時型のトレンチ溝をエッチングして形成した場合、Ｔ字部のトレンチ内部近傍にシリコンのエッチングガスが滞留し、ここに高密度にラジカルが発生し、局所的にシリコンのエッチングレートが早くなることでシリコンが深くエッチングされる領域ができ、これによって均一な厚みの電極を形成することが難しかった。電極の厚みが局所的に薄くなると、電極を良好に接続することが困難になるため、電気特性に変化が生じたり、また局所的にトレンチが深くなる部分があることで耐圧が低下するなど、安定した電気特性を有するトレンチゲート型ＭＯＳを得ることが困難であった。
The prior art shows a semiconductor element having a structure in which a buried electrode and a gate electrode are buried in a plurality of stripe-shaped trench grooves, and the trench groove has a T-shape at the end. However, when a T-type trench is etched by plasma etching or the like, a silicon etching gas stays in the vicinity of the inside of the T-shaped trench, radicals are generated at a high density, and silicon is locally generated. As a result of the higher etching rate, a region in which silicon is deeply etched is formed, which makes it difficult to form an electrode having a uniform thickness. When the thickness of the electrode is locally reduced, it becomes difficult to connect the electrode satisfactorily, resulting in a change in the electrical characteristics, and the breakdown voltage is reduced due to the locally deep trench, etc. It was difficult to obtain a trench gate type MOS having stable electrical characteristics.

本発明は上記問題点を解決し、トレンチ溝内部の電極が良好に接続され、かつ耐圧の低下がなく、安定した電気特性を有するトレンチゲート型ＭＯＳを得ることを目的とする。
An object of the present invention is to solve the above-mentioned problems and to obtain a trench gate type MOS having stable electrical characteristics in which electrodes inside the trench groove are well connected and the breakdown voltage is not lowered.

トレンチゲート型ＭＯＳのトレンチ溝のレイアウトにおいて、Ｔ字型のトレンチ溝を作らず、ガスの滞留が少なく、エッチングレートを均一にできるＬ字型および直線でレイアウトする。

In the trench groove layout of the trench gate type MOS, a T-shaped trench groove is not formed, and the L-shaped and straight lines are laid out so that the residence of gas is small and the etching rate is uniform.

本発明におけるトレンチ溝のレイアウトは、Ｔ字型のトレンチ溝を含まず、Ｌ字型トレンチ溝と直線トレンチ溝のみでレイアウトを行うため、シリコンのエッチングガスが局所的に滞留せず、均一なエッチングレートが得られることでトレンチ溝の深さが均一になり、トレンチ内部で電極を良好に接続することができ、安定した電気特性を有するトレンチゲート型ＭＯＳを得が得られる。また、本発明はトレンチゲート型ＭＯＳ以外のトレンチを有する半導体デバイスにも適用可能である
The trench groove layout according to the present invention does not include the T-shaped trench groove, and the layout is performed only by the L-shaped trench groove and the straight trench groove, so that the silicon etching gas does not stay locally and uniform etching is performed. By obtaining the rate, the depth of the trench becomes uniform, the electrodes can be connected well inside the trench, and a trench gate type MOS having stable electrical characteristics can be obtained. The present invention is also applicable to semiconductor devices having trenches other than trench gate type MOS.

本発明のトレンチゲート型ＭＯＳの断面図である。It is sectional drawing of the trench gate type MOS of this invention. 従来品のトレンチ溝の平面図である。It is a top view of the trench groove | channel of a conventional product. 本発明の実施例1に係る、レンチ溝の平面図である。FIG. 3 is a plan view of a wrench groove according to Example 1 of the present invention. 本発明の実施例２に係る、トレンチ溝の平面図である。It is a top view of a trench groove concerning Example 2 of the present invention.

以下、本発明の実施の形態となる構造について説明する。
Hereinafter, the structure which becomes embodiment of this invention is demonstrated.

図１、図３は、実施例１に係るトレンチゲート型ＭＯＳの断面図、平面図である。従来品の平面図である図２と比較して、本発明の実施例においてはレイアウト的にＴ字型のトレンチ溝がなく、長方形状にトレンチ溝が配置され、前記トレンチ溝の中には２つの分断されたゲート電極と、２つのゲート電極間に位置するシールド電極が具備される。このようにＴ字型のトレンチをなくすことで、シリコンのエッチングガスが局所的に滞留することがなくなり、均一なエッチングレートが得られることでトレンチ溝の深さが均一になり、トレンチ内部で電極を良好に接続でき、安定した電気特性を有するトレンチゲート型ＭＯＳが得られる。
長方形において、長さが長いトレンチ溝のトレンチ幅をa、長さが短いトレンチ溝のトレンチ幅をb、長いトレンチ溝間のシリコンの幅をｃとすると、c＞a、ｃ＞ｂの関係が好ましく、ｃは、１．４μｍ以上６．５μｍ以下、aおよびｂは１．２μｍ以上４μｍ以下であることが好ましい。また、aとｂは、ｂ≧aの関係を有し、さらに３≧b/a≧1の関係にあることが好ましい。
1 and 3 are a cross-sectional view and a plan view of a trench gate type MOS according to the first embodiment. Compared with FIG. 2 which is a plan view of a conventional product, in the embodiment of the present invention, there is no T-shaped trench groove in the layout, and the trench groove is arranged in a rectangular shape, and 2 in the trench groove. One divided gate electrode and a shield electrode positioned between the two gate electrodes are provided. By eliminating the T-shaped trench in this way, the silicon etching gas does not stay locally, and a uniform etching rate is obtained, so that the trench groove has a uniform depth, and an electrode is formed inside the trench. Can be connected well, and a trench gate type MOS having stable electrical characteristics can be obtained.
In a rectangle, if the trench width of a long trench groove is a, the trench width of a short trench groove is b, and the silicon width between long trench grooves is c, the relationship of c> a and c> b is satisfied. Preferably, c is from 1.4 μm to 6.5 μm, and a and b are from 1.2 μm to 4 μm. Further, a and b have a relationship of b ≧ a, and preferably 3 ≧ b / a ≧ 1.

図1、図4は、実施例２に係るトレンチゲート型ＭＯＳの断面図、平面図である。トレンチ溝はＬ字型トレンチ溝を含む、矩形波形状のトレンチ溝で構成されている。このようにＴ字型のトレンチをなくすことで、シリコンのエッチングガスが局所的に滞留することがなくなり、均一なエッチングレートが得られることでトレンチ溝の深さが均一になり、トレンチ内部で電極を良好に接続でき、安定した電気特性を有するトレンチゲート型ＭＯＳが得られる。
矩形波形状において、長さが長いほうのトレンチ溝の幅をa、長さが短いほうのトレンチ溝の幅をb、トレンチ溝間のシリコン領域の幅をｃとすると、c＞a、ｃ＞ｂの関係にあり、ｃは、１．４μｍ以上６．５μｍ以下、aおよびｂは１．２μｍ以上４μｍ以下であることが望ましい。また、aとｂは、ｂ≧aの関係を有し、３≧b/a≧1の関係にあることが望ましい。
1 and 4 are a sectional view and a plan view of a trench gate type MOS according to the second embodiment. The trench groove is formed of a rectangular wave-shaped trench groove including an L-shaped trench groove. By eliminating the T-shaped trench in this way, the silicon etching gas does not stay locally, and a uniform etching rate is obtained, so that the trench groove has a uniform depth, and an electrode is formed inside the trench. Can be connected well, and a trench gate type MOS having stable electrical characteristics can be obtained.
In the rectangular wave shape, if the width of the longer trench groove is a, the width of the shorter trench groove is b, and the width of the silicon region between the trench grooves is c, c> a, c> It is in the relation of b, c is preferably 1.4 μm or more and 6.5 μm or less, and a and b are preferably 1.2 μm or more and 4 μm or less. In addition, a and b have a relationship of b ≧ a, and desirably 3 ≧ b / a ≧ 1.

１０、半導体基板
２０、ドリフト層
３０、ベース層
４０、ソース層
５０、シールド電極
６０、ゲート電極
７０、絶縁膜
８０、ドレイン電極
９０、ソース電極
１００、トレンチ
10, semiconductor substrate 20, drift layer 30, base layer 40, source layer 50, shield electrode 60, gate electrode 70, insulating film 80, drain electrode 90, source electrode 100, trench

Claims

A trench groove formed on a semiconductor substrate has a layout of a combination of a straight line and an L shape, and has two divided gate electrodes and a shield electrode positioned between the gate electrodes in the trench groove. Trench gate type MOS.

The semiconductor device according to claim 1, wherein the trench groove has a rectangular shape.

The semiconductor device according to claim 1, wherein the trench groove has a rectangular wave shape.

In the trench having a rectangular shape, when the trench width of the longer trench is a and the trench width of the shorter trench is b, a and b have a relationship of b ≧ a, 3. The semiconductor device according to claim 2, wherein a relationship of 3 ≧ b / a ≧ 1 is satisfied.

In the trench having a rectangular wave shape, when the trench width of the longer trench is a and the trench width of the shorter trench is b, a and b have a relationship of b ≧ a. 4. The semiconductor device according to claim 3, wherein a relationship of 3 ≧ b / a ≧ 1 is satisfied.