JP2016062974A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a quantity of resin which covers a semiconductor chip.SOLUTION: A semiconductor device comprises: a semiconductor chip; a plurality of first leads which are arranged around the semiconductor chip and electrically connected to the semiconductor chip; a plurality of second leads which are arranged at positions farther from the first leads and link to the first leads; and a first resin which covers the semiconductor chip and partially covers the first leads. The plurality of first leads extend radially with respect to the semiconductor chip in plan view and project from lateral faces of the first resin in plan view, and each some of the plurality of second leads extend in parallel with each other in plan view.SELECTED DRAWING: Figure 2A

Description

  The present invention relates to a semiconductor device.

One type of semiconductor package (semiconductor device) is QFP (Quad Flat Package). Q
The FP is a thin plate semiconductor package in which a lead frame and a semiconductor chip (semiconductor element) are sealed with a resin. Leads (connecting terminals) of the lead frame are led out from each of the four sides of the semiconductor package. Leads derived from the semiconductor package are called outer leads, and leads inside the semiconductor package are called inner leads.

JP-A-5-251502

  The size of the portion covered with the resin is defined according to the size of the lead frame. In the case of the same type of semiconductor package, since the resin thickness is constant, the size of the portion covered with the resin is determined by the product of the vertical dimension of the resin and the horizontal dimension of the resin. Hereinafter, the product of the vertical dimension of the resin and the horizontal dimension of the resin is referred to as a body size. The body size usually includes the resin thickness, but is omitted here because the thickness is basically constant. As the body size increases, the amount of resin covering the semiconductor chip increases and the stress in the semiconductor package increases. When the stress in the semiconductor package is increased, the semiconductor chip and the resin may be peeled off in the reflow process when the semiconductor package is mounted. Therefore, if the amount of resin is large, the mounting rank of the semiconductor package (for example, the allowable days from unpacking the semiconductor package to the mounting, the reflow conditions, and the number of reflows) tends to be severe. Further, as the amount of resin covering the semiconductor chip increases, the weight of the semiconductor package increases.

  The present case provides a technique for reducing the amount of resin covering a semiconductor chip.

  A semiconductor device according to an aspect of the present invention includes a semiconductor chip, a plurality of first leads disposed around the semiconductor chip and electrically connected to the semiconductor chip, and a plurality of first leads from the semiconductor chip. A plurality of second leads connected to the plurality of first leads, and a first resin that covers the semiconductor chip and partially covers each of the first leads, The plurality of first leads extend radially with respect to the semiconductor chip in a plan view and protrude from the side surface of the first resin, and a part of the plurality of second leads is mutually in a plan view. Stretch in parallel.

  According to this case, the amount of resin covering the semiconductor chip can be reduced.

FIG. 1A is a diagram illustrating an example of a semiconductor package, and is a plan view of the semiconductor package. FIG. 1B is a diagram illustrating an example of a semiconductor package, and is a plan view of the semiconductor package. FIG. 1C is a diagram illustrating an example of a semiconductor package, and is a cross-sectional view of the semiconductor package. FIG. 2A is a diagram illustrating an example of the semiconductor package according to the first embodiment, and is a plan view of the semiconductor package. FIG. 2B is a diagram illustrating an example of the semiconductor package according to the first embodiment, and is a plan view of the semiconductor package. FIG. 2C is a diagram illustrating an example of the semiconductor package according to the first embodiment, and is a cross-sectional view of the semiconductor package. FIG. 3A is a diagram illustrating an example of a semiconductor package according to the second embodiment, and is a plan view of the semiconductor package. FIG. 3B is a diagram illustrating an example of the semiconductor package according to the second embodiment, and is a plan view of the semiconductor package. FIG. 3C is a diagram illustrating an example of the semiconductor package according to the second embodiment, and is a cross-sectional view of the semiconductor package. FIG. 4A is a diagram illustrating an example of a semiconductor package according to the second embodiment, and is a plan view of the semiconductor package. FIG. 4B is a diagram illustrating an example of the semiconductor package according to the second embodiment, and is a plan view of the semiconductor package. FIG. 4C is a diagram illustrating an example of the semiconductor package according to the second embodiment, and is a cross-sectional view of the semiconductor package. FIG. 5 is a diagram illustrating an example of a semiconductor package according to the second embodiment, and is a cross-sectional view of the semiconductor package. FIG. 6 is a diagram illustrating an example of a semiconductor package according to the second embodiment, and is a cross-sectional view of the semiconductor package. FIG. 7 is a view showing an example of a semiconductor package according to the third embodiment, and is a cross-sectional view of the semiconductor package. FIG. 8 is a diagram illustrating an example of a semiconductor package according to the third embodiment, and is a cross-sectional view of the semiconductor package. FIG. 9 is a diagram illustrating an example of a semiconductor package according to the fourth embodiment, and is a cross-sectional view of the semiconductor package.

  1A to 1C are diagrams illustrating an example of a semiconductor package 101. FIG. 1A and 1B are plan views of the semiconductor package 101, and FIG. 1C is a cross-sectional view of the semiconductor package 101. The semiconductor package 101 includes a semiconductor chip 102, a lead frame 103, a plurality of wires (fine metal wires) 104 and a resin 105. The lead frame 103 includes a stage 111, a plurality of support bars 112, a plurality of first leads 113, and a plurality of second leads 114. The semiconductor chip 102 is mounted on the stage 111 with the electrode surface of the semiconductor chip 102 facing upward (face up). The semiconductor chip 102 and the plurality of first leads 113 are electrically connected via a plurality of wires 104. For example, a plurality of electrode pads (not shown) of the semiconductor chip 102 and a plurality of first leads 113 are electrically connected via a plurality of wires 104.

Resin 105 covers semiconductor chip 102, each wire 104, stage 111, and each support bar 112. Resin 105 partially covers each first lead 113. The semiconductor chip 102 and the stage 111 are held at the center of the semiconductor package 101 by the resin 105 and the support bars 112. In FIG. 1A, illustration of each wire 104 and resin 105 is abbreviate | omitted, and the position of the side surface of resin 105 is shown by the thick line. In FIG. 1C, since each support bar 112 and each first lead 113 overlap each other, illustration of each support bar 112 is omitted. The plurality of first leads 113 and the plurality of second leads 114 are arranged around the semiconductor chip 102. The plurality of second leads 114 are arranged at positions farther from the semiconductor chip 102 than the positions of the plurality of first leads 113 in plan view. Each first lead 113 and each second lead 114 are connected. That is, each first lead 113 and each second lead 114 are integrally formed.

  As shown in FIGS. 1A to 1C, in the semiconductor package 101, the side surface portion of the resin 105 is located at the boundary portion between each first lead 113 and each second lead 114. Therefore, the amount of the resin 105 that covers the semiconductor chip 102 is increased.

  The semiconductor device according to the embodiment will be described below with reference to the drawings. The configuration of the semiconductor device shown below is an example, and the configuration of the semiconductor device according to the embodiment is not limited to the configuration shown below.

<First Embodiment>
2A to 2C are diagrams illustrating an example of the semiconductor package 1 according to the first embodiment. 2A and 2B are plan views of the semiconductor package 1, and FIG. 2C is a cross-sectional view of the semiconductor package 1. The semiconductor package 1 includes a semiconductor chip (semiconductor element) 2, a lead frame 3, a plurality of wires (metal thin wires) 4, and a resin 11. The lead frame 3 includes a stage 5, a plurality of support bars 6, a plurality of first leads 7, and a plurality of second leads 8. The semiconductor chip 2 is mounted on the stage 5 with the electrode surface of the semiconductor chip 2 facing upward (face up). The semiconductor chip 2 and the plurality of first leads 7 are electrically connected via a plurality of wires 4. For example, a plurality of electrode pads (not shown) of the semiconductor chip 2 and a plurality of first leads 7 are electrically connected via a plurality of wires 4. The semiconductor package 1 is an example of a semiconductor device. The resin 11 is an example of a first resin.

  Resin 11 covers semiconductor chip 2, each wire 4, stage 5, and each support bar 6. Resin 11 partially covers each first lead 7. The resin 11 covers the semiconductor chip 2 and each wire 4, and the resin 11 partially covers each first lead 7, whereby the semiconductor chip 2 and each wire 4 are protected by the resin 11. A connection portion with each first lead 7 is protected by the resin 11. The semiconductor chip 2 and the stage 5 are held at the center of the semiconductor package 1 by the support bars 6 and the resin 11. In FIG. 2A, illustration of each wire 4 and resin 11 is abbreviate | omitted, and the position of the side surface of resin 11 is shown by the thick line. In FIG. 2C, each support bar 6 and each first lead 7 overlap each other, and therefore the illustration of each support bar 6 is omitted.

  The plurality of first leads 7 and the plurality of second leads 8 are arranged around the semiconductor chip 2. The plurality of second leads 8 are arranged at positions farther from the semiconductor chip 2 than the positions of the plurality of first leads 7 in plan view. Each first lead 7 and each second lead 8 are connected. That is, each first lead 7 and each second lead 8 are integrally formed.

  The plurality of first leads 7 extend radially with respect to the semiconductor chip 2 in plan view. The first end of each first lead 7 is directed to the semiconductor chip 2, and the semiconductor chip 2 and the first end of each first lead 7 are connected by each wire 4. The second end of each first lead 7 is connected to the first end of each second lead 8. The second end of each second lead 8 is bent in a so-called gull wing shape, and the tip of the second end of each second lead 8 is a substrate (for example, a printed circuit board) on which the semiconductor package 1 is mounted. Connected to the electrode.

Some of the plurality of second leads 8 extend in parallel with each other in plan view. As shown in FIGS. 2A and 2B, for example, some of the plurality of second leads 8 (second leads 8A to 8I) extend in parallel with each other in plan view. The width of each first lead 7 increases from the first end of each first lead 7 toward the second end of each first lead 7. That is, the width of each first lead 7 becomes wider in the direction away from the semiconductor chip 2. Each first lead 7 may be bent in plan view. Each first lead 7 may be curved in a plan view. The width of each second lead 8 is the same from the first end of each second lead 8 to the second end of each second lead 8. The width and pitch of each second lead 8 are basically larger than the width and pitch of the first end of each first lead 7.

  As shown in FIGS. 2A and 2B, the side surface of the resin 11 is located at a position approaching the semiconductor chip 2 from the boundary portion between each first lead 7 and each second lead 8 in plan view. Therefore, the plurality of first leads 7 protrude from the side surface of the resin 11. That is, a part of each first lead 7 exists in the resin 11, and a part of each first lead 7 protrudes from the side surface of the resin 11. 2A to 2C, dotted lines indicate the outer shape of the resin 105 included in the semiconductor package 101 illustrated in FIGS. 1A to 1C. Compared to the semiconductor package 101 shown in FIGS. 1A to 1C, the semiconductor package 1 has a reduced amount of resin 11 covering the semiconductor chip 2 and a reduced body size. Since the amount of the resin 11 covering the semiconductor chip 2 is reduced, the stress in the semiconductor package 1 is reduced. Therefore, in the reflow process when the semiconductor package 1 is mounted, the separation between the semiconductor chip 2 and the resin 11 is suppressed. As a result, the mounting rank of the semiconductor package 1 (for example, the allowable days from unpacking the semiconductor package 1 to the mounting, the reflow conditions, and the number of reflows) is improved. Further, since the amount of the resin 11 covering the semiconductor chip 2 is reduced, the weight of the semiconductor package 1 is reduced as compared with the semiconductor package 101 shown in FIGS. 1A to 1C.

  The resin 11 may have a plurality of through holes. Each through hole of the resin 11 passes through the resin 11 in the thickness direction of the resin 11. Each through hole of the resin 11 is disposed between the adjacent first leads 7 in a plan view, for example. Each through hole of the resin 11 may have a rectangular shape or a circular shape in plan view, or may have another shape. Since the resin 11 has a plurality of through holes, the amount of the resin 11 covering the semiconductor chip 2 is further reduced, so that the weight of the semiconductor package 1 is further reduced as compared with the semiconductor package 101 shown in FIGS. 1A to 1C. To do. Further, when the resin 11 has a plurality of through holes, a portion where the resin 11 is present and a portion where the resin 11 is not present may be alternated when viewed from the side surface of the semiconductor package 1. Furthermore, the film thickness of the upper part of the resin 11 and the film thickness of the lower part of the resin 11 may be the same or different. The film thickness of the upper portion of the resin 11 is, for example, the film thickness of the resin 11 formed on the first lead 7. The film thickness of the lower part of the resin 11 is, for example, the film thickness of the resin 11 formed under the first lead 7.

Second Embodiment
3A to 3C are diagrams illustrating an example of the semiconductor package 1 according to the second embodiment. 3A and 3B are plan views of the semiconductor package 1, and FIG. 3C is a cross-sectional view of the semiconductor package 1. The semiconductor package 1 includes a semiconductor chip 2, a lead frame 3, a plurality of wires 4, and resins 11 and 12. The lead frame 3 includes a stage 5, a plurality of support bars 6, a plurality of first leads 7, and a plurality of second leads 8. The semiconductor chip 2, the lead frame 3, each wire 4, the stage 5, each support bar 6, each first lead 7, and each second lead 8 are the same as in the first embodiment. In FIG. 3A, illustration of each wire 4 and resin 11 and 12 is abbreviate | omitted, and the position of each side surface of resin 11 and 12 is shown by the thick line. In FIG. 3C, each support bar 6 and each first lead 7 overlap each other, and therefore the illustration of each support bar 6 is omitted. 3A to 3C, dotted lines indicate the outer shape of the resin 105 included in the semiconductor package 101 illustrated in FIGS. 1A to 1C.

The width of each first lead 7 becomes narrower as it approaches the semiconductor chip 2. If the position of the side surface of the resin 11 is too close to the semiconductor chip 2, each first lead 7 is bent without being able to support the weight of the resin 11. When each first lead 7 bends, the resin 11 sinks. Therefore, when the semiconductor package 1 is mounted on the substrate, the resin 11 may come into contact with the substrate, or each second lead 8 may float from the substrate, causing a contact failure. Therefore, in the second embodiment, the resin 12 is arranged around the resin 11, and the first leads 7 protruding from the side surfaces of the resin 11 are fixed by the resin 12. That is, the first leads 7 outside the outer shape of the resin 11 are fixed by the resin 12. Thereby, the bending of each first lead 7 is suppressed, and the sinking of the resin 11 can be suppressed. The resin 12 is an example of a second resin.

  The resin 12 is disposed around the resin 11 in a plan view, and is disposed at a position approaching the semiconductor chip 2 from a boundary portion between each first lead 7 and each second lead 8. Further, the resin 12 may be disposed so as to overlap with a boundary portion between each first lead 7 and each second lead 8 in a plan view. That is, the resin 12 may cover the boundary portion between each first lead 7 and each second lead 8. The resin 11 and the resin 12 are arranged in a separated state, and the resin 11 and the resin 12 are not connected.

  The resin 12 covers each first lead 7 so as to surround the periphery of the resin 11 in plan view. Therefore, the first leads 7 protruding from the side surfaces of the resin 11 are connected by the resin 12, whereby the first leads 7 protruding from the side surfaces of the resin 11 are fixed by the resin 12. 3A to 3C show an example in which each support bar 6 extends to a portion where the resin 12 is disposed. The second embodiment is not limited to the example shown in FIGS. 3A to 3C. Each support bar 6 may not extend to a portion where the resin 12 is disposed. A plurality of resins 12 may be disposed around the resin 11 in a plan view. For example, a plurality of resins 12 may be arranged so as to surround the resin 11 and the first leads 7 protruding from the side surface of the resin 11 may be connected by the plurality of resins 12. In this case, the plurality of resins 12 are separated from each other, and the plurality of resins 12 are not connected to each other.

  The resin 11 and the resin 12 may be connected in a lattice shape. For example, the resin 12 may have a plurality of protrusions toward the semiconductor chip 2, and the resin 11 and the resin 12 may be connected by the protrusions of the resin 12. For example, the resin 11 may have a plurality of protrusions in the direction away from the semiconductor chip 2, and the resin 11 and the resin 12 may be connected by the protrusions of the resin 11. In this case, a plurality of holes are opened between the resin 11 and the resin 12 in plan view. Each hole may have a rectangular shape or a circular shape in plan view, or may have another shape.

  The resin 11 may have a plurality of through holes. Each through hole of the resin 11 is the same as each through hole of the resin 11 in the first embodiment. The resin 12 may have a plurality of through holes. Each through hole of the resin 12 passes through the resin 12 in the thickness direction of the resin 12. Each through hole of the resin 12 is disposed between the adjacent first leads 7 in plan view. Each through hole of the resin 12 may have a rectangular shape or a circular shape in plan view, or may have another shape. Since the resin 12 has a plurality of through holes, the amount of the resin 12 is reduced. Further, when the resin 12 has a plurality of through holes, the portion where the resin 12 exists and the portion where the resin 12 does not exist may be alternated when viewed from the side surface of the semiconductor package 1. Furthermore, the film thickness of the upper part of the resin 11 and the film thickness of the lower part of the resin 11 may be the same or different. The film thickness of the upper part of the resin 12 and the film thickness of the lower part of the resin 12 may be the same or different. The film thickness of the upper part of the resin 12 is, for example, the film thickness of the resin 12 formed on the first lead 7. The film thickness of the lower part of the resin 12 is, for example, the film thickness of the resin 12 formed under the first lead 7.

As shown in FIGS. 4A to 4C, the resin 13 may be disposed outside the resin 12. 4A, 4B, and 4C are diagrams illustrating an example of the semiconductor package 1 according to the second embodiment. 4A to 4C are diagrams illustrating an example in which two stages of resins 12 and 13 are arranged around the resin 11. 4A and 4B are plan views of the semiconductor package 1, and FIG. 4C is a cross-sectional view of the semiconductor package 1. In FIG. 4A, illustration of each wire 4 and resin 11-13 is abbreviate | omitted, and the position of each side surface of resin 11-13 is shown by the thick line. In FIG. 4C, since each support bar 6 and each first lead 7 overlap, illustration of each support bar 6 is omitted. In FIG. 4C, a dotted line shows the outer shape of the resin 105 provided in the semiconductor package 101 shown in FIGS. 1A to 1C.

  Resins 12 and 13 cover the first leads 7 so as to surround the periphery of the resin 11. Accordingly, the first leads 7 protruding from the side surfaces of the resin 11 are connected by the resins 12 and 13, whereby the first leads 7 protruding from the side surfaces of the resin 11 are fixed by the resins 12 and 13. The resin 13 covers each first lead 7 so as to surround the periphery of the resin 12. Therefore, the resin 12 is disposed between the resin 11 and the resin 13. The interval between the resin 12 and the resin 13 may be the same as or different from the interval between the resin 11 and the resin 12.

  The resin 13 is disposed around the resin 12 in a plan view, and is disposed at a position approaching the semiconductor chip 2 from a boundary portion between each first lead 7 and each second lead 8. Further, the resin 13 may be arranged so as to overlap with a boundary portion between each first lead 7 and each second lead 8 in a plan view. That is, the resin 13 may cover the boundary portion between each first lead 7 and each second lead 8.

  Each of the resins 12 and 13 covers each first lead 7 so as to surround the periphery of the resin 11 in a plan view. Accordingly, the first leads 7 protruding from the side surfaces of the resin 11 are connected by the resins 12 and 13, whereby the first leads 7 protruding from the side surfaces of the resin 11 are fixed by the resins 12 and 13. The resin 11 and the resin 12 are arranged in a separated state, and the resin 11 and the resin 12 may not be connected. Further, similarly to the first embodiment, the resin 11 and the resin 12 may be connected in a lattice shape. The resin 12 and the resin 13 are arranged in a separated state, and the resin 12 and the resin 13 may not be connected. Further, the resin 12 and the resin 13 may be connected in a lattice shape. 4A to 4C show an example in which each support bar 6 extends to a portion where the resins 12 and 13 are arranged. The second embodiment is not limited to the examples shown in FIGS. 4A to 4C. Each support bar 6 may not extend to a portion where the resins 12 and 13 are disposed. Further, three or more stages of resins may be arranged around the resin 11.

  The resin 11 may have a plurality of through holes. Each through hole of the resin 11 is the same as each through hole of the resin 11 in the first embodiment. The resin 12 may have a plurality of through holes. The resin 13 may have a plurality of through holes. Each through hole of the resin 13 passes through the resin 13 in the thickness direction of the resin 13. Each through hole of the resin 13 is disposed between the adjacent first leads 7 in plan view. Each through hole of the resin 13 may have a rectangular shape or a circular shape in plan view, or may have another shape. Since the resin 13 has a plurality of through holes, the amount of the resin 13 is reduced. Further, when the resin 13 has a plurality of through holes, the portion where the resin 13 exists and the portion where the resin 13 does not exist may be alternated when viewed from the side surface of the semiconductor package 1. Furthermore, the film thickness of the upper part of the resin 11 and the film thickness of the lower part of the resin 11 may be the same or different. The film thickness of the upper part of the resin 12 and the film thickness of the lower part of the resin 12 may be the same or different. The film thickness of the upper part of the resin 13 and the film thickness of the lower part of the resin 13 may be the same or different. The film thickness of the upper portion of the resin 13 is, for example, the film thickness of the resin 13 formed on the first lead 7. The film thickness of the lower part of the resin 13 is, for example, the film thickness of the resin 13 formed under the first lead 7.

  3A to 3C show an example in which the thickness of the resin 11 and the thickness of the resin 12 are approximately the same. The second embodiment is not limited to the example shown in FIGS. 3A to 3C. The thickness of the resin 11 and the thickness of the resin 12 may be different. For example, as shown in FIG. 5, the resin 12 may be thinner than the resin 11. FIG. 5 is a diagram illustrating an example of the semiconductor package 1 according to the second embodiment. FIG. 5 is a cross-sectional view of the semiconductor package 1. In FIG. 5, since each support bar 6 and each first lead 7 overlap each other, illustration of each support bar 6 is omitted. In FIG. 5, the dotted line indicates the outer shape of the resin 105 included in the semiconductor package 101 illustrated in FIGS. 1A to 1C.

  4A to 4C show examples in which the thickness of the resin 11 and the thicknesses of the resins 12 and 13 are approximately the same. The second embodiment is not limited to the examples shown in FIGS. 4A to 4C. The thickness of the resin 11 and the thicknesses of the resins 12 and 13 may be different. For example, as shown in FIG. 6, each of the resins 12 and 13 may be thinner than the resin 11. The thickness of the resin 12 and the thickness of the resin 13 may be different. FIG. 6 is a diagram illustrating an example of the semiconductor package 1 according to the second embodiment. FIG. 6 is a cross-sectional view of the semiconductor package 1. In FIG. 6, each support bar 6 and each first lead 7 overlap each other, and therefore each support bar 6 is not shown. In FIG. 6, the dotted line indicates the outer shape of the resin 105 included in the semiconductor package 101 illustrated in FIGS. 1A to 1C.

<Third Embodiment>
FIG. 7 is a diagram illustrating an example of the semiconductor package 1 according to the third embodiment. FIG. 7 is a cross-sectional view of the semiconductor package 1. The semiconductor package 1 includes a semiconductor chip 2, a lead frame 3, a plurality of wires 4, and resins 11, 12, and 14. The lead frame 3 includes a stage 5, a plurality of support bars 6, a plurality of first leads 7, and a plurality of second leads 8. The semiconductor chip 2, the lead frame 3, each wire 4, the stage 5, each support bar 6, each first lead 7, and each second lead 8 are the same as in the first embodiment. In FIG. 7, each support bar 6 and each first lead 7 overlap each other, and therefore the illustration of each support bar 6 is omitted. In FIG. 7, the dotted line indicates the outer shape of the resin 105 included in the semiconductor package 101 illustrated in FIGS. 1A to 1C.

  A resin 14 is disposed between the resin 11 and the resin 12. Accordingly, the resin 14 is disposed around the resin 11 in a plan view and is disposed at a position approaching the semiconductor chip 2 from the boundary portion between each first lead 7 and each second lead 8. The resin 14 partially covers each first lead. Resin 11 and resin 12 are connected by resin 14. Therefore, the resins 11, 12, and 14 are integrally formed. The thickness of the resin 14 is different from the thickness of each of the resins 11 and 12. For example, as shown in FIG. 7, the thickness of the resin 14 may be smaller than the thickness of each of the resins 11 and 12. The thickness of the resin 11 and the thickness of the resin 12 may be the same or different. For example, the resin 12 may be thinner than the resin 11. The resin 14 is an example of a third resin.

  The integrally formed resins 11, 12, and 14 are referred to as a resin 21 in the third embodiment. Therefore, the resin 21 covers the semiconductor chip 2, the wires 4, the stage 5, and the support bars 6. Resin 21 partially covers each first lead. The side surface of the resin 21 is located at a position approaching the semiconductor chip 2 from a boundary portion between each first lead 7 and each second lead 8 in plan view. Therefore, the plurality of first leads 7 protrude from the side surface of the resin 21. That is, a part of each first lead 7 exists in the resin 21, and a part of each first lead 7 protrudes from the side surface of the resin 21. Further, the side surface of the resin 21 may overlap with a boundary portion between each first lead 7 and each second lead 8 in a plan view. That is, the resin 21 may cover the boundary portion between each first lead 7 and each second lead 8.

  The resin 21 has a recess 31 around the semiconductor chip 2. The resin 21 may have a recess 31 so as to surround the semiconductor chip 2. A recess 31 may be formed on the upper surface of the resin 21. A recess 31 may be formed on the lower surface of the resin 21. Concave portions 31 may be formed on the upper and lower surfaces of the resin 21. Compared with the semiconductor package 101 shown in FIGS. 1A to 1C, the amount of the resin 21 covering the semiconductor chip 2 is reduced in the semiconductor package 1 shown in FIG. 7.

  The resin 11 may have a plurality of through holes. Each through hole of the resin 11 is the same as each through hole of the resin 11 in the first embodiment. The resin 12 may have a plurality of through holes. The through holes of the resin 12 are the same as the through holes of the resin 12 in the second embodiment. The resin 14 may have a plurality of through holes. Each through hole of the resin 14 passes through the resin 14. Each through hole of the resin 14 is disposed between the adjacent first leads 7 in plan view. Each through hole of the resin 14 may have a rectangular shape or a circular shape in plan view, or may have another shape. Since the resin 14 has a plurality of through holes, the amount of the resin 14 is reduced. Therefore, as compared with the semiconductor package 101 shown in FIGS. 1A to 1C, the amount of the resin 21 covering the semiconductor chip 2 is further reduced in the semiconductor package 1 shown in FIG.

  FIG. 8 is a diagram illustrating an example of the semiconductor package 1 according to the third embodiment. FIG. 8 is a cross-sectional view of the semiconductor package 1. The semiconductor package 1 includes a semiconductor chip 2, a lead frame 3, a plurality of wires 4, and resins 11 to 15. The lead frame 3 includes a stage 5, a plurality of support bars 6, a plurality of first leads 7, and a plurality of second leads 8. The semiconductor chip 2, the lead frame 3, each wire 4, the stage 5, each support bar 6, each first lead 7, and each second lead 8 are the same as in the first embodiment. In FIG. 8, each support bar 6 and each first lead 7 overlap each other, and therefore each support bar 6 is not shown. In FIG. 8, the dotted line indicates the outer shape of the resin 105 included in the semiconductor package 101 illustrated in FIGS. 1A to 1C.

  A resin 14 is disposed between the resin 11 and the resin 12, and a resin 15 is disposed between the resin 12 and the resin 13. Accordingly, the resins 14 and 15 are arranged around the resin 11 in a plan view and are arranged at positions approaching the semiconductor chip 2 from the boundary portions between the first leads 7 and the second leads 8. Yes. Resins 14 and 15 partially cover each first lead 7. Resin 11 and resin 12 are connected by resin 14, and resin 12 and resin 13 are connected by resin 15. Therefore, the resins 11 to 15 are integrally formed. The thickness of the resin 14 is different from the thickness of each of the resins 11 and 12. For example, as shown in FIG. 8, the thickness of the resin 14 may be smaller than the thickness of each of the resins 11 and 12. The thickness of the resin 15 is different from the thickness of each of the resins 12 and 13. For example, as shown in FIG. 8, the thickness of the resin 15 may be smaller than the thickness of each of the resins 12 and 13. The thicknesses of the resins 11 to 13 may be different from each other. For example, the thickness of each of the resins 12 and 13 may be smaller than the thickness of the resin 11.

  Hereinafter, the integrally formed resins 11 to 15 are referred to as a resin 22. Therefore, the resin 22 covers the semiconductor chip 2, the wires 4, the stage 5, and the support bars 6. Resin 22 partially covers each first lead 7. The side surface of the resin 22 is located at a position approaching the semiconductor chip 2 from the boundary portion between each first lead 7 and each second lead 8 in plan view. Therefore, the plurality of first leads 7 protrude from the side surface of the resin 22. That is, a part of each first lead 7 exists in the resin 22, and a part of each first lead 7 protrudes from the side surface of the resin 22. Further, the side surface of the resin 22 may overlap with a boundary portion between each first lead 7 and each second lead 8 in a plan view. That is, the resin 22 may cover the boundary portion between each first lead 7 and each second lead 8.

  The resin 22 has recesses 32 and 33 around the semiconductor chip 2. The resin 22 may have recesses 32 and 33 so as to surround the semiconductor chip 2. Concave portions 32 and 33 may be formed on the upper surface of the resin 22. A plurality of recesses 32 and a plurality of recesses 33 may be formed on the upper surface of the resin 22. Concave portions 32 and 33 may be formed on the lower surface of the resin 22. A plurality of recesses 32 and a plurality of recesses 33 may be formed on the lower surface of the resin 22. Concave portions 32 and 33 may be formed on the upper and lower surfaces of the resin 22. A plurality of recesses 32 and a plurality of recesses 33 may be formed on the upper and lower surfaces of the resin 22. Compared with the semiconductor package 101 shown in FIGS. 1A to 1C, the amount of the resin 22 covering the semiconductor chip 2 is reduced in the semiconductor package 1 shown in FIG. 8. As a result, the weight of the semiconductor package 1 shown in FIG. 8 is reduced as compared with the semiconductor package 101 shown in FIGS. 1A to 1C. When viewed from the side surface of the semiconductor package 1, the portion where the resin 11 exists and the portion where the resin 11 does not exist may be alternated. Furthermore, the film thickness of the upper part of the resin 11 and the film thickness of the lower part of the resin 11 may be the same or different. The film thickness of the upper part of the resin 12 and the film thickness of the lower part of the resin 12 may be the same or different. The film thickness of the upper part of the resin 13 and the film thickness of the lower part of the resin 13 may be the same or different.

  The resin 11 may have a plurality of through holes. Each through hole of the resin 11 is the same as each through hole of the resin 11 in the first embodiment. The resin 12 may have a plurality of through holes. The through holes of the resin 12 are the same as the through holes of the resin 12 in the second embodiment. The resin 13 may have a plurality of through holes. The through holes of the resin 13 are the same as the through holes of the resin 12 in the second embodiment. The resin 14 may have a plurality of through holes. The resin 15 may have a plurality of through holes. Each through hole of the resin 15 passes through the resin 15. Each through hole of the resin 15 is disposed between the adjacent first leads 7 in plan view. Each through hole of the resin 15 may have a rectangular shape or a circular shape in plan view, or may have another shape. Since the resin 15 has a plurality of through holes, the amount of the resin 15 is reduced. Therefore, as compared with the semiconductor package 101 shown in FIGS. 1A to 1C, the amount of the resin 22 covering the semiconductor chip 2 is further reduced in the semiconductor package 1 shown in FIG. As a result, the weight of the semiconductor package 1 shown in FIG. 8 is further reduced as compared with the semiconductor package 101 shown in FIGS. 1A to 1C.

<Fourth embodiment>
FIG. 9 is a diagram illustrating an example of the semiconductor package 1 according to the fourth embodiment. FIG. 9 is a cross-sectional view of the semiconductor package 1. The semiconductor package 1 includes a semiconductor chip 2, a lead frame 3, a plurality of wires 4, and resins 11 and 16. The lead frame 3 includes a stage 5, a plurality of support bars 6, a plurality of first leads 7, and a plurality of second leads 8. The semiconductor chip 2, the lead frame 3, each wire 4, the stage 5, each support bar 6, each first lead 7, and each second lead 8 are the same as in the first embodiment. In FIG. 9, each support bar 6 and each first lead 7 overlap each other, and therefore each support bar 6 is not shown. In FIG. 9, the dotted line indicates the outer shape of the resin 105 included in the semiconductor package 101 illustrated in FIGS. 1A to 1C.

Resin 11 covers semiconductor chip 2, each wire 4, stage 5, and each support bar 6. Resin 11 partially covers each first lead 7. The side surface of the resin 11 is located at a position approaching the semiconductor chip 2 from the boundary portion between each first lead 7 and each second lead 8 in plan view. Resin 16 partially covers each first lead 7. Therefore, the plurality of first leads 7 protrude from the side surface of the resin 11, and the resin 16 covers the portions of the plurality of first leads 7 protruding from the side surface of the resin 11. That is, a part of each first lead 7 exists in the resin 11 and a part of each first lead 7 exists in the resin 16. The resin 16 is arranged around the resin 11 and connected to the resin 11. Therefore, the resins 11 and 16 are integrally formed. The thickness of the resin 11 is different from the thickness of the resin 16. In FIG.
The thickness of the resin 16 is thinner than the thickness of the resin 11. Therefore, compared to the semiconductor package 101 shown in FIGS. 1A to 1C, the total resin amount of the resins 11 and 16 covering the semiconductor chip 2 is reduced in the semiconductor package 1 shown in FIG. As a result, the weight of the semiconductor package 1 shown in FIG. 9 is reduced as compared with the semiconductor package 101 shown in FIGS. 1A to 1C. The resin 16 is an example of a fourth resin.

  For example, the resin 11 covers the connection portion between each wire 4 and each first lead 7, and the resin 16 partially covers each first lead 7 outside the connection portion between each wire 4 and each first lead 7. May be covered. The side surface of the resin 16 is located farther from the semiconductor chip 2 than the position of the side surface of the resin 11 in plan view. The side surface of the resin 16 may be at a position approaching the semiconductor chip 2 from the boundary portion between each first lead 7 and each second lead 8 in plan view.

  The resin 11 may have a plurality of through holes. Each through hole of the resin 11 is the same as each through hole of the resin 11 in the first embodiment. The resin 16 may have a plurality of through holes. Each through hole of the resin 16 is disposed between the adjacent first leads 7 in a plan view, for example. Each through hole of the resin 16 may have a rectangular shape or a circular shape in plan view, or may have another shape. Since the resin 16 has a plurality of through holes, the amount of the resin 16 is reduced. As a result, the weight of the semiconductor package 1 shown in FIG. 9 is further reduced as compared with the semiconductor package 101 shown in FIGS. 1A to 1C. Moreover, the film thickness of the upper part of the resin 11 and the film thickness of the lower part of the resin 11 may be the same or different. The film thickness of the upper part of the resin 16 and the film thickness of the lower part of the resin 16 may be the same or different. The film thickness of the upper portion of the resin 16 is, for example, the film thickness of the resin 16 formed on the first lead 7. The film thickness of the lower part of the resin 16 is, for example, the film thickness of the resin 16 formed under the first lead 7.

  According to the second to fourth embodiments, as in the first embodiment, the amount of the resin 11 covering the semiconductor chip 2 is reduced, so that the stress in the semiconductor package 1 is reduced. Therefore, in the reflow process when the semiconductor package 1 is mounted, the separation between the semiconductor chip 2 and the resin 11 is suppressed. As a result, the mounting rank of the semiconductor package 1 is improved. Further, since the amount of the resin 11 covering the semiconductor chip 2 is reduced, the weight of the semiconductor package 1 is reduced as compared with the semiconductor package 101 shown in FIGS. 1A to 1C. According to the first to fourth embodiments, since the lead frame 3 is not changed, the semiconductor package 1 can be mounted on the substrate without changing the substrate on which the semiconductor package 1 is mounted.

<Resin formation method>
A method for forming the resins 11 to 16, 21, and 22 will be described. Resins 11 to 16, 21, and 22 are formed by performing resin sealing by a transfer molding method or a compression molding method. In the transfer molding method, the semiconductor chip 2, the lead frame 3, each wire 4, the stage 5, and each support bar 6 are placed in a mold, and a sealing resin is put into the mold from a hole formed in the mold. The resin sealing is performed by injecting and performing heat treatment. By combining the upper mold and the lower mold, one mold is obtained. The sealing resin is, for example, a thermosetting epoxy resin. In the transfer molding method, a sealing resin is injected into the mold by applying pressure, so that the upper and lower surfaces of each first lead 7 can be simultaneously resin-sealed, corresponding to various types of molds. be able to.

When the resins 11 and 12 in the second embodiment are formed by the transfer molding method, the resin 11 and the resin 12 are connected. The resin 11 and the resin 12 can be separated by cutting or polishing the resin where the resin 11 and the resin 12 are connected. For example, when the resin of the part where the resin 11 and the resin 12 are connected is formed on each support bar 6, the resin of the part where the resin 11 and the resin 12 are connected may be cut together with the support bars 6. it can. Resin 11 is formed by injecting a sealing resin into the mold from the upper part of the mold, and forming resin 12 by injecting a sealing resin into the mold from the lower part of the mold. And resin 12 may be formed separately.

  Also in the case of forming the resins 11 to 13 in the second embodiment, by cutting or polishing the resin in the portion where the resin 11 and the resin 12 are connected and the resin in the portion where the resin 12 and the resin 13 are connected. The resins 11 to 13 can be separated from each other. In particular, in FIG. 4, in the case where the resin 11 to 13 is formed by injecting a sealing resin into the mold from the side of a normal mold, when the resins are separated, they are inside. Formation of the resins 11 to 12 is difficult. In this case, the sealing resin is injected into the mold from the upper part of the mold to form the resin 11, and the sealing resin is injected into the mold from the lower part of the mold to form the resin 12. Alternatively, the resin 11 and the resin 12 may be formed separately. Although explanation of the formation of the resins 14 to 16 is omitted, the resins 14 to 16 can also be formed by the transfer molding method.

  In the compression molding method, the semiconductor chip 2, the lead frame 3, each wire 4, the stage 5, and each support bar 6 are placed in a mold, and the mold is immersed in a sealing resin to perform resin sealing. . The sealing resin is, for example, a thermosetting epoxy resin. In the compression molding method, since there is no injection path for the sealing resin, waste of the sealing resin is suppressed. Further, in the compression molding method, since the sealing resin is not injected into the mold, deformation of each wire 4 due to the injection of the sealing resin is suppressed. Therefore, the compression molding method is advantageous for thinning each wire 4.

  Here, two examples of resin sealing by the compression molding method will be described. A first example of resin sealing by the compression molding method will be described. First, the semiconductor chip 2, the lead frame 3, the wires 4, the stage 5, and the support bars 6 are placed in the upper mold, and the upper mold is dipped in the sealing resin to reach the inside of the upper mold. Is filled with a sealing resin. Next, the upper portion of the resin 11 is formed by performing heat treatment. Next, the semiconductor chip 2, the lead frame 3, the wires 4, the stage 5, and the support bars 6 are placed in the lower mold, and the lower mold is immersed in a sealing resin to reach the lower mold. Fill the part with sealing resin. Next, the lower portion of the resin 11 is formed by performing heat treatment.

  A second example of resin sealing by the compression mold method will be described. The semiconductor chip 2, the lead frame 3, each wire 4, the stage 5 and each support bar 6 are placed in a mold, the mold is immersed in a sealing resin, and the mold is filled with the sealing resin. Then, resin sealing is performed by performing heat processing. By combining the upper mold and the lower mold, one mold is obtained. The lower mold is provided with a hole through which sealing resin flows, and the upper mold is provided with a hole through which air flows out. By immersing the mold in the sealing resin, the sealing resin flows from the hole provided in the lower mold, and the air flows out from the hole provided in the upper mold, for sealing in the mold. The resin is filled. The mold may be immersed in the sealing resin by immersing the mold in a resin tank filled with the sealing resin. Alternatively, the mold may be immersed in the sealing resin by lifting the resin tank filled with the sealing resin. Furthermore, the mold may be immersed in the sealing resin by bringing the mold close to the resin tank filled with the sealing resin.

  When forming the resins 11 and 12 in the second embodiment by the compression molding method, the resin 11 and the resin 12 are formed separately. Moreover, when forming the resins 11 to 13 in the second embodiment by the compression molding method, the resins 11 to 13 can be formed separately. Although explanation of the formation of the resins 14 to 16 is omitted, the resins 14 to 16 can also be formed by the compression molding method.

Regarding the above first to fourth embodiments, the following additional notes are further disclosed.
(Appendix 1)
A semiconductor chip;
A plurality of first leads disposed around the semiconductor chip and electrically connected to the semiconductor chip;
A plurality of second leads arranged at positions away from the plurality of first leads from the semiconductor chip and connected to the plurality of first leads;
A first resin that covers the semiconductor chip and partially covers the first leads;
With
The plurality of first leads extend radially with respect to the semiconductor chip in a plan view and protrude from a side surface of the first resin,
Part of the plurality of second leads extends in parallel with each other in a plan view.
(Appendix 2)
A second resin disposed around the first resin and partially covering each of the first leads;
The semiconductor device according to appendix 1, wherein the first leads protruding from a side surface of the first resin are connected by the second resin.
(Appendix 3)
The semiconductor device according to appendix 2, wherein the thickness of the second resin is thinner than the thickness of the first resin.
(Appendix 4)
A third resin disposed between the first resin and the second resin and partially covering each of the first leads;
The third resin is connected to the first resin and the second resin,
The semiconductor device according to appendix 2 or 3, wherein the thickness of the third resin is thinner than the thickness of the first resin.
(Appendix 5)
A fourth resin disposed around the first resin and partially covering each of the first leads;
The fourth resin is connected to the first resin,
The semiconductor device according to appendix 1, wherein a thickness of the fourth resin is thinner than a thickness of the first resin.
(Appendix 6)
The semiconductor device according to any one of appendices 1 to 5, wherein the first resin has a hole penetrating the first resin between the adjacent first leads.
(Appendix 7)
The semiconductor device according to any one of appendices 2 to 4, wherein the second resin has a hole penetrating the second resin between the adjacent first leads.
(Appendix 8)
The semiconductor device according to appendix 4, wherein the third resin has a hole penetrating the third resin between the adjacent first leads.
(Appendix 9)
The semiconductor device according to appendix 5, wherein the fourth resin has a hole penetrating the fourth resin between the adjacent first leads.

DESCRIPTION OF SYMBOLS 1 Semiconductor package 2 Semiconductor chip 3 Lead frame 4 Wire 5 Stage 6 Support bar 7 1st lead 8 2nd lead 11-16, 21, 22 Resin 31-33 Recessed part

Claims (5)

A semiconductor chip;
A plurality of first leads disposed around the semiconductor chip and electrically connected to the semiconductor chip;
A plurality of second leads arranged at positions away from the plurality of first leads from the semiconductor chip and connected to the plurality of first leads;
A first resin that covers the semiconductor chip and partially covers the first leads;
With
The plurality of first leads extend radially with respect to the semiconductor chip in a plan view and protrude from a side surface of the first resin,
Part of the plurality of second leads extends in parallel with each other in a plan view. A second resin disposed around the first resin and partially covering each of the first leads;
The semiconductor device according to claim 1, wherein the first leads protruding from a side surface of the first resin are connected to each other by the second resin. The semiconductor device according to claim 2, wherein a thickness of the second resin is thinner than a thickness of the first resin. A third resin disposed between the first resin and the second resin and partially covering each of the first leads;
The third resin is connected to the first resin and the second resin,
The semiconductor device according to claim 2, wherein a thickness of the third resin is thinner than a thickness of the first resin. The semiconductor device according to claim 4, wherein the third resin has a hole penetrating the third resin between the adjacent first leads.

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