JP2016058835A - Relay system and switch device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a relay system and a switch device that are capable of transmitting a correct control frame at accurate timing.SOLUTION: A relay system comprises a first and second switch devices across which a LAG is set and which perform communication of a control frame through bridge ports. Each switch device comprises: a memory unit 42 for reading out, at transmission timing based on a timer unit 40, data on a control frame CF stored in a memory address output from a selection unit 43; and a software processing unit 31 that writes, in the case of changing first information to second information in a state in which data on a control frame including the first information is stored in a data region [k] 48a and a first pointer PT1 is selected by the selection unit 43, data on a control frame including the second information in a data region [k] 48b and, after the writing has completed, makes the selection unit 43 select a second pointer PT2.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a relay system and a switch device, for example, a relay system and a switch device in which a link aggregation group is set across two switch devices.

  For example, Patent Document 1 discloses a network system including two physical network devices in which cross-device link aggregation is set. The two physical network devices virtually constitute one network device and exchange control signals for the virtualization control with each other.

  Patent Document 2 discloses a frame output device that performs next scheduling in advance without waiting for completion of frame reading in order to guarantee a set output bandwidth. The frame output apparatus includes a management unit that generates a write address and a read address for a frame buffer, a scheduler unit that generates a read request by adjusting a frame read order, and stores the read requests, and sequentially extracts and manages the read requests. Request buffer means for supplying to the means.

JP 2011-250185 A JP 2011-049983 A

  For example, as shown in Patent Document 1, as a redundancy method, a method of setting a link aggregation group (hereinafter abbreviated as LAG) to a plurality of ports including the respective ports of two switch devices is known. . In the redundancy method, unlike a general LAG set by one switch device, a LAG is set across two switch devices. For this reason, in addition to the effects obtained by general LAG such as redundancy for communication line failures and expansion of communication bandwidth, it is possible to realize redundancy for switch device failures.

  In this specification, such a LAG across devices is referred to as a multi-chassis link aggregation group (hereinafter abbreviated as MCLAG). A group of two switch devices in which MCLAG is set is called an MCLAG switch. Furthermore, the other switch device when the other is viewed from one of the two switch devices is referred to as a peer device.

  As shown in Patent Document 1, the two switch devices constituting the MCLAG switch transmit control frames to each other. This control frame includes, for example, information on the presence / absence of a failure related to MCLAG, and is transmitted periodically. In this case, when one of the two switch devices does not receive a control frame from the peer device within a predetermined period, the peer device can determine that there is a failure.

  Such control frame transmission processing can be performed, for example, by software processing. However, in the software processing, there is a possibility that the control frame transmission interval may vary. Furthermore, when it is required to transmit the control frame at a certain short interval, this transmission interval may not be satisfied. If a variation in the transmission interval or a situation in which the transmission interval cannot be satisfied occurs, for example, there is a risk of erroneous determination in determining whether or not there is a failure with respect to the peer device.

  Therefore, the present inventors have examined that the control frame transmission processing is performed by hardware processing instead of software processing. Specifically, a method of determining a periodic transmission timing by hardware processing and transmitting a control frame stored in advance in a memory unit based on the transmission timing was examined. However, it has been found that in this method, when information in the control frame is changed, a case where a correct control frame cannot be transmitted may occur.

  The present invention has been made in view of such circumstances, and one of its purposes is to provide a relay system and a switch device capable of transmitting a correct control frame with high-precision timing.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

  The relay system according to the present embodiment includes first and second switch devices each having a bridge port and an MCLAG port and connected to each other via a communication line via the bridge port. Each of the first and second switching devices has a control frame processing unit that periodically transmits a control frame from the bridge port to the other device and receives a control frame from the other device at the bridge port. Then, a link aggregation group is set between the MCLAG port of the own device and the MCLAG port of the other device. The control frame processing unit includes a timer unit, first and second pointers, a selection unit, a memory unit, and a software processing unit. The timer unit determines the periodic transmission timing of the control frame. The first and second pointers hold first and second memory addresses, respectively. The selection unit selects the first pointer or the second pointer, and outputs a memory address held by the selected pointer. The memory unit reads the data of the control frame from the memory address output from the selection unit at a regular transmission timing determined by the timer unit. The software processing unit includes a processor, and the control frame has data stored in the control frame having the first information at the first memory address of the memory unit, and the selection unit selects the first pointer. When the information is changed from the first information to the second information, the first and second processes are executed. The software processing unit writes the data of the control frame having the second information to the second memory address of the memory unit in the first process, and after the data writing in the first process is completed in the second process, The selection unit is caused to select the second pointer.

  The effects obtained by the representative embodiments of the invention disclosed in the present application will be briefly described. In a relay system including an MCLAG switch, a correct control frame can be transmitted with high accuracy.

In the relay system by Embodiment 1 of this invention, it is the schematic which shows the structural example. (A) And (b) is explanatory drawing which shows the schematic operation example at the time of a frame relay in the relay system of FIG. It is the schematic which shows the structural example of the control frame in FIG. FIG. 2 is a block diagram illustrating a configuration example of a main part of a switch device configuring an MCLAG switch in the relay system of FIG. 1. (A) is the schematic which shows the structural example of the address table in FIG. 4, (b) is the schematic which shows the structural example of the MCLAG table in FIG. FIG. 5 is a schematic diagram illustrating a configuration example around a control frame transmission unit in FIG. 4 in the switching device according to the first embodiment of the present invention. FIG. 7 is a sequence diagram illustrating a schematic operation example when the configuration example of FIG. 6 is used. FIG. 8 is a sequence diagram illustrating a schematic operation example performed after FIG. 7. FIG. 9 is a sequence diagram showing a schematic operation example different from FIG. 8 performed after FIG. 7 in the switch device according to the second embodiment of the present invention. FIG. 7 is a schematic diagram showing a configuration example different from FIG. 6 around the control frame transmission unit in FIG. 4 in the switch device according to the third embodiment of the present invention. FIG. 5 is a schematic diagram illustrating a configuration example around a control frame transmission unit in FIG. 4 in a switch device studied as a comparative example of the present invention. FIG. 12 is a sequence diagram illustrating a schematic operation example when the configuration example of FIG. 11 is used.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
<< Relay system configuration and frame relay operation >>
FIG. 1 is a schematic diagram showing a configuration example of a relay system according to Embodiment 1 of the present invention. The relay system shown in FIG. 1 includes an MCLAG switch MCLAGSW composed of two switch devices (first and second switch devices) SW1 and SW2, and a plurality (in this case, n) of communication devices 10 [1] -10. [N]. Each of the switch devices SW1 and SW2 is an L2 switch that performs a relay process for Layer 2 (L2), an L3 switch that performs a relay process for Layer 3 (L3), or the like. In this embodiment, a case where an L2 switch is used is taken as an example.

  Each of the switch devices (first and second switch devices) SW1 and SW2 has a bridge port Pb and a plurality (n in this case) of ports P1 to Pn, and are connected to each other via the bridge port Pb. 12 is connected. The communication line 12 may be composed of an Ethernet (registered trademark) line or a dedicated line. Each of the n ports P1 to Pn is assumed to be an MCLAG port here. However, the n ports P1 to Pn do not have to be all MCLAG ports, and at least one of them may be MCLAG ports. In this case, the remaining ports are general ports for which MCLAG is not set.

  Each of the n communication devices 10 [1] to 10 [n] is, for example, an information processing device such as a server device or a switch device such as an L2 switch. Each of the communication devices 10 [1] to 10 [n] has ports (LAG ports) Pu1 and Pu2. The MCLAG ports P1 of the switch devices SW1 and SW2 are connected to the LAG ports Pu1 and Pu2 of the communication device 10 [1] via the communication line 13, respectively. In this example, the LAG port Pu1 is connected to the switch device SW1 side, and the LAG port Pu2 is connected to the switch device SW2 side.

  Similarly, the MCLAG ports P2 of the switch devices SW1 and SW2 are connected to the LAG ports Pu1 and Pu2 of the communication device 10 [2] via the communication line 13, respectively, and are used for the MCLAG of the switch devices SW1 and SW2. The ports Pn are connected to the LAG ports Pu1 and Pu2 of the communication device 10 [n] via the communication line 13, respectively. The communication line 13 is composed of, for example, an Ethernet line.

  Here, each of the switching devices SW1 and SW2 sets LAG (that is, MCLAG) between the MCLAG port of the own device and the MCLAG port of the other device. For example, the switching device SW1 sets MCLAG [1] between the MCLAG port P1 of the own device (SW1) and the MCLAG port P1 of the other device (SW2), and the switching device SW2 is also set to the own device (SW2). MCLAG [1] is set between the MCLAG port P1 of () and the MCLAG port P1 of the other device (SW1).

  Similarly, the switch device SW1 sets MCLAG [2] between the MCLAG port P2 of the own device (SW1) and the MCLAG port P2 of the other device (SW2), and the switch device SW2 MCLAG [2] is set between the MCLAG port P2 of SW2) and the MCLAG port P2 of the other device (SW1). Thereafter, similarly, the switch devices SW1 and SW2 both set MCLAG [n] to the MCLAG port Pn.

  On the other hand, the communication device 10 [1] sets MCLAG [1] to the LAG ports Pu1 and Pu2. Similarly, the communication device 10 [2] sets MCLAG [2] to the LAG ports Pu1 and Pu2, and the communication device 10 [n] sets MCLAG [n] to the LAG ports Pu1 and Pu2. Here, each of the communication devices 10 [1] to 10 [n] is configured to set MCLAG to the LAG ports Pu1 and Pu2, but actually, it is only necessary to set a normal LAG. It is not necessary to distinguish between MCLAG and LAG.

  FIGS. 2A and 2B are explanatory diagrams illustrating a schematic operation example at the time of frame relay in the relay system of FIG. Here, the communication device 10 [1] is an information processing device having a MAC (Media Access Control) address MA1, and the communication device 10 [n] is an information processing device having a MAC address MA2, etc. Assume that a user frame is transferred from 10 [1] to the communication device 10 [n]. 2A shows an operation example when there is no failure, and FIG. 2B shows a case where there is a failure in the communication line 13 between the switch device SW1 and the communication device 10 [n]. An example of operation is shown.

  2 (a) (or FIG. 2 (b)), the communication device 10 [1] generates a user frame UF1a (or UF1b), and based on a predetermined distribution rule in MCLAG [1], the LAG port Pu1 , Pu2 transmits user frame UF1a (or UF1b). Here, it is assumed that the communication device 10 [1] transmits the user frame UF1a (or UF1b) from the LAG port Pu1 to the switch device SW1. The switching device SW1 receives the user frame UF1a (or UF1b) at the MCLAG port P1, and learns the source MAC address (here, MA1) in the address table (FDB) in association with MCLAG [1].

  Further, the switching device SW1 searches the address table (FDB) using the destination MAC address (here, MA2) included in the user frame UF1a (or UF1b) as a search key. As a result, the switching device SW1 obtains MCLAG [n] as the destination port. Here, as shown in FIG. 2A, the switch device SW1 relays the user frame UF1a to the MCLAG port Pn when there is no failure in the MCLAG port Pn of its own device that is a member port of MCLAG [n]. To do. As a result, the user frame UF1a is transferred to the communication device 10 [n].

  On the other hand, as shown in FIG. 2B, the switch device SW1 relays the user frame UF1b to the bridge port Pb when there is a failure in the MCLAG port Pn of its own device that is a member port of MCLAG [n]. . That is, the switching device SW1 recognizes that MCLAG [n] is set between the MCLAG port Pn of the own device (SW1) and the MCLAG port Pn of the other device (SW2), and at the same time the switching device SW2 After recognizing that there is no failure in the MCLAG port Pn, the user frame UF1b is relayed to the bridge port Pb. The switching device SW2 relays the user frame UF1b received at the bridge port Pb to the MCLAG port Pn of its own device corresponding to the destination port MCLAG [n]. As a result, the user frame UF1b is transferred to the communication device 10 [n].

  In FIG. 2B, the switching device SW2 can relay the user frame UF1b using various methods. For example, the switch device SW2 receives the user frame UF1b to which the identifier of the destination port MCLAG [n] is added from the switch device SW1, and relays the user frame UF1b based on the identifier. Alternatively, when receiving the user frame UF1b, the switching device SW2 searches its own address table (FDB) and relays the user frame UF1b based on the search result.

  As described above, in the MCLAG switch MCLAGSW, for example, even when one member port (for example, Pn of SW1) of the MCLAG has a failure, an alternative route using the other member port of the MCLAG (for example, Pn of SW2). Can be built. As a premise thereof, each of the switching devices SW1 and SW2 periodically transmits a control frame CF to and from a peer device via a bridge port Pb as shown in FIGS. 2 (a) and 2 (b). It is necessary to recognize that there is no device failure in the peer device by performing reception. For example, the switch device SW1 needs to recognize that the switch device SW2 has no device failure by receiving the control frame CF from the switch device SW2 within a predetermined period.

  Further, each of the switching devices SW1 and SW2 needs to share information on the presence / absence of a failure by periodically transmitting and receiving the control frame CF. For example, in the example of FIG. 2B, when the switch device SW1 transmits the control frame CF to the switch device SW2, the member port (MCLAG [n] of the own device is included in the control frame CF. That is, information indicating that there is a failure in the MCLAG port Pn) of the own apparatus is provided. By receiving the control frame CF, the switching device SW2 recognizes that there is a failure in the member port of the MCLAG [n] of the switching device SW1.

  On the other hand, when the switch device SW2 transmits the control frame CF to the switch device SW1, the member port of the MCLAG [n] of the own device (that is, the MCLAG port Pn of the own device) is included in the control frame CF. ) Has information indicating that there is no failure. By receiving the control frame CF, the switching device SW1 recognizes that there is no failure in the member port of the MCLAG [n] of the switching device SW2. Based on this recognition, the switching device SW1 relays the user frame UF1b to the bridge port Pb as shown in FIG.

  The operation of the MCLAG switch is not limited to the operation shown in FIGS. 2A and 2B, and various operation methods can be used. For example, there is a method in which two switch devices are given priority, and in principle, frames are transmitted from the switch device on the priority side. In FIG. 2A, when the switch device SW2 is given priority, the switch device SW1 relays the user frame UF1a to the bridge port Pb even when there is no failure as shown in FIG. 2B.

  In some cases, a method of distributing a port for transmitting a user frame to two switch devices SW1 and SW2 based on a distributed ID or the like is also conceivable. Regardless of which method is used, each of the switch devices SW1 and SW2 uses the control frame CF to monitor the presence or absence of a device failure in the peer device and share failure information of the MCLAG port. This is necessary.

<< Frame format of control frame >>
FIG. 3 is a schematic diagram showing an example of the structure of the control frame in FIG. The control frame CF shown in FIG. 3 has a structure according to a general Ethernet frame, for example. The control frame includes a destination MAC address 15, a transmission source MAC address 16, a VLAN (Virtual Local Area Network) identifier (VID) 17, an Ethernet type 18, MCLAG data 19, and the like.

  The destination MAC address 15 and the source MAC address 16 store the MAC addresses of the switch devices SW1 and SW2. In the VLAN identifier 17, for example, a VLAN value for the network between the bridge ports Pb is stored. The Ethernet type 18 stores a predetermined fixed value. The MCLAG data 19 stores various types of information necessary for functioning as an MCLAG switch, with information on whether or not there is a failure in each MCLAG port as a representative.

<< Configuration and operation of switch device >>
FIG. 4 is a block diagram illustrating a configuration example of a main part of a switch device configuring the MCLAG switch in the relay system of FIG. FIG. 5A is a schematic diagram illustrating a configuration example of the address table in FIG. 4, and FIG. 5B is a schematic diagram illustrating a configuration example of the MCLAG table in FIG.

  4 includes a plurality (n) of MCLAG ports P1 to Pn, a bridge port Pb, an interface unit 25, a relay processing unit 26, a processor CPU, and a control frame hardware processing unit 27. And an address table FDB and an MCLAG table 28. As described above, the plurality of MCLAG ports P1 to Pn are not necessarily all MCLAG ports, and at least one MCLAG port may be the MCLAG port.

  The interface unit 25 includes a reception buffer and a transmission buffer, and transmits or receives a frame (user frame or control frame) to and from a plurality of ports (MCLAG ports P1 to Pn and bridge port Pb). When the interface unit 25 receives a frame at a port, the interface unit 25 adds a port identifier representing the reception port (referred to as a reception port identifier) to the frame. When the interface unit 25 receives a frame to which a destination port identifier representing a destination port is added, the interface unit 25 transmits the frame from the destination port.

  Further, the interface unit 25 includes a frame identification unit 29 and a failure detection unit 30. The frame identification unit 29 identifies whether the frame is a user frame (such as UF1a in FIG. 2A) or a control frame CF for a frame received by the reception buffer. Although not particularly limited, the frame identification unit 29 performs an identification operation based on a destination MAC address (for example, whether or not it is addressed to the own device) and various identifiers in the frame. The frame identification unit 29 transmits the user frame to the relay processing unit 26 when the identification result is a user frame, and transmits the control frame CF to the control frame hardware processing unit 27 when the identification result is a control frame CF. .

  The failure detection unit 30 detects the presence / absence of a failure (link presence / absence) in each port (P1 to Pn, Pb) by hardware. For example, the failure detection unit 30 monitors the received optical signal level, and detects the presence of link down when an abnormal state such as an insufficient optical signal level continues for a predetermined period. Alternatively, the failure detection unit 30 monitors the presence or absence of the link pulse signal generated in the idle state or the presence or absence of the data signal in the non-idle state from the received signal, and the abnormal state such that both the link pulse signal and the data signal are absent. Is detected when the link is down for a predetermined period.

  As shown in FIG. 5A, the address table FDB includes a port identifier / MCLAG identifier, a MAC address existing ahead of the port / MCLAG indicated by the identifier, and a VLAN (Virtual Local Area Network) corresponding to the MAC address. ) Holds correspondence with identifiers. 5A, for example, {MCLAG [1]} represents an identifier (ID) of MCLAG [1]. In the present specification, similarly, {AA} is an identifier (ID) of “AA”. ).

  In the address table FDB of FIG. 5A, the correspondence between the MAC address MA1 and the MCLAG identifier {MCLAG [1]}, the MAC address MA2, and the case of FIG. 2A and FIG. And the correspondence relationship with the MCLAG identifier {MCLAG [n]}. If any of the ports P1 to Pn is a general port, the address table FDB uses a port identifier instead of the MCLAG identifier for this general port.

  As shown in FIG. 5B, the MCLAG table 28 holds an MCLAG identifier, a port identifier of each member port of the MCLAG, and information on the presence / absence of a failure for each member port. In the MCLAG table 28 of FIG. 5B, for example, in the case of FIG. 2B, for example, the MCLAG identifier {MCLAG [n]} and the port identifiers of the member ports {Pn} (SW1), {Pn} (SW2) and information indicating that there is a failure in one of the member ports (the MCLAG port Pn of the switch device SW1) are held.

  The relay processing unit 26 mainly learns and searches the address table FDB, and relays frames (for example, user frames) between the ports (P1 to Pn, Pb) based on the address table FDB and the like. Specifically, when the relay processing unit 26 receives the user frame received at the MCLAG ports P1 to Pn via the interface unit 25, the relay processing unit 26 sets the transmission source MAC address of the user frame, the reception port identifier, and a predetermined value. The address table FDB is learned in association with the VLAN identifier. At this time, based on the MCLAG table 28, the relay processing unit 26 learns the address table FDB using the MCLAG identifier instead of the reception port identifier when the port indicated by the reception port identifier is a member port of the MCLAG. .

  In addition, the relay processing unit 26 searches the address table FDB using the destination MAC address of the user frame and a predetermined VLAN identifier as search keys, and acquires the destination port identifier. When the destination port identifier is an MCLAG identifier, the relay processing unit 26 recognizes MCLAG ports of the own device and other devices (peer devices) that are member ports of the MCLAG identifier based on the MCLAG table 28.

  Here, based on the MCLAG table 28, the relay processing unit 26 transmits a user frame to which the destination port identifier indicating the MCLAG port is added to the interface unit 25 when the MCLAG port of the own apparatus has no failure. To do. The interface unit 25 transmits a user frame from the MCLAG port indicated by the destination port identifier. On the other hand, based on the MCLAG table 28, the relay processing unit 26, when the MCLAG port of the own device is faulty and the MCLAG port of the peer device is not faulty, is a destination port identifier representing the bridge port Pb. The user frame with {Pb} added is transmitted to the interface unit 25. In response to this, the interface unit 25 transmits a user frame from the bridge port Pb.

  Further, as described with respect to the switch device SW2 in FIG. 2B, the relay processing unit 26 performs various processes when the user frame is relayed to the bridge port Pb or when the user frame is received at the bridge port Pb. I do. For example, the relay processing unit 26 relays a user frame to which the MCLAG identifier (destination port identifier) obtained by searching the address table FDB is added to the bridge port Pb, or the MCLAG identifier (destination port identifier) is added. When the user frame is received at the bridge port Pb, the relay is performed based on the destination port identifier. Note that the processing content of the relay processing unit 26 is not particularly limited to this, and can be appropriately changed according to the operation method of the MCLAG switch MCLAGSW as described in FIGS. 2 (a) and 2 (b). It is.

  The control frame hardware processing unit 27 is configured by hardware typified by an FPGA (Field Programmable Gate Array), for example, and includes a control frame reception unit 32 and a control frame transmission unit 33. The control frame receiving unit 32 receives the control frame CF from another device (peer device) at the bridge port Pb. In this example, the control frame receiving unit 32 receives the control frame CF received at the bridge port Pb via the interface unit 25.

  Then, the control frame receiving unit 32 determines whether or not the control frame CF is received within a predetermined period, and notifies the determination result to the processor CPU. The predetermined period is determined in advance based on the regular transmission timing of the control frame CF. Further, the control frame receiving unit 32 transmits, for example, the MCLAG data 19 included in the control frame CF to the processor CPU.

  Although details will be described later, the control frame transmission unit 33 periodically transmits the control frame CF from the bridge port Pb to the other device (peer device). In this example, the control frame transmission unit 33 periodically transmits, for example, the control frame CF to which the destination port identifier {Pb} representing the bridge port Pb is added to the interface unit 25, and bridges the bridge via the interface unit 25. Transmit from port Pb.

  The control frame hardware processing unit 27 may perform processing such as Ethernet OAM (Operations, Administration, and Maintenance) in addition to the processing of the control frame CF for MCLAG. In Ethernet OAM, for example, by periodically transmitting and receiving a control frame (test frame) called CCM (Continuity Check Message) or the like, communication with the outside of the apparatus can be monitored. The presence / absence of a failure in each port can be detected.

  The processor CPU includes various processing units configured by executing programs stored in a RAM (Random Access Memory) or a ROM (Read Only Memory) (not shown). As one of them, the processor CPU includes a control frame software processing unit (software processing unit) 31. The control frame software processing unit 31 constitutes a control frame processing unit together with the control frame hardware processing unit 27 described above, and performs various processes related to the control frame CF in cooperation with the control frame hardware processing unit 27.

  For example, the control frame software processing unit 31 receives the MCLAG data 19 from the control frame receiving unit 32, and information on the presence / absence of failure of the MCLAG port included in the MCLAG data 19 (that is, the presence / absence of failure of the MCLAG port of the peer device). The MCLAG table 28 is updated based on the information. When the control frame software processing unit 31 receives a notification from the control frame receiving unit 32 that the control frame CF has not been received within a predetermined period, it manages the state of the bridge port Pb as being faulty. To do.

  Further, the control frame software processing unit 31 generates a control frame CF based on the detection result of the failure detection unit 30 (for example, information on the presence / absence of failure of the MCLAG port of its own device). Various processes for causing the transmission unit 33 to transmit the control frame CF are performed. As described above, when the control frame hardware processing unit 27 performs Ethernet OAM processing, the control frame software processing unit 31 detects the presence / absence of the failure (for example, the failure of the MCLAG port of its own device). The MCLAG table 28 may be updated based on the presence / absence information). At this time, the control frame software processing unit 31 may generate a control frame CF based on the detection result of the presence or absence of the failure.

  In addition to the processing in the control frame software processing unit 31, the processor CPU updates the MCLAG table 28 based on the detection result in the failure detection unit 30, software processing in cooperation with the relay processing unit 26 related to the user frame, Also, the entire switch device SW is managed.

<< Examples of problems in switch devices >>
FIG. 11 is a schematic diagram illustrating a configuration example around the control frame transmission unit in FIG. 4 in a switch device studied as a comparative example of the present invention. The control frame transmission unit 33 ′ illustrated in FIG. 11 includes a timer unit 40, a read control unit 41, a packet memory (memory unit) 42, and a pointer table [1] (first pointer) PT1. The timer unit 40 periodically outputs a trigger signal 46, thereby determining the regular transmission timing of the control frame CF. The read control unit 41 outputs a read command 47 when the trigger signal 46 is input. The pointer table [1] (first pointer) PT1 holds a memory address (first memory address) ADR [k].

  When the read command 47 is input, the packet memory (memory unit) 42 reads the data stored in the memory address held in the pointer table [1] PT1. The data area [k] 48a accessed by the memory address ADR [k] of the packet memory 42 stores data of the control frame CF in advance. As a result, the packet memory 42 reads the data of the control frame CF stored in the memory address (first memory address) ADR [k] at a regular transmission timing determined by the timer unit 40.

  The control frame CF has many variations such as having different information for each different failure location (for example, the MCLAG data 19 in FIG. 3 is different). Therefore, the data of the control frame CF is generated by the control frame software processing unit 31 ', and is written in the data area [k] 48a in advance by the control frame software processing unit 31'.

  FIG. 12 is a sequence diagram showing a schematic operation example when the configuration example of FIG. 11 is used. In FIG. 12, it is assumed that the data of the control frame CF1 at the normal time (when there is no failure) is already stored in the data area [k] 48a of the packet memory 42. In this state, the packet memory 42 first stores the data of the control frame CF1 stored in the memory address ADR [k] (that is, the data area [k] 48a) held in the pointer table [1] PT1 in the control frame. Read at transmission timing t1 (step S401).

  Thereafter, the control frame software processing unit 31 'recognizes that there is a failure in the MCLAG port of the own device based on, for example, the detection result of the failure detection unit 30 (step S402). In response to this, the control frame software processing unit 31 'generates data of the control frame CF2 including the failure information (step S403). Then, the control frame software processing unit 31 'performs write access to the data area [k] 48a of the packet memory 42, and writes the data of the control frame CF2 to the data area [k] 48a (steps S404 and S405).

  Here, for example, the data size per memory address of the packet memory 42 may be larger than the data size per write access by the control frame software processing unit 31 ′. Then, in the data area [k] 48a, when reading the data of the control frame CF2, the read control unit 41 performs one read access, whereas when writing the data of the control frame CF2, The control frame software processing unit 31 ′ may require a plurality of write accesses. As a result, the data writing time of the control frame CF2 can be longer than the data reading time of the control frame CF2.

  Then, as shown in FIG. 12, an incomplete control frame CF2 may be read out and transmitted to the peer device. Specifically, while the write access is performed a plurality of times by the control frame software processing unit 31 ′ (step S405), the next transmission timing t2 of the control frame occurs, and the packet memory 42 receives the data in response to this. There is a case where the area [k] 48a is read (step S406).

  In this case, the read control frame can have information such as new information (data of the control frame CF2) and past information (data of the control frame CF1), for example. Then, the peer device that has received the control frame may malfunction due to the erroneous control frame.

<< Configuration and operation of main part of control frame processing section (this embodiment) >>
FIG. 6 is a schematic diagram showing a configuration example around the control frame transmission unit in FIG. 4 in the switch device according to Embodiment 1 of the present invention. FIG. 6 shows a configuration example of a main part of the control frame processing unit including the control frame transmission unit 33 and the control frame software processing unit 31 in FIG. In addition to the timer unit 40, the read control unit 41, the packet memory (memory unit) 42, and the pointer table [1] (first pointer) PT1 illustrated in FIG. A pointer table [2] (second pointer) PT2 and a selection unit 43 are provided. Since the timer unit 40, the read control unit 41, and the pointer table [1] (first pointer) PT1 are the same as those in FIG. 11, detailed description thereof is omitted.

  The pointer table [2] (second pointer) PT2 holds a memory address (second memory address) ADR [j]. The selection unit 43 selects the pointer table [1] (first pointer) PT1 or the pointer table [2] (second pointer) PT2, and outputs a memory address held by the selected pointer. Unlike the case of FIG. 11, the packet memory (memory unit) 42 reads the data of the control frame CF from the memory address output from the selection unit 43 at a regular transmission timing determined by the timer unit 40.

  In response to this, the packet memory (memory unit) 42 adds the data area [j] 48b accessed by the memory address ADR [j] in addition to the data area [k] 48a accessed by the memory address ADR [k]. It has. The control frame software processing unit 31 outputs a selection signal 45 to the selection unit 43 in addition to performing memory access to the packet memory 42 as in the case of FIG.

  FIG. 7 is a sequence diagram showing a schematic operation example when the configuration example of FIG. 6 is used. In FIG. 7, as in the case of FIG. 12, the data of the control frame CF1 at the normal time is already stored in the memory address (first memory address) ADR [k] (that is, the data area [k] 48a) of the packet memory 42. It shall be remembered. In other words, the data of the control frame CF1 at the normal time is data having information (first information) indicating no failure. Further, it is assumed that the selection unit 43 has already selected the pointer table [1] (first pointer) PT1.

  In this state, the packet memory 42, based on the selection unit 43, stores the control frame CF1 stored in the memory address ADR [k] (that is, the data area [k] 48a) held in the pointer table [1] PT1. Data is read at control frame transmission timing t1 (step S101). Thereafter, the control frame software processing unit 31 recognizes that there is a failure in the MCLAG port (for example, P1) of the own device based on, for example, the detection result of the failure detection unit 30 (step S102).

  In response to this, the control frame software processing unit (software processing unit) 31 generates data of the control frame CF2 including the failure information (step S103). In other words, the control frame software processing unit 31 changes the information included in the control frame CF from information indicating no failure (first information) to information indicating that there is a failure at a predetermined MCLAG port (for example, P1) (second information). Change to Then, unlike the case of FIG. 12, the control frame software processing unit 31 performs write access to the memory address (second memory address) ADR [j] (that is, the data area [j] 48b) of the packet memory (memory unit) 42. And write the data of the control frame CF2 having the failure information (second information) in the data area [j] 48b (steps S104 and S105 (first processing)).

  Here, in FIG. 7, during the writing to the data area [j] 48 b in steps S <b> 104 and S <b> 105, the transmission timing t <b> 2 next to the transmission timing t <b> 1 occurs as in the case of FIG. 12. However, unlike the case of FIG. 12, the packet memory 42 is still in the middle of writing according to the transmission timing t2, because the selection unit 43 still selects the pointer table [1] (first pointer) PT1. k] The normal control frame CF1 data can be read from 48a. That is, it is possible to prevent a control frame having information such as new information and past information from being transmitted to the peer device.

  Then, the control frame software processing unit (software processing unit) 31 uses the selection signal 45 to send the pointer table [2] to the selection unit 43 after completing the data writing in steps S104 and S105 (first processing). (Second pointer) PT2 is selected (step S107 (second processing)). In response to this, the selection unit 43 selects the pointer table [2] PT2 (step S108). Thereafter, based on the selection unit 43, the packet memory 42 transmits the data of the control frame CF2 stored in the memory address ADR [j] (that is, the data area [j] 48b) held in the pointer table [2] PT2. Reading is performed at the transmission timing t3 next to the timing t2 (step S109).

  FIG. 8 is a sequence diagram illustrating a schematic operation example performed after FIG. In FIG. 8, first, as described in FIG. 7, the selection unit 43 selects the pointer table [2] (second pointer) PT2, and the packet memory 42 starts from the data area [j] 48b at the transmission timing t10. Data of the control frame CF2 is read (step S201).

  In this state, the control frame software processing unit (software processing unit) 31 recognizes the failure recovery of its own MCLAG port (for example, P1) based on the detection result of the failure detection unit 30, for example (step S202). . In response to this, the control frame software processing unit 31 changes the information held by the control frame CF from the information with failure (second information) at the predetermined MCLAG port (for example, P1) (first information). ). However, the control frame software processing unit 31 recognizes that the data of the normal control frame CF1 having the failure-free information (first information) is already stored in the data area [k] 48a.

  Therefore, the control frame software processing unit 31 causes the selection unit 43 to select the pointer table [1] (first pointer) PT1 using the selection signal 45 (step S203 (third processing)). In response to this, the selection unit 43 selects the pointer table [1] PT1 (step S204). Thereafter, based on the selection unit 43, the packet memory 42 transmits the data of the control frame CF1 stored in the memory address ADR [k] (that is, the data area [k] 48a) held in the pointer table [1] PT1. Reading is performed at a transmission timing t11 next to the timing t10 (step S205).

<< Main effects of the first embodiment >>
As described above, by using the relay system and the switch device according to the first embodiment, it is typically possible to transmit a correct control frame CF at a highly accurate timing. As a result, malfunction of the MCLAG switch MCLAGSW can be prevented. Specifically, first, since the control frame CF is periodically transmitted by hardware processing as shown in FIG. 6, the transmission interval of the control frame CF can be kept constant with high accuracy. In particular, by specifying the memory address using the pointer table (PT1, PT2) and determining the read timing using the timer unit 40, no software processing is involved in the read, and the transmission interval can be highly accurate. .

  In addition, by using the hardware processing, even when it is necessary to shorten the transmission interval of the control frame CF, the transmission interval can be highly accurate. As described above, by increasing the transmission interval, it is possible to correctly determine the presence / absence of the failure of the peer device based on the presence / absence of reception of the control frame CF, and to prevent malfunction of the MCLAG switch MCLAGSW. Further, by shortening the transmission interval of the control frame CF, for example, the switching operation at the time of failure in the MCLAG switch MCLAGSW can be quickly performed.

  Furthermore, by using the method as shown in FIG. 7, it is possible to transmit the correct control frame CF even when it is necessary to change the information held in the control frame CF. That is, it is possible to prevent a situation in which an erroneous control frame CF having mixed information is transmitted. From this point of view, it is possible to prevent malfunction of the MCLAG switch MCLAGSW.

(Embodiment 2)
<< Operation of main part of control frame processing part (modified example) >>
FIG. 9 is a sequence diagram showing a schematic operation example different from FIG. 8 performed after FIG. 7 in the switch device according to the second embodiment of the present invention. In FIG. 9, first, as described in FIG. 7, the selecting unit 43 selects the pointer table [2] (second pointer) PT2, and the packet memory 42 starts from the data area [j] 48b at the transmission timing t10. Data of the control frame CF2 is read (step S301).

  In this state, the control frame software processing unit (software processing unit) 31, for example, based on the detection result of the failure detection unit 30 or the like, in addition to the MCLAG port (for example, P1), another MCLAG port (for example, P2). Is recognized as being faulty (step S302). In response to this, the control frame software processing unit 31 generates data of the control frame CF3 including the failure information (step S303). In other words, the control frame software processing unit 31 changes the information held in the control frame CF from a failure information (second information) at a single MCLAG port (for example, P1) to a plurality of MCLAG ports (for example, P1, P1). The information is changed to information with failure (third information) in P2).

  Then, the control frame software processing unit 31 performs write access to the memory address (first memory address) ADR [k] (that is, the data area [k] 48a) of the packet memory (memory part) 42, and the data area [k]. The data of the control frame CF3 having the information with the failure (third information) is written in 48a (steps S304 and S305 (fourth processing)).

  Here, in FIG. 9, the transmission timing t11 next to the transmission timing t10 occurs during the writing to the data area [k] 48a in steps S304 and S305. However, since the selection unit 43 still selects the pointer table [2] (second pointer) PT2, the packet memory 42 controls the control frame CF2 from the data area [j] 48b that is not in the middle of writing according to the transmission timing t11. Can be read. That is, it is possible to prevent a situation in which a control frame having information such as new information (data of the control frame CF3) and past information (data of the control frame CF2) is transmitted to the peer device.

  Then, the control frame software processing unit (software processing unit) 31 uses the selection signal 45 to send the pointer table [1] to the selection unit 43 after the completion of data writing in steps S304 and S305 (fourth processing). (First pointer) PT1 is selected (step S307 (fifth process)). In response to this, the selection unit 43 selects the pointer table [1] PT1 (step S308). Thereafter, based on the selection unit 43, the packet memory 42 transmits the data of the control frame CF3 stored in the memory address ADR [k] (that is, the data area [k] 48a) held in the pointer table [1] PT1. Reading is performed at the transmission timing t12 next to the timing t11 (step S309).

  As described above, by using the data area [k] 48a and the data area [j] 48b alternately, how the information of the control frame CF changes the various effects as described in the first embodiment. Even if it is done, it can be obtained.

(Embodiment 3)
<Configuration of main part of control frame processing unit (application example)>
FIG. 10 is a schematic diagram showing a configuration example different from FIG. 6 around the control frame transmission unit in FIG. 4 in the switch device according to the third embodiment of the present invention. The control frame transmission unit 33 illustrated in FIG. 10 has a configuration in which a pointer table [3] PT3 that holds a memory address ADR [i] is further added to the configuration example of FIG. In response to this, the selection unit 43 selects one of the pointer table [1] PT1 to the pointer table [3] PT3 based on the selection signal 45, and selects the memory address held in the selected pointer table. Output.

  In addition to the data area [k] 48a and the data area [j] 48b, the packet memory 42 includes a data area [i] 48c accessed by the memory address ADR [i]. Here, for example, in the data area [k] 48a, the control frame CF1 at the normal time (when there is no failure) is stored. On the other hand, the data area [k] 48b and the data area [k] 48c are reserved for storing the control frame CF when there is a failure.

  For example, when the method of the second embodiment is used, the data of the normal control frame CF1 is overwritten. Therefore, when the failure is recovered, the data of the normal control frame CF1 is generated again and stored in a predetermined data area. Need to write. Further, the data area in which the data of the control frame CF1 at the normal time is written can be changed as appropriate. Since the data in the normal control frame CF1 is normally used for many periods, it may not be desirable to overwrite the data in the normal control frame CF1 or change the stored data area. .

  Therefore, when the method of FIG. 10 is used, in addition to the various effects described in the first and second embodiments, the data area [k] 48a is fixed for the data of the control frame CF1 in the normal state. The same operation as in the second embodiment can be performed using the data area [j] 48b and the data area [i] 48c. Further, at the time of failure recovery, the same operation as in FIG. 8 may be performed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described. Further, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. . Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  For example, the switch device of the present embodiment can be realized by a box type configuration or a chassis type configuration. The chassis type switch device includes, for example, a plurality of line cards that perform frame communication with the outside of the device, and a management card that is connected to the plurality of line cards and manages the plurality of line cards. When such a chassis type configuration is used, the control frame processing unit shown in FIG. 6 and the like can be provided on the line card or the management card.

10 [1] to 10 [n] Communication device 12, 13 Communication line 15 Destination MAC address 16 Source MAC address 17 VLAN identifier 18 Ethertype 19 MCLAG data 25 Interface unit 26 Relay processing unit 27 Control frame hardware processing unit 28 MCLAG table DESCRIPTION OF SYMBOLS 29 Frame identification part 30 Failure detection part 31, 31 'Control frame soft process part 32 Control frame receiving part 33, 33' Control frame transmission part 40 Timer part 41 Read control part 42 Packet memory 43 Selection part 45 Selection signal 46 Trigger signal 47 Read command 48a, 48b, 48c Data area CF control frame CPU processor FDB address table MCLAGSW MCLAG switch P1 to Pn ports (ports for MCLAG)
PT1 to PT3 Pointer table Pb Bridge port Pu1, Pu2 port (LAG port)
SW, SW1, SW2 Switch device UL1a, UL1b User frame

Claims (10)

A relay system including a first switch device and a second switch device, each having a bridge port and an MCLAG port and connected to each other via a communication line via the bridge port;
Each of the first switch device and the second switch device periodically transmits a control frame from the bridge port to the other device, and receives the control frame from the other device at the bridge port. Having a control frame processing unit, setting a link aggregation group between the MCLAG port of its own device and the MCLAG port of the other device;
The control frame processing unit
A timer unit for determining a periodic transmission timing of the control frame;
A first pointer holding a first memory address;
A second pointer holding a second memory address;
A selection unit that selects the first pointer or the second pointer and outputs a memory address held by the selected pointer;
From the memory address output from the selection unit, a memory unit that reads data of the control frame at the regular transmission timing determined by the timer unit;
A software processing unit composed of a processor;
Have
The software processing unit stores the control frame data in a state where the data of the control frame having first information is stored in the first memory address of the memory unit and the selection unit selects the first pointer. When changing the information held by the first information to the second information,
A first process of writing data of the control frame having the second information to the second memory address of the memory unit;
A second process for causing the selection unit to select the second pointer after the writing of data in the first process is completed;
Run the
Relay system. The relay system according to claim 1,
When the control frame processing unit does not receive the control frame from the other device within a predetermined period that is determined in advance based on the periodic transmission timing, the other device determines that there is a failure.
Relay system. The relay system according to claim 2, wherein
The control frame includes information on the presence or absence of a failure of the MCLAG port.
Relay system. The relay system according to claim 1,
When the software processing unit changes the information to be given to the control frame from the second information to the first information after the first processing and the second processing, the software processing unit sends the first pointer to the selection unit. Execute a third process for selecting
Relay system. The relay system according to claim 1,
The software processing unit, when changing the information to be given to the control frame from the second information to the third information after the first process and the second process,
A fourth process of writing data of the control frame having the third information to the first memory address of the memory unit;
A fifth process for causing the selection unit to select the first pointer after the data writing in the fourth process is completed;
Run the
Relay system. A bridge port and an MCLAG port, the bridge port being connected to a bridge port of another switch device, and a link between the MCLAG port of the own device and the MCLAG port of the other switch device; A switch device for setting an aggregation group,
A control frame processing unit that periodically transmits a control frame from the bridge port to the other switch device, and receives a control frame from the other switch device at the bridge port;
The control frame processing unit
A timer unit for determining a periodic transmission timing of the control frame;
A first pointer holding a first memory address;
A second pointer holding a second memory address;
A selection unit that selects the first pointer or the second pointer and outputs a memory address held by the selected pointer;
From the memory address output from the selection unit, a memory unit that reads data of the control frame at the regular transmission timing determined by the timer unit;
A software processing unit composed of a processor;
Have
The software processing unit stores the control frame data in a state where the data of the control frame having first information is stored in the first memory address of the memory unit and the selection unit selects the first pointer. When changing the information held by the first information to the second information,
A first process of writing data of the control frame having the second information to the second memory address of the memory unit;
A second process for causing the selection unit to select the second pointer after the writing of data in the first process is completed;
Switch device. The switch device according to claim 6, wherein
When the control frame processing unit does not receive a control frame from the other switch device within a predetermined period determined based on the periodic transmission timing, the control frame processing unit determines that the other switch device has a failure. ,
Switch device. The switch device according to claim 7, wherein
The control frame includes information on the presence or absence of a failure of the MCLAG port.
Switch device. The switch device according to claim 6, wherein
When the software processing unit changes the information to be given to the control frame from the second information to the first information after the first processing and the second processing, the software processing unit sends the first pointer to the selection unit. Execute a third process for selecting
Switch device. The switch device according to claim 6, wherein
The software processing unit, when changing the information to be given to the control frame from the second information to the third information after the first process and the second process,
A fourth process of writing data of the control frame having the third information to the first memory address of the memory unit;
A fifth process for causing the selection unit to select the first pointer after the data writing in the fourth process is completed;
Run the
Switch device.

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