JP2016057817A - Information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent data from being broken during execution of writing processing on a memory in spite of initialization request input by a reset switch.SOLUTION: An information processing device comprises: a reset generation part which outputs a first reset signal in response to an initialization request; a delay part which outputs a second reset signal after a predetermined delay time has elapsed since the first reset signal is input; a control part comprising an input terminal for receiving the first reset signal and a reset terminal for receiving the second reset signal; and a storage part comprising a reset terminal for receiving the second reset signal, the control part confirming whether the first reset signal is received before making a request to write data to the storage part and not executing data writing to the storage part when the first reset signal is received.SELECTED DRAWING: Figure 5

Description

  The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus having a reset control function capable of initializing or stopping operations of a CPU and a memory.

Conventionally, an information processing apparatus generally uses a microcomputer including a CPU, ROM, RAM, flash memory, I / O controller, etc., and the CPU is based on a program stored in the ROM or the like. The requested function is executed by reading / writing the requested data to / from the RAM or flash memory and operating various hardware.
Some of such information processing apparatuses are provided with a reset switch for forcibly turning off the power supply or for initialization.

When the reset switch is depressed, a reset signal is given to hardware such as CPU, ROM, RAM, and flash memory almost simultaneously, and the hardware is initialized or the supply of power supply voltage is stopped.
If a write command from the CPU is given to the flash memory and the reset switch is pushed down while data is being written to the flash memory, the power supply to the flash memory is temporarily stopped, so the data being written May be damaged, resulting in data write errors and subsequent data read errors.

  In Patent Document 1, even if a reset signal is generated when data is written to a writable ROM or nonvolatile RAM, a reset signal delayed from the first reset signal supplied to the CPU is written in order to prevent a write error. There has been proposed a reset signal generating circuit which is supplied to a possible ROM and a non-volatile RAM.

JP 2001-142792 A

However, in a conventional device for controlling a reset signal, a data write command is given from a CPU to a memory such as a RAM regardless of whether the reset signal is input, and so-called chattering occurs when the reset switch is pressed. As a result, it may be erroneously detected that the reset signal has been input.
In order to prevent damage to the write data during the process of writing data to a memory such as RAM or flash memory, after confirming whether a reset signal has been input, send a write command from the CPU to the memory. It is desirable to do.
Therefore, the present invention has been made in view of the above circumstances, and in consideration of the timing of the reset signal generated due to the reset switch being pressed and the like, and the write request to the memory, It is an object to prevent data written to a memory from being damaged.

  According to the present invention, a reset generation unit that outputs a first reset signal in response to an initialization request, and a second reset signal that is output after a predetermined delay time has elapsed after the first reset signal has been input. A control unit including a delay unit, an input terminal for inputting the first reset signal and a reset terminal for inputting the second reset signal, and a storage unit including a reset terminal for inputting the second reset signal. And the controller checks whether or not the first reset signal is input before making a data write request to the storage unit, and if the first reset signal is input, An information processing apparatus is provided that does not execute data writing to a storage unit.

In addition, when the control unit confirms whether or not the first reset signal is input, if the first reset signal is not input, data writing to the storage unit is executed. .
According to this, when the first reset signal output in response to the initialization request is not input, the data writing to the storage unit is executed, and the first reset signal is input as described above. In the case where the data is written, the data writing is not executed. Therefore, the data writing is started at a timing at which the written data is not damaged.

The input terminal of the control unit is a general-purpose input terminal, and the delay time includes a maximum writing time required to write data to the storage unit and a maximum time required to erase data in the storage unit. A time longer than any of the erasing times is preset, and the second reset signal is transmitted from the delay unit to the control unit and the storage at a time when the data writing process is not actually performed in the storage unit. It is output to the part.
According to this, since the second reset signal is output to the control unit and the storage unit when the data writing process is not performed, it is possible to prevent the write data from being damaged.

In addition, an input unit having a reset switch for inputting a forced initialization request is further provided, and the reset generation unit outputs the first reset signal when an input operation is performed to depress the reset switch. It is characterized by that.
In addition, after the first reset signal is input to the input terminal of the control unit, if the first reset signal is input even after a predetermined time has elapsed, data is written to the storage unit It is characterized by not. According to this, as described in Example 2 described later, it is possible to prevent erroneous detection of the reset signal.
In addition, the storage unit may be a flash memory including memory cells composed of a plurality of pages, and writing and reading of data to and from the memory cells are performed in units of pages. According to the present invention, it is possible to prevent the data to be written to the memory cell of the flash memory from being damaged.

  According to the present invention, the control unit checks whether or not the first reset signal is input, and when the first reset signal is input, the data is not written to the storage unit. After being performed, the data writing process to the storage unit is not performed, and it is possible to prevent the data from being damaged by the writing process when a reset request is generated.

It is a schematic structure block diagram of the part relevant to the reset process of the information processing apparatus of this invention. 1 is a block diagram showing a configuration of an embodiment of a flash memory according to the present invention. FIG. It is a time chart explaining one Example of the reset process of this invention. It is a time chart of one Example of the reset process at the time of the erasure | elimination process of this invention. It is a flowchart of Example 1 of the reset process of this invention. It is a flowchart of Example 2 of the reset process of this invention.

The best mode for carrying out the present invention will be described below with reference to the drawings. However, this does not limit the present invention.
In the following embodiments, the first reset signal described above corresponds to a reset start signal, and the second reset signal corresponds to a reset request signal.
<Configuration of information processing apparatus>
FIG. 1 shows a configuration block diagram of a portion related to reset processing of the information processing apparatus of the present invention.
In FIG. 1, a reset generation unit 1 is a part that outputs a reset start signal in response to an initialization request. When the user performs an input operation for initialization (reset request input), a reset start signal Rst Is the part that outputs
The reset request input includes, for example, pressing down the reset switch 12 or long pressing the power switch 13 for a predetermined number of seconds. The reset switch 12 and the power switch 13 correspond to an input unit for a user to input a forced initialization request.
The reset generation unit 1 always monitors whether there is a reset request input from the reset switch 12 or the like.

The reset generator 1 includes a terminal RO11 that outputs a reset start signal Rst.
When the reset generation unit 1 confirms that an input operation for depressing the reset switch 12 is performed by the user, a reset start signal Rst is output from the output terminal RO11.
In the following embodiments, when the reset start signal Rst is output, the output terminal RO is in the H state (for example, +5 V), and when not output, the output terminal RO is in the L state (for example, 0 V). To do.
This reset start signal Rst is given to the delay unit 2 and the control unit (CPU) 3.

The delay unit 2 is a part that outputs a signal (referred to as a reset request signal Rrq) requesting reset after a predetermined time (delay time Trd) has elapsed after the input start signal Rst is input.
The delay unit 2 includes at least an input terminal for inputting a reset start signal Rst and a terminal RD21 for outputting a reset request signal Rrq, and is configured by an existing delay circuit including a resistor, a capacitor, and the like.
As will be described later, for example, when the storage unit 4 is a flash memory, the length of the delay time Trd is data to be written to the flash memory given from the CPU from the viewpoint of preventing damage to data written to the flash memory. Is set in advance to be longer than both the maximum write time required to write the data in the memory cell of the flash memory and the maximum erase time required to erase the data in the memory cell.

Similarly to the reset start signal Rst, the reset request signal Rrq is a binary signal composed of an H state and an L state, and is given to a reset terminal of an electronic component to be reset.
For example, as shown in FIG. 1, the reset request signal Rrq is given to the control unit (CPU) 3 and the storage unit (flash memory) 4. In particular, in the storage unit 4, data write processing is actually performed. At a time when the delay is not performed, the signal is output from the delay unit 2 to the control unit 3 and the storage unit 4.
The reset terminal is a terminal mainly for initializing the function of the electronic component having the terminal when a reset signal is input. Immediately after the reset signal is input to the reset terminal, the initial state of the electronic component is reset. Is done.

The control part 3 is a part which performs the function of information processing apparatus, for example, is corresponded to CPU (central processing unit).
Alternatively, a microcomputer that incorporates a CPU, a ROM, a RAM, an I / O controller, a timer, and the like into one chip corresponds to the control unit 3.
Hereinafter, a case where a CPU is used as the control unit 3 will be described.
The CPU 3 has a large number of general-purpose input / output terminals (I / O terminals) and a reset terminal CR32.
The general-purpose input terminal PIN has a plurality of input terminals. In the present invention, the reset start signal Rst is input to one of the input terminals RI31.
That is, the output terminal RO11 of the reset generator 1 and the input terminal RI31 of the CPU 3 are electrically connected.
The reset terminal CR32 is a terminal for inputting the above-described reset request signal Rrq. For example, when a reset request signal in the H state is input for a predetermined time or more, the reset terminal CR32 is a terminal for initializing the CPU.
Even if the reset start signal Rst is input to the input terminal RI31, the CPU is not initialized. However, when the reset request signal Rrq is input to the reset terminal CR32, the CPU is forcibly initialized.

In the present invention, even when a data write request to the storage unit 4 is generated when the CPU 3 confirms that the reset start signal Rst is input to the input terminal RI31, the CPU 3 sends a write request to the storage unit 4. No command (hereinafter referred to as W command) is issued.
In other words, whether or not the reset start signal Rst is input to the input terminal RI31 before sending a write request command to the storage unit 4 when a data write request to the storage unit 4 occurs. If the reset start signal Rst is input, data writing to the storage unit 4 is not executed. That is, the control unit 3 does not issue a write request command (W command) to the storage unit 4.
As described above, when there is a possibility that the reset request signal Rrq is input to the reset terminal CR32 after a predetermined time has elapsed after the reset start signal Rst is input, the write request command is not issued to the storage unit 4. As a result, the data to be written to the storage unit 4 is prevented from being damaged.
On the other hand, when it is confirmed whether or not the reset start signal Rst is input, if the reset start signal Rst is not input, data is written to the storage unit 4.

The data terminal DT33 is a terminal for inputting / outputting data, addresses and commands, and is mainly connected to a data line (I / O line) 51 connected to the storage unit 4.
The R / B terminal 34 is an input terminal for receiving a notice of Ready or Busy from another electronic component connected to the R / B line 52 to the CPU.
For example, when the flash memory in the storage unit 4 is reading from or writing to the memory cell, the CPU 3 is notified via the R / B line 52 that the flash memory is busy.

The control terminal CNT35 is an output terminal that supplies various control signals to other electronic components via the control line 53.
The control terminal CNT35 includes a plurality of terminals. For example, the control terminal CNT35 receives control signals such as ALE (address latch enable), CLE (command latch enable), CE (chip enable), WE (write enable), and RE (read enable). , Each of which consists of a terminal group that transmits to the control line 53.
ALE and CLE are control signals for distinguishing whether information input / output via the data line 51 is data, command or address, and CE indicates that the CPU is using the data bus. WE is a control signal indicating that data is being written to the storage unit 4 via the data line 51, and RE is a control indicating that data is being read from the storage unit 4. Signal.

For example, when data is written from the CPU 3 to the flash memory 4, the data (D 1, D 2,... Dn) to be written is output to the data line 51 in a state where the WE signal is output to the control line 53. A request command (W command) is transmitted to the data line 51.
Thereafter, a Busy signal is transmitted from the flash memory 4 to the CPU 3 to the R / B line 52 while data is being written to the memory cell of the flash memory.

The storage unit 4 is a part that stores information, and corresponds to a semiconductor storage element such as a ROM, a RAM, or a flash memory.
In the following embodiments, a case where a flash memory is used as the storage unit 4 will be described.
The flash memory 4 also mainly includes a reset terminal FR41, a data terminal DT43, an R / B terminal 44, and a control terminal CNT45.
The data terminal DT43 is connected to the data terminal DT33 of the CPU 3 via the data line 51, and the R / B terminal 44 is connected to the R / B terminal 34 of the CPU 3 via the R / B line 52. The control terminals CNT45 are connected to the control terminals 35 of the corresponding CPUs 3 through the control lines 53, respectively.
The reset terminal FR41 is a terminal for inputting the above-described reset request signal Rrq. For example, when the reset request signal in the H state is input for a predetermined time or more, the reset terminal FR41 is a terminal for immediately initializing the flash memory itself.

In the present invention, the reset request signal Rrq output from the delay unit 2 is input to the reset terminal CR32 of the CPU 3 and the reset terminal FR41 of the flash memory 4 almost simultaneously.
As described above, even when the reset start signal Rst is output from the reset generation unit 1, the reset request signal Rrq after a delay time longer than the time required for the writing process and the erasing process in the memory cell of the flash memory has elapsed. Is input to the reset terminal FR41 of the flash memory 4.
That is, according to the present invention, during the writing process to the memory cell of the flash memory, the delay time is set so that the reset request signal Rrq is not input to the reset terminal FR41, and the writing process to the memory cell is actually performed. If not, the reset request signal Rrq output from the delay unit 2 is input to the reset terminal FR.

<Configuration of flash memory>
FIG. 2 shows a configuration block diagram of an embodiment of the flash memory 4.
FIG. 2A shows a schematic configuration of a NAND flash memory. The flash memory 4 is mainly composed of a controller 46, a memory cell 47, and a page buffer 48.
The NAND flash memory 4 generally does not have an address bus, and a write command, a read command, and the like are input / output from the data terminal 43 via the data line 51, and write start, page address designation, memory cell Processing such as rewriting and reading of page data is performed.

The command, the specified address, and the write data are all input to the controller 46 via the data line 51, and the command is distinguished based on the control signal input to the control terminal 45.
For example, when ALE is input to the corresponding control terminal 45, the data input to the data terminal 43 is an address, and when CLE is input to the corresponding control terminal 45, The input data is processed as a command.

The controller 46 is a part that controls reading and writing of data with respect to the memory cell 47 using a control signal input / output from the outside.
Data reading and writing are performed via the page buffer 48.
The page buffer 48 is a part that temporarily stores data to be stored in the memory cell 47 and is a volatile memory.
The memory cell 47 is a non-volatile memory including a plurality of pages, and is a memory in which data is written and read in units of pages. In addition, data erasure processing is performed in units of blocks composed of a plurality of pages.
In addition, in the flash memory, when data is written to the memory cell 47, the data cannot be directly overwritten on a desired page, but data in a predetermined block area is once read and temporarily stored in the block. After erasing the area, the held data including the data to be written is written back (rewritten) to the erased block area.

When the controller 46 receives write data (D 1 to Dn) from the data line 51, the write data is first transferred to the page buffer 48. Thereafter, when a write request command (W command) is input via the data line 51, the data temporarily stored in the page buffer 48 is written to the designated page in the memory cell 47.
While data is being written to the memory cell 47, a Busy signal is output from the R / B terminal 44 to the CPU 3 via the R / B line 52.
As signals output from the R / B terminal 44, there are a Ready signal and a Busy signal. The Ready signal indicates that it is currently in a ready state and is capable of accepting an external control signal. The Busy signal is currently executing internal processing such as writing, and an external control signal. Is in a state where it cannot accept.
In the following description, it is assumed that when the R / B terminal 44 is in the L state, it is in the output state of the Ready signal, and in the H state, it is in the output state of the Busy signal.

FIG. 2B shows a time chart of an embodiment of information input to the data terminal DT43 and a signal output from the R / B terminal 44.
In FIG. 2B, first, assuming that write data (D1 to Dn) is input via the data line 51, the input write data (D1 to Dn) is transferred to the page buffer 48.
During the transfer period to the page buffer 48, the write data is only stored in the page buffer 48. Therefore, even if a reset is applied and the data stored in the page buffer 48 is erased, the memory cell 47 The data stored in the memory is not affected, and the written data itself is not yet saved, but no damage occurs.

Thereafter, after the transfer of data (D1 to Dn) to the page buffer 48 is completed, a write request command (W command) is input to the data terminal 43.
When the controller 46 confirms the W command, the Busy signal is output from the R / B terminal 44, the data line 51 is in the Busy state, and the data (D1 to Dn) stored in the page buffer 48 is stored in the memory. The data is written at a predetermined page position in the cell 47.
While data is being written to the memory cell 47 (memory cell transfer period), a busy signal in the H state is output from the R / B terminal 44.
After writing to the memory cell 47 is completed, that is, after the memory cell transfer period has elapsed, a Ready signal is output from the R / B terminal 44.
In the present invention, the reset request signal Rrq is prevented from being input to the reset terminal FR41 during the memory cell transfer period.
Further, even if a data write request occurs in the CPU 3, if the reset start signal Rst has already been input, the write request command is not transferred to the flash memory 4 via the data line 51. Like that.

<Description of reset processing>
FIG. 3 shows a time chart of an embodiment of a reset process performed on the CPU 3 and the flash memory 4 when a reset signal is output from the reset generator 1.
FIG. 3A shows an explanatory diagram when the reset request signal Rrq is input to the CPU 3 and the flash memory 4 after the memory cell transfer period ends.
In FIG. 3A, initially, write data (D1 to Dn) is transferred from the CPU 3 to the flash memory 4 via the data line 51 in a state where neither the reset start signal Rst nor the reset request signal Rrq is output. And is transferred to the page buffer 48 in the page buffer transfer period.
Thereafter, when the CPU 3 confirms that the reset start signal Rst is not input to the input terminal RI31, it outputs a write request command (W command) to the data line 51.

When the flash memory 4 confirms that the W command has been received, the flash memory 4 starts a process of transferring the write data (D1 to Dn) temporarily stored in the page buffer 48 to the memory cell 47.
At this time, it is assumed that it takes only the memory cell transfer period Tbs to transfer data from the page buffer 48 to the memory cell 47. This memory cell transfer period Tbs corresponds to the maximum write time which is the maximum value of the time for writing data to the page of the memory cell.
It is assumed that after the transfer to the memory cell 47 is started, the reset switch 12 is pushed down during the transfer, and an H-state reset start signal Rst is output from the output terminal RO11 of the reset generation unit 1.
The reset start signal Rst is input to the CPU input terminal RI31 and the delay unit 2.
When the reset start signal Rst is input, the delay unit 2 delays by a predetermined delay time Trd and outputs an H-state reset request signal Rrq from the output terminal RD21.
The delay time Trd is set in advance to a time sufficiently longer than the time required to write data to the memory cell (maximum write time Tbs).

Therefore, since Trd> Tbs, after the memory cell transfer period Tbs has elapsed and the writing of all data to the memory cells is completed, the reset request signal Rrq is sent to the reset terminal CR32 of the CPU 3 and the reset terminal FR41 of the flash memory 4. Entered. When this reset request signal Rrq is input to the reset terminals (CR, FR), the CPU and the flash memory are actually reset.
Since the reset request signal Rrq is given to the CPU and the flash memory after the data write to the memory cell is completed, the write to the memory cell is not performed during execution of the actual reset process, and the write data is stored in the memory cell. Data is not erroneously written, and data corruption is prevented.

FIG. 3B shows an explanatory diagram when the CPU 3 confirms that the reset start signal Rst is input before issuing a write request command to the flash memory 4.
In this case, even if there is a write request to the memory for the write data, the reset request signal Rst is input, so that a write request command is not transmitted to the flash memory 4.
In FIG. 3B, the write data (D1 to Dn) is transmitted to the flash memory 4 in a state where the reset signal (Rst, Rrq) is not output, and is transferred to the page buffer 48 in the page buffer transfer period. Suppose.
Thereafter, it is assumed that the reset start signal Rst is input to the input terminal RI31 and the delay unit 2 of the CPU 3 before the CPU 3 issues a write request command (W command) to the flash memory 4.

When the CPU 3 confirms that the reset start signal Rst has been input, the CPU 3 does not issue the W command that should have been output.
Thereafter, when the reset start signal Rst is input to the delay unit 2, the reset request signal Rrq is output from the output terminal RD 21 of the delay unit 2 to the CPU 3 and the flash memory 4 after the delay time Trd has elapsed.
When the reset request signal Rrq is input to the reset terminals (CR, FR) of the CPU 3 and the flash memory 4, initialization is performed.
In the flash memory 4, when initialization is performed, data (D1 to Dn) stored in the page buffer 48 is lost, but writing to the memory cell has not yet been performed. The write data is not damaged.

FIG. 4 shows an explanatory diagram when the CPU 3 confirms the input of the reset start signal Rst after issuing the erase command (E command) to the flash memory.
As shown in FIG. 3 above, the reset request signal Rrq is not input during data writing to the memory cell 47 itself to prevent data corruption. However, the data in the memory cell 47 is erased. It is necessary to prevent the reset request signal Rrq from being input even when
If the flash memory 4 receives an erase command from the CPU 3 and the erase process of the memory cell 47 is executed and before the erase process is completed, the reset request signal Rrq is input. This is because the data stored in the memory cell 47 may be interrupted.

As shown in FIG. 4, the delay time Trd is set to a time sufficiently longer than the time required for erasing the memory cell (maximum erase time Te), and the timing at which the reset request signal Rrq is input is delayed (Te <Trd).
For example, as shown in FIG. 4, after an erase command (E command) is issued from the CPU 3 to the flash memory 4, the reset start signal Rst is sent from the reset generation unit 1 during the erase process of the memory cell 47. Suppose that it is output.
When the reset start signal Rst is input to the delay unit 2, the reset request signal Rrq is output after being delayed by the delay time Trd (> Te) and input to the CPU 3 and the flash memory 4.
Since Trd> Te, the reset request signal Rrq is input to the CPU 3 and the flash memory 4 after the maximum erase time Te has already elapsed and the erase process of the memory cell is completed.

Thereafter, the CPU 3 and the flash memory 4 are initialized by resetting, but the initialization process is performed in a state where the process for the memory cell 47 is not performed, so that the data in the memory cell 47 is not damaged.
The delay time Trd is longer than the memory cell transfer period (maximum write time) Tbs shown in FIG. 3 (Trd> Tbs) and longer than the maximum erase period Te shown in FIG. 4 (Trd> Te). Must be set.
As described above, in the flash memory 4, data writing (rewriting) processing is performed in units of pages, whereas erasing processing is performed in units of blocks including a plurality of pages.
Accordingly, the time required for the erasing process is longer than the time required for the writing process, and generally Te> Tbs. Therefore, the delay time Trd may be longer than the maximum erasing period Te.

When Trd = Te + Tm is considered in consideration of the margin time Tm, at least the CPU 3 confirms that the reset start signal Rst is input after the reset start signal Rst is input as the time Tm. It is preferable to set a time in consideration of the time taken to determine whether to stop the erase command (E command).
Specifically, it is preferable to secure a sufficient time as the margin time Tm, which is at least twice Te.

<Example 1 of reset processing>
FIG. 5 shows a flowchart of the reset processing according to the first embodiment of the present invention.
Here, when the CPU 3 confirms that the reset start signal Rst has been input after the data write request is generated based on the program being executed, the CPU 3 issues a write request command to the flash memory 4. (W command) is not transferred.
In the flowchart of FIG. 5, only the processing related to the data write request and the reset processing is shown.
In step S1 of FIG. 5, the CPU 3 confirms that there is a data write request to the flash memory based on the program.
If there is no data write request, step S1 is looped. If there is a data write request, the process proceeds to step S2.
In step S2, the CPU 3 monitors the input terminal RI31 and checks whether or not the reset start signal Rst is input.

In step S3, when the reset start signal Rst is input, the process ends without transferring the write request command (W command) to the flash memory 4.
On the other hand, if the reset start signal Rst is not input, the process proceeds to step S4, and a write request command (W command) is transferred to the flash memory 4. As a result, the data requested to be written is written into the memory cell 47 of the flash memory. Thereafter, the process ends.
Thus, before the reset request signal Rrq is directly input to the reset terminals (CR, FR) of the CPU 3 and the flash memory 4, the CPU 3 confirms the reset start signal Rst, whereby the data is sent to the memory cell 47. If the reset start signal Rst is input before writing is actually performed, a data write request command is not sent to the flash memory 4.
Therefore, when a reset is executed, for example, when the user performs an input operation to depress the reset switch, it is possible to prevent unexpected data from being written to the memory cell 47 of the flash memory. Can be prevented.

<Example 2 of reset processing>
FIG. 6 shows a flowchart of the reset process according to the second embodiment of the present invention.
Here, unlike the first embodiment, the input of the reset start signal Rst is confirmed every time a predetermined time elapses, and it is detected that there is no input of the reset start signal in the reconfirmation after the predetermined time elapses. If so, a write request command is transferred to the flash memory 4.
On the other hand, if the reset start signal Rst is input even after a predetermined time has elapsed after the reset start signal Rst is input to the input terminal RI31 of the CPU 3, data is not written to the flash memory. To.
Thereby, erroneous input of a reset signal due to so-called chattering that occurs in the reset switch 12 or the like can be prevented.

In the flowchart of FIG. 6, the same number is assigned to the step performing the same process as in FIG. 5.
In FIG. 6, as in the flow of FIG. 5, in step S <b> 1 and S <b> 2, when there is a data write request, it is confirmed whether or not the reset start signal Rst is input.
In step S3, if the reset start signal Rst is not input, the process proceeds to step S4, the write request command (W command) is transferred to the flash memory 4, and the process ends.
On the other hand, when the reset start signal Rst is input, the process proceeds to step S11, and a timer for counting a predetermined set time is started.
In step S12, after the set time has elapsed, the process returns to step S2, and it is confirmed again whether or not the reset start signal Rst has been input.

Thereafter, if the reset start signal Rst is not input, the process proceeds to step S4, and a write request command (W command) is transmitted.
However, when the input of the reset start signal Rst is confirmed again, if the reset is actually input, the reset request signal Rrq output from the delay unit 2 after the delay time has elapsed is the CPU 3 Are input to the flash memory 4, the CPU 3 is initialized, and this flowchart is also terminated.

In this flowchart, the set time set in the timer is preferably longer than the delay time Trd.
Once the reset request signal Rrq is input after the delay time Trd has elapsed after confirming the input of the reset start signal Rst, the CPU itself can be reset before the timer set time elapses. It is.
If the reset does not occur even after the delay time Trd elapses, a timeout occurs in step S12, and the process returns to step S2 to reconfirm the reset start signal Rst.
Thereby, erroneous detection of the reset signal due to chattering or the like can be prevented.

DESCRIPTION OF SYMBOLS 1 Reset generation part 2 Delay part 3 Control part (CPU)
4 Storage unit (flash memory)
11 Output terminal RO
12 Reset switch 13 Power switch 21 Output terminal RD
31 Input terminal RI
32 Reset terminal CR
33 Data terminal DT
34 R / B terminal 35 Control terminal CNT
41 Reset terminal FR
43 Data terminal DT
44 R / B terminal 45 Control terminal CNT
51 Data line (I / O line)
52 R / B line 53 Control line Rst Reset start signal Rrq Reset request signal

Claims (6)

A reset generator for outputting a first reset signal in response to an initialization request;
A delay unit that outputs a second reset signal after a predetermined delay time has elapsed after the first reset signal is input;
A control unit including an input terminal for inputting the first reset signal and a reset terminal for inputting the second reset signal;
A storage unit including a reset terminal for inputting the second reset signal;
Before the control unit makes a data write request to the storage unit, the control unit checks whether or not the first reset signal is input, and if the first reset signal is input, the storage unit An information processing apparatus that does not execute data writing to a computer.   The control section executes data writing to the storage section when the first reset signal is not inputted when the presence of the first reset signal is confirmed. The information processing apparatus according to 1. The input terminal of the control unit is a general-purpose input terminal,
The delay time is set in advance to a time longer than either the maximum writing time required to write data to the storage unit or the maximum erasing time required to erase data in the storage unit,
2. The second reset signal is output from the delay unit to the control unit and the storage unit during a time when data is not actually written in the storage unit. Or the information processing apparatus according to 2; An input unit having a reset switch for inputting a forced initialization request;
When an input operation is performed to depress the reset switch,
The information processing apparatus according to claim 1, wherein the reset generation unit outputs the first reset signal.   After the first reset signal is input to the input terminal of the control unit, if the first reset signal is input even after a predetermined time has elapsed, data is not written to the storage unit. The information processing apparatus according to claim 1, wherein: The storage unit is a flash memory including memory cells composed of a plurality of pages.
6. The information processing apparatus according to claim 1, wherein writing and reading of data to and from the memory cell are performed in units of pages.

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