JP2016051829A - Light emitting device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of manufacturing processes in a manufacturing method of a wafer level light emitting device of forming internal wiring by electrolytic plating.SOLUTION: A light emitting device manufacturing method comprises: a process of preparing a wafer formed by arrangement of a plurality of semiconductor light emitting elements; a process of forming a first resin layer having an opening on an electrode of a semiconductor light emitting element which is formed in a manner such that positive and negative electrodes are to be short-circuited in a boundary region; a process of forming a first metal layer on the opening of the first resin layer by electrolytic plating; a process of forming a second resin layer having an opening on the first metal layer and the boundary region; a process of forming a second metal layer on the opening of the second resin layer on the first metal layer by electrolytic plating; a process of removing the first resin layer formed on the boundary region, by anisotropic etching using the second resin layer as a mask; a process of removing the electrode formed on the boundary region to isolate the positive and negative electrodes; and a process of dicing the wafer.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a method for manufacturing a light emitting device including a semiconductor light emitting element and a resin layer having internal wiring.

A light-emitting device using a semiconductor light-emitting element such as a light-emitting diode is widely used because it can be easily downsized and high luminous efficiency can be obtained.
A light-emitting device using a semiconductor light-emitting element can be broadly divided into a face-up type in which a surface on which a pad electrode is provided on the semiconductor light-emitting element is a surface opposite to the mounting substrate, and a light-emitting element that is a surface facing the mounting substrate. There are two types of face-down type with electrodes on the bottom surface.

  In the face-up type, the semiconductor light emitting element is mounted on a lead or the like, and the semiconductor light emitting element and the lead are connected by a bonding wire or the like. For this reason, when mounted on a mounting substrate and viewed in plan from the direction perpendicular to the surface of the substrate, a part of the bonding wire needs to be positioned outside the semiconductor light emitting element, and there is a limit to downsizing.

On the other hand, in the face-down type (flip chip type), when the pad electrode provided on the surface of the semiconductor light emitting element and the wiring provided on the mounting substrate are viewed in a plan view from a direction perpendicular to the surface of the mounting substrate, semiconductor light emission Electrical connection can be made by connecting means such as bumps or metal pillars located within the size range of the element.
As a result, it is possible to realize a CSP (Chip Size Package or Chip Scale Package) in which the size of the light emitting device (particularly, the size in plan view from the direction perpendicular to the mounting substrate) is reduced to a level close to the chip of the semiconductor light emitting element. .

  In recent years, there has been a face-down type light emitting device in which a growth substrate (translucent substrate) such as sapphire is removed or the thickness thereof is reduced in order to further reduce the size or increase the light emission efficiency. It is used.

The growth substrate is a substrate used for growing an n-type semiconductor layer and a p-type semiconductor layer constituting the semiconductor light-emitting device thereon, and supports the semiconductor light-emitting device having a small thickness and a low strength, thereby supporting the light-emitting device. It also has the effect of improving the strength.
For this reason, in the light emitting device in which the growth substrate is removed after the semiconductor light emitting element is formed or the light emitting device in which the thickness of the growth substrate is reduced, for example, as shown in Patent Document 1, in order to support the semiconductor light emitting element A resin layer is provided on the electrode side (the side facing the mounting substrate), and an internal wiring made of a metal pillar or other wiring is formed so as to penetrate the resin layer to electrically connect the electrode and the external terminal. It is configured as follows.
And by having the resin layer containing this internal wiring, a light-emitting device can ensure sufficient intensity | strength.

JP 2010-141176 A

  When a light emitting device is manufactured by WCSP (CSP manufactured at a wafer level), for example, Patent Document 1 describes that an internal wiring provided in a resin layer is formed by an electrolytic plating method. The manufacturing method described in Patent Document 1 will be described in more detail. In order to form internal wiring in a predetermined region, a seed layer serving as a current path in electrolytic plating is formed on the entire surface of the wafer via an insulating film. A plating mask is formed using a photoresist in an area where plating is not grown, and the mask is removed after electrolytic plating is completed. When the internal wiring has a multilayer structure, the formation of the plating mask, the electrolytic plating, and the removal of the plating mask are repeated for each layer. Then, after forming the internal wiring, a resin layer is formed so as to cover the internal wiring with resin. As described above, when forming the resin layer having the internal wiring, a large number of processes are required, and therefore, it is desired to reduce the number of manufacturing processes.

During the manufacturing process in the wafer state, it is not preferable to grow the plating on the boundary region of each light emitting device to be cut later in order to facilitate cutting. For this reason, when performing electroplating, the seed layer is covered with a plating mask in the boundary region. That is, when the internal wiring is formed by the electrolytic plating method, a step of forming a plating mask and a step of removing the plating mask after completion of the electrolytic plating are required, which requires a large number of steps.
Accordingly, an object of the present invention is to reduce the number of manufacturing steps in a method for manufacturing a light emitting device at a wafer level in which internal wiring is formed by electrolytic plating.

  In order to solve the above-described problems, a method for manufacturing a light emitting device according to an embodiment of the present invention includes a semiconductor light emitting device including a semiconductor stacked body and an electrode provided on one surface of the semiconductor stacked body. A plurality of the semiconductor light emitting elements are arranged and provided so that the electrodes of the adjacent semiconductor light emitting elements are short-circuited in a boundary region partitioning the semiconductor light emitting elements. A wafer preparing step of preparing a wafer, and a first resin layer forming step of forming a first resin layer having an opening in a part of a region where the electrode is provided on the one surface side of the semiconductor stacked body; A first metal layer forming step of forming a first metal layer on the electrode exposed in the opening of the first resin layer, and a region in which the first metal layer is formed on the first resin layer And the boundary A second resin layer forming step of forming a second resin layer having an opening in each region, and a second metal layer formed on the first metal layer exposed in the opening of the second resin layer A metal layer forming step, a first resin layer removing step of removing the first resin layer formed on the boundary region so that the electrodes are exposed, and the wafer along the boundary region. And an individualization step for individualizing each light emitting element.

  According to the method for manufacturing a light emitting device according to the embodiment of the present invention, the first resin layer is used as a plating mask, and the second resin layer is used as an etching mask for removing the plating mask. As a result, the number of manufacturing steps can be reduced.

It is a schematic diagram which shows the structure of the light-emitting device which concerns on embodiment of this invention, (a) is a top view, (b) is sectional drawing in the II line | wire of (a). It is a typical perspective view which shows the structure of the light-emitting device which concerns on embodiment of this invention. It is a typical top view which shows the layer structure of the light-emitting device which concerns on embodiment of this invention, (a) shows the arrangement | positioning area | region of a p-type semiconductor layer and a cover electrode, (b) shows the arrangement | positioning area | region of a light reflection electrode. . It is a typical top view which shows the layer structure of the light-emitting device which concerns on embodiment of this invention, (a) shows the arrangement | positioning area | region of an insulating film, (b) shows the arrangement | positioning area | region of an n side electrode and a p side electrode. It is a typical top view which shows the layer structure of the light-emitting device which concerns on embodiment of this invention, (a) shows the arrangement | positioning area | region of a 1st resin layer and a 1st metal layer, (b) shows a 2nd resin layer and 2nd resin layer. The arrangement | positioning area | region of 2 metal layers is shown. It is a flowchart which shows the flow of the manufacturing method of the light-emitting device which concerns on embodiment of this invention. It is typical sectional drawing which shows a part of manufacturing process of the light-emitting device which concerns on embodiment of this invention, (a) is a semiconductor laminated body formation process, (b) is a light reflection electrode formation process, (c) is a cover electrode. (D) shows an n-type semiconductor layer exposing step, and (e) shows an insulating film forming step. It is a schematic diagram which shows the pad electrode formation process in the manufacturing process of the light-emitting device which concerns on embodiment of this invention, (a) is a top view, (b) is sectional drawing in the II-II line of (a). It is typical sectional drawing which shows a part of manufacturing process of the light-emitting device which concerns on embodiment of this invention, (a) is 1st resin layer formation process, (b) is 1st metal layer formation process, (c) is A 2nd resin layer formation process is shown. It is typical sectional drawing which shows a part of manufacturing process of the light-emitting device which concerns on embodiment of this invention, (a) shows a 2nd metal layer formation process, (b) shows a 1st resin layer removal process. It is a schematic diagram which shows the pad electrode separation process in the manufacturing process of the light-emitting device which concerns on embodiment of this invention, (a) is a top view, (b) is sectional drawing in the II-II line of (a). It is typical sectional drawing which shows the growth substrate removal process in the manufacturing process of the light-emitting device which concerns on embodiment of this invention. It is a typical sectional view showing the composition of the light emitting device concerning the 1st modification of the embodiment of the present invention. It is typical sectional drawing which shows a part of manufacturing process of the light-emitting device which concerns on the 1st modification of embodiment of this invention, (a) is a 2nd metal layer formation process, (b) is a 1st resin layer removal process. Indicates. It is typical sectional drawing which shows the structure of the light-emitting device which concerns on the 2nd modification of embodiment of this invention. It is typical sectional drawing which shows a part of manufacturing process of the light-emitting device which concerns on the 2nd modification of embodiment of this invention, (a) is a 2nd metal layer formation process, (b) is a 1st resin layer removal process. Indicates.

Embodiments of a light emitting device and a method for manufacturing the same according to the present invention will be described below.
Note that the drawings referred to in the following description schematically show the present invention, and therefore the scale, spacing, positional relationship, etc. of each member are exaggerated, or some of the members are not shown. There is a case. In addition, the scale and interval of each member may not match between a perspective view, a plan view, and a cross-sectional view. Moreover, in the following description, the same name and the code | symbol are showing the same or the same member in principle, and suppose that detailed description is abbreviate | omitted suitably.

  Further, in the light emitting device according to each embodiment of the present invention, “upper”, “lower”, “left”, “right”, and the like are interchanged depending on the situation. In the present specification, “upper”, “lower” and the like indicate relative positions between components in the drawings referred to for explanation, and indicate absolute positions unless otherwise specified. Not intended.

[Configuration of light emitting device]
First, with reference to FIGS. 1-5, the structure of the light-emitting device which concerns on embodiment of this invention is demonstrated.
Note that the cross-sectional view shown in FIG. 1B schematically shows a cross-section taken along line II of the plan view shown in FIG. The positions A1 to A6 on the I-I line shown in FIG. 1A correspond to the positions A1 to A6 indicated by arrows in FIG. 1B, but in order to show the sectional structure in an easy-to-understand manner. The distance interval in the cross-sectional view of FIG. 1B is shown by appropriately extending or shortening the distance interval (length of the member) in the plan view of FIG. Does not match. Further, other sectional views to be described later also show a section corresponding to the II line of the plan view shown in FIG. 1A, as in FIG. 1B, unless otherwise specified.
3 to 5 show the arrangement area in a plan view for each layer by hatching in order to explain the laminated structure of the light emitting device 100 according to the present embodiment.

  As shown in FIGS. 1 to 5, the light emitting device 100 according to the present embodiment has a substantially square prism shape and an LED (light emitting diode) structure from which a growth substrate is removed. Hereinafter, the CSP is appropriately referred to as a “light emitting element”) and a support 2 provided on one surface side of the light emitting element 1. Moreover, although mentioned later for details, the light-emitting device 100 is WCSP (CSP by a wafer level process) produced at a wafer level.

  An n-side electrode 13 and a p-side electrode 15 are provided on one surface side of the light emitting element 1 (upper surface in FIG. 1B), and a first resin layer 21 and a second resin layer 22 are laminated. A support 2 is provided. Further, in the first resin layer 21 and the second resin layer 22, a first metal layer (n-side first metal layer) 31n and a first metal layer (p-side first metal layer) are provided as internal wirings, respectively. 31p, a second metal layer (n-side second metal layer) 32n, and a second metal layer (p-side second metal layer) 32p are provided. The second metal layer 32n is electrically connected to the n-side electrode 13 via the first metal layer 31n, the second metal layer 32p is electrically connected to the p-side electrode 15 via the first metal layer 31p, The upper surfaces of the second metal layers 32n and 32p exposed from the second resin layer 22 are mounting surfaces for electrical connection with the outside. In plan view, the second metal layer 32n is partitioned by the second resin layer 22 between the second metal layer 32n and the second metal layer 32p. Further, the upper surfaces of the second metal layers 32 n and 32 p have a “height” that is a distance from the semiconductor stacked body 12 in the stacking direction of the semiconductor stacked body 12 higher than the upper surface of the second resin layer 22. Is provided. Further, the lower surface side of the light emitting element 1 is a light extraction surface.

  In the light emitting element 1, the growth substrate 11 (see FIG. 7A) used when forming the semiconductor stacked body 12 is removed, but the growth substrate 11 is left as it is or thinned by polishing. Also good. Further, a phosphor layer containing a phosphor may be provided on the back surface side of the semiconductor stacked body 12 after the growth substrate 11 is peeled off or on the back surface side of the growth substrate 11.

Next, the configuration of each part of the light emitting device 100 will be described in detail sequentially.
The light-emitting element 1 is a face-down type LED chip having a plate-like shape having a substantially square shape in plan view and including an n-side electrode 13 and a p-side electrode 15 on one surface side.

  The light emitting element 1 includes a semiconductor stacked body 12 in which an n-type semiconductor layer 12n and a p-type semiconductor layer 12p are stacked. The semiconductor stacked body 12 emits light by passing a current between the n-side electrode 13 and the p-side electrode 15, and an active layer 12a is provided between the n-type semiconductor layer 12n and the p-type semiconductor layer 12p. It is preferable to provide.

  As shown in FIGS. 1 and 3A, in the semiconductor stacked body 12, the p-type semiconductor layer 12p and the active layer 12a are not partially present, that is, n-type recessed from the surface of the p-type semiconductor layer 12p. A region where the semiconductor layer 12n is exposed (this region is referred to as a “first exposed portion 12b”) is formed. The light emitting element 1 is provided with a total of 12 circular first exposed portions 12b in three rows of four each in a plan view. The bottom surface of the first exposed portion 12b is the exposed surface of the n-type semiconductor layer 12n, and the n-type semiconductor layer 12n is connected to the n-type semiconductor layer 12n through the opening 16n of the insulating film 16 provided in a part of the bottom surface of the first exposed portion 12b. The n-side electrode 13 is electrically connected.

A second exposed portion 12 c that is a region where the p-type semiconductor layer 12 p and the active layer 12 a do not exist is provided along the outer periphery of the semiconductor stacked body 12. The second exposed portion 12c is provided in a boundary region (dicing street) that is a region along the boundary line 40 (see FIG. 7D) of the light emitting element 1 in the wafer state.
The first exposed portion 12b and the second exposed portion 12c are all or partly covered with the insulating film 16, the first resin layer 21, the second resin layer 22, and the like in the completed light emitting device 100. For convenience, it is called an “exposed portion”.

  Further, the side surface serving as the outer edge of the semiconductor stacked body 12 in plan view, that is, the side surface serving as the outer edge of the n-type semiconductor layer 12 n is not covered with either the insulating film 16 or the first resin layer 21. In the individualization step S114 (see FIG. 6), which is the last step of the manufacturing process of the light emitting device 100 by the wafer level process, the semiconductor stacked body 12 is cleaved, and the cut section is formed as a side surface that becomes an outer edge in plan view. . For this reason, in the separated light emitting device 100, the side surface that is the outer edge of the semiconductor stacked body 12 is exposed.

  Further, as shown in FIGS. 1B, 3A, and 3B, a light reflecting electrode 14a and a cover electrode 14b are formed on substantially the entire upper surface of the p-type semiconductor layer 12p of the semiconductor stacked body 12. Is provided on the entire surface electrode 14. That is, in FIG. 3A, the hatched region is a region where the p-type semiconductor layer 12p and the cover electrode 14b are provided. The light reflecting electrode 14a is covered with a cover electrode 14b on the top and side surfaces, and is included in the region where the cover electrode 14b is arranged in plan view as shown by hatching in FIG. It is arranged in the inner area.

  Further, as shown in FIGS. 1B and 4A, the upper surface and side surfaces of the full-surface electrode 14 and the upper surface and side surfaces of the semiconductor stacked body 12 (regions hatched in FIG. 4A). Is provided with an insulating film 16. The insulating film 16 has an opening 16n on the bottom surface of the first exposed portion 12b, and an opening 16p on a part of the cover electrode 14b. The openings 16n are provided in a circular shape on the bottom surfaces of the first exposed portions 12b provided at twelve locations, and the openings 16p are rectangular shapes with rounded corners at ten locations on the cover electrode 14b. Is provided. The insulating film 16 also has an opening on the bottom surface of the second exposed portion 12c. However, the insulating film 16 may cover the top surface of the n-type semiconductor layer 12n to the end without having the opening. Good.

As shown in FIGS. 1B and 4B, the p-side electrode 15 that is the p-side pad electrode of the light-emitting element 1 is electrically connected to the cover electrode 14b in the opening 16p. Further, the insulating film 16 is formed so as to extend to a part of the upper surface of the cover electrode 14b and the side surface and the bottom surface of the second exposed portion 12c in the right half region in FIG.
In addition, the n-side electrode 13 which is the n-side pad electrode of the light emitting element 1 is electrically connected to the n-type semiconductor layer 12n in the opening 16n, and the first exposed portion 12b of the first exposed portion 12b is interposed through the insulating film 16. The bottom and side surfaces, the region where the p-side electrode 15 is provided, and the upper and side surfaces of the cover electrode 14b excluding the vicinity thereof, and the side and bottom surfaces of the second exposed portion 12c are provided.
That is, in the light emitting element 1, both the n-side electrode 13 and the p-side electrode 15 are provided on one surface side of the semiconductor stacked body 12.
In addition, by providing the n-side electrode 13 and / or the p-side electrode 15 in a wide range on the upper surface and side surface of the light emitting element 1 as described above, heat is efficiently applied to the resin layer 31 of the support 3 described later. The heat dissipation of the light emitting device 100 can be improved.

The semiconductor laminate 12 (n-type semiconductor layer 12n, the active layer 12a and the p-type semiconductor layer 12p) _{is, In X Al Y Ga 1-} X-Y N (0 ≦ X, 0 ≦ Y, X + Y <1) , etc. Preferred is Used for. In addition, each of these semiconductor layers may have a single layer structure, but may have a laminated structure of layers having different compositions and film thicknesses, a superlattice structure, or the like. In particular, the active layer 12a preferably has a single quantum well or multiple quantum well structure in which thin films that produce quantum effects are stacked.

The full-surface electrode 14 has a function as a current diffusion layer and a reflection layer, and is configured by laminating a light reflection electrode 14a and a cover electrode 14b.
The light reflecting electrode 14a is provided so as to cover substantially the entire upper surface of the p-type semiconductor layer 12p. A cover electrode 14b is provided so as to cover the entire upper surface and side surfaces of the light reflecting electrode 14a. The light reflecting electrode 14a is a layer for uniformly diffusing the current supplied through the cover electrode 14b and the p-side electrode 15 provided on a part of the upper surface of the cover electrode 14b to the entire surface of the p-type semiconductor layer 12p. It is. In addition, the light reflecting electrode 14a has good light reflectivity, and also functions as a layer that reflects light emitted from the light emitting element 1 in a downward direction as a light extraction surface.

  The light reflecting electrode 14a can be made of a metal material having good conductivity and reflectivity. In particular, as a metal material having good reflectivity in the visible light region, Ag, Al, or an alloy containing these metals as a main component can be preferably used. The light reflecting electrode 14a may be a single layer or a laminate of these metal materials.

The cover electrode 14b is a barrier layer for preventing migration of the metal material that constitutes the light reflecting electrode 14a. In particular, when the light reflecting electrode 14a is made of Ag that easily causes migration or an alloy containing Ag as a main component, the cover electrode 14b is preferably provided.
As the cover electrode 14b, a metal material having good conductivity and barrier properties can be used. For example, Al, Ti, W, Au, AlCu alloy, or the like can be used. The cover electrode 14b may be a single layer or a laminate of these metal materials.
In FIG. 1, the arrangement region of the cover electrode 14b in plan view is shown so as to coincide with the arrangement region of the p-type semiconductor layer 12p for convenience, but the cover electrode 14b is formed from the p-type semiconductor layer 12p. Is also provided slightly inside. The same applies to the manufacturing process diagrams described later.

The n-side electrode 13 is electrically connected to the n-type semiconductor layer 12n through the opening 16n of the insulating film 16 on the bottom surface of the first exposed portion 12b provided at twelve locations. By connecting to the n-type semiconductor layer 12n in such a wide range, the current supplied through the n-side electrode 13 can be evenly diffused to the n-type semiconductor layer 12n, so that the light emission efficiency is improved. Can do.
In addition, the p-side electrode 15 is electrically connected to the cover electrode 14b in the openings 16p of the insulating film 16 provided at ten locations on the upper surface of the cover electrode 14b.
As shown in FIG. 5A, ten first metal layers 31 n are provided on the upper surface of the n-side electrode 13 so as to be electrically connected to the n-side electrode 13, and the upper surface of the p-side electrode 15. The ten first metal layers 31 p are provided so as to be electrically connected to the p-side electrode 15.

  As the n-side electrode 13 and the p-side electrode 15, a metal material can be used. For example, a single metal such as Ag, Al, Ni, Rh, Au, Cu, Ti, Pt, Pd, Mo, Cr, or W can be used. An alloy containing these metals as a main component can be preferably used. In addition, when using an alloy, you may contain nonmetallic elements, such as Si, as a composition element like an AlSiCu alloy (ASC), for example. In addition, the n-side electrode 13 and the p-side electrode 15 may be a single layer or a laminate of these metal materials. As the stacked structure, for example, Ti / ASC / Ni and Ti / ASC / Pd can be used sequentially from the semiconductor stacked body 12 side.

  The insulating film 16 is a film that covers the upper surface and side surfaces of the semiconductor stacked body 12 and the entire surface electrode 14. The insulating film 16 functions as a protective film and an antistatic film for the light emitting element 1. In addition, an n-side electrode 13 and a p-side electrode 15 are provided so as to extend complementarily over a wide area on the upper surface of the insulating film 16. As the insulating film 16, a metal oxide or a metal nitride can be used. For example, at least one oxide or nitride selected from the group consisting of Si, Ti, Zr, Nb, Ta, and Al is preferably used. Can be used. Alternatively, the insulating film 16 may be laminated by using two or more kinds of light-transmitting dielectrics having different refractive indexes to form a DBR (Distributed Bragg Reflector) film.

  Note that the light-emitting element 1 illustrated in FIG. 1 is an example, and the present invention is not limited to this. In the light emitting element 1, the n-side electrode 13 and the p-side electrode 15 may be provided on one surface side of the semiconductor stacked body 12, and the arrangement region of the first exposed portion 12 b, the n-side electrode 13 and the p-side electrode 15 Etc. can be determined as appropriate. Further, instead of or in addition to the first exposed portion 12b, the n-type semiconductor layer 12n and the n-side electrode 13 may be electrically connected by the second exposed portion 12c.

The support 2 has a quadrangular prism shape that is substantially the same as the outer shape of the light emitting element 1 in plan view, and is joined to the surface side of the light emitting element 1 on which the n-side electrode 13 and the p-side electrode 15 are provided. And a reinforcing member for mechanically maintaining the structure of the light-emitting element 1 from which the growth substrate 11 (see FIG. 7A) is removed. The support 2 is configured by laminating a first resin layer 21 having first metal layers 31n and 31p inside and a second resin layer 22 having second metal layers 32n and 32p inside.
The light emitting device 100 shown in FIG. 1 is configured such that the support 2 is included in the light emitting element 1 in plan view, but may be configured to overlap in the plan view. May be configured to include the light emitting element 1.

  The laminate composed of the first resin layer 21 and the second resin layer 22 is a base body as a reinforcing member of the light emitting element 1. As shown in FIG. 1, the first resin layer 21 and the second resin layer 22 are substantially the same as the outer shape of the light emitting element 1 in plan view, and the outer shape of the second resin layer 22 is the same as that of the first resin layer 21. It is formed to match the outer shape.

As shown in FIG. 1B and FIG. 5A, the first resin layer 21 includes ten first metal layers 31n and ten first metal layers as internal wirings so as to penetrate in the thickness direction. 1 metal layer 31p.
Further, as shown in FIG. 1B and FIG. 5B, the second resin layer 22 includes one second metal layer 32n and one piece as an internal wiring so as to penetrate in the thickness direction. The second metal layer 32p. The second resin layer 22 partitions the second metal layer 32n and the second metal layer 32p, which are two polar external connection electrodes, and an upper surface in a region that is an outer edge in plan view, and an upper surface in the partition region Are formed at the same height. For this reason, when the light-emitting device 100 is mounted face-down, the light-emitting device 100 can be satisfactorily adhered to the mounting substrate, and the adhesive material used on the second metal layer 32n side by the inner wall constituting the partition region can be used. It is possible to prevent the adhesive material used on the two metal layer 32p side from coming into contact.
In the second resin layer 22, the width of the region separating the second metal layer 32n and the second metal layer 32p is preferably about 200 μm or more and 500 μm or less.

  As the resin material for the first resin layer 21 and the second resin layer 22, those known in the art can be used, but it is preferable to use a photosensitive resin material used as a photoresist. By using the photosensitive resin material, the first resin layer 21 and the second resin layer 22 can be easily patterned by photolithography.

The combined thickness of the first resin layer 21 and the second resin layer 22 can be set at a lower limit so that the growth substrate has sufficient strength as a reinforcing member of the light-emitting element 1 that has been peeled or thinned.
For example, from the viewpoint of the reinforcing member, the total thickness of the first resin layer 21 and the second resin layer 22 is preferably about 30 μm or more, and more preferably about 90 μm or more.
Further, in consideration of the volume ratio of the metal in the first resin layer 21 and the second resin layer 22 and the heat generation amount of the light emitting element 1, the first resin layer 21 and the second resin layer 21 and the second resin layer 21 are obtained so that sufficient heat dissipation is obtained. The upper limit of the combined thickness of the resin layer 22 can be determined. For example, it is preferably about 150 μm or less, and more preferably about 120 μm or less.

The first resin layer 21 is provided so as to cover the boundary region of the light emitting element 1 formed in a wafer state in a first resin layer forming step S107 (see FIG. 6) of the manufacturing method described later. The first resin layer 21 formed in the boundary region is a first metal layer 31n, 31p and a second metal layer 32n in a first metal layer formation step S108 and a second metal layer formation step S110 (see FIG. 6) described later. , 32p is used as a plating mask for preventing the plating from growing in the boundary region. Then, the first resin layer 21 formed in the boundary region is removed by anisotropic etching using the second resin layer 22 formed in the second resin layer forming step S109 (see FIG. 6) as a mask. For this reason, the film thickness of the first resin layer 21 is formed thinner than the film thickness of the second resin layer 22.
Details of these manufacturing processes will be described later.

The first metal layer (n-side first metal layer) 31n is provided inside the first resin layer 21 so as to penetrate in the thickness direction, and is connected to the n-side electrode 13 that is the electrode of the light-emitting element 1 and the outside. This is an n-side internal wiring for electrically connecting the second metal layer 32n serving as an electrode for the purpose.
In the present embodiment, as shown in FIG. 5 (a), on the n-side electrode 13 (see FIG. 4 (b)) in the left half region of the light emitting device 100, 10 pieces arranged in two rows of 5 pieces each. A first metal layer 31n (a region hatched with a diagonal line rising to the right in FIG. 5A) is provided. In addition, the top surfaces of the ten first metal layers 31n are, as shown in FIGS. 1B and 5B, one second metal layer 32n (see FIG. 5) provided in the left half of the light emitting device 100. 5 (b) is electrically connected to the lower surface of the hatched area with a downward slanting line.

The first metal layer (p-side first metal layer) 31p is provided inside the first resin layer 21 so as to penetrate in the thickness direction, and is connected to the p-side electrode 15 that is the electrode of the light-emitting element 1 and the outside. This is a p-side internal wiring for electrically connecting the second metal layer 32p serving as an electrode for the purpose.
In the present embodiment, as shown in FIG. 5 (a), on the p-side electrode 15 (see FIG. 4 (b)) in the right half region of the light emitting device 100, 10 pieces arranged in two rows of 5 pieces each. A first metal layer 31p (a region hatched with a right-down oblique line in FIG. 5A) is provided. Further, the upper surfaces of the ten first metal layers 31p are formed as one second metal layer 32p (see FIG. 5B) provided in the right half of the light emitting device 100, as shown in FIGS. 5 (b) is electrically connected to the lower surface of the hatched area that is hatched to the right.

The second metal layer (n-side second metal layer) 32n is provided inside the second resin layer 22 so as to penetrate in the thickness direction, and the upper surface is an n-side that serves as a mounting surface for connection to the outside. Internal wiring.
As shown in FIG. 5A and FIG. 5B, in the present embodiment, one second metal layer 32n is provided in the left half region of the light emitting device 100, and on the lower surface of the second metal layer 32n. The upper surfaces of the ten first metal layers 31n are electrically connected.

The second metal layer (p-side second metal layer) 32p is provided inside the second resin layer 22 so as to penetrate in the thickness direction, and the upper surface is a mounting surface for connecting to the outside. Internal wiring.
As shown in FIGS. 5A and 5B, in the present embodiment, one second metal layer 32p is provided in the right half region of the light emitting device 100, and the lower surface of the second metal layer 32p is provided. The upper surfaces of the ten first metal layers 31p are electrically connected.

1 and 2 is formed so that the upper surfaces of the second metal layers 32n and 32p are flat surfaces that are horizontal (perpendicular to the stacking direction of the semiconductor stacked body 12). The entirety is provided so as to be higher than the upper surface of the second resin layer 22.
The upper surfaces of the second metal layers 32n and 32p may be formed to be the same height as or lower than the upper surface of the second resin layer 22. Moreover, the shape of the upper surface of the second metal layers 32n and 32p is not limited to this. The upper surfaces of the second metal layers 32n and 32p may be inclined flat surfaces or may have irregular shapes.

  The first metal layers 31n and 31p and the second metal layers 32n and 32p also function as a heat transfer path for radiating the heat generated by the light emitting element 1. Therefore, the one where the ratio of the volume of the metal with respect to the 1st resin layer 21 and the 2nd resin layer 22 is large is preferable.

As the first metal layers 31n and 31p and the second metal layers 32n and 32p, metals such as Cu, Au, and Ni can be suitably used. The first metal layers 31n and 31p and the second metal layers 32n and 32p may have a laminated structure using a plurality of types of metals. In particular, the second metal layers 32n and 32p whose upper surfaces are the mounting surfaces are at least the most suitable for preventing corrosion and improving the bondability with a mounting substrate using an Au alloy-based adhesive member such as Au-Sn eutectic solder. The upper layer is preferably formed of Au. In addition, when the lower layer portion of the second metal layers 32n and 32p is formed of a metal other than Au, such as Cu, the upper layer portion is formed of Ni / Au or Ni / Pd / in order to improve adhesion with Au. A laminated structure such as Au may be used.
Alternatively, solder such as Sn—Cu or Sn—Ag—Cu can be used as the adhesive member. In that case, it is preferable that the uppermost layer of the second metal layers 32n and 32p is made of a material that can provide good adhesion to the adhesive member to be used.
The first metal layers 31n and 31p and the second metal layers 32n and 32p can be formed by an electrolytic plating method. Details of the method of forming the first metal layers 31n and 31p and the second metal layers 32n and 32p will be described later.

[Operation of light emitting device]
Next, the operation of the light emitting device 100 will be described with reference to FIG.
The light emitting device 100 emits light through the first metal layers 31n and 31p when an external power source is connected to the second metal layers 32n and 32p, which are electrodes for connection with the outside, via a mounting substrate (not shown). A current is supplied between the n-side electrode 13 and the p-side electrode 15 of the element 1. When a current is supplied between the n-side electrode 13 and the p-side electrode 15, the active layer 12a of the light emitting element 1 emits light.

Light emitted from the active layer 12a of the light emitting element 1 propagates through the semiconductor stacked body 12, is emitted from the lower surface or the side surface of the light emitting element 1, and is extracted outside.
The light propagating upward in the light emitting element 1 is reflected by the light reflecting electrode 14a, is emitted from the lower surface of the light emitting element 1, and is extracted outside.

[Method for Manufacturing Light Emitting Device]
Next, with reference to FIG. 6, the manufacturing method of the light-emitting device 100 shown in FIG. 1 is demonstrated.
As shown in FIG. 6, the method for manufacturing the light emitting device 100 includes a semiconductor stacked body forming step S101, a light reflecting electrode forming step S102, a cover electrode forming step S103, an n-type semiconductor layer exposing step S104, and an insulating film forming. Step S105, pad electrode formation step S106, first resin layer formation step S107, first metal layer formation step S108, second resin layer formation step S109, second metal layer formation step S110, and first resin It includes a layer removal step S111, a pad electrode separation step S112, a growth substrate removal step S113, and an individualization step S114, and each step is performed in this order.
Further, the semiconductor stacked body forming step S101 to the pad electrode forming step S106 are included as a wafer preparation step for preparing the light emitting element 1 in a wafer state, and the light reflecting electrode forming step S102 and the cover electrode forming step S103 are included in the entire surface electrode forming step. Included as

Hereinafter, each step will be described in detail with reference to FIGS. 7 to 12 (see FIGS. 1 to 6 as appropriate). 7 to 12, the shape, size, and positional relationship of each member may be simplified or exaggerated as appropriate.
Further, in the manufacturing process of the light emitting device 100 at the wafer level, each process is performed in a state where a large number of light emitting elements are two-dimensionally arranged. FIGS. 7 to 12 show two light emitting elements in a cross-sectional view and 2 × 2 = 4 light emitting elements in a plan view, among a plurality of light emitting element arrays.
The cross-sectional views shown in FIGS. 7 to 12 correspond to the cross-section taken along the line I-I in FIG. 1A, similarly to the cross-sectional view shown in FIG. The cross section of is shown.

  In the method for manufacturing a light-emitting device according to an embodiment of the present invention, first, a wafer preparation process is performed in which a light-emitting element 1 in which a plurality of light-emitting elements 1 are arranged on a single growth substrate 11 is prepared. In the wafer preparation process, as described above, the semiconductor laminate forming process S101, the light reflecting electrode forming process S102, the cover electrode forming process S103, the n-type semiconductor layer exposing process S104, the insulating film forming process S105, the pad Electrode forming step S106.

  First, in the semiconductor stacked body forming step S101, as shown in FIG. 7A, an n-type semiconductor layer 12n, active layers 12a and p are formed on the upper surface of a growth substrate 11 made of sapphire or the like using the semiconductor material described above. The semiconductor stacked body 12 is formed by sequentially stacking the type semiconductor layers 12p.

  Next, in the light reflecting electrode formation step S102, as shown in FIG. 7B, the light reflecting electrode 14a is formed in a predetermined region. The light reflecting electrode 14a can be formed by a lift-off method. That is, after forming a resist pattern having an opening in the region where the light reflecting electrode 14a is disposed by photolithography, a metal material having good reflectivity such as Ag is formed on the entire surface of the wafer by sputtering or vapor deposition. Film. Then, by removing the resist pattern, the deposited metal material is patterned, and the light reflecting electrode 14a is formed.

  Next, in the cover electrode forming step S103, as shown in FIG. 7C, the cover electrode 14b is formed so as to cover the upper surface and side surfaces of the light reflecting electrode 14a. The cover electrode 14b is formed by depositing a metal material on the entire surface of the wafer by sputtering or vapor deposition using a predetermined metal material, and then forming a resist pattern having an opening in the region where the cover electrode 14b is disposed by photolithography. Form. And the metal material formed into a film is patterned by etching using the said resist pattern as a mask, and the cover electrode 14b is formed by removing a resist pattern after that.

Next, in the n-type semiconductor layer exposing step S104, as shown in FIG. 7D, the p-type semiconductor layer 12p, the active region of the partial region of the semiconductor stacked body 12 as shown in FIG. Part of the layer 12a and the n-type semiconductor layer 12n is removed by dry etching to form a first exposed portion 12b and a second exposed portion 12c where the n-type semiconductor layer 12n is exposed on the bottom surface.
Note that an etching mask (not shown) at the time of dry etching is formed so as to cover the cover electrode 14b by photolithography. Therefore, in FIG. 7D, for convenience, the end portion of the cover electrode 14b and the end portion of the p-type semiconductor layer 12p (that is, the end portions of the first exposed portion 12b and the second exposed portion 12c) coincide. Although described, the p-type semiconductor layer 12p is left in a range wider than the region where the cover electrode 14b is disposed by the thickness of the etching mask provided on the side surface of the cover electrode 14b.

Next, in the insulating film forming step S105, as shown in FIG. 7E, an opening 16n and an opening are formed in a part of the upper surface of the first exposed portion 12b and the cover electrode 14b using a predetermined insulating material, respectively. An insulating film 16 having a portion 16p is formed. In addition, the insulating film 16 is formed so as to open also at a part of the bottom surface of the second exposed portion 12 c that is a region along the boundary line 40. Note that the entire bottom surface of the second exposed portion 12c may be covered with the insulating film 16 without having an opening.
The insulating film 16 can be patterned by forming an insulating film over the entire surface of the wafer by sputtering or the like, forming a resist pattern having an opening in the predetermined region, and etching the insulating film.

Next, in a pad electrode formation step (electrode formation step) S106, as shown in FIG. 8, a metal layer 50 is formed on the insulating film 16 by, for example, sputtering. The metal layer 50 can be patterned by, for example, a lift-off method.
The metal layer 50 becomes the n-side electrode 13 and the p-side electrode 15 which are pad electrodes as the light emitting element 1. Therefore, the metal layer 50 is connected to the n-type semiconductor layer 12n at the opening 16n of the insulating film 16 provided in the region to be the n-side electrode 13 (the region to which the hatching of the right-down oblique line in FIG. 8 is applied). Has been. In addition, the metal layer 50 is connected to the cover electrode 14b at the opening 16p of the insulating film 16 provided in the region to be the p-side electrode 15 (the region to which the hatching of the right-up oblique line in FIG. 8 is applied). Yes.

In the region of each light emitting element 1 partitioned by the boundary line 40, the metal layer 50 is formed separately so that the region serving as the n-side electrode 13 and the region serving as the p-side electrode 15 do not contact each other. Are connected in a region along the boundary line 40, and are formed so that the metal layers 50 of all the light-emitting elements 1 arranged on the wafer are conductive.
The metal layer 50 is used as a seed layer when the first metal layers 31n and 31p are formed by the electrolytic plating method in the first metal layer forming step S108 which is a subsequent step, and the second metal layer forming step S110 in the second metal layer forming step S110. It is also used as a seed layer when the metal layers 32n and 32p are formed by an electrolytic plating method, that is, as a current path. In the present embodiment, the metal layer 50 to be the n-side electrode 13 and the p-side electrode 15 that are pad electrodes is formed so as to serve also as a seed layer for electrolytic plating, so that the manufacturing process can be simplified.

Next, in the first resin layer forming step S107, as shown in FIG. 9A, the first resin layer 21 is formed on the metal layer 50 by photolithography. The first resin layer 21 is formed so as to have an opening 21 n on a region that becomes the n-side electrode 13 of the metal layer 50 and an opening 21 p on a region that becomes the p-side electrode 15 of the metal layer 50. .
The first resin layer 21 is formed so as to cover the metal layer 50 provided in the second exposed portion 12c, which is the boundary region, and the first metal layer forming step S108 and the second metal layer forming step which are subsequent steps. In S110, it is used as a plating mask for preventing plating growth in the boundary region.

In FIG. 9A, the first exposed portion 12b (see FIG. 7D) formed in the element region is completely filled with the first resin layer 21.
When the first resin layer 21 is formed by the photolithography method, first, a liquid photoresist is uniformly applied on the wafer by a coating method such as a spin coating method or a spray method, and further an exposure / development process is performed. As a result, the openings 21n and 21p are formed. During the application of the photoresist, small recesses on the wafer surface are filled with the photoresist. In FIG. 9A, for the sake of convenience, the widths of the first exposed portion 12b and the second exposed portion 12c are shown to be approximately the same, but the first exposed portion 12b is larger than the width of the second exposed portion 12c. Since the width of the first exposed portion 12b is sufficiently narrow, the first exposed portion 12b is completely filled with the photoresist when applied, and as a result, a recess is formed on the surface of the first resin layer 21 located on the first exposed portion 12b. It will be in a state that is not.
The first exposed portion 12b does not need to be completely filled with a photoresist, and a recess may be formed on the surface of the first resin layer 21. In this case, the concave portion is filled with the second resin layer 22 in the second resin layer forming step S109.

The first resin layer 21 formed in the boundary region is removed by anisotropic etching using the second resin layer 22 as a mask in the first resin layer removal step S111. For this reason, it is preferable to form the maximum film thickness of the first resin layer 21 formed in the boundary region so as to be smaller than the minimum film thickness of the second resin layer 22. With this configuration, even when the film thickness of the second resin layer 22 is uneven when the first resin layer 21 in the boundary region is removed by etching in the first resin layer removing step S111, the second resin It is possible to prevent the region 22 from being completely removed.
The film thickness of the 1st resin layer 21 should just be more than the thickness which can be used as an above-described plating mask, and it is preferable that it is the thickness which is easy to remove in 1st resin layer removal process S111. The film thickness of the first resin layer 21 can be, for example, about 10 μm to 20 μm.

  Thus, since the first resin layer 21 constituting the support 2 is used as a plating mask formed by the electrolytic plating method, the first metal layer 31n, 31p and the second metal layer 32n, 32p are used. The step of separately forming a plating mask used in the formation step S108 and the second metal layer formation step S110 and the step of removing the plating mask can be omitted.

Next, in the first metal layer forming step S108, as shown in FIG. 9B, the first metal layers 31n and 31p are formed in the openings 21n and 21p of the first resin layer 21 by electrolytic plating. . As described above, the first metal layers 31n and 31p use the metal layer 50 formed so as to be conductive as a whole as a seed layer serving as a current path for electrolytic plating, and the opening 21n of the first resin layer 21. , 21p.
Moreover, in this process, since the metal layer 50 is covered with the first resin layer 21 in the second exposed portion 12c that is a region along the boundary line 40, plating growth does not occur. Accordingly, since a thick plating layer is not formed in the boundary region, the unnecessary metal layer 50 can be easily removed in the pad electrode separation step S112 which is a subsequent step.

  In the example shown in FIG. 9B, the upper surfaces of the first metal layers 31n and 31p are formed at the same height as the upper surface of the first resin layer 21, but the present invention is not limited to this. The upper surfaces of the first metal layers 31 n and 31 p may be formed to be higher or lower than the upper surface of the first resin layer 21.

Next, in the second resin layer forming step S109, as shown in FIG. 9C, the second resin layer 22 is formed on the first resin layer 21 by photolithography. The second resin layer 22 has an opening 22n including a region where the first metal layer 31n is formed and an opening 22p including a region where the first metal layer 31p is formed in a plan view. Formed. Furthermore, the second resin layer 22 has an opening 22 a on a region along the boundary line 40, and is formed separately for each region of each light emitting element 1.
Further, in the region along the boundary line 40, that is, in the second exposed portion 12 c that is the outer edge portion of the completed light emitting device 100, the side surface of the second resin layer 22 covers the side surface of the second exposed portion 12 c. It is formed so as to be in the same position as the side surface of one resin layer 21 in plan view.

  9C, the thickness of the second resin layer 22 and the metal layer 50 (from the n-type semiconductor layer 12n (see FIG. 9A) on the bottom surface of the first exposed portion 12b and the second exposed portion 12c). Although the thickness up to the upper surface in FIG. 9A is described for the sake of convenience, the thickness of the second resin layer 22 is different from the thickness of the latter, which is about several μm. Is sufficiently thick, for example, about 20 μm or more. Therefore, as described above, even when a recess is formed on the surface of the first resin layer 21 filled in the first exposed portion 12b (see FIG. 7D), the recess is not formed in the second resin layer. It is filled with 22 being filled.

  Next, in the second metal layer forming step S110, as shown in FIG. 10A, the second metal layers 32n and 32p are formed in the openings 22n and 22p of the second resin layer 22 by electrolytic plating. . As described above, the second metal layers 32n and 32p are formed by using the metal layer 50 and the first metal layers 31n and 31p, which are formed so as to be conductive as a whole, as seed layers for electrolytic plating, that is, current paths. The two resin layers 22 are formed by plating in the openings 22n and 22p. At this time, the electrolytic plating is finished in a state where the upper surfaces of the second metal layers 32 n and 32 p are at the same height as the upper surface of the second resin layer 22.

In the first resin layer removing step S111, the second resin layer 22 is etched from the upper surface, so that the film thickness is reduced. Therefore, in consideration of the film thickness of the second resin layer 22 after the first resin layer removal step S111, the second metal layers 32n and 32p are formed more than the upper surface of the second resin layer 22 when the light emitting device 100 is completed. The film thickness of the second metal layers 32n and 32p depends on the conditions for electrolytic plating so that the upper surface is higher or lower, or the upper surfaces of the second metal layers 32n and 32p are the same height as the upper surface of the second resin layer 22. You may make it adjust. Further, instead of or in addition to the adjustment of the film thickness of the second metal layers 32n and 32p, the film thickness of the second resin layer 22 formed in the second resin layer forming step S109 may be adjusted.
In this way, the relative positional relationship between the upper surface of the second resin layer 22 and the upper surfaces of the second metal layers 32n and 32p can be arbitrarily adjusted.

  Further, when the second metal layers 32n and 32p are formed by the electrolytic plating method, the plating layers grow isotropically from the portions exposed from the first resin layer 21 of the first metal layers 31n and 31p. For this reason, when the exposed surfaces of the first metal layers 31n and 31p are not uniformly arranged on the entire bottom surfaces of the openings 22n and 22p of the second resin layer 22, an uneven shape is formed on the upper surface after plating growth. May be. Therefore, a second metal layer 32n is formed by forming a metal film on the entire bottom surface of the openings 22n and 22p of the second resin layer 22 by sputtering or the like and performing electrolytic plating using the metal film as a current path. , 32p may be formed to be flatter.

  In the example shown in FIG. 10A, the upper surfaces of the second metal layers 32n and 32p are formed to be flat surfaces, and the whole is formed to be lower than the upper surface of the second resin layer 22. However, the present invention is not limited to this. You may make it form so that the upper surface of the 2nd metal layers 32n and 32p may protrude from the upper surface of the 2nd resin layer 22, or may be lower than the upper surface of the 2nd resin layer 22. FIG. Further, the upper surfaces of the second metal layers 32n and 32p may be formed flat or may be formed with irregularities.

  Next, in the first resin layer removing step S111, as shown in FIG. 10B, the first resin layer 21 is anisotropically etched in the direction perpendicular to the wafer surface using the second resin layer 22 as a mask. Thereby, the first resin layer 21 in the opening 22a of the second resin layer 22 is removed, and the opening 21a is formed in the first resin layer 21, and as a result, the metal layer 50 is formed on the bottom surface of the opening 21a. Exposed.

In this step, anisotropic etching is performed so that the entire wafer is etched in a direction perpendicular to the wafer surface. Specifically, a dry etching method such as an RIE (reactive ion etching) method can be used. At this time, it is preferable to use an etchant whose etching rate for the second metal layers 32n and 32p is sufficiently smaller than the etching rate for the first resin layer 21 and the second resin layer 22. Thereby, the first resin layer 21 and the second resin layer 22 can be selectively etched substantially.
Further, since the upper surface of the second resin layer 22 is also etched, the upper portions of the second metal layers 32n and 32p project from the second resin layer 22 as shown in FIG.

  In this manner, the portion of the first resin layer 21 used as the plating mask in the first metal layer forming step S108 and the second metal layer forming step S110 is removed by etching using the second resin layer 22 as a mask. For this reason, it is not necessary to separately perform a step of forming a mask and a step of removing the mask in order to remove a portion used as a plating mask by etching, and the manufacturing process can be simplified.

Next, in the pad electrode separation step (electrode separation step) S112, as shown in FIG. 11, the metal layer 50 exposed on the bottom surface of the opening 21a of the first resin layer 21 is removed by etching. Thereby, the metal layer 50 is separated for each light emitting device 100, and also in each light emitting device 100, a region to be the n-side electrode 13 and a region to be the p-side electrode 15 are separated. In this step, an etchant that selectively etches the metal material forming the metal layer 50 without etching the resin material constituting the first resin layer 21 and the second resin layer 22 is used. In particular, the wet etching method is preferable because the metal layer 50 can be selectively removed.
Further, by performing the pad electrode separation step S112 by etching, it is possible to easily divide each light emitting device 100 only by cleaving the semiconductor stacked body 12 in the individualization step S114 described later.

  When the metal layer 50 is etched, a mask may be provided on the upper surfaces of the second metal layers 32n and 32p so that the second metal layers 32n and 32p are not etched. If the second metal layers 32n and 32p are sufficiently thicker than the metal layer 50, the thickness of the second metal layers 32n and 32p may be reduced by the same amount as the thickness of the metal layer 50. The metal layer 50 may be etched without providing a mask on the upper surfaces of the second metal layers 32n and 32p.

  Further, the pad electrode separation step S112 may be omitted, and the metal layer 50 may be divided together with the semiconductor multilayer body 12 in the boundary region in the individualization step S114 described later. That is, the metal layer 50 can also be separated into the n-side electrode 13 and the p-side electrode by performing the singulation step S114.

Next, in the growth substrate removing step S113, as shown in FIG. 12, the growth substrate 11 is removed by peeling off by an LLO (laser lift-off) method, a chemical lift-off method, or the like.
The growth substrate removal step S113 is not an essential step, and the growth substrate 11 may not be peeled off. Further, instead of peeling off the growth substrate 11, the lower surface side of the growth substrate 11 may be polished and thinned.
Alternatively, after the growth substrate 11 is peeled off, the lower surface of the semiconductor stacked body 12 may be wet etched to form an uneven shape.
Furthermore, a phosphor that converts the wavelength of light emitted from the light-emitting element 1 is contained on the lower surface side that is the light extraction surface of the light-emitting device 100 after the growth substrate 11 is peeled off or without peeling off the growth substrate 11. A phosphor layer may be provided.

Next, in the singulation step S114, the light emitting device 100 is singulated by cutting the wafer along the boundary line 40 shown in FIG. 12 by a dicing method or a scribing method. As shown in FIG. 1B, the side surface that is the outer edge of the semiconductor stacked body 12 formed by singulation is not covered by either the insulating film 16 or the first resin layer 21 and is exposed.
In addition, after performing 1st resin layer removal process S111, the 1st resin layer 21 and the 2nd resin layer 22 have the opening part 21a and the opening part 22a in the area | region along the boundary line 40, respectively. Each light emitting device 100 is separated. For this reason, it is possible to easily divide the semiconductor laminate 12 by simply cleaving the semiconductor laminate 12.

<First Modification>
Next, a light emitting device according to a first modification of the above-described embodiment will be described with reference to FIG.
As illustrated in FIG. 13, in the light emitting device 100A according to the first modification, the second resin layer 22 extends outside the first resin layer 21 on the side surface of the second exposed portion 12c provided on the outer edge of the light emitting device 100A. It differs from the light-emitting device 100 shown in FIG.

In the light emitting device 100 </ b> A, the second resin layer 22 is in contact with the side surface in addition to the upper surface of the first resin layer 21.
Note that the other configuration of the light emitting device 100A is the same as that of the light emitting device 100, and thus the description thereof is omitted. Further, since the operation of the light emitting device 100A is the same as that of the light emitting device 100, description thereof is omitted.

Next, with reference to FIG. 14, the manufacturing method of the light-emitting device 100A which concerns on a 1st modification is demonstrated.
The light emitting device 100A according to the first modification differs in the range in which the second resin layer 22 is formed on the first resin layer 21 in the second resin layer forming step S109 of the method for manufacturing the light emitting device 100 shown in FIG. By doing so, it can be manufactured. Since other processes are the same as those of the method for manufacturing the light emitting device 100, description thereof will be omitted as appropriate.

  In the second resin layer forming step S109 in the first modified example, as shown in FIG. 14A, the second resin layer 22 is the first resin in the second exposed portion 12c that is a region along the boundary line 40. The layer 21 is formed so as to further cover the outside of the side surface of the second exposed portion 12c. That is, the second resin layer 22 is provided so as to cover the first resin layer 21 provided on the side surface of the second exposed portion 12 c continuously from the upper surface of the first resin layer 21. Moreover, the 2nd resin layer 22 has the opening part 22a in the area | region along the boundary line 40, and the 1st resin layer 21 is exposed to the bottom face of the said opening part 22a.

  FIG. 14A shows a state in which the second metal layer forming step S110, which is the next step, is performed and the second metal layers 32n and 32p are formed. The shape of the second resin layer 22 is as follows. It is not changed from the one formed in the two resin layer forming step S109.

  Further, in the first resin layer removing step S111 in the first modification, as shown in FIG. 14B, the first resin layer 21 is etched using the second resin layer 22 as a mask, so that the bottom surface of the opening 22a. The first resin layer 21 exposed to is removed. Thereby, the opening 21a is formed in the first resin layer 21, and the metal layer 50 is exposed on the bottom surface of the opening 21a.

  Furthermore, the light emitting device 100A shown in FIG. 13 is formed by performing the steps subsequent to the pad electrode separation step S112 in the same manner as the method for manufacturing the light emitting device 100.

<Second Modification>
Next, a light emitting device according to a second modification of the above-described embodiment will be described with reference to FIG.
As shown in FIG. 15, the light emitting device 100 </ b> B according to the second modification is provided with a step 21 b on the side surface that is the outer edge of the first resin layer 21 so that the lower part is outside the upper part in plan view. This is different from the light emitting device 100 shown in FIG.

  Since the light emitting device 100B has the step 21b on the side surface of the first resin layer 21, when the light emitting device 100B is mounted, a second resin layer is formed from the second metal layers 32n and 32p on which a bonding member such as molten solder becomes the mounting surface. 22 and the first resin layer 21 crawl up along the surface of the first resin layer 21, it is possible to prevent the solder from further climbing by the step 21 b. For this reason, it is possible to prevent an adhesive member such as excessive solder from being short-circuited by scooping up to the exposed side surface of the semiconductor stacked body 12 and from fouling the side surface and upper surface of the semiconductor stacked body 12 serving as a light extraction surface. Can do.

  Note that other configurations of the light-emitting device 100B are the same as those of the light-emitting device 100, and thus description thereof is omitted. Further, since the operation of the light emitting device 100B is the same as that of the light emitting device 100, description thereof is omitted.

Next, with reference to FIG. 16, the manufacturing method of the light-emitting device 100B which concerns on a 2nd modification is demonstrated.
The light emitting device 100B according to the second modification differs in the range in which the second resin layer 22 is formed on the first resin layer 21 in the second resin layer forming step S109 of the method for manufacturing the light emitting device 100 shown in FIG. By doing so, it can be manufactured. Since other processes are the same as those of the method for manufacturing the light emitting device 100, description thereof will be omitted as appropriate.

  In the second resin layer forming step S109 in the second modified example, as shown in FIG. 16A, the end surface of the second resin layer 22 is a side surface of the second exposed portion 12c that is a region along the boundary line 40. It forms so that it may become an inner side rather than the end surface of the 1st resin layer 21 to coat | cover. Moreover, the 2nd resin layer 22 has the opening part 22a in the area | region along the boundary line 40, and the 1st resin layer 21 is exposed to the bottom face of the said opening part 22a.

  In addition, it is preferable that the position of the end surface of the 2nd resin layer 22 exists in the range of the film thickness of the 1st resin layer 21 provided in the side surface of the 2nd exposed part 12c. Thus, when the first resin layer 21 is etched as the second resin layer 22 mask in the first resin layer removing step S111, for example, in the region where the entire surface electrode 14 (see FIG. 15) is provided, the n-side electrode The metal layer 50 left as the 13 or p-side electrode 15 can be prevented from being exposed.

  FIG. 16A shows a state in which the second metal layer forming step S110, which is the next step, is performed and the second metal layers 32n and 32p are formed. The shape of the second resin layer 22 is as follows. It is not changed from the one formed in the two resin layer forming step S109.

  Further, in the first resin layer removing step S111 in the second modification, as shown in FIG. 16B, the first resin layer 21 is etched using the second resin layer 22 as a mask, so that the bottom surface of the opening 22a. The first resin layer 21 exposed to is removed. Thereby, the opening 21a is formed in the first resin layer 21, and the metal layer 50 is exposed on the bottom surface of the opening 21a.

  Further, the light emitting device 100B shown in FIG. 15 is formed by performing the steps after the pad electrode separation step S112 in the same manner as the method for manufacturing the light emitting device 100.

  The light emitting device and the method for manufacturing the same according to the present invention have been specifically described above by the embodiments for carrying out the invention. However, the gist of the present invention is not limited to these descriptions, and the scope of the claims is as follows. It must be interpreted widely based on the description. Needless to say, various changes and modifications based on these descriptions are also included in the spirit of the present invention.

1 Light emitting device (semiconductor light emitting device)
DESCRIPTION OF SYMBOLS 11 Growth substrate 12 Semiconductor laminated body 12n n-type semiconductor layer 12a active layer 12p p-type semiconductor layer 12b 1st exposed part 12c 2nd exposed part 13 n side electrode 14 whole surface electrode 14a light reflecting electrode 14b cover electrode 15 p side electrode 16 insulation Membrane 2 Support 21 First resin layer 21a Opening 21b Step 21n Opening 21p Opening 22p Second resin layer 22a Opening 22n Opening 22p Opening 23 Step 31n First metal layer (n-side first metal layer)
31p first metal layer (p-side first metal layer)
32n second metal layer (n-side second metal layer)
32p second metal layer (p-side second metal layer)
40 boundary line 50 metal layer 100, 100A, 100B light emitting device

Claims (7)

A method of manufacturing a light emitting device including a semiconductor light emitting element having a semiconductor stacked body and an electrode provided on one surface of the semiconductor stacked body,
A wafer preparation step of preparing a wafer in which a plurality of the semiconductor light emitting elements are arranged and formed so that the electrodes of adjacent semiconductor light emitting elements are short-circuited in a boundary region that partitions the semiconductor light emitting elements When,
A first resin layer forming step of forming a first resin layer having an opening in a part of a region where the electrode is provided on the one surface side of the semiconductor laminate;
A first metal layer forming step of forming a first metal layer on the electrode exposed in the opening of the first resin layer;
On the first resin layer, a second resin layer forming step of forming a second resin layer having an opening in each of the region where the first metal layer is formed and the boundary region;
A second metal layer forming step of forming a second metal layer on the first metal layer exposed in the opening of the second resin layer;
A first resin layer removing step of removing the first resin layer formed on the boundary region so that the electrode is exposed;
A method for manufacturing a light emitting device, comprising: a step of dividing the wafer into pieces for each of the semiconductor light emitting elements along the boundary region.   The method for manufacturing a light emitting device according to claim 1, wherein the first resin layer removing step is performed by anisotropic etching.   The maximum film thickness of the portion covering the boundary region in the first resin layer formed in the first resin layer forming step is the minimum film thickness of the second resin layer formed in the second resin layer forming step. The method for manufacturing a light-emitting device according to claim 1, wherein the light-emitting device is thinner.   4. The method of manufacturing a light emitting device according to claim 1, further comprising an electrode removing step of removing the electrode exposed in the boundary region after the first resin layer removing step. 5. .   The method for manufacturing a light emitting device according to claim 4, wherein the electrode removing step is performed by wet etching.   The first metal layer and the second metal layer are formed by electrolytic plating in the first metal layer forming step and the second metal layer forming step, respectively. The manufacturing method of the light-emitting device as described in any one of Claims 5. 7. The first resin layer forming step and the second resin layer forming step, wherein the first resin layer and the second resin layer are each formed by a photolithography method. The manufacturing method of the light-emitting device as described in any one of these.

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