JP2016049178A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of preventing performance information from being fraudulently read.SOLUTION: A game machine comprises: main control means for controlling a game; performance control means for executing a game performance; and performance information storage means for storing performance information for executing the performance. The performance control means comprises performance execution means for executing the performance. The performance execution means comprises: performance control information reception means for receiving performance control information; and performance information acquisition means for determining whether or not to read the performance information when reading the performance information, and when reading the performance information, reading the performance information stored in the performance information storage means, and when not reading the performance information, regulating reading of the performance information stored in the performance information storage means.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a gaming machine such as a so-called ball-type gaming machine (hereinafter also referred to as “pachinko gaming machine”) and a rotating gaming machine (hereinafter referred to as “pachislot gaming machine”).

  In order to enhance the interest of the game, the gaming machine displays a variety of images including a large number of material images, or outputs lights and sounds using lamps and speakers to execute a variety of effects (see, for example, Patent Document 1). ).

JP 2014-97292 A

  The non-volatile memory provided in the gaming machine stores a storage area (game control storage area) for storing game control data (game control program and data) and presentation control data (program and data for controlling presentation). A storage area (effect control storage area) for storage and a storage area (effect information storage area) for storing material information (effect information) for effects such as images and sounds output at the time of effect execution are also allocated.

  At this time, reading of game control data from the game control storage area is restricted in order to prevent game fraud. On the other hand, there is a case where production related data (production control data, production information), in particular, production information read from the production information storage area is not particularly restricted because it has little influence on the game result. Therefore, there is a possibility that material information such as images and sounds stored in the effect information storage area may be read out illegally.

  Therefore, an object of the present invention is to prevent the production information from being read out illegally from the production information storage area.

  The gaming machine according to the present invention stores main control means for controlling a game, effect control means for executing a game effect based on an execution instruction from the main control means, and effect information for executing the effect. In the gaming machine provided with the effect information storage means, the effect control means includes an effect execution means for executing the effect, a read restricting means for restricting reading of the effect information from the effect information storage means, and the effect. An effect of determining at a predetermined timing whether or not to restrict the reading of the effect information stored in the effect information storage means. It is determined that normal reading of the production information stored in the production information storage unit is regulated by the information readout regulation judgment unit and the production information read regulation judgment unit If the read restriction means restricts normal reading of the effect information stored in the effect information storage means, and if it is determined not to restrict, the read restriction release means causes the effect information storage means. Production information acquisition means for enabling normal reading of the production information stored in

  According to the gaming machine according to the present invention, it is possible to prevent the effect information stored in the effect information storage area (effect information storage means) from being read illegally.

It is a perspective view which shows the state which open | released the main body frame with respect to the outer frame of the pachinko game machine which is one Embodiment of this invention, and opened the door frame with respect to the main body frame. It is the disassembled perspective view seen from the outer frame, main body frame, game board, and door frame which comprise a pachinko game machine. It is a perspective view of the game board seen from the back side of a pachinko gaming machine. It is a front view of a game board. It is a perspective view of a door frame. It is a block diagram of a main control board, a payout control board, and a peripheral control board. FIG. 7 is a block diagram showing a configuration example of a peripheral control board shown in FIG. 6 and a board connected to the peripheral control board. It is a block diagram which shows the outline of peripheral control MPU. It is a block diagram which shows the structural example of VDP periphery with a sound source in a liquid crystal and a sound control part. It is a table which shows an example of the various commands transmitted to a peripheral control board from a main control board. 11 is a table showing a continuation of various commands transmitted from the main control board to the peripheral control board in FIG. 10. It is a flowchart which shows an example of the main control side power-on process. FIG. 13 is a flowchart showing a continuation of main-control-side power-on processing in FIG. 12. FIG. It is a flowchart which shows an example of the main control side timer interruption process. It is a flowchart which shows an example of a peripheral control part power-on process. It is a flowchart which shows an example of the peripheral control part V blank interruption process. It is a flowchart which shows an example of a peripheral control part 1ms timer interruption process. It is a flowchart which shows an example of a peripheral control part command reception interruption process. It is a figure explaining the control data sequence prepared beforehand by liquid crystal and sound control ROM, (A) is a figure which shows an example of the storage state of a control data sequence, (B) is a data format which shows the detail of a control data sequence An example is shown. It is a figure which shows the structural example of the storage area of a frame buffer. It is a figure which shows an example of the correspondence management table which distinguishes and manages the kind of non-video production | presentation execution part with a classification code. It is a flowchart which shows an example of a control data extraction process. It is a figure which shows an example of a structure of control data. It is a block diagram of the periphery control board explaining the composition which releases concealment of production information based on the directions from peripheral control MPU. It is a block diagram of a peripheral control board for explaining a configuration in which the sound source built-in VDP independently releases the concealment of the production information.

[1. Pachinko machine structure]
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings. First, the configuration of the pachinko gaming machine according to the embodiment will be described. FIG. 1 is a perspective view illustrating a state in which a main body frame is opened with respect to an outer frame of a pachinko gaming machine according to an embodiment and a door frame is opened with respect to the main body frame. FIG. 2 is an exploded perspective view as seen from the rear of the outer frame, the main body frame, the game board, and the door frame constituting the pachinko gaming machine.

  As shown in FIGS. 1 and 2, the pachinko gaming machine 1 according to the present embodiment includes an outer frame 2 installed in an island facility (not shown) of the game hall, and is pivotally supported by the outer frame 2 so as to be freely opened and closed. A game frame 4 having a box frame-shaped main body frame 3 opened on the side, a game area 1100 in which a game ball as a game medium is inserted and fixed to the main body frame 3 from the front side, and the main body frame 3 and the game board 4 A door frame 5 that is pivotally supported to be openable and closable with respect to the main body frame 3 so as to close the front surface from the player side. The door frame 5 of the pachinko gaming machine 1 stores a gaming window 101 formed so that a gaming area 1100 of the gaming board 4 can be viewed from the player side, and a gaming ball disposed below the gaming window 101. A dish-shaped upper plate 301 and lower plate 302, and a handle device 500 that is operated by the player to drive the game balls stored in the upper plate 301 into the game area 1100 of the game board 4 are provided.

  In the pachinko gaming machine 1 according to the present embodiment, the outer frame 2, the main body frame 3, and the door frame 5 are each formed in a vertically long rectangular shape extending in the vertical direction when viewed from the front. The dimensions of the body frame 3 and the door frame 5 are slightly shorter than the outer frame 2 in terms of the vertical dimension in the vertical direction. A decorative cover 23 is attached to the front surface of the outer frame 2 at a position below the main body frame 3 and the door frame 5, and the front surface of the outer frame 2 is completely closed by the door frame 5 and the decorative cover 23. It has become so. The outer frame 2, the main body frame 3, and the door frame 5 are arranged so that their upper ends are substantially aligned, and the main body frame 3 and the door frame 5 can be rotated at a position on the left end front side of the outer frame 2. The right end of the main body frame 3 and the door frame 5 moves to the front side with respect to the outer frame 2 so as to be in an open state.

  In the front view, the pachinko gaming machine 1 is desired to have a gaming area 1100 into which a game ball is driven through a substantially circular gaming window 101, and so as to project forward to the lower side of the gaming window 101. Two upper plates 301 and lower plates 302 are arranged one above the other. In addition, a handle device 500 for the player to operate is disposed at the lower right corner of the front surface of the door frame 5. When the rotation operation is performed, the game ball in the upper plate 301 is driven into the game area 1100 of the game board 4 with a hitting strength corresponding to the rotation angle, and a game can be played.

  Note that the game window 101 of the door frame 5 is closed by a transparent glass unit 590, and the player can visually recognize the inside of the game area 1100, but the player inserts a hand or the like into the game area 1100. Thus, it is impossible to touch game balls, obstacle nails, various winning holes, and bonuses in the game area 1100.

[1-1. Body frame]
The main body frame 3 is pivotally supported on the left side when viewed from the front with respect to the outer frame 2, and is supported in a door shape so as to open and close the front surface of the outer frame 2 on the rear side of the door frame 5. The frame 5 can be opened and closed. Further, the main body frame 3 can hold the game board 4 detachably from the front side at a position corresponding to the game window 101 of the door frame 5.

  The main body frame 3 forms a skeleton of the main body frame 3 and penetrates in the front-rear direction to have a rectangular game board holding port 601 for holding the game board 4, and a front surface of the main body frame base 600. An upper shaft support bracket 630 and a lower shaft support bracket 640 that are attached to the upper end and the lower end of the left end portion of the view and are pivotally supported by the outer frame 2 and pivotally support the door frame 5, respectively, and the lower front surface of the main body frame base 600 A ball hitting device 650 for driving a game ball into the game area 1100 of the game board 4 and an award for paying out the game ball to the upper plate 301 of the plate unit 300 attached to the rear side of the main body frame base 600. A ball outlet that is attached to the front surface of the ball unit 700 and the main body frame base 600 and blocks the flow of game balls from the prize ball unit 700 to the dish unit 300 of the door frame 5 when the door frame 5 is opened with respect to the main body frame 3. Opening and closing uni Is provided with a door 790, a.

  The main body frame 3 is attached to the lower rear surface of the main body frame base 600, and includes various control boards for controlling electrical components provided in the door frame 5 and the main body frame 3 except the game board 4, a power supply board 851, and the like. Are combined into a unit board unit 800, a back cover 900 that covers the rear opening of the game board holding port 601 in the main body frame base 600, and a side security plate 950 that covers the left end of the main body frame base 600 in front view And a locking device 1000 that is attached to the right end of the main body frame base when viewed from the front and that opens and closes the main body frame 3 to the outer frame 2 and opens and closes the door frame 5 to the main body frame 3. The board unit 800 includes a board unit base 810, a speaker box 820, a launch power board box 830, a power board box holder 840, a power board box 850, a payout control board box 860, a terminal board box 870, and the like. The power board 851 is housed inside the power board box 850.

  Further, on the rear side of the main body frame 3, various control boards are provided, and a back cover 900 that is closed so as to cover the back of the game board 4 is provided. The back cover 900 operates the main control board 4100 through the connection notch 910 and the confirmation opening 912 in a state of being closed with respect to the main body frame 3 without opening the back cover 900 with respect to the main body frame 3. Confirmation, appearance confirmation, management status confirmation, etc. can be performed.

[1-2. Game board]
Next, the whole structure of the game board 4 is demonstrated with reference to FIG.3 and FIG.4. FIG. 3 is a perspective view of the game board viewed from the back side in the present embodiment. FIG. 4 is a front view of the game board in the present embodiment.

  The game board 4 in the pachinko gaming machine 1 of the present embodiment has an outer rail 1111 and an inner rail 1112, and a game ball (also simply referred to as “ball”) as a game medium when the player operates the handle device 500. A frame-shaped front component member 1110 that partitions and forms an inner periphery of a game area 1100 into which a game is inserted, and a plate-like game panel 1200 are provided.

  The gaming panel 1200 includes a transparent panel board 1210 having a plate shape capable of partitioning the rear end of the gaming area 1100 whose inner periphery is partitioned by the front component member 1110 and having a smaller outer shape than the front component member 1110, and a panel plate And a frame-like panel holder 1220 attached to the rear surface of the front component member 1110 while holding the detachable 1210 from the front side. An opening of the game panel 1200 is formed in a transparent panel plate 1210.

  Further, the game board 4 includes a front unit 2000 attached from the front side to the opening of the game panel 1200, a back unit 3000 attached to the rear surface of the game panel 1200 (panel holder 1220), and a left end of the front end of the back unit 3000. A function display unit 1180 disposed at a position that is visible from the player side through the transparent panel board 1210 and is visible from the game window 101 of the door frame 5 to the player side when attached to the pachinko gaming machine 1; A liquid crystal display device 1900 having a rectangular display screen (display area) which is attached to the rear side of the back unit 3000 so as to be visible from the player side and can display a predetermined effect image, and a lower part of the back unit 3000 from the rear side. A substrate holder 1160 attached to the lower rear surface of the gaming panel 1200 so as to cover the rear of the substrate holder 1160 A main control board box 1170 attached to, and a.

  The front unit 2000 includes an attacker unit 2100 that is disposed at a substantially lower center in the left-right direction in the gaming area 1100 and above the out port 1151 and is supported on the front surface of the gaming panel 1150. And a side prize opening member 2200 supported by the front surface of the game panel 1150 and a frame-shaped center accessory 2300 supported by the game panel 1150 and disposed at a substantially central portion of the game area 1100.

  The back unit 3000 is attached and fixed to the rear surface of the game panel 1150, and a back box 3001 that supports the liquid crystal display device 1900 at a position away from the game panel 1150 by a predetermined distance, and a liquid crystal display in the back box 3001. The upper unit 3100 disposed on the upper side of the device 1900, the character unit 3400 disposed on the right side of the liquid crystal display device 1900 in the back box 3001, and the gear decoration disposed on the left side of the liquid crystal display device 1900 in the back box 3001. A body unit 3500. The upper unit 3100, the character unit 3400, and the gear decoration body unit 3500 can be moved independently or in conjunction with each other depending on the game state. It is possible to suggest the arrival of an opportunity, and to entertain the player.

  As shown in FIG. 3, the liquid crystal display device 1900 includes a peripheral control board box 1910 that houses a peripheral control unit 4150, a liquid crystal and sound control unit 4160 (see FIG. 7), and the lower part of the peripheral control board box 1910. And an extended volume 1912.

  The peripheral control board box 1910 includes an attachment base attached to the gaming machine, and a lid member attached to the attachment base and defining a storage space for accommodating the game control board between the attachment base. The peripheral control board box 1910 is made of a transparent synthetic resin, and the peripheral control board 4140 housed inside can be seen through even when the lid member is attached to the attachment base.

  Further, the mounting base and the lid member are sealed (caulking structure) by, for example, a one-way screw (fixing tool) that can be turned only in the tightening direction. Therefore, in order to take out the game control board, it is necessary to disconnect the one-way screw. The main control board box 1170 described above has the same configuration. Therefore, when the attachment between the mounting base and the lid member is released, a trace remains, which is easy when an illegal act such as replacing the peripheral control board (production control board) 4140 or the main control board (game control board) 4100 is performed. Can be found in.

[1-3. Door frame]
Next, the door frame 5 that can be freely opened and closed on the front side of the main body frame 3 will be described with reference to FIG. FIG. 5 is a perspective view of the door frame 5 in the present embodiment. As shown in FIG. 4, the door frame 5 includes a door frame base unit 100 having a gaming window 101 whose outer shape is formed in a vertically long rectangular shape and whose inner peripheral shape is a slightly vertically long circular shape (elliptical shape). A right side decoration unit 200 attached to the right outer periphery of the gaming window 101 on the front surface of the frame base unit 100, and a left side facing the right side decoration unit 200 and attached to the left outer periphery of the gaming window 101 on the front surface of the door frame base unit 100. The decoration unit 240, the upper decoration unit 280 attached to the upper outer periphery of the gaming window 101 in front of the door frame base unit 100, and the door frame base unit disposed below the lower ends of the right side decoration unit 200 and the left side decoration unit 240. And a pair of side speaker covers 290 attached to the front surface of 100.

  The door frame 5 is attached to the front side of the door frame base unit 100 at the lower part of the gaming window 101, the operation unit 400 attached to the upper center of the dish unit 300, and the right side of the dish unit 300. , An upper plate side liquid crystal display device 244, a transparent touch panel 246 that covers the upper surface of the upper plate side liquid crystal display device 244, and a tray unit 300 that is attached to the lower right corner of the door frame base unit 100 and is used for driving a game ball. Handle device 500, a foul cover unit 540 disposed on the rear side of the dish unit 300 with the door frame base unit 100 interposed therebetween, and a door on the right side of the foul cover unit 540. A ball feeding unit 580 attached to the rear surface of the frame base unit 100, and a door frame Provided on the rear side of the Suyunitto 100 glass unit 590 mounted to close the game window 101, the.

[2. Main control board, payout control board and peripheral control board]
Next, a control board for performing various controls of the pachinko gaming machine 1 will be described with reference to FIGS. FIG. 6 is a block diagram of the main control board, the payout control board, and the peripheral control board. FIG. 7 is a block diagram showing a configuration example of the peripheral control board 4140 shown in FIG. FIG. 8 is a block diagram showing an outline of the peripheral control MPU, and FIG. 9 is a block diagram showing a peripheral configuration example of a sound source built-in VDP in the liquid crystal and sound control unit.

  As shown in FIG. 6, the pachinko gaming machine 1 is mainly configured by a main control board 4100, a payout control board 4110, and a peripheral control board 4140, and various controls are shared. . First, the main control board will be described, and then the peripheral control board will be described. The details of the payout control board 4110 will be omitted.

[2-1. Main control board]
The main control board 4100 for controlling the progress of the game is a microprocessor in which various control programs such as a main control program for controlling game operations, a ROM for storing various commands, a RAM for temporarily storing data, and the like are incorporated. Main control MPU 4100a, a main control input circuit 4100b to which detection signals from various detection switches are input, a main control output circuit 4100c for outputting various signals to an external substrate, etc., and for driving various solenoids Mainly includes a main control solenoid drive circuit 4100d and a power failure monitoring circuit 4100e for monitoring a sign of a predetermined power failure or an instantaneous power failure state (hereinafter referred to as “instantaneous power failure”). The above-described main control program is executed after a predetermined time has elapsed since power-on, and controls power-on processing that is performed when power is turned on.

  The main control MPU 4100a includes a built-in RAM (corresponding to the “main control built-in RAM”) and a built-in ROM (hereinafter referred to as “main control built-in ROM”). A watchdog timer for monitoring the operation (system) and functions for preventing fraud are also built-in. The above-described main control built-in RAM has, as part of its storage area, a jackpot determination random number storage area, a special symbol random number storage area, and a reach determination random number for each start storage information stored in a start storage information storage area described later. It has a storage area, random numbers for variation pattern 1, 2 and a random number storage area for variation type, and a starting storage information storage area and a transmission information storage area described later. Of these, the start memory information storage area includes a first start memory information storage area for the first special symbol and a second start memory information storage area for the second special symbol. In addition, the main control built-in RAM also includes a jackpot flag area capable of storing a jackpot flag value to be described later. As will be described later, the big hit flag represents not only a loss (00H) or a big hit (01H) but also a small hit (02H). Therefore, if the main control MPU 4100a accesses one storage area called the big hit flag area without accessing the small hit flag area in which the value of the big hit flag can be stored, the main control MPU 4100a only determines whether it is a big hit or lost. In addition, it is possible to grasp at the same time whether it is a small hit.

  The main control MPU 4100a has a built-in nonvolatile RAM. In this non-volatile RAM, a unique ID code with a unique code (a code that exists only in the world) for identifying an individual by the manufacturer that manufactured the main control MPU 4100a is stored in advance. Since the ID code once attached is stored in the nonvolatile RAM, it cannot be rewritten using an external device. The main control MPU 4100a can take out the ID code from the nonvolatile RAM and refer to it.

  The main control input circuit 4100b is not provided with a reset terminal for forcibly resetting information whose detection signals from various detection switches are input to the various input terminals, and does not have a reset function. Therefore, the main control input circuit 4100b is configured as a circuit to which a system reset signal from a main control system reset described later is not input. That is, the main control input circuit 4100b does not reset the information based on the detection signals from the various detection switches input to the various input terminals by a main control system reset to be described later. The circuit is configured to be output from the output terminal.

  The main control output circuit 4100c is configured as an open collector output type in which an emitter terminal is grounded with a ground (GND), and various signals for outputting various signals to an external substrate or the like are input to the various input terminals. Main control output circuit 4100ca with a reset function having a reset function in which a reset terminal for forcibly resetting the received information is provided, and a main control output circuit 4100cb without reset function without a reset function in which no reset terminal is provided. And is composed of. The main control output circuit 4100ca with a reset function is configured as a circuit to which a system reset signal from a main control system reset described later is input. That is, the main control output circuit 4100ca with a reset function is reset when information for outputting various signals input to the various input terminals to an external board or the like is reset by a main control system reset described later. Is configured as a circuit that does not output any signal from the various output terminals. On the other hand, the main control output circuit 4100cb without a reset function is configured as a circuit to which a system reset signal from a main control system reset described later is not input. That is, the main control output circuit 4100cb having no reset function does not reset the information for outputting various signals input to the various input terminals to an external board or the like by a main control system reset described later. The signal based on this is comprised as a circuit from which the various output terminals are output.

  A first start port switch 3022 that detects a game ball that has entered the first start port 2101, a second start port switch 2109 that detects a game ball that has entered the second start port 2102, and a ball that enters the general winning port 2104 A detection signal from the general prize opening switch 3020 for detecting the played game ball and a signal from the power failure monitoring circuit 4100e are input to an input terminal of a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b. Also, a game ball is placed in the distribution detection sensor 2580, a gate switch 2301 that detects a game ball that has passed through the gate portion 2350, a general winning port switch 3020 that detects a game ball that has entered the general winning port 2201, and a big winning port 2103. The detection signal from the count switch 2110 that outputs a detection signal upon detecting acceptance, and the magnetic detection switch 3024 that detects fraud using a magnet, includes a panel relay terminal plate 4161 attached to the game board 4, and The signal is inputted to the input terminal of a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b.

  The main control MPU 4100a outputs a drive signal from the output terminal of the predetermined output port to the main control output circuit 4100ca with reset function based on the detection signals from these switches, so that the main control output circuit with reset function is output. 4100ca outputs a control signal to the main control solenoid drive circuit 4100d, and the start port solenoid 2105, the attack solenoid 2108A, the attack solenoid 2108B, and the distribution drive motor 2558 (see FIG. (Not shown), each of which outputs a drive signal, or outputs a drive signal from the output terminal of the predetermined output port to the main control output circuit 4100ca with reset function, thereby relaying the panel from the main control output circuit 4100ca with reset function. The first special symbol indicator 1185, the second special symbol indicator 1186, the first special symbol memory indicator 1184, the second special symbol memory indicator 1187, and the normal symbol indicator via the daughter board 4161 and the function display board 1191. 1189, the normal symbol memory display 1188, the game status display 1183, and the round display 1190 are output drive signals.

  Further, the main control MPU 4100a outputs various information (game information) relating to the game from the output terminal of the predetermined output port to the main control output circuit 4100ca with reset function, so that payout control is performed from the main control output circuit 4100ca with reset function. Main control output with reset function by outputting various information (game information) to the substrate 4110 or by outputting a signal (power failure clear signal) from the output terminal of the predetermined output port to the main control output circuit 4100ca with reset function A signal (power failure clear signal) is output from the circuit 4100ca to the power failure monitoring circuit 4100e.

  In this embodiment, a non-contact type electromagnetic proximity switch is used as the first start port switch 3022, the second start port switch 2109, the gate switch 2301, and the count switch 2110. The general winning opening switches 3020 and 3020 are contact type ON / OFF operation type mechanical switches. This is because game balls frequently enter the first start port 2101 and the second start port 2102 and frequently pass through the gate portion 2350, so that the first start port switch 3022, the second start port switch 2109, and Detection of game balls by the gate switch 2301 also frequently occurs. Therefore, long-life proximity switches are used for the first start port switch 3022, the second start port switch 2109, and the gate switch 2301. In addition, when a big hit gaming state that is advantageous to the player occurs, the game winning balls 2103 are opened and game balls are frequently entered, so that the game balls are frequently detected by the count switch 2110. For this reason, a proximity switch having a long life is also used as the count switch 2110. On the other hand, detection by the general winning opening switches 3020 and 3020 does not occur frequently at the general winning opening 2104 and 2201 where game balls do not enter frequently. For this reason, mechanical switches having a shorter lifetime than the proximity switches are used as the general winning award opening switches 3020 and 3020.

  Further, the main control MPU 4100a transmits various commands related to payout as serial data from the output terminal of the predetermined serial output port to the main control output circuit 4100cb without reset function, thereby performing payout control from the main control output circuit 4100cb without reset function. Various commands are transmitted to the substrate 4110 as serial data. When the payout control board 4110 completes normal reception of various commands from the main control board 4100 as serial data, the payout control board 4110 outputs a signal (payer ACK signal) to that effect to the main control board 4100. This signal (payer ACK signal) is input to an input terminal of a predetermined input port of the main control MPU 4100a through the main control input circuit 4100b.

  Also, the main control MPU 4100a receives various commands related to the state of the pachinko gaming machine 1 from the payout control board 4110 as serial data by the main control input circuit 4100b, so that the main control input circuit 4100b receives the predetermined serial input port. Receives various commands as serial data at the input terminal. When the main control MPU 4100a completes normal reception of various commands from the payout control board 4110 as serial data, a main control output with a reset function is sent from the output terminal of the predetermined output port to that effect (main payout ACK signal). The signal is output to the circuit 4100ca, and a signal (main payment ACK signal) is output from the main control output circuit 4100ca with reset function to the payout control board 4110.

  Further, the main control MPU 4100a transmits, as serial data, various commands relating to control of game effects and various commands relating to the state of the pachinko gaming machine 1 to the main control output circuit 4100cb having no reset function from the output terminal of the predetermined serial output port. Thus, various commands are transmitted as serial data from the main control output circuit 4100cb having no reset function to the peripheral control board 4140.

  Here, a main peripheral serial transmission port for transmitting various commands as serial data to the peripheral control board 4140 will be briefly described. The main control MPU 4100a is configured with a main control CPU core 4100aa as the center. In addition to the main control built-in RAM described above, a main peripheral serial transmission port 4100ae, which is one of various main control serial I / O ports, and the like. Circuit connection is made via a bus 4100ah (see FIG. 7). The main peripheral serial transmission port 4100ae transmits various commands as main peripheral serial data to the peripheral control board 4140, and mainly includes a transmission shift register 4100aea, a transmission buffer register 4100aeb, a serial management unit 4100aec, and the like (FIG. 7). When the main control CPU core 4100aa sets a command in the transmission buffer register 4100aeb and outputs a transmission start signal to the serial management unit 4100aec, the serial management unit 4100aec sends the command set in the transmission buffer register 4100aeb from the transmission buffer register 4100aeb. The data is transferred to the transmission shift register 4100aea, and transmission to the peripheral control board 4140 is started as main peripheral serial data. In the present embodiment, the transmission buffer register 4100aeb has a storage capacity of 32 bytes. The main control CPU core 4100aa continuously transmits a plurality of commands to the peripheral control board 4140 by setting a plurality of commands in the transmission buffer register 4100aeb and then outputting a transmission start signal to the serial management unit 4100aec.

  The power supply board 851 for supplying various voltages to the main control board 4100 is an electric double layer capacitor (hereinafter simply referred to as “capacitor”) as a backup power supply for supplying power to the main control board 4100 for a predetermined time even when the power is shut off. It has BC0. With this capacitor BC0, the main control MPU 4100a stores various types of information in the main control built-in RAM even when the power is turned off. Various kinds of information stored in the main control built-in RAM are stored in an operation signal (RAM clear) from an operation switch 952 when an operation switch 952 of a payout control board 4110 (to be described later) is operated within a predetermined period from when the power is turned on. Signal) is output from the payout control board 4110 and is input to the input terminal of a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b. Is erased (cleared).

[2-2. Peripheral control board]
As shown in FIG. 7, the peripheral control board 4140 performs effect control based on various commands from the main control board 4100, while the peripheral control unit 4150 performs detection control of the touch state of the touch panel 246, and the game board side liquid crystal The drawing control of the display device 1900 and the upper liquid crystal display device 244 is performed, and sound control such as music and sound effects flowing from the speaker housed in the speaker box 920 provided in the main body frame 3 and the speaker provided in the door frame 5 is performed. A liquid crystal and sound control unit 4160 for performing the operation, a real-time clock (hereinafter referred to as “RTC”) control unit 4165 holding calendar information for specifying the date and time, and time information for specifying the hour, minute, second, and main body Volumes of music, sound effects, etc. flowing from the speakers housed in the speaker box 920 provided in the frame 3 and the speakers provided in the door frame 5 It includes a volume control volume 4140a adjusted by knob rotation operation (first sound volume operation means), a. The peripheral control unit 4150 and the liquid crystal / sound control unit 4160 may be separate from each other as illustrated or may be integrated. In this case, the processing performed by the peripheral control MPU 4150a of the peripheral control board 4140 can be performed by the liquid crystal and sound control unit 4160 with the built-in sound source VDP 4160a or vice versa.

[2-2-1. Peripheral control unit]
As shown in FIG. 7, the peripheral control unit 4150 that performs the effect control controls the peripheral control MPU 4150a as a microprocessor and the power-on process executed when the power is turned on, and after a predetermined time has elapsed since the power was turned on. Various control programs such as a sub-control program that is executed and controls the production operation, a peripheral control ROM 4150b that stores various data, various control data, and various schedule data, and a VDP 4160a with a built-in sound source of the liquid crystal and sound control unit 4160 described later. Various information inherited across the peripheral control unit steady process executed each time the V blank signal is input (for example, schedule data defining a screen to be drawn on the game board side liquid crystal display device 1900, light emission of various LEDs, etc. Manage schedule data that defines aspects Peripheral control RAM 4150c for storing information for storing information, etc., and various types of information continued across days (for example, information for managing the history of occurrence of big hit gaming states, information for managing special performance flags, etc.) ) And peripheral control external watchdog timer 4150e (hereinafter referred to as “peripheral control external WDT 4150e”) for monitoring whether or not the peripheral control MPU 4150a is operating normally. I have.

  Peripheral control RAM 4150c can retain the stored content only for the time when power is restored immediately after an instantaneous power failure, and power is cut off for a long time (when a long-time power interruption occurs) ), The peripheral control SRAM 4150d is supplied with backup power by a large-capacity electrolytic capacitor (not shown) provided on the power supply board 851 (hereinafter referred to as “electrolytic capacitor for SRAM”). The stored contents are retained for about 50 hours. By providing the electrolytic capacitor for SRAM on the power supply board 851, when the game board 4 is detached from the pachinko gaming machine 1, backup power is not supplied to the peripheral control SRAM 4150d. Therefore, the peripheral control SRAM 4150d stores the stored contents. Loses its contents because it can no longer hold.

  The peripheral control external WDT 4150e is a timer for monitoring whether or not the system of the peripheral control MPU 4150a is running out of control. When this timer is tie-mapped, the peripheral control external WDT 4150e is reset by hardware. That is, the peripheral control MPU 4150a is reset when a clear signal for clearing the timer of the peripheral control external WDT 4150e is not output to the peripheral control external WDT 4150e within a certain period (until the timer tie-maps). When the peripheral control MPU 4150a outputs a clear signal to the peripheral control external WDT 4150e within a certain period, the peripheral control external WDT 4150e can restart the timer count of the peripheral control external WDT 4150e, and therefore no reset is applied.

  The peripheral control MPU 4150a incorporates a plurality of parallel I / O ports, serial I / O ports, and the like, and upon receiving various commands from the main control board 4100, each decorative board of the game board 4 is received based on these various commands. The game board side light emission data for outputting lighting signals, blinking signals or gradation lighting signals to a plurality of LEDs etc. provided in the lamp is outputted from the serial I / O port for lamp driving board via a peripheral control output circuit (not shown). The game board side motor drive data for transmitting a drive signal to an electric drive source such as a motor or a solenoid for transmitting various kinds of movable bodies provided in the game board 4 to the drive board 4170 is serialized for the motor drive board. Transmission from the I / O port to the motor drive board 4180 via the peripheral control output circuit, or the power of the dial drive motor 414 provided on the door frame 5 or the like. Door side motor drive data for outputting a drive signal to the general drive source from the frame decoration drive amplifier board motor serial I / O port to the peripheral control output circuit, frame peripheral relay terminal plate 868, and peripheral door relay terminal plate 882 The door-side light emission data for transmitting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs provided on each decoration board of the door frame 5 is transmitted to the frame decoration drive amplifier board 194 via The frame decoration drive amplifier board LED serial I / O port transmits the frame decoration drive amplifier board 194 via the peripheral control output circuit, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882.

  Various commands from the main control board 4100 are input to the serial I / O port for main control board of the peripheral control MPU 4150a via a peripheral control input circuit (not shown). In addition, a detection signal from a rotation detection switch for detecting the rotation (rotation direction) of the dial operation unit 401 and a pressure detection switch for detecting the operation of the pressing operation unit 405 provided in the operation unit 400. The detection signal is serialized by a door-side serial transmission circuit (not shown) provided on the frame decoration drive amplifier board 194, and the serialized operation unit detection data is transmitted from the door-side serial transmission circuit to the peripheral door relay terminal plate 882, the frame. The signal is input to the operation unit detection serial I / O port of the peripheral control MPU 4150a via the peripheral relay terminal plate 868 and the peripheral control input circuit.

  Detection signals from various detection switches (for example, photosensors) for detecting the original positions and movable positions of various movable bodies provided on the game board 4 are on the game board side (not shown) provided on the motor drive board 4180. Serialized by the serial transmission circuit, and this serialized movable body detection data is input to the serial I / O port for the motor drive board of the peripheral control MPU 4150a from the serial transmission circuit on the game board via the peripheral control input circuit. Yes. The peripheral control MPU 4150a exchanges various data between the peripheral control board 4140 and the motor drive board 4180 by switching the input / output of the serial I / O port for the motor drive board.

  Peripheral control MPU 4150a has a built-in watchdog timer (hereinafter referred to as “peripheral control built-in WDT”). It is diagnosed whether or not.

<Peripheral control MPU>
Next, the peripheral control MPU 4150a which is a microcomputer will be described. As shown in FIG. 8, the peripheral control MPU 4150a has a peripheral control built-in RAM 4150ab, a peripheral control DMA (Direct Memory Access) controller 4150ac, a peripheral control bus controller 4150ad, a peripheral control various serial I, and the peripheral control CPU core 4150aa. / O port 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O ports 4150ag, peripheral control analog / digital converter (hereinafter referred to as peripheral control A / D converter) 4150ak, and the like.

  Peripheral control CPU core 4150aa reads / writes various data to / from peripheral control built-in RAM 4150ab and peripheral control DMA controller 4150ac via internal bus 4150ah, while peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT 4150af, Various data are read from and written to the various peripheral control parallel I / O ports 4150ag and the peripheral control A / D converter 4150ak via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai.

  The peripheral control CPU core 4150aa reads various data from the peripheral control ROM 4150b via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h, while reading from the peripheral control RAM 4150c and the peripheral control SRAM 4150d. Various data are read and written via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h.

  The peripheral control DMA controller 4150ac includes storage devices such as a peripheral control built-in RAM 4150ab, a peripheral control ROM 4150b, a peripheral control RAM 4150c, and a peripheral control SRAM 4150d, peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O port 4150ag and a dedicated controller that transfers data independently between the input / output devices such as the peripheral control A / D converter 4150ak without using the peripheral control CPU core 4150aa. ~ It has four channels called DMA3.

  Specifically, the peripheral control DMA controller 4150ac includes a storage device of a peripheral control built-in RAM 4150ab incorporated in the peripheral control MPU 4150a, various peripheral control serial I / O ports 4150ae and peripheral control built-in WDT 4150af incorporated in the peripheral control MPU 4150a. In order to transfer data independently between the peripheral control various parallel I / O ports 4150ag and the input / output devices such as the peripheral control A / D converter 4150ak without the peripheral control CPU core 4150aa. The peripheral control built-in RAM 4150ab reads / writes data from / to the storage device via the internal bus 4150ah, while the peripheral control serial I / O port 4150ae, the peripheral control built-in WDT 4150af, and the peripheral control various parallel I / O port 4150. g, and the peripheral control A / D converter input and output devices such as 4150Ak, via the peripheral control bus controller 4150ad and peripheral bus 4150Ai, reading and writing.

  The peripheral control DMA controller 4150ac is a storage device such as a peripheral control ROM 4150b, a peripheral control RAM 4150c, and a peripheral control SRAM 4150d, which are externally attached to the peripheral control MPU 4150a. Without the peripheral control CPU core 4150aa between the input / output devices such as the O port 4150ae, the peripheral control built-in WDT 4150af, the peripheral control various parallel I / O ports 4150ag, and the peripheral control A / D converter 4150ak. In order to transfer data independently, peripheral control bus controller 4150ad and external bus 4150h are connected to storage devices such as peripheral control ROM 4150b, peripheral control RAM 4150c, and peripheral control SRAM 4150d. The peripheral control I / O port 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O port 4150ag, peripheral control A / D converter 4150ak, etc. Reading and writing are performed via the control bus controller 4150ad and the peripheral bus 4150ai.

  The peripheral control bus controller 4150ad controls the internal bus 4150ah, peripheral bus 4150ai, and external bus 4150h to control the central processing unit of the peripheral control CPU core 4150aa, peripheral control built-in RAM 4150ab, peripheral control ROM 4150b, peripheral control RAM 4150c, and peripheral control Various devices such as storage devices such as SRAM 4150d, peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O ports 4150ag, and peripheral control A / D converter 4150ak It is a dedicated controller that exchanges various data between them.

  Peripheral control various serial I / O ports 4150ae are: lamp drive board serial I / O port, motor drive board serial I / O port, frame decoration drive amplifier board motor serial I / O port, frame decoration drive amplifier board LED Serial I / O port, frame decoration drive amplifier board motor serial I / O port, main control board serial I / O port, and operation unit information acquisition serial I / O port.

  Peripheral control built-in watchdog timer (peripheral control built-in WDT) 4150af is a timer for monitoring whether the system of the peripheral control MPU 4150a is running out of control. It has become. That is, if the peripheral control CPU core 4150aa starts the watchdog timer, the peripheral control CPU core 4150aa resets if it does not output a clear signal for clearing the timer to the peripheral control built-in WDT 4150af within a certain period (until the timer tie-maps). Will take. When the peripheral CPU core 4150aa starts the watchdog timer and outputs a clear signal to the peripheral control built-in WDT 4150af within a certain period, the peripheral count CPU core 4150aa can restart the timer count and is not reset.

  The peripheral control various parallel I / O port 4150ag outputs various latch signals such as a game board side motor drive latch signal and a door side motor drive light emission latch signal, and also outputs a clear signal to the peripheral control external WDT 4150e, The detection signals from various detection switches for detecting the original position and the movable position of various movable bodies provided on the board 4 are serialized by a game board side serial transmission circuit (not shown) provided on the motor drive board 4180, and this serial A movable body information acquisition latch signal for receiving the converted movable body detection data from the serial transmission circuit on the game board side by the serial I / O port for the motor drive board of the peripheral control MPU 4150a, or an upper decoration in the door frame 5 The lighting signal of the LED mounted on the upper decorative board of the unit 280 is output. This LED is a high-intensity white LED and serves as a confirmation notification lamp for informing that the occurrence of the big hit gaming state has been confirmed. In the present embodiment, by adopting a configuration in which the LED and the peripheral control various parallel I / O port 4150ag are electrically connected directly, the path between the LED and the peripheral control various parallel I / O port 4150ag is shortened. Therefore, it is possible to take noise countermeasures for lighting control of the LED having a significant meaning in games. The LED lighting control is executed in a peripheral control unit 1 ms timer interrupt process described later, and other LEDs and the like other than this LED are executed in a peripheral control unit steady process described later. It has become.

  The peripheral control A / D converter 4150ak is electrically connected to the volume adjustment volume 4140a, and the resistance value is changed by rotating the knob portion of the volume adjustment volume 4140a, and the resistance at the rotation position of the knob portion is changed. The voltage divided by the value is converted from an analog value to a digital value, and converted to a value in 1024 steps from a value 0 to a value 1023. In the present embodiment, the values of 1024 levels are divided into seven and managed as substrate volumes 0-6. The substrate volume 0 is set to mute, the substrate volume 6 is set to the maximum volume, and the volume is set to increase from the substrate volume 0 toward the substrate volume 6. The liquid crystal and sound control unit 4160 (a sound source built-in VDP 4160a to be described later) is controlled so that the volume is set to the substrate volume 0 to 6 and the speaker and door frame 5 housed in the speaker box 920 provided in the main body frame 3 Music and sound effects can be heard from the speakers. In this way, music and sound effects flow from the speakers housed in the speaker box 920 provided in the main body frame 3 and the speakers provided in the door frame 5 by volume adjustment based on the turning operation of the knob portion.

  In addition, in this embodiment, in addition to music and sound effects, notification sounds for notifying a hall clerk or the like of the occurrence of a malfunction of the pachinko gaming machine 1 or fraudulent acts on the pachinko gaming machine 1, contents related to game effects, etc. (For example, the screen spread on the game board side liquid crystal display device 1900 is rendered more powerful, or the game state is likely to shift to a game state advantageous to the player). ) Also flows from the speaker housed in the speaker box 920 provided in the main body frame 3 and the speaker provided in the door frame 5, but the notification sound and notification sound are used for volume adjustment based on the turning operation of the knob portion. It is a mechanism that flows without depending at all, and the volume from the mute to the maximum volume is controlled by a liquid crystal and sound control unit 4160 (a sound source built-in VDP 4160a described later). To control the adjusted. The volume adjusted by this program can be smoothly changed from the mute to the maximum volume, unlike the substrate volume divided into the above seven stages. Thus, for example, even when a hall clerk or the like rotates the knob portion of the volume adjustment volume 4140a to set the volume to a low level, the speaker and the door accommodated in the speaker box 920 provided in the main body frame 3 Although the production sound such as music and sound effects flowing from the speaker provided in the frame 5 is reduced, the volume is increased when the pachinko gaming machine 1 is malfunctioning or when the player is cheating (this embodiment) Then, the notification sound set to the maximum volume) can be played. Therefore, even if the volume of the production sound is reduced, it is possible to prevent the hall clerk or the like from becoming difficult to notice the occurrence of a malfunction or the player's cheating due to the notification sound. Also, based on the current board volume set by volume adjustment based on the turning operation of the knob part, the volume of the advertisement sound is reduced so as not to interfere with the music and sound effects. In addition to music and sound effects, there is a possibility that the screen unfolded on the game board side liquid crystal display device 1900 will be rendered more powerful, or the game state may be shifted to an advantageous game state. You can also announce that it is expensive.

<Peripheral control ROM>
The peripheral control ROM 4150b includes various control programs for controlling the peripheral control unit 4150, the liquid crystal and sound control unit 4160, the RTC control unit 4165, various data, various control data, various schedule data, and predetermined individual information (hereinafter, “ (Referred to as “regulated individual information”) (effect control storage unit). The various schedule data includes screen generation schedule data for generating a screen to be drawn on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 244, light emission mode generation schedule data for generating light emission modes of various LEDs, music And sound generation schedule data for generating sound effects and the like, and electric drive source schedule data for generating drive modes of electric drive sources such as motors and solenoids. The screen generation schedule data is configured by arranging screen data for defining the screen configuration in time series, and the order of screens to be drawn on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 244 is defined. Has been. The light emission mode generation schedule data is configured by arranging light emission data defining the light emission modes of various LEDs in time series. The sound generation schedule data is configured by arranging sound command data in time series, and defines the order in which music and sound effects flow. The sound command data includes an output channel number for instructing which output channel to use among a plurality of output channels in a built-in sound source of the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 described later, and a sound source built-in VDP 4160a. A track number for instructing which track to incorporate sound data such as music and sound effects out of a plurality of tracks in the built-in sound source is defined. The electrical drive source schedule data is configured by arranging drive data of electrical drive sources such as motors and solenoids in time series, and defines the operation of electrical drive sources such as motors and solenoids.

  Various control programs stored in the peripheral control ROM 4150b may be read out and executed directly from the peripheral control ROM 4150b, or copied to various control program copy areas of the peripheral control RAM 4150c described later when the power is turned on. Some are read and executed. In addition, various data, various control data, and various schedule data stored in the peripheral control ROM 4150b may be directly read from the peripheral control ROM 4150b, or when various power control data copy areas of the peripheral control RAM 4150c described later are turned on. Some of which are copied in the above are read out.

  Further, the peripheral control ROM 4150b is one of various control programs for controlling the RTC control unit 4165 to correct the luminance of the game board side liquid crystal display device 1900 according to the usage time of the game board side liquid crystal display device 1900. A brightness correction program is included. This brightness correction program corrects a decrease in brightness due to aging of the game board side liquid crystal display device 1900 when the backlight of the game board side liquid crystal display device 1900 is mounted with an LED type. The date and time when the game board side liquid crystal display device 1900 is first turned on, the current date and time, the luminance setting information, and the like are acquired from the built-in RAM of the RTC control unit 4165 described later, and the acquired luminance setting information is based on the correction information. To correct. This correction information is stored in advance in the peripheral control ROM 4150b. As will be described later, the brightness setting information includes brightness adjustment information for adjusting the range of the brightness of the LED, which is the backlight of the game board side liquid crystal display device 1900, from 100% to 70% in increments of 5%, The brightness of the LED that is the backlight of the game board side liquid crystal display device 1900 that is set is included. For example, the date and time when the game board side liquid crystal display device 1900 was first turned on and the current date and time From the date when the game board side liquid crystal display device 1900 is first powered on, when six months have already passed, the corresponding correction information (for example, 5%) is obtained from the peripheral control ROM 4150b, and the brightness When the brightness of the LED included in the setting information is 75% and the backlight of the game board side liquid crystal display device 1900 is turned on, the correction information acquired for this 75% is used. On the game board side, the brightness of the backlight of the game board side liquid crystal display device 1900 is adjusted based on the brightness adjustment information included in the brightness setting information so that the brightness is further increased by 5%. If December has already passed since the date when the liquid crystal display device 1900 was first turned on, the corresponding correction information (for example, 10%) is acquired from the peripheral control ROM 4150b, and the LED included in the luminance setting information When the backlight of the game board side liquid crystal display device 1900 is turned on with the brightness of 75%, the brightness setting is set so that the brightness is further increased by 10%, which is the correction information acquired with respect to 75%, to 85%. Based on the luminance adjustment information included in the information, the luminance of the backlight of the game board side liquid crystal display device 1900 is adjusted to light up.

<Peripheral control RAM>
A peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a, as shown in FIG. 8, is a backup that exclusively stores information to be backed up among various information updated by executing various control programs. A management target work area 4150ca, a backup first area 4150cb and a backup second area 4150cc for storing a copy of various information stored in the backup management target work area 4150ca, and a peripheral control ROM 4150b. Various control program copy area 4150cd for storing a copy of various control programs exclusively, and various data, various control data, various schedule data, etc. stored in peripheral control ROM 4150b Various control data copy area 4150ce that stores the data that has been copied, and various information that is updated when various control programs are executed. And a work area 4150cf.

  When the pachinko gaming machine 1 is turned on (including when power is restored due to a momentary power failure or a power failure), the value 0 is forcibly written to the backup unmanaged work area 4150cf and cleared to zero. For the backup management target work area 4150ca, the backup first area 4150cb, and the backup second area 4150cc, when the supply of power is started by the power source of the pachinko gaming machine 1 (at power-on), the main control board 4100 (power-on) The power-on command (see FIG. 10) outputted by the command output means instructs the start of the RAM clear effect and the start of each state effect (for example, in FIG. 6 within a predetermined period from when the power is turned on. Instructing the start of production when the indicated operation switch 952 is operated A) sometimes cleared to zero.

  The backup management target work area 4150ca is effect information (various information updated in the peripheral control unit steady process executed each time a V blank signal from the VDP 4160a with built-in sound source of the liquid crystal and sound control unit 4160 described later is input) Bank 0 (1fr) for storing 1fr) exclusively as a backup target, and production information (1ms) which is various information updated in the peripheral control unit 1ms timer interrupt process executed every time a 1ms timer interrupt described later occurs. Bank 0 (1 ms) is stored exclusively as a backup target. Here, the names of Bank0 (1fr) and Bank0 (1 ms) will be briefly described. “Bank” is a minimum management unit representing the size of a storage area for storing various information. The following 0 means a normally used storage area for storing various information updated by executing various control programs. That is, “Bank 0” means that the size of the storage area that is normally used is the minimum management unit. “Bank1,” “Bank2,” “Bank3,” and “Bank4” provided in an area extending from a backup first area 4150cb to a backup second area 4150cc, which will be described later, are stored in the same storage area as “Bank0”. It means having a size. As will be described later, “(1fr)” indicates that when the built-in sound source VDP 4160a outputs drawing data for one screen (one frame) to the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 244, the peripheral control MPU 4150a Since the V blank signal indicating that the screen data from the camera can be received is output to the peripheral control MPU 4150a, every time the V blank signal is input, in other words, one frame (1 frame) Since the peripheral control unit steady process is executed every time, “Bank 0”, “Bank 1”, “Bank 2”, “Bank 3”, and “Bank 4” are respectively added (effect information (1fr) and an effect described later) The backup information (1fr) is also used in the same meaning). As described later, “(1 ms)” indicates that “Bank 0”, “Bank 1”, “Bank 2”, “Bank 3”, And “Bank 4”, respectively (effect information (1 ms) and effect backup information (1 ms) to be described later are also used in the same meaning).

  Bank0 (1fr) includes a lamp drive board side transmission data storage area 4150caa, a frame decoration drive amplifier board side LED transmission data storage area 4150cab, a reception command storage area 4150cac, an RTC information acquisition storage area 4150cad, and a schedule data storage area 4150cae. Etc. are provided. In the lamp drive board side transmission data storage area 4150caa, game board side light emission data SL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs provided on each decoration board of the game board 4 is stored. The frame decoration drive amplifier board side LED transmission data storage area 4150cab is a storage area to be set. The lighting data, blinking signal, or gradation lighting signal for a plurality of LEDs provided on each decoration board of the door frame 5 is stored. This is a storage area in which door-side emission data STL-DAT for output is set, and the reception command storage area 4150cac receives various commands transmitted from the main control board 4100 and sets the received various commands. The RTC information acquisition storage area 4150cad is an RTC control unit 4165 (in the RTC of the RTC 4165a described later). Various information acquired from the RAM 4165aa) is a storage area in which the schedule data storage area 4150cae is based on a command received from the main control board 4100 (the main control MPU 4100a) and various schedules corresponding to the received command. A storage area in which data is set. In the schedule data storage area 4150cae, some schedule data copied from the peripheral control ROM 4150b to the various control data copy areas 4150ce are read and set, and various schedule data are directly read from the peripheral control ROM 4150b. Some are set.

  Bank 0 (1 ms) includes a frame decoration drive amplifier board side motor transmission data storage area 4150caf, a motor drive board side transmission data storage area 4150cag, a movable body information acquisition storage area 4150cah, an operation unit information acquisition storage area 4150cai, and history information. A storage area 4150caj and the like are provided. The frame decoration drive amplifier board side motor transmission data storage area 4150caf is set with door side motor drive data STM-DAT for outputting a drive signal to an electric drive source such as a dial drive motor 414 provided on the door frame 5. The motor drive board side transmission data storage area 4150cag is a game board for outputting a drive signal to an electric drive source such as a motor or solenoid for operating various movable bodies provided in the game board 4 This is a storage area in which the side motor drive data SM-DAT is set. In the movable body information acquisition storage area 4150cah, various information obtained by acquiring the original position and movable position of various movable bodies provided on the game board 4 based on detection signals from various detection switches provided on the game board 4 is set. The operation unit information acquisition storage area 4150cai is a rotation (rotation direction) of the dial operation unit 401 and an operation of the pressing operation unit 405 based on detection signals from various detection switches provided in the operation unit 400. And the like (for example, rotation history information of the dial operation unit 401 created based on detection signals from various detection switches provided in the operation unit 400, and operation history information of the pressing operation unit 405) Etc.) is a storage area to be set. On the other hand, the history information storage area 4150 caj has an operation history storage area in addition to a display history storage area described later. In this operation history storage area, information related to “specified handwriting” is stored in advance as an example of a specified contact state on the operation surface of the touch panel 246 (effect control storage means). The information on the prescribed handwriting includes, for example, information on at least one of a change in thickness and a change in drawing speed due to increase or decrease in writing pressure during drawing, which is a straight line or a curve.

  The bank 0 (1fr) lamp drive board side transmission data storage area 4150caa and the frame decoration drive amplifier board side LED transmission data storage area 4150cab, and the Bank 0 (1 ms) frame decoration drive amplifier board side motor transmission data storage area 4150caf. The motor drive board side transmission data storage area 4150cag is divided into two areas, a first area and a second area, respectively.

  In the lamp drive board side transmission data storage area 4150caa, when the peripheral control unit steady process described later is executed, the game board side light emission data SL-DAT is set in the first area of the lamp drive board side transmission data storage area 4150caa. When the next peripheral control unit steady process is executed, the game board side light emission data SL-DAT is set in the second area of the lamp drive board side transmission data storage area 4150caa. Each time the process is executed, the game board side light emission data SL-DAT are alternately set in the first area and the second area of the lamp drive board side transmission data storage area 4150caa. For example, when the game board side light emission data SL-DAT is set in the second area of the lamp drive board side transmission data storage area 4150caa in the current peripheral control part steady process, When the control unit steady process is executed, the process proceeds based on the game board side light emission data SL-DAT set in the first area of the lamp drive board side transmission data storage area 4150caa.

  When the peripheral control unit steady process is executed, the frame decoration drive amplifier board side LED transmission data storage area 4150cab has the door side light emission data STL in the first area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. -DAT is set, and when the next peripheral control unit steady process is executed, the door side light emission data STL-DAT is set in the second area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. Each time the peripheral control unit steady process is executed, the door side light emission data STL-DAT is alternately set in the first area and the second area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. The For example, when the door side light emission data STL-DAT is set in the second area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab in the current peripheral control part steady process, When the previous peripheral control unit steady process is executed, the process proceeds based on the door side light emission data STL-DAT set in the first area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. It has become.

  The frame decoration drive amplifier board side motor transmission data storage area 4150caf has a door in the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf when a later-described peripheral control unit 1 ms timer interrupt process is executed. When the side motor drive data STM-DAT is set and the next peripheral control unit 1 ms timer interrupt process is executed, the door side motor drive data STM is stored in the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. -DAT is set, and each time the peripheral control unit 1 ms timer interrupt process is executed, the door side is connected to the first area and the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. Motor drive data STM-DAT is set alternately. The peripheral control unit 1 ms timer interrupt process is executed. For example, in this peripheral control unit 1 ms timer interrupt process, the door side motor drive data STM-DAT is stored in the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. When set, the door side motor drive data STM-DAT set in the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf when the previous peripheral control unit 1 ms timer interrupt process was executed. The process is based on this.

  When the peripheral control unit 1 ms timer interrupt process is executed, the motor drive board side transmission data storage area 4150cag is set with the game board side motor drive data SM-DAT in the first area of the motor drive board side transmission data storage area 4150cag. When the next peripheral control unit 1 ms timer interrupt process is executed, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150cag, Each time the peripheral control unit 1 ms timer interrupt process is executed, the game board side motor drive data SM-DAT are alternately set in the first area and the second area of the motor drive board side transmission data storage area 4150cag. The peripheral control unit 1 ms timer interrupt process is executed. For example, in the current peripheral control unit 1 ms timer interrupt process, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150cag. Sometimes, when the previous peripheral control unit 1 ms timer interrupt process is executed, the process proceeds based on the game board side motor drive data SM-DAT set in the first area of the motor drive board side transmission data storage area 4150cag. It is like that.

  Next, the backup first area 4150cb and backup second area 4150cc that store specially copied production information, which is various information stored in the backup management target work area 4150ca, will be described. In the backup first area 4150cb and the backup second area 4150cc, two pairs each having two banks as one pair are managed as one page. Production information (1fr), which is the content stored in Bank0 (1fr), which is a storage area that is normally used, is produced as production backup information (1fr) every time the peripheral control unit steady process is executed for each frame (1frame). In addition, the production information (1 ms) which is the content stored in Bank0 (1 ms), which is a storage area normally used, is copied to the backup first area 4150 cb and the backup second area 4150 cc at high speed by the peripheral control DMA controller 4150ac. As the production backup information (1 ms), the peripheral control DMA controller 41 is assigned to the backup first area 4150 cb and the backup second area 4150 cc each time the peripheral control unit 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. It is copied to the high speed by 0ac. The consistency of one page is determined by whether or not the contents of two banks constituting the page match.

  Specifically, the backup first area 4150cb is managed as a pair of Bank1 (1fr) and Bank2 (1fr) as one pair, and Bank1 (1ms) and Bank2 (1ms) as one pair. ing. The contents stored in Bank0 (1fr), which is a storage area that is normally used, are the peripheral control DMA in Bank1 (1fr) and Bank2 (1fr) each time the peripheral control unit steady process is executed for each frame (1frame). The memory that is copied at a high speed by the controller 4150ac and stored in Bank0 (1 ms), which is a storage area that is normally used, is stored every time a peripheral control unit 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. The peripheral control DMA controller 4150ac copies the data to Bank1 (1ms) and Bank2 (1ms) at high speed. The consistency of this page is determined by whether or not the contents of Bank1 (1fr) and Bank2 (1fr) match. Bank1 (1ms) and Bank2 ( It carried out by whether or not the contents of the ms) are the same.

  The backup second area 4150cc is managed as one page with a total of two pairs, with Bank3 (1fr) and Bank4 (1fr) as one pair and Bank3 (1ms) and Bank4 (1ms) as one pair. The contents stored in Bank0 (1fr), which is a storage area that is normally used, are the peripheral control DMA in Bank3 (1fr) and Bank4 (1fr) each time the peripheral control unit steady process is executed for each frame (1frame). The memory that is copied at a high speed by the controller 4150ac and stored in Bank0 (1 ms), which is a storage area that is normally used, is stored every time a peripheral control unit 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. It is copied to Bank 3 (1 ms) and Bank 4 (1 ms) at high speed by the peripheral control DMA controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank 3 (1 fr) and Bank 4 (1 fr) match. Bank3 (1 ms) and Bank4 ( It carried out by whether or not the contents of the ms) are the same.

  As described above, in this embodiment, the backup first area 4150cb has one pair of Bank1 (1fr) and Bank2 (1fr), and one pair of Bank1 (1ms) and Bank2 (1ms). It is an area to manage as a page, and the backup second area 4150 cc has a total of 2 pairs, with Bank 3 (1 fr) and Bank 4 (1 fr) as one pair, Bank 3 (1 ms) and Bank 4 (1 ms) as one pair This is an area for management as one page. Different ID codes are stored at the beginning and end of each page, that is, at the beginning and end of the backup first area 4150cb and backup second area 4150cc.

  In the present embodiment, the production information (1fr) that is the content stored in Bank0 (1fr) that is a storage area that is normally used is the production control information (1fr), and the peripheral control unit for each frame (1frame). Every time the steady process is executed, the contents are copied to the backup first area 4150cb and the backup second area 4150cc at high speed by the peripheral control DMA controller 4150ac and stored in Bank0 (1 ms) which is a storage area used normally. The production information (1 ms) is, as production backup information (1 ms), every time the 1 ms timer interrupt is generated, the backup first area 4150 cb and the backup second area 4150 cc are executed each time the peripheral control unit 1 ms timer interruption process is executed. Peripheral control Although designed to be copied at a high speed by the MA controller 4150Ac, a program for executing a fast copy from these peripheral control DMA controller 4150Ac are common. That is, in this embodiment, the production information (1fr) and the production information (1 ms) are managed by a common management method (execution of a common program).

<Peripheral control SRAM>
A peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a includes a backup management target work area 4150da that exclusively stores information to be backed up among various information updated by executing various control programs. A backup first area 4150db and a backup second area 4150dc are provided for storing a copy of various information stored in the backup management target work area 4150da. The content stored in the peripheral control SRAM 4150d is a power-on command (see FIG. 10) from the main control board 4100 when the pachinko gaming machine 1 is powered on (including when power is restored due to a momentary power failure or a power failure). Instructing the start of the RAM clear effect and the start of each state effect (for example, instructing the start of the effect when the operation switch 952 shown in FIG. 6 is operated within a predetermined period from when the power is turned on. It is not cleared to zero. This is completely different from the point that the backup management target work area 4150ca, the backup first area 4150cb, and the backup second area 4150cc of the peripheral control RAM 4150c described above are cleared to zero. Further, when the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the power of the pachinko gaming machine 1 is turned on, a screen for performing the setting mode is displayed on the game board side liquid crystal display device 1900. It has come to be. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the setting mode screen, each content (item) stored in the peripheral control SRAM 4150d (for example, a history of occurrence of a big hit gaming state, etc.) On the other hand, the contents (items) stored in the peripheral control RAM 4150c are not displayed at all and cannot be cleared in the setting mode. This point is also completely different between the peripheral control RAM 4150c and the peripheral control SRAM 4150d.

  The backup management target work area 4150da is production information (SRAM) which is various information continued across days (for example, information for managing the history of occurrence of the big hit gaming state and special production flag management) Information) and the like are stored in a dedicated manner as a backup target. Here, the name of Bank0 (SRAM) will be briefly described. As described above, “Bank” is a minimum management unit that represents the size of a storage area for storing various types of information. The following 0 means a normally used storage area for storing various information updated by executing various control programs. That is, “Bank 0” means that the size of the storage area that is normally used is the minimum management unit. “Bank1,” “Bank2,” “Bank3,” and “Bank4” provided in an area extending from a backup first area 4150db to a backup second area 4150dc, which will be described later, are in the same storage area as “Bank0”. It means having a size. Since “(SRAM)” is a backup target of various information stored in the peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a, “Bank0”, “Bank1”, “Bank2”, “Bank3” , And “Bank4”, respectively (effect information (SRAM) and effect backup information (SRAM) to be described later are also used in the same meaning).

  Next, the backup first area 4150db and backup second area 4150dc that store specially copied production information (SRAM), which is various information stored in the backup management target work area 4150da, will be described. The backup first area 4150db and the backup second area 4150dc are managed with one pair of two banks, and one pair as one page. Production information (SRAM), which is the content stored in Bank0 (SRAM), which is a storage area that is normally used, is production backup information (SRAM) each time the peripheral control unit steady process is executed for each frame (1 frame). The peripheral control DMA controller 4150ac copies the backup first area 4150db and backup second area 4150dc at high speed. The consistency of one page is determined by whether or not the contents of two banks constituting the page match.

  Specifically, in the backup first area 4150db, Bank1 (SRAM) and Bank2 (SRAM) are managed as one pair, and this one pair is managed as one page. The contents stored in Bank0 (SRAM), which is a storage area that is normally used, are stored in the peripheral control DMA in Bank1 (SRAM) and Bank2 (SRAM) each time the peripheral control unit steady process is executed for each frame (1 frame). This page is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank1 (SRAM) and Bank2 (SRAM) match.

  In the backup second area 4150dc, Bank3 (SRAM) and Bank4 (SRAM) are managed as one pair, and this one pair is managed as one page. The contents stored in Bank0 (SRAM), which is a storage area that is normally used, are stored in the peripheral control DMA in Bank3 (SRAM) and Bank4 (SRAM) each time the peripheral control unit steady process is executed for each frame (1 frame). This page is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank3 (SRAM) and Bank4 (SRAM) match.

  As described above, in this embodiment, the backup first area 4150db is an area for managing Bank 1 (SRAM) and Bank 2 (SRAM) as one pair, and managing this one pair as one page. Reference numeral 4150 dc is an area for managing Bank 1 (SRAM) and Bank 4 (SRAM) as one pair, and managing this one pair as one page. Different ID codes are stored at the beginning and end of each page, that is, at the beginning and end of the backup first area 4150db and backup second area 4150dc.

[2-2-2. Liquid crystal and sound control unit]
The drawing control of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 244, the sound housed in the speaker box 920 provided in the main body frame 3 and the sound and the sound effected from the speakers provided in the door frame 5 The liquid crystal and sound control unit 4160 that performs control incorporates a sound source for performing sound control such as music and sound effects (hereinafter referred to as “built-in sound source”), and the game board side liquid crystal display device 1900 and A sound source built-in VDP (Video Display Processor) 4160a that performs drawing control of the upper plate side liquid crystal display device 244, a display area (first display region) of the game board side liquid crystal display device 1900, and an upper plate side liquid crystal display device 244 Various character data (and sprites with sprite numbers) as display contents displayed in the display area (second display area) Data) and sound control ROM 4160b (effect information storage area, effect information storage means) for storing various sound data such as music and sound effects, and serialized music and sound effects as audio data And an audio data transmission IC 4160c that transmits the frame decoration drive amplifier board 194.

  Further, in the liquid crystal and sound control ROM 4160b, as sprite data used for displaying a screen or an image to be described later, for example, annular image data used for displaying a ring-shaped display object (annular display object), an operation menu background image described later. Operation menu background image data used for display, selection display object image data used for displaying at least one selection display object described later, tone adjustment background image data used for displaying a volume adjustment screen including a volume scale described later, volume adjustment described later In addition to volume setting icon image data used for displaying icons, main body frame rear image data used for displaying the main body frame rear image in which the position of each part on the rear surface of the main body frame 3 is visible when viewed from the player, service mode screen Used to display service mode screen image data and break timer setting screen Break timer setting screen image data, and, during breaks screen image data used for displaying the break in the screen is stored. It should be noted that the liquid crystal and sound control ROM 4160b is only suggested display object image data used for display of a suggested display object to be described later for prompting the user to operate the display button shown in the display area of the upper dish side liquid crystal display device 244. First, contact prompting display object data used for displaying a touch prompting display object to be displayed on the upper plate side liquid crystal display device 244 for prompting to touch the operation surface of the touch panel 246 (contact type input means) is stored. (Data storage means).

  Furthermore, the liquid crystal and sound control ROM 4160b has display sizes for the display area (first display area) of the game board side liquid crystal display device 1900 and the display area (second display area) of the upper plate side liquid crystal display device 244. Size-converted image data used for changing and displaying each common image is stored in advance (effect control storage means).

  In the peripheral control unit 4150, the peripheral control MPU 4150a extracts screen generation schedule data corresponding to the command from the main control board 4100 from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. To 4150cae in the schedule data storage area of the peripheral control RAM 4150c. The peripheral control MPU 4150a extracts the top screen data of the screen generation schedule data set in the schedule data storage area 4150cae from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. After the output to the sound source built-in VDP 4160a, the next screen data following the first screen data according to the screen generation schedule data set in the schedule data storage area 4150cae is triggered when a V blank signal described later is input, Extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the VDP 4160a with built-in sound source. As described above, the peripheral control MPU 4150a converts the screen data arranged in time series into the screen generation schedule data according to the screen generation schedule data set in the schedule data storage area 4150cae every time the V blank signal is input. In addition, the first screen data is output to the built-in sound source VDP 4160a one by one.

  Also, the peripheral control MPU 4150a receives the sound command data at the head of the sound generation schedule data corresponding to the command from the main control board 4100 from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. Extracted and set to 4150cae in the schedule data storage area of the peripheral control RAM 4150c, and the head sound command data of the sound generation schedule data set in the schedule data storage area 4150cae is the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral After extracting from the various control data copy area 4150ce of the control RAM 4150c and outputting it to the sound source built-in VDP 4160a, the schedule data recording is triggered by the input of the V blank signal. In accordance with the sound generation schedule data set in the area 4150cae, the next sound command data following the head sound command data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c, and the sound source Output to built-in VDP 4160a. As described above, the peripheral control MPU 4150a receives the sound command data arranged in time series in the sound generation schedule data according to the sound generation schedule data set in the schedule data storage area 4150cae, and the V blank signal is input. Each time, the head sound command data is output to the built-in sound source VDP 4160a one by one.

<VDP with built-in sound source>
The sound source built-in VDP 4160a (drawing control means) includes a built-in RAM capable of temporarily storing data in addition to the above-described built-in sound source. As a part of such a built-in RAM, the sound source built-in VDP 4160a can store material image data such as sprite data temporarily, and a material image RAM (to be described later) as a transfer memory overwritten with a large number of material image data repeatedly. (Not shown).

  Furthermore, when the screen data included in the screen generation schedule data is input from the peripheral control MPU 4150a as a part of such a built-in RAM, the built-in sound source VDP 4160a is shown in FIG. 9 based on the input screen data. Thus, the game board side character data and the upper plate side character data are respectively extracted from the liquid crystal and sound control ROM 4160b to create the game board side sprite data and the upper plate side sprite data (hereinafter simply referred to as “sprite data”). The drawing data for one screen (one frame) respectively generated for display on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 244 is stored, and one screen (1 frame) is further used for video processing. A VRAM for storing drawing data for frames) is also built in (hereinafter referred to as “built-in VR”). To as M ".). The sound source built-in VDP 4160a outputs image data for the game board side liquid crystal display device 1900 out of the drawing data generated on the built-in VRAM (frame buffer) from the channel CH1 to the game board side liquid crystal display device 1900. By outputting image data for the liquid crystal display device 244 from the channel CH2 to the upper plate side liquid crystal display device 244, the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 244 are synchronized. Thus, when the peripheral control MPU 4150a outputs the screen data for one screen (one frame) displayed on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 244 to the sound source built-in VDP 4160a, the sound source built-in VDP 4160a Character data is extracted from the liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data and displayed on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 244 (1 Frame data) is generated on the built-in VRAM, and among the generated drawing data, image data for the game board side liquid crystal display device 1900 is output from the channel CH1 to the game board side liquid crystal display device 1900, and the upper plate side The image data for the liquid crystal display device 244 is moved up from the channel CH2. And outputs to the side the liquid crystal display device 244. That is, “screen data for one screen (for one frame)” means drawing data for one screen (for one frame) displayed on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 244. This is the data to generate above. In the following description, the extraction of character data from the liquid crystal and sound control ROM 4160b (reading) to create sprite data is also abbreviated as “reading sprite data from the liquid crystal and sound control ROM 4160b”.

  The sound source built-in VDP 4160a outputs drawing data for one screen (one frame) from the channel CH1 to the game board side liquid crystal display device 1900, and also outputs image data for the upper plate side liquid crystal display device 244 from the channel CH2. When output to the dish-side liquid crystal display device 244, a V blank signal indicating that the screen data from the peripheral control MPU 4150a can be received is output to the peripheral control MPU 4150a. In this embodiment, since the frame frequency (number of screen updates per second) of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 244 is set to approximately 30 fps per second, a V blank signal is output. The interval is about 33.3 ms (= 1000 ms ÷ 30 fps). The peripheral control MPU 4150a executes a peripheral control unit V blank signal interrupt process to be described later when this V blank signal is input. Here, the interval at which the V blank signal is output varies somewhat depending on the liquid crystal sizes of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 244. In addition, even in the manufacturing lot of the peripheral control board 4140 on which the peripheral control MPU 4150a and the built-in sound source VDP 4160a are mounted, the interval at which the V blank signal is output may change somewhat.

  The sound source built-in VDP 4160a employs a frame buffer method. In this “frame buffer system”, drawing data for one screen (one frame) to be drawn on the screens of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 244 is held in a frame buffer (built-in VRAM). The drawing data for one screen (one frame) held in the frame buffer is output to the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 244. In this embodiment, a so-called double buffer method is adopted.

  When the sound command data described above is input from the peripheral control MPU 4150a based on a command from the main control board 4100, the built-in sound source VDP 4160a, as shown in FIG. 9, stores music stored in the liquid crystal and sound control ROM 4160b. By extracting sound data such as sound and sound effects and controlling the built-in sound source, sound data such as music and sound effects are incorporated into the track according to the track number specified in the sound command data and used according to the output channel number The output channel is set and the music, sound effects, etc. flowing from the speaker housed in the speaker box 920 provided in the main body frame 3 and the speaker provided in the door frame 5 are serialized and output as audio data to the audio data transmission IC 4160c.

  Note that the sound command data also includes a sub-volume value for adjusting the volume of the track in which the sound data is incorporated, and a plurality of tracks in the built-in sound source of the sound source built-in VDP 4160a include effect sounds such as music and sound effects. In addition to the sound data and the sub-volume value for adjusting the sound volume, the sound data of the notification sound and the sound volume for notifying the clerk of the hall of the occurrence of the malfunction of the pachinko gaming machine 1 and the illegal act against the pachinko gaming machine 1 Incorporates a sub-volume value that adjusts. Specifically, for the production sound, the substrate volume adjusted by rotating the knob portion of the volume adjustment volume 4140a described above is set as the sub volume value, and for the notification sound, the volume adjustment is performed. The maximum volume is set as the sub-volume value without depending on the volume adjustment based on the turning operation of the knob portion of the volume 4140a. The sub-volume value of the effect sound is adjusted by shifting to a setting mode to be described later by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400.

  The sound designation data also includes a master volume value for adjusting the volume of the output channel. A plurality of output channels in the built-in sound source of the built-in sound source VDP 4160a include a plurality of sound channels in the built-in sound source of the sound source built-in VDP 4160a. Of the tracks, the sound data of the production sound built into the track to be used is combined with the sub-volume value that adjusts the volume of the production sound built into the track to be used. Actually, it amplifies the master volume value that is the volume that flows from the speaker housed in the speaker box 920 provided in the main body frame 3 and the speaker provided in the door frame 5, and serializes the amplified effect sound as audio data. The data is output to the data transmission IC 4160c.

  In the present embodiment, the master volume value is set to a constant value, and when the volume of the combined production sound is the maximum volume, the master volume value is amplified to the speaker volume 920 provided in the main body frame 3. The volume that flows from the speaker housed in the speaker and the speaker provided on the door frame 5 is set to be an allowable maximum volume. Specifically, for the production sound, among the multiple tracks, the sound data of the production sound incorporated in the track to be used and the sub-volume value that adjusts the volume of the production sound incorporated in the track to be used The set volume of the volume adjustment volume 4140a is combined with the substrate volume adjusted by turning the volume, and the volume of the combined effect sound is actually applied to the speaker box 920 provided in the main body frame 3. It amplifies up to the master volume value that is the volume that flows from the speakers that are housed and the speakers provided on the door frame 5, serializes the amplified effect sound, and outputs it to the audio data transmission IC 4160c as audio data. , Sound data of the notification sound built into the track to be used and the volume of the notification sound built into the track to be used By combining the maximum volume without depending on the volume adjustment based on the turning operation of the knob portion of the volume adjustment volume 4140a set as the sub-volume value to be adjusted, the volume of the synthesized notification sound is actually Amplification is performed up to a master volume value that is a volume flowing from a speaker housed in the speaker box 920 provided in the main body frame 3 and a speaker provided in the door frame 5, and the amplified notification sound is serialized and audio data transmission IC 4160c as audio data. Output to.

  Here, when the production sound is flowing from the speaker housed in the speaker box 920 provided in the main body frame 3 and the speaker provided in the door frame 5, the occurrence of the malfunction of the pachinko gaming machine 1 or the illegality to the pachinko gaming machine 1 A brief explanation of the control for playing a notification sound in order to notify the store clerk of the action, etc. First, the sub volume value of the track in which the production sound is incorporated is forcibly set to mute, and this production sound is incorporated. The sound data of the track, the sub-volume value set to mute the sound, the sound data of the track in which the notification sound is incorporated, and the sub-volume value where the volume of the notification sound is set to the maximum volume are combined, and this combination The volume of the produced sound and the volume of the notification sound are actually set in the speaker housed in the speaker box 920 provided in the main body frame 3 and the speaker provided in the door frame 5. Amplified to a master volume value as the volume flowing from over, and outputs the amplified effect sound and alarm sound as an audio data to the audio data transmission IC4160c Serialize.

  In other words, the sound that flows from the speaker housed in the speaker box 920 provided in the main body frame 3 and the speaker provided in the door frame 5 is only the notification sound of the maximum volume. At this time, since the production sound is muted, the production sound does not flow from the speaker housed in the speaker box 920 provided in the main body frame 3 and the speaker provided in the door frame 5, but the production sound is the sound generation schedule described above. Progressing according to data. In this embodiment, the notification sound flows from the speaker housed in the speaker box 920 provided in the main body frame 3 and the speaker provided in the door frame 5 for a predetermined period (for example, 90 seconds). After a lapse of time, the volume of the effect sound that has been progressing according to the sound generation schedule data that has been forcibly set to mute so far has been adjusted by rotating the knob portion of the volume adjustment volume 4140a. Is set again as a value (at this time, when the display button is operated to adjust to the setting mode, the sub-volume value of the adjusted effect sound is set) and provided in the body frame 3 From the speakers accommodated in the speaker box 920 and the speakers provided on the door frame 5.

  As described above, when the production sound flows from the speaker housed in the speaker box 920 provided in the main body frame 3 and the speaker provided in the door frame 5, the occurrence of the malfunction of the pachinko gaming machine 1 or the pachinko gaming machine 1 When a notification sound flows to notify the store clerk or the like of an illegal act, the volume of the production sound is muted and the notification sound is provided in the speaker and door frame 5 housed in the speaker box 920 provided in the main body frame 3. Although the silenced production sound flows from the speaker, it proceeds according to the schedule data for sound generation, and therefore the speaker and door accommodated in the speaker box 920 provided in the main body frame 3 after a predetermined period of time has passed. When the speaker provided in frame 5 stops flowing, the production sound does not start again from where the notification sound started to flow, So that the start flowing again from where it proceeds in accordance with sound generation schedule data up to the point where it was starting to flow the lapse of a predetermined period of time.

<LCD and sound control ROM>
As shown in FIG. 9, the liquid crystal and sound control ROM 4160b is used for drawing on the game board side character data for drawing in the display area of the game board side liquid crystal display device 1900 and in the display area of the upper plate side liquid crystal display device 244. The upper plate side character data is stored in advance, and various sound data such as music, sound effects, notification sounds, and notification sounds are also stored in advance.

<Audio data transmission IC>
When the audio data transmission IC 4160c receives the serialized audio data from the sound source built-in VDP 4160a, the audio data transmission IC 4160c transmits the right audio data to the frame decoration drive amplifier substrate 194 as differential serial data having a plus signal and a minus signal. At the same time, the left audio data is transmitted toward the frame decoration drive amplifier board 194 as differential serial data using a plus signal and a minus signal. Thereby, music, sound effects, etc. adapted to various effects are reproduced in stereo from the speakers housed in the speaker box 920 provided in the main body frame 3 and the speakers provided in the door frame 5.

  Note that the audio data transmission IC 4160c outputs audio data between the boards extending from the peripheral control board 4140 to the frame decoration drive amplifier board 194 as left and right difference type serial data, for example, a positive signal of left audio data, Even when the negative signal is affected by noise, the frame decoration drive amplifier board 194 combines the noise component riding on the plus signal and the noise component riding on the minus signal into one left audio data. Since noise components are canceled by canceling each other, noise countermeasures can be taken.

[2-2-3. RTC control unit]
As shown in FIG. 7, the RTC control unit 4165 that holds calendar information for specifying the date and time and time information for specifying the hour, minute, and second is configured with the RTC 4165a as the center. The RTC 4165a incorporates a RAM 4165aa (timekeeping storage unit) that holds calendar information and time information (hereinafter referred to as “RTC built-in RAM 4165aa”). The RTC 4165a is supplied with power from a battery 4165b (a button battery is used in this embodiment) as a driving power source and a backup power source (second power source) for the RTC built-in RAM 4165aa. That is, the RTC 4165a is not supplied with any power from the peripheral control board 4140 (pachinko gaming machine 1), but is supplied with power from the battery 4165b independently of the peripheral control board 4140 (pachinko gaming machine 1). Thereby, even if the power of the pachinko gaming machine 1 is cut off, the RTC 4165a updates and holds calendar information and time information by supplying power from the battery 4165b. The battery 4165b supplies power (second power) triggered by the reception of a power failure warning signal described later, separately from the main power supply (first power supply) that supplies power (first power). The supply of power (second power) may be stopped when the supply of power by the main power supply is started. In such a power supply form, the RTC 4165a is connected to the main power supply or the battery 4165b. Is supplied with power.

[2-2-4. Volume adjustment volume]
As described above, the volume adjustment volume 4140a is used to rotate the knob portion to adjust the volume of music, sound effects, etc. flowing from the speaker housed in the speaker box 920 provided in the main body frame 3 and the speaker provided in the door frame 5. To adjust. As described above, the volume adjustment volume 4140a is configured such that the resistance value can be changed by rotating the knob portion, and the electrically connected peripheral control A / D converter 4150ak is connected to the knob portion. The voltage divided by the resistance value at the rotational position is converted from an analog value to a digital value, and converted into a value in 1024 steps from 0 to 1023. In the present embodiment, as described above, the values of the 1024 steps are divided into seven and managed as the substrate volumes 0 to 6. The substrate volume 0 is set to mute, the substrate volume 6 is set to the maximum volume, and the volume is set to increase from the substrate volume 0 toward the substrate volume 6. The liquid crystal and sound control unit 4160 (VDP 4160a with built-in sound source) is controlled so that the volume is set to the substrate volume 0 to 6, and the speaker and door frame 5 provided in the speaker box 920 provided in the main body frame 3 are provided. Music and sound effects are heard from the speakers.

[3. Various commands sent from the main control board]
Next, various commands transmitted from the main control board 4100 to other control boards will be described. Control boards to which various commands are transmitted from the main control board 4100 include, for example, a payout control board 4110 that performs payout control of game balls, and a peripheral control board 4140 that provides game effects. Here, various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described with reference to FIGS.

  FIG. 10 is a table showing an example of various commands transmitted from the main control board to the peripheral control board, and FIG. 11 is a table showing the continuation of various commands transmitted from the main control board to the peripheral control board in FIG. .

  The main control MPU 4100a of the main control board 4100 transmits various commands to the peripheral control board 4140 based on the progress of the game. As shown in FIG. 10 and FIG. 11, the various commands are related to special figure 1 synchronized effect, special figure 2 synchronized effect related, jackpot related, power-on, general synchronized effect related, ordinary electric role effect related, notification display, state Classified into display, test related, and others. These various commands are commands having a storage capacity of 2 bytes (16 bits). As shown in FIG. 10 and FIG. 11, the status (1) has a storage capacity of 1 byte (8 bits) and indicates the type of command. (STTS value) and a mode (MODE value) having a storage capacity of 1 byte (8 bits) and showing variations in performance.

  For these status (STTS value) and mode (MODE value), values of a plurality of transmission information storage areas (hereinafter also referred to as “RWM”) secured in the transmission information storage area of the main control built-in RAM are used. That is, among the 8 bits of each command, for example, the upper 3 bits use the value of the first transmission information storage area (RWM1), while the lower 5 bits use the value of the second transmission information storage area (RWM2). In this way, in the peripheral control board 4140, when the peripheral control MPU 4150a receives a command transmitted from the main control board 4100, the command can be disassembled bit by bit to grasp the status and mode.

[3-1. Special Figure 1 Entrainment Production Related]
The special figure 1 tuning effect related is based on the detection signal from the first starter switch 3022 shown in FIG. 6, and is divided into the function display board 1191 shown in FIG. 6 as shown in FIG. The first special symbol display 1185 is composed of commands named special figure 1 synchronization effect start, special symbol 1 designation, special figure 1 tuning effect end, and variable state designation. These various commands are assigned “A * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The special figure 1 synchronized production start command is a command for instructing the start of the special figure synchronized production with the production pattern designated in the mode, and the special symbol 1 designation command is used for designating off, specific big hit, and non-specific big hit. Command. The special figure 1 tuning effect end command is a command for instructing the end of the special figure 1 tuning effect, and the change state designation command is a command for instructing a transition to at least one of the probability and the short time state.

  As for the transmission timing of these various commands, the special symbol 1 tuning effect start command is transmitted at the start of the special symbol 1 fluctuation start, and the special symbol 1 designation command is transmitted immediately after the special symbol 1 tuning effect starts. The synchronized production end command is transmitted when the special symbol 1 variation time elapses (when the special symbol 1 is confirmed), and the variation state designation command is transmitted immediately after the special symbol winning information designation. These various commands are actually transmitted in the peripheral control board command transmission process (step S92) in the main control timer interruption process described later (command transmission means).

[3-2. Special figure 2 synchronized production]
The special figure 2 synchronization effect related is based on the detection signal from the second start port switch 2109 shown in FIG. 6, and is divided into the function display board 1191 shown in FIG. 6 as shown in FIG. The second special symbol display 1186 is composed of commands with names of special figure 2 synchronization effect start, special symbol 2 designation, and special figure 2 synchronization effect end. These various commands are assigned “B * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The special figure 2 synchronized production start command instructs the start of the special figure synchronized production with the production pattern designated in the mode, and the special symbol 2 designated command designates the off, specific big hit, and non-specific big hit. The end of the special figure 2 synchronization effect instructs the end of the special figure 2 synchronization effect.

  As the transmission timing of these various commands, the special symbol 2 tuning effect start command is transmitted when the special symbol 2 fluctuation starts, and the special symbol 2 designation command is transmitted immediately after the start of the special symbol 2 tuning effect. The effect end command is transmitted when the special symbol 2 variation time has elapsed (when the special symbol 2 is confirmed). These various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control timer interrupt process.

[3-3. Jackpot related]
As shown in FIG. 10, the jackpot-related category includes a jackpot opening, a grand prize opening 1 open Nth display, a big prize opening 1 closing display, a big prize opening 1 count display, a big hit ending, a big hit symbol display, and a small hit opening , A small hit opening display, a small hit count display, and a command with the names of small hit ending. These commands are assigned “C * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The jackpot opening command is for instructing the start of the jackpot opening, and the Nth display command for the winning prize opening 1 is started during the opening of the winning prize opening 1 for the 1st to 16th rounds (the opening of the winning prize opening 2103 of the attacker unit 2100). The Nth round opening is instructed, and the grand prize opening 1 closing display command is the start of closing the big winning opening 1 between rounds (between the rounds of the big winning opening 2103 of the attacker unit 2100) The winning prize 1 count display command indicates that 0 to 10 counts have been counted (in the winning prize opening 2103 detected by the count switch 2110 shown in FIG. 6). The number of game balls entered), the jackpot ending command indicates the start of the jackpot ending Are those, big hit symbol display command is for instructing the big hit symbol information display.

  The small hit opening command is for instructing the start of the small hit opening, and the small hit opening display command is for starting the small hit opening (during opening or releasing the big winning opening 2103 of the attacker unit 2100 at the time of the small hit). The small hit count display command is used when the count switch 2110 detects a game ball that has entered the big winning opening 2103 during the small hit. The small hit ending command is an instruction to start the small hit ending.

  As the transmission timing of these various commands, the big hit opening command is sent at the start of the big hit opening, and the big winning opening 1 opening N-th display command is when the big winning opening 1 is opened in the 1st to 16th rounds (the large amount of the attacker unit 2100). The winning prize opening 1 closing display command is sent when the winning prize opening 1 is closed (when the closing of the big winning opening 2103 of the attacker unit 2100 is started). The winning opening 1 count display command is used when the winning opening 1 is opened and when the count of the winning opening 1 is changed (when the winning opening 2103 of the attacker unit 2100 is opened and when the game ball has entered the winning opening 2103 is counted. The jackpot ending command is sent to the jackpot ending when it is detected by the switch 2110) Is sent to the big hit symbol display command is sent during the special winning opening open (when opening the special winning opening 2103 attacker unit 2100).

  The small hit opening command is transmitted at the start of the small hit opening, and the small hit release display command is transmitted when the small hit is released (when the big winning opening 2103 of the attacker unit 2100 is opened at the small hit). The hit count display command is transmitted at the time of winning a small hit medium / large winning opening (when a game ball that has entered the large winning opening 2103 is detected by the count switch 2110 during the small hit), and the small hit ending command is Sent when a small hit ending starts. These various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control timer interrupt process.

[3-4. Power on]
As shown in FIG. 10, the power-on category includes various commands named power-on. This power-on command is assigned “D * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The power-on command instructs the start of the RAM clear effect and the start of each state effect (for example, instructs to start the effect when the operation switch 952 of the payout control board 4110 is operated when the power is turned on. Is).

  As the transmission timing of the power-on command, it is transmitted when the main control board power is turned on when the RAM is not cleared and when the RAM is not cleared. Specifically, when the power of the pachinko gaming machine 1 is turned on, when the operation switch 952 of the payout control board 4110 is operated when returning from a power failure or a momentary power failure, the main control side power-on process described later Is executed, and a power-on command is transmitted in the peripheral control board command transmission process of step S92 in the main control timer interrupt process.

[3-5. General drawing related production]
The general-synchronization effect is based on the detection signal from the gate switch 2301 shown in FIG. 6, and is divided into the normal symbol display of the function display board 1191 shown in FIG. The command 1189 is composed of commands with the names of general drawing synchronization production start, universal symbol designation, universal drawing synchronization production end, and variable state designation. These various commands are assigned “E * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The general pattern synchronization production start command is for instructing the general pattern synchronization production start with the production pattern specified in the mode, and the general pattern designation command is for specifying off, specific big hit, non-specific big hit, The figure synchronization effect end command is for instructing the end of the common figure synchronization effect, and the change state designation command is for instructing the probability and the short time state.

  As the transmission timings of these various commands, the general symbol synchronization effect start command is transmitted at the time of the normal symbol 1 fluctuation start, the general symbol designation command is transmitted immediately after the general symbol synchronization effect start, and the general symbol synchronization effect end command is Is transmitted when the normal symbol fluctuation time has elapsed (when the normal symbol is determined), and the variable state designation command is transmitted immediately after the normal symbol winning information designation. These various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control timer interrupt process.

[3-6. Ordinary electric role production related]
The ordinary electric role effect is related to a pair of movable pieces 2106 that are opened and closed by driving of the start opening solenoid 2105. As shown in FIG. It consists of commands named ending per usual figure. These various commands are assigned “F * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The opening command per base map is an instruction to start the opening per base map, and the open command display command is a normal power open start (a pair of movable pieces 2106 are expanded in the horizontal direction by driving the start opening solenoid 2105). The ending command per universal map indicates the start of ending per universal map.

  As the transmission timing of these various commands, the opening command per base map is transmitted at the start of the opening per base map, and the general power open display command is displayed when the general power is open (the pair of movable pieces 2106 are driven by the start opening solenoid 2105). The ending command per universal map is transmitted at the start of ending per universal map. These various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control timer interrupt process.

[3-7. Notification display]
As shown in FIG. 11, the notification display section is composed of commands named as winning abnormality display, connection abnormality display, disconnection / short circuit abnormality display, magnetic detection switch abnormality display, door opening, and door closing. These various commands are assigned “6 * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The winning abnormality display command is used when a game ball enters the big winning port 2103 of the attacker unit 2100 when the ball enters the big winning port 2103 other than during the big hit (when the condition device is operating). When the ball is detected by the count switch 2110), the start of a prize abnormality notification is instructed. The connection abnormality display command is, for example, instructing the start of connection abnormality notification when there is an electrical connection abnormality in the path between the main control board 4100 and the payout control board 4110. The display command is, for example, when the electrical connection between the main control board 4100 and the first start port switch 3022, the second start port switch 2109, the count switch 2110, or the like is disconnected or short-circuited. The start of abnormality display is instructed, and the magnetic detection switch abnormality display command is an instruction to start the magnetic detection switch abnormality notification when an abnormality occurs in the magnetic detection switch 3024.

  The door frame opening command is generated when the door frame 5 is opened with respect to the main body frame 3 based on a detection signal (open signal) from the door frame opening switch 618 input via the payout control board 4110. In some cases, the door opening notification is instructed, and the door frame closing command is a state in which the door frame 5 is closed with respect to the main body frame 3 based on a detection signal from the door frame opening switch 618. In this case, the end of door opening notification is instructed. On the other hand, the main body frame opening command is generated in a state where the main body frame 3 is released from the outer frame 2 based on a detection signal (open signal) from the main body frame opening switch 619 input via the payout control board 4110. In some cases, a body frame opening notification is instructed, and the body frame closing command is issued in a state where the body frame 3 is closed with respect to the outer frame 2 based on a detection signal from the body frame opening switch 619. In some cases, an instruction to end the body frame release notification is given.

  As the transmission timing of these various commands, the winning abnormality display command is transmitted when winning a big winning opening other than during the big hit (the condition device is operating), and the connection abnormality displaying command is sent from the main control board 4100 to the payout control board 4110. The command is sent when there is no ACK reply (ACK signal) from the payout control board 4110 at the time of command transmission, and the disconnection / short circuit abnormality display command includes the first start port switch 3022, the second start port switch 2109, the count switch 2110, etc. The magnetic detection switch abnormality display command is transmitted when an abnormality of the magnetic detection switch 3024 is detected. The door frame opening command is transmitted when door opening is detected (when the door frame 5 is in an open state with respect to the main body frame 3 based on a detection signal from the door frame opening switch 618). The door frame closing command is transmitted when door closing is detected (when the door frame 5 is closed with respect to the main body frame 3 based on a detection signal from the door frame opening switch 618). The body frame release command is transmitted when the body frame release is detected (when the body frame 3 is opened to the outer frame 2 based on the detection signal from the body frame release switch 619). The frame closing command is transmitted when the body frame closing is detected (when the body frame 3 is closed with respect to the outer frame 2 based on the detection signal from the body frame opening switch 619). These various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control timer interrupt process.

[3-8. Status display]
As shown in FIG. 11, the status display section is composed of commands named frame status 1 command (corresponding to an error occurrence command), error canceling navigation command (corresponding to error canceling command), and frame status 2 command. Yes. These various commands are assigned a status of “7 * H” and a mode of “** H” (“H” represents a hexadecimal number) (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The frame state 1 command, the error canceling navigation command, and the frame state 2 command are each commands having a storage capacity of 1 byte (8 bits) transmitted from the payout control board 4110, and detailed description thereof will be described later. . When the main control MPU 4100a of the main control board 4100 receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, as shown in FIG. 11, “7 * H” is displayed. While setting as a status, the received command is set as a mode as it is. That is, when the main control MPU 4100a receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, it adds “7 * H” as additional information to these received commands. Thus, the command is shaped into a command having a storage capacity of 2 bytes (16 bits).

  The shaped frame status 1 command is transmitted when the power is restored, when the status of the frame is changed, and when the error cancellation navigation is performed. The error cancellation navigation command is transmitted during the error cancellation navigation. The frame status 2 command is transmitted when the power is restored. And when the frame state changes. Note that the shaped frame state 1 command, error release navigation command, and frame state 2 command are actually transmitted in the peripheral control board command transmission process of step S92 in the main control timer interrupt process.

[3-9. Test related]
As shown in FIG. 11, the test-related category includes various commands named “test”. This test command is assigned “8 * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). And is predetermined according to the specification content of the pachinko gaming machine 1).

  The test command is a command transmitted from the main control board 4100 to the peripheral control board 4140 and instructs various inspections of the peripheral control board 4140. Examples of such test commands include various substrates such as the peripheral control unit 4150, the liquid crystal and sound control unit 4160, the lamp driving substrate 4170, the motor driving substrate 4180, and the frame decoration driving amplifier substrate 194 shown in FIG. List the commands that perform the inspection.

  In this main control board 4100, test command ports are assigned one by one for the convenience of the hardware, so that it is difficult to manage on the hardware side. Ports that can be managed by a software timer are assigned to a predetermined port among a plurality of ports, while those that can be managed by a flag are assigned to specific ports.

  As a test command transmission timing, it is transmitted when the main control board power is turned on when the RAM is not cleared and when the RAM is not cleared. Specifically, when the power of the pachinko gaming machine 1 is turned on, when the operation switch 952 of the payout control board 4110 is operated when returning from a power failure or a momentary power failure, the main control side power-on process described later And the test command is transmitted in the peripheral control board command transmission process in step S92 in the main control timer interruption process.

[3-10. Others]
The other categories include, as shown in FIG. 11, start opening prize, change shortening operation end designation, high probability end designation, special symbol 1 memory, special symbol 2 memory, normal symbol memory, special symbol 1 memory pre-reading effect, and A command with a name of special symbol 2 storage prefetching effect is included. These various commands are assigned a status of “9 * H” and a mode of “** H” (“H” represents a hexadecimal number) (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The start opening prize command is an instruction to start the start opening winning effect, and the start of the effect when a game ball enters the first start opening 2101 based on the detection signal from the first start opening switch 3022. , And the start of the effect when a game ball enters the second start port 2102 based on the detection signal from the second start port switch 2109, respectively, A command for instructing a state transition from a shortened operating state to a variable shortening non-operating state, and a high-probability end designation command is performed from a high-probability state (corresponding to a probability variation state described later) to a low-probability state (such as a normal gaming state described later). The special symbol 1 storage command (special symbol storage command) is a special symbol 1 hold 0-4 pieces (free play to the first starting port 2101). The ball enters and the first special symbol display 1185 of the function display board 1191 informs the number of balls not yet used for the special symbol variable display (the number of holdings), and the special symbol 2 storage command (special The special symbol 2 hold 0 to 4 special symbols 2 (game balls have entered the second start port 2102 and the second special symbol indicator 1186 of the function display board 1191 is still used for the special symbol variation display. The normal symbol storage command is 0 to 4 normal symbols 1 held (the game ball passes through the gate part 2350 and the normal symbol display 1189 on the function display board 1191). The special symbol 1 storage pre-reading effect command (preceding judgment instruction command) indicates that the special symbol 1 hold is a function display base. Before the first special symbol display 1185 of 1191 is used to display the variation of the special symbol, the pre-reading effect is started to pre-read and notify the advance notice of the display result by the first special symbol display 1185 based on the special symbol 1 hold. The special symbol 2 storage pre-reading effect command (preceding judgment instruction command) is used before the special symbol 2 hold is used for the special symbol variable display on the second special symbol display 1186 of the function display board 1191. In addition, pre-reading is instructed to notify the advance notice of the display result by the second special symbol display 1186 based on the special symbol 2 reservation. In the present embodiment, these special symbol 1 storage pre-reading effect commands and special symbol 2 storage pre-reading effect commands are also collectively referred to as “special symbol storage pre-reading effect commands”.

  As the transmission timing of these various commands, the start opening prize command is the start opening prize (when a game ball enters the first start opening 2101 based on the detection signal from the first start opening switch 3022, When a game ball enters the second start port 2102 based on a detection signal from the start port switch 2109), the speaker housed in the speaker box 920 provided in the main body frame 3 shown in FIG. The change reduction operation end designation command is transmitted from the speaker provided in the door frame 5 shown in order to notify the effect mainly by voice. The high probability end designation command is sent at the end of the stop period after the change is confirmed after digesting the high probability count in the case of “high probability N times” (after the stoppage stop period has elapsed). The special symbol 1 storage command is received when the special symbol 1 operation holding ball number changes (the game ball enters the first start port 2101 and the special symbol 1118 of the function display board 1191 changes the special symbol). In a state where there is a number of reserves that are not yet used for display, when a game ball enters the first starting port 2101 and the number of reserves increases, the special symbol is displayed on the first special symbol display 1185 from the number of reserves. The special symbol 2 storage command is used when the number of special symbol 2 actuated reserve balls changes (the game ball enters the second starting port 2102 and functions). When there is a reserve number that is not yet used for the special symbol variation display on the second special symbol display 1186 of the display board 1191, when the game ball enters the second start port 2102 and the reserve number increases. And its maintenance The second special symbol display 1186 is used to display the change in the number of reserved symbols when the number of reserved symbols decreases, and the normal symbol storage command is used when the number of normal symbols 1 operation reserved balls changes (gate unit 2350). And the game ball passes through the gate portion 2350, and the number of holds is increased. The special symbol 1 storage pre-reading effect command is held when the number of reserves increases or when the number of reserves decreases by using the normal symbol display 1189 to display the fluctuation of the normal symbols. It is sent when the number of balls increases (when a game ball enters the first start port 2101 and the number of holds increases), the special symbol 2 memory pre-reading effect command is sent when the number of balls held for special symbol 2 increases (second When the game ball enters the start port 2102 and the number of held balls increases, this is transmitted. These various commands are actually transmitted in the peripheral control board command transmission process in step S92 in the main control timer interrupt process.

  By the way, as described above, the start opening prize command is given at the start opening winning (when a game ball enters the first start opening 2101 based on the detection signal from the first start opening switch 3022, Based on the detection signal from the switch 2109, when a game ball enters the second starting port 2102), the speaker housed in the speaker box 920 provided in the main body frame 3 and the speaker provided in the door frame 5 are mainly used. Although it is transmitted to notify that effect by voice, how the peripheral control board 4140 shown in FIG. 7 uses the start opening winning command may differ depending on the specifications of the pachinko gaming machine. For example, in the pachinko gaming machine 1 according to the present embodiment, in addition to notifying by voice from speakers housed in the speaker box 920 provided in the main body frame 3 and speakers provided in the door frame 5, the presence or absence of fraudulent acts is monitored. It is a thing of the specification to use also for. On the other hand, in other pachinko gaming machines, the peripheral control board 4140 simply receives the start opening prize command, and the speaker accommodated in the speaker box 920 provided in the main body frame 3 and the speaker provided in the door frame 5 There is also a specification that does not notify by voice.

[4. Various control processes of main control board]
Next, various control processes performed by the main control board 4100 in accordance with the progress of the game of the pachinko gaming machine 1 will be described with reference to FIGS. 12 is a flowchart showing an example of main control-side power-on processing, FIG. 13 is a flowchart showing continuation of main-control-side power-on processing in FIG. 12, and FIG. 14 is an example of main control-side timer interrupt processing. It is a flowchart which shows. First, various random numbers used for game control will be described, and then the operation of the initial value update type counter, main control side power-on processing, and main control side timer interrupt processing will be described.

[4-1. Various random numbers]
As the various random numbers used for game control, a big hit judgment random number for use in determining whether or not to generate a big hit gaming state or a small hit gaming state, and a big hit for use in determining the initial value of this big hit judgment random number A random number for determining an initial value for determination, a random number for determination of reach for use in determining whether or not a reach (reach out of reach) is generated when a big hit gaming state is not generated, a first special symbol display 1185 and a second The random display pattern random number used for determining the variable display pattern of the special symbol variably displayed on the special symbol display 1186, and the first special symbol display 1185 and the second special symbol display when the big hit gaming state is generated. The jackpot symbol used in determining the jackpot symbol derived and displayed by the device 1186, and the jackpot symbol used for determining the initial value of the jackpot symbol The initial value determination random number or the like are prepared for pattern. Note that the random number for the big hit symbol described above is used for determining the small hit symbol that is derived and displayed by the first special symbol indicator 1185 and the second special symbol indicator 1186 when the small hit gaming state is generated. It is also used as a random number. On the other hand, the big hit symbol initial value determining random number described above is also used as a small hit symbol initial value determining random number for use in determining the initial value of the small hit symbol random number. In addition to these random numbers, a random number for normal symbol determination for use in determining whether to open or close the pair of movable pieces 2106 and an initial value for the random number for determination per normal symbol are used. Random numbers for determining an initial value for determining normal symbols, and random numbers for normal symbol variation display patterns for use in determining the variation display pattern of the normal symbols variably displayed on the normal symbol display 1189 are prepared.

  For example, the counter that updates the jackpot determination random number is configured by hardware built in the chip, and has a predetermined fixed numerical value range from the minimum value to the maximum value (in this embodiment, the value 0 as the minimum value). Is updated within the value 32767) as the maximum value, and the range from this minimum value to the maximum value is incremented by incrementing by 1 every time a main control timer interrupt process described later is performed. This counter counts up from the big hit determination initial value determination random number toward the maximum value, and then counts up from the minimum value (value 0) toward the big hit determination initial value determination random number. When the counter finishes counting up the range from the minimum value to the maximum value of the jackpot determination random number, the random number for determining the initial value for jackpot determination is updated. Such a counter updating method is referred to as an “initial value updating type counter”. The random number for determining the initial value for determining the big hit is obtained by executing an initial value lottery process for drawing one value from the fixed numerical range of the counter for updating the random number for determining the big hit. On the other hand, the random numbers for normal symbol determination and the initial value determination random numbers for normal symbol determination described above are also updated by the same method as the method for updating the jackpot determination random number described above.

  In the present embodiment, as described above, when the counter for updating the big hit determination random number is counted up, the initial value for determining the big hit determination is determined in the range from the minimum value to the maximum value of the big hit determination random number. The random number is updated by executing the initial value lottery process. However, when the operation switch 952 of the payout control board 4110 is operated when the power is turned on, or in the main control side power-on process described later. The check sum value (sum value) obtained by calculating the sum of the game information stored in the main control built-in RAM of the main control MPU 4100a as a numerical value is the main control side power-off process (at power-off). When clearing the entire area of the main control built-in RAM, such as when it does not match the stored checksum value (sum value), the big hit determination initial value determination disturbance Is an initial value at which the main control MPU 4100a always derives the same fixed value from the fixed value range of the counter that extracts the ID code from the built-in nonvolatile RAM and updates the jackpot determination random number based on the extracted ID code. A derivation process is executed, and this derived fixed value is set. In other words, the initial value determination random number for jackpot determination is always overwritten and updated with the same fixed value derived based on the ID code by executing the initial value derivation process. As described above, the value set as the initial value for determining the initial value for jackpot determination is derived using the ID code, and the ID that is stored in the nonvolatile RAM built in the main control MPU 4100a by the manufacturer of the main control MPU 4100a. Based on the ID code by executing the initial value derivation process when clearing the entire area of the main control built-in RAM and the first security measure that the ID code is not rewritten even if an external device is used when the code is stored Thus, the second security measure of deriving the same fixed value and the two steps of security measures are taken to prevent analysis.

  Here, an advantage will be described in which an ID code is extracted from a nonvolatile RAM incorporated in the main control MPU 4100a and the extracted ID code is used as a random number for determining an initial value for determining a big hit. For example, a person who illegally acquires a game ball to be paid out as a prize ball obtains the game board 4 by some method and disassembles it, and uses an ID code stored in advance in a nonvolatile RAM built in the main control MPU 4100a. Even if it is possible to grasp the timing when the value of the counter for updating the jackpot determination random number and the jackpot determination value coincide with each other, the ID code is assigned a unique code for identifying the individual. Therefore, the ID code is completely different from the ID code stored in advance in the non-volatile RAM built in the main control MPU provided in another game board. That is, in other game boards, the timing at which the counter value for updating the jackpot determination random number matches the jackpot determination value is also completely different from that of the acquired game board 4. In other words, the ID code obtained by disassembling and analyzing the obtained game board 4 is completely useless in other game boards, that is, other pachinko gaming machines. Even if a momentary power failure is generated at every interval and a game winning ball is entered at the first start port 2101 or the second start port 2102 at every predetermined interval, a big hit gaming state cannot be generated. .

[4-2. Operation of counter with initial value update type]
In the initial value update type counter, when the entire area of the main control built-in RAM is cleared (when the RAM is cleared), the main control MPU 4100a extracts the ID code from the built-in non-volatile RAM, and based on the extracted ID code. An initial value deriving process for always deriving the same fixed value from the fixed numerical range of the counter for updating the big hit determination random number is executed, and this derived fixed value is set. The initial value update type counter counts up from this fixed value toward the maximum value and then counts up from the minimum value toward the fixed value as the first cycle. When the counter finishes counting up the range from the minimum value to the maximum value of the big hit determination random number, one value is randomly selected from the fixed numerical range of the counter that updates the big hit determination random number as the initial value determination random number for the big hit determination The initial value lottery process is executed, and the value obtained by this lottery is set. In the second cycle, the initial value update type counter counts up from the value obtained by the lottery toward the maximum value, and then counts up from the minimum value to the value obtained by the lottery. When the counter finishes counting up the range from the minimum value to the maximum value of the big hit determination random number, the initial value lottery process is executed again, the value obtained by this lottery is set, and the initial value update type counter As the third cycle, the value obtained by the lottery is counted up toward the maximum value. In the present embodiment, the value 32668 to the value 32767 are set for the low probability as the range of the big hit determination value (the jackpot determination range), which is read from the normal determination table, whereas the value 31768 to the value for the high probability. 32767 is set and is read from the probability variation determination table. In the present embodiment, the counter for updating the big hit determination random number updates a predetermined fixed numerical range ranging from a value 0 as a minimum value to a value 32767 as a maximum value. In other words, the range of the jackpot determination value (the jackpot determination range) is a range closer to the maximum value from the intermediate value (value 16384) between the minimum value and the maximum value in either of the low probability and the high probability. Is set.

  Here, in the present embodiment, as a big hit determination value range (big hit determination range), a value 10 to a value 209 are set for a low probability, and a value 10 to a value 339 are set for a high probability. That is, with a low probability, the number of random numbers (big hit determination random numbers) that are jackpots is 200, and with a high probability, the number of random numbers (big hit determination random numbers) that are jackpots is 330. Here, in this embodiment, in order to prevent a plurality of random numbers to be counted and updated from being synchronized with each other, the number of other random number values acquired at the same time is the 200, except when the acquisition times of random number values are different. Other than that, for example, a prime number. In other words, in the present embodiment, if the acquisition time of the random number value is different from the big hit determination random number (for example, the value of the random number for determining the big hit game mode acquired when the game ball passes through the gate 2575 described later) The number of random numbers that are jackpots can be made non-prime. In the present embodiment, the small hits described above are, for example, big hit determination random numbers corresponding to the number (50) of the number of big hit symbols (200) with low probability divided by four.

  Considering the case where such a big hit judgment value range is set, the minimum and maximum values are the same regardless of whether the jackpot judgment value range (big hit judgment range) is low probability or high probability. Is set to a range closer to the minimum value side from the intermediate value (value 16384). In such a case, the period from the timing when the value of the initial value update type counter becomes 0 to the time when it becomes the first value 10 in the range of the big hit determination value (big hit determination range), and this value 10 When the period from the next value 11 to the maximum value (value 32767) is compared, the probability of the former period being drawn by the above-described initial value lottery process is much lower than that of the latter period. In other words, the range from the timing when the value of the initial value update type counter becomes 0 to the last value (value 209 for low probability, value 339 for high probability) in the range of jackpot determination value (big hit determination range). And the range from the value after this last value (value 210 for low probability, value 340 for high probability) to the maximum value (value 32767), the former range is the latter Compared with the range, the probability of being drawn by the initial value lottery process is extremely low. Then, for example, the game ball is obtained by illegally acquiring the timing at which the value of the initial value update type counter becomes 0 by some method and irradiating the first start port 2101 and the second start port 2102 with radio waves. When a fraudulent act pretending to have entered the first start port 2101 or the second start port 2102 is performed, the value of the initial value update type counter is one of the jackpot determination value ranges (jackpot determination range). It can be said that there is a high probability that

  On the other hand, as in the present embodiment, the range of the jackpot determination value (the jackpot determination range) is from an intermediate value (value 16384) between the minimum value and the maximum value in either the low probability or the high probability. If it is set to the range close to the maximum value side, the initial value update type counter value immediately before the value that becomes the first value in the range of the big hit judgment value (big hit judgment range) from the timing when the value becomes zero. A period extending to the time when the value (value 32667 for low probability, value 31767 for high probability) and a period extending from the first value (value 32668 for low probability, value 31768 for high probability) to the maximum value (value 32767) And the former period has a higher probability of being drawn by the above-described initial value lottery process than the latter period. In other words, the value before the first value in the range of the big hit determination value (big hit determination range) from the timing when the value of the initial value update type counter becomes 0 (value 32667 for low probability, value 31767 for high probability). And the range from the first value (value 32668 for low probability, value 31768 for high probability) to the maximum value (value 32767), the former range is compared to the latter range The probability of being drawn by the initial value lottery process is extremely high. Then, the initial value update type counter has a range from the value 0 to the value before the first value (value 32667 for low probability, value 31767 for high probability) in the range of jackpot determination value (big hit determination range). Of these values, one of the values becomes a value drawn by the initial value lottery process, and is set in the above-described big hit determination initial value determination random number. Counting up, and then counting up from the minimum value to the value obtained by lottery. When the counter finishes counting up the range from the minimum value to the maximum value of the big hit determination random number, the initial value lottery process is executed again, the value obtained by this lottery is set, and the initial value update type counter Then, the value obtained by the lottery is counted up toward the maximum value.

  That is, as in the present embodiment, the range of the big hit determination value (big hit determination range) is either the low probability or the high probability, and the maximum value side from the intermediate value (value 16384) between the minimum value and the maximum value. Is set to a range close to the initial value update type counter value from the timing when the value becomes 0, the first value in the range of the big hit determination value (big hit determination range) (low value) The period extending to the time when the probability becomes 32667 and the value 31767) with high probability is irregular and rich in randomness. Thereby, for example, the game ball is obtained by illegally acquiring the timing when the value of the initial value update type counter becomes 0 by some method and irradiating the first start port 2101 or the second start port 2102 with radio waves. Even if an illegal act pretending to have entered the first start port 2101 or the second start port 2102 is performed, the value of the initial value update type counter is within the range of the big hit determination value (big hit determination range) It can be said that the probability of any value is low.

  The initial value update type counter is repeatedly updated in the range from the minimum value to the maximum value. Until the counter reaches the minimum value (first value) in the range of the big hit judgment value (big hit judgment range) in the second cycle from the minimum value (first value) of the range from the initial value to the big hit judgment value (big hit judgment range) The time required is time T0. The time required for the counter to reach the minimum value (first value) of the big hit determination value range (big hit determination range) in the third cycle from time T0 is time T1, and time T1 is shorter than time T0. . The time required for the counter to reach the minimum value (first value) of the big hit determination value range (big hit determination range) in the fourth cycle from time T1 is time T2, and time T2 is shorter than time T1. . As described above, in the initial value update type counter, fluctuation is given to the time when the updated counter becomes the minimum value (first value) of the range of the big hit determination value (big hit determination range) (periodicity). The player is not perceived by the player).

[4-3. Main control side power-on processing]
When the pachinko gaming machine 1 is turned on, the main control program described above performs the main control side power-on process as shown in FIGS. 12 and 13 under the control of the main control MPU 4100a of the main control board 4100. Do. When the main control side power-on process is started, the main control program sets the stack pointer under the control of the main control MPU 4100a (step S10). The stack pointer indicates, for example, the address accumulated on the stack to temporarily store the contents of the memory element (register) being used, or temporarily returns the return address of this routine when returning to this routine after completing the subroutine. It indicates the address that is stacked on the stack for storage, and the stack pointer advances each time the stack is stacked. In step S10, the main control program sets an initial address in the stack pointer, and from this initial address, the contents of the register, the return address, etc. are stacked on the stack. Then, the stack pointer returns to the initial address by sequentially reading from the last stacked stack to the first stacked stack.

  Subsequent to step S10, the main control program starts outputting a power failure clear signal to the power failure monitoring circuit 4100e (step S11). The power failure monitoring circuit 4100e includes a comparator MIC that is a voltage comparison circuit and a D-type flip-flop MIC. The comparator MIC, which is a voltage comparison circuit, compares the voltage between + 24V and the reference voltage, or compares the voltage between + 12V and the reference voltage, and outputs the comparison result. This comparison result shows that when no power failure or instantaneous power failure occurs, the logic becomes HI and is input to the PR terminal which is the preset terminal of the D-type flip-flop MIC, while when a power failure or instantaneous power failure occurs. The logic becomes LOW and is inputted to the PR terminal which is a preset terminal of the D type flip-flop MIC. In step S11, output of the power failure clear signal is started to the CLR terminal which is the clear terminal of the D type flip-flop MIC. This power failure clear signal is input from the output terminal of the predetermined output port of the main control MPU 4100a to the CLR terminal which is the clear terminal of the D-type flip-flop IC via the main control output circuit 4100ca with a reset function by setting the logic to LOW. Is done. As a result, the main control MPU 4100a can release the latch state of the D-type flip-flop MIC, and the logic input to the PR terminal which is the preset terminal of the D-type flip-flop MIC until the latch state is set. It can be inverted and output from the 1Q terminal, which is the output terminal, and the signal from the 1Q terminal can be monitored.

  Subsequent to step S12, the main control program performs wait timer process 1 (step S12), and determines whether or not a power failure notice signal is input (step S14). The voltage does not increase immediately from when the power is turned on until the voltage reaches the predetermined voltage. On the other hand, when there is a power failure or a momentary power failure (a phenomenon in which the supply of power is temporarily stopped), when the voltage drops and becomes lower than the power failure warning voltage, a power failure warning signal is input as a power failure warning from the power failure monitoring circuit 4100e. Similarly, if the voltage becomes lower than the power failure warning voltage from when the power is turned on until it reaches the predetermined voltage, a power failure warning signal is input from the power failure monitoring circuit 4100e. Therefore, the wait timer process 1 in step S12 is a process for waiting after the power is turned on until the voltage becomes larger than the power failure warning voltage and stabilizes. ms) is set. In step S14, it is determined whether or not the power failure notice signal is input. This determination is performed based on the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC, as the power failure warning signal.

  If no power failure warning signal is input after the power is turned on in step S14 until the voltage becomes higher than the power failure warning voltage and stabilizes, the main control program applies power failure to the CLR terminal which is the clear terminal of the D-type flip-flop MIC. The output of the clear signal is stopped (step S15). Here, the power failure clear signal is output from the output terminal of a predetermined output port of the main control MPU 4100a, the logic is HI, and the CLR terminal which is the clear terminal of the D-type flip-flop IC via the main control output circuit 4100ca with reset function. Is input. Thereby, the main control MPU 4100a can set the D-type flip-flop MIC to the latched state. When the D-type flip-flop MIC latches a state where the logic is LOW and is input to the PR terminal which is the preset terminal, the D-type flip-flop MIC outputs a power failure warning signal from the 1Q terminal which is the output terminal.

  Subsequent to step S15, the main control program makes a state in which RAM clear processing for initializing the main control built-in RAM (game storage unit) can be executed for a predetermined time from when the power is turned on (when the game side power is turned on) Operation control means). Specifically, the main control program first determines whether or not the operation switch 952 of the payout control board 4110 shown in FIG. 16 is operated (step S16). In this determination, the main control program inputs an error release navigation command (first error release command) based on an operation signal (detection signal) associated with the operation switch 952 of the payout control board 4110 being operated to the main control MPU 4100a. Depending on whether or not it is done. Based on the logic value of the operation signal, the main control program determines that the RAM is not instructed to be cleared when the logic value of the operation signal from the operation switch 952 is HI, and the operation switch 952 operates On the other hand, when the logical value of the operation signal from the operation switch 952 is LOW, it is determined that the instruction to perform the RAM clear is made and it is determined that the operation switch 952 is operated.

  In step S16, when the operation switch 952 is operated, the main control program sets a value 1 to the RAM clear notification flag RCL-FLG (step S18). On the other hand, when the operation switch 952 is not operated in step S16, the main control program sets a value 0 to the RAM clear notification flag RCL-FLG (step S20). That is, the main control program can execute a RAM clear process for initializing a RAM (hereinafter referred to as “main control built-in RAM”) built in the main control MPU 4100a for a predetermined time from when the power is turned on. (Game control side power-on operation control means). The above-mentioned RAM clear notification flag RCL-FLG indicates whether or not to erase game information related to games such as probability variation, unpaid prize balls, etc. stored in the main control built-in RAM (game storage unit) of the main control MPU 4100a. This flag is set to a value of 1 when erasing game information and a value of 0 when not erasing game information. Note that the value of the RAM clear notification flag RCL-FLG set in step S18 and step S20 is stored in the general-purpose storage element (general-purpose register) of the main control MPU 4100a.

  Subsequent to step S18 or step S20, the main control program performs wait timer processing 2 (step S22). In this wait timer process 2, the system for controlling drawing of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 246 by the liquid crystal and sound control unit 4160 of the peripheral control board 4140 shown in FIG. Waiting to boot). In this embodiment, 2 seconds (s) is set as a time until booting (boot timer).

  Subsequent to step S22, the main control program determines whether or not the RAM clear notification flag RCL-FLG is 0 (step S24). As described above, the RAM clear notification flag RCL-FLG is set to a value of 1 when erasing game information and a value of 0 when not erasing game information. When the RAM clear notification flag RCL-FLG is 0 in step S24, that is, when the game information is not erased, a checksum is calculated (step S26). This checksum is calculated by regarding the game information stored in the main control built-in RAM as a numerical value and calculating the sum.

  Subsequent to step S26, the main control program uses the calculated checksum value (sum value) as the checksum value (sum value) stored in the main control side power-off processing (power-off) described later. It is determined whether or not they match (step S28). If they match, the main control program determines whether or not the backup flag BK-FLG is 1 (step S30). This backup flag BK-FLG stores game backup information such as game information, checksum value (sum value) and backup flag BK-FLG in the main control built-in RAM in the main control side power-off process described later. This flag is set to a value of 1 when the main control-side power-off process is normally terminated, and a value of 0 when the main-control-side power-off process is not terminated normally.

  When the backup flag BK-FLG has a value of 1 in step S30, that is, when the main control side power-off process is normally terminated, the main control program sets the work area of the main control built-in RAM as the power is restored ( Step S32). In this setting, the backup flag BK-FLG is set to a value 0, and the power recovery time information is read from a ROM built in the main control MPU 4100a (hereinafter referred to as “main control built-in ROM”). Time information is set in the work area of the main control built-in RAM. In addition, “recovery” means not only the state where the power is turned off but also the state where the power is turned on, the state where the power is restored after a power outage or a momentary power failure, and the detection that a high frequency has been applied. It also includes the state of returning after that.

  Subsequent to step S32, the main control program performs a power-on command creation process (step S34). In the power-on command creation process, game information is read from the game backup information, and various commands corresponding to the game information are stored in a predetermined storage area of the main control built-in RAM.

  On the other hand, when the RAM clear notification flag RCL-FLG is not 0 (value 1) in step S24, that is, when the game information is deleted, or when the checksum value (sum value) does not match in step S28. Alternatively, when the backup flag BK-FLG is not a value 1 (value 0) in step S30, that is, when the main control side power-off process has not been terminated normally, the main control program stores all the main control built-in RAM. The area is cleared (step S36). That is, the main control program executes the game control side RAM clearing process triggered by the input of the detection signal accompanying the operation of the operation switch 952 described above (payout control side power-on operation control means). Specifically, the main control program is executed by writing the value 0 into the main control built-in RAM. Alternatively, the main control program may read and set a predetermined value from the main control built-in ROM as an initial value. In addition, the main control MPU 4100a performs processing when the logical value of the operation signal from the operation switch 952 indicates RAM clear and when the game information is erased, the sum values do not match, or when the main control side power is cut off. When the process is not completed normally, a unique ID code stored in advance in the nonvolatile RAM of the main control MPU 4100a is taken out, and the big hit determination random number is updated based on the taken out ID code. An initial value deriving process for deriving the same fixed value is performed, and this fixed value is set to the big hit determination initial value determining random number used for determining the initial value of the big hit determining random number.

  Subsequent to step S36, the main control program sets the work area of the main control built-in RAM as an initial setting (step S38). This setting is performed by reading the initial information from the main control built-in ROM and setting the initial information in the work area of the main control built-in RAM.

  Subsequent to step S38, the main control program performs RAM clear notification and test command creation processing (step S40). In the RAM clear notification and test command creation processing, a power-on command classified into power-on shown in FIG. 35 for notifying that the main control built-in RAM is cleared and initial setting is performed is created. Test commands classified into test relations shown in FIG. 36 for performing various inspections of the control board 4140 are created and stored as transmission information in the transmission information storage area of the main control built-in RAM.

  Subsequent to step S34 or step S40, the main control program performs interrupt initialization (step S42). This setting is to set an interrupt cycle when a main control timer interrupt process described later is performed. In this embodiment, it is set to 4 ms.

  Subsequent to step S42, the main control program performs interrupt permission setting (step S44). With this setting, the main control side timer interrupt process is repeated every interrupt cycle set in step S42, that is, every 4 ms.

  Subsequent to step S44, when a predetermined time elapses from when the power is turned on, that is, when the main process on the main control side is started, an error cancel navigation command associated with the operation of the operation switch 952 (operation switch) is displayed. Execution of the game control side RAM clear process triggered by the reception will be restricted (normal operation control means). As described above, the main control program uses the error sharing navigation command for a predetermined time from the time of power-on as described above, based on the concept of time sharing, based on the concept of time sharing. When the input is triggered, the RAM clear process is executed (game control side power-on operation control means), and after the predetermined time has elapsed, the execution of the RAM clear process is restricted even if the error canceling navigation command is input ( The game control side normal operation control means) is handled as a release switch for releasing the error notification associated with the error that has occurred. In other words, the operation switch 952 (error release unit) that should have been originally used to release an error that has occurred with respect to the payout operation is used as a game storage unit instead of a predetermined time from the power-on. The main control built-in RAM (and a payout control built-in RAM as a payout storage unit to be described later) functions as an operation unit for executing a RAM clear process for starting initialization, and after the predetermined time has elapsed, It can function as an operation unit for canceling an error that has occurred with respect to the ball dispensing operation.

  Next, the main control program sets a value A in the watchdog timer clear register WCL (step S46). The watchdog timer is cleared by setting value A, value B and value C in this order in this watchdog timer clear register WCL.

  Subsequent to step S46, the main control program determines whether or not a power failure notice signal is input (step S48). As described above, when the power of the pachinko gaming machine 1 is shut off, or when a power failure or a momentary power failure occurs, a power failure notice signal is input from the power failure monitoring circuit 4100e as a power failure notice if the voltage falls below the power failure notice voltage. The determination in step S48 is made based on this power failure notice signal.

  When no power failure warning signal is input in step S48, the main control program performs a non-winning random number update process (step S50). In this non-winning random number update process, the reach determination random number, the variable display pattern random number, the big hit symbol initial value determining random number, the small hit symbol initial value determining random number, and the like are updated. In this way, in the non-winning random number update process, random numbers that are not involved in the winning determination (big hit determination) are updated. It should be noted that the above-described random numbers for normal symbol determination, random numbers for initial value determination for normal symbol determination, random numbers for normal symbol variation display pattern, and the like described above are also updated by this non-winning random number update process.

  Following step S50, the process returns to step S46 again, the main control program sets a value A in the watchdog timer clear register WCL, determines whether or not a power failure warning signal is input in step S48, and this power failure warning notification. If there is no signal input, non-winning random number update processing is performed in step S50, and steps S46 to S50 are repeated. Note that the processing in steps S46 to S50 is referred to as “main control side main processing”.

  On the other hand, when a power failure warning signal is input in step S48, the main control program performs interrupt prohibition setting (step S52). By this setting, the main control side timer interrupt processing described later is not performed, writing to the main control built-in RAM is prevented, and rewriting of game information is protected.

  Subsequent to step S52, the main control program starts outputting a power failure clear signal (step S53). Here, the same process as the process that started outputting the power failure clear signal in step S11 is performed. Thereby, the main control program can release the latch state of the D-type flip-flop MIC under the control of the main control MPU 4100a.

  Subsequent to step S53, the main control program displays the start port solenoid 2105, the attacker solenoids 2108A and 2108B, the first special symbol display 1185, the second special symbol display 1186, and the first special symbol storage display shown in FIG. The drive signal output to the display 1184, the second special symbol storage display 1187, the normal symbol display 1189, the normal symbol storage display 1188, the game status display 1183, the round display 1190, etc. is stopped (step S54). .

  Subsequent to step S54, the main control program calculates a checksum and stores the calculated value (step S56). This checksum is calculated by regarding the game information in the work area of the main control built-in RAM as a numerical value excluding the storage area for the checksum value (sum value) and backup flag BK-FLG described above.

  Subsequent to step S56, the main control program sets a value 1 to the backup flag BK-FLG (step S58). Thereby, storage of game backup information is completed.

  Subsequent to step S58, the main control program performs clear setting of the watchdog timer (step S60). As described above, the clear setting is performed by sequentially setting the value A, the value B, and the value C in the watchdog timer clear register WCL.

  Following step S60, an infinite loop is entered. In this infinite loop, the value A, the value B, and the value C are not sequentially set in the watchdog timer clear register WCL, so that the watchdog timer is not cleared. Therefore, the main control MPU 4100a is reset, and then the main control MPU 4100a performs the main control side power-on process again. Note that the processing of step S52 to step S60 and the infinite loop are referred to as “main control side power-off processing”.

  The pachinko gaming machine 1 (main control MPU 4100a) is reset when a power failure occurs or when an instantaneous power failure occurs, and performs power-on processing on the main control side by subsequent power recovery.

  In step S28, it is checked whether or not the game backup information stored in the main control built-in RAM is normal. Subsequently, in step S30, whether or not the main control side power-off process has been normally completed. Are inspected. In this way, by checking the game backup information stored in the main control built-in RAM twice, it is checked whether or not the game backup information is stored by an illegal act.

[4-4. Main control timer interrupt processing]
Next, the main control timer interrupt process will be described. This main control side timer interrupt process is repeated at every interrupt period (4 ms in this embodiment) set in the main control side power-on process shown in FIGS.

  When the main control side timer interrupt process is started, in the main control board 4100, under the control of the main control MPU 4100a, the main control program sets a value B in the watchdog timer clear register WCL as shown in FIG. (Step S70). At this time, the value B is set in the watchdog timer clear register WCL following the value A set in step S46 of the main control side power-on process (main control side main process).

  Subsequent to step S70, the main control program clears the interrupt flag (step S72). When the interrupt flag is cleared, the interrupt cycle is initialized, and the next interrupt cycle is counted from the initial value.

  Subsequent to step S72, the main control program performs switch input processing (step S74). In this switch input process, various signals input to input terminals of various input ports of the main control MPU 4100a are read and stored as input information in an input information storage area of the main control built-in RAM. Specifically, for example, the main control program enters each of the detection signals from the general winning opening switches 3020 and 3020 for detecting a game ball that has entered the general winning opening 2104 and 2201 and the large winning opening 2103. A detection signal from the count switch 2110 for detecting the game ball, a detection signal from the first start port switch 3022 for detecting the game ball that has entered the first start port 2101, and a game ball that has entered the second start port 2102 A detection signal from the second start port switch 2109 to detect, a detection signal from the gate switch 2352 that detects a game ball that has passed through the gate portion 2350, a detection signal from the magnetic detection switch 3024 that detects fraud using a magnet, A payout control board 41 for notifying that the payout control board 4110 has normally received a prize ball command transmitted in a prize ball control process to be described later. Reading 払主 ACK signal from 0, respectively, it is stored in the input information storage area as the input information. Further, a detection signal from the first start port switch 3022 that detects a game ball that has entered the first start port 2101, and a detection from the second start port switch 2109 that detects a game ball that has entered the second start port 2102 When each signal is read, the corresponding start port winning command shown in FIG. 10 and corresponding thereto is stored as transmission information in the transmission information storage area described above. That is, when there is a detection signal from the first start port switch 3022, a corresponding start port winning command is stored as transmission information in the transmission information storage area, and there is a detection signal from the second start port switch 2109. The start opening winning command corresponding to this is stored as transmission information in the transmission information storage area.

  In the present embodiment, the detection signal from the general winning opening switches 3020 and 3020 for detecting the game balls that have entered the general winning opening 2104 and 2201, and the count switch 2110 for detecting the gaming balls that have entered the large winning opening 2103 are shown. , A detection signal from the first start port 3022 that detects the game ball that has entered the first start port 2101, a second start port switch 2109 that detects the game ball that has entered the second start port 2102 , And the detection signal from the gate switch 2352 that detects the game ball that has passed through the gate portion 2350 are first read as a first time when this switch input process is started, for a predetermined time (for example, 10 μs). ) After the passage, each is read again as the second time. Then, the result read at the second time is compared with the result read at the first time. It is determined whether there is a comparison result among the comparison results. Those that are not the same result are read again as the third time, and the result read at the third time is compared with the result read at the second time. It is determined again whether there is a comparison result among the comparison results. Those that are not the same result are read again as the fourth time, and the result read at the fourth time is compared with the result read at the third time. It is determined again whether there is a comparison result among the comparison results. Those with the same result are treated as having no game balls.

  Thus, in the switch input process, the main control program receives the detection signals from the general winning award port switches 3020 and 3020, the count switch 2110, the first start port switch 3022, the second start port switch 2109, and the gate switch 2352. Due to the influence of chattering, noise, etc., by reading twice, a total of two times of reading, which is compared twice for the first to third times, and twice for comparing the second time to the fourth time. Since false detection can be avoided, detection signals from the general prize opening switches 3020 and 3020, the count switch 2110, the first starting port switch 3022, the second starting port switch 2109, and the gate switch 2352 are displayed. Reliability can be increased.

  Subsequent to step S74, the main control program performs timer subtraction processing (step S76). In this timer subtraction process, for example, the time during which the first special symbol display 1185 and the second special symbol display 1186 are turned on in accordance with the variable display pattern determined in the special symbol and special electric accessory control processing described later, In addition to the time that the normal symbol display 1189 is turned on in accordance with the normal symbol variation display pattern determined by the symbol and normal electric accessory control process, various commands transmitted by the main control board 4100 (main control MPU 4100a) are issued. When determining whether or not a payer ACK signal indicating that the signal is normally received is input, time management such as an ACK signal input determination time set as a determination condition is performed. Specifically, when the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is 5 seconds, the timer interruption period is set to 4 ms. Therefore, every time this timer subtraction process is performed, the fluctuation time is subtracted by 4 ms. When the subtraction result is 0, the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is accurately measured.

  In this embodiment, the ACK signal input determination time is set to 100 ms. Each time this timer subtraction process is performed, the ACK signal input determination time is subtracted by 4 ms, and the subtraction result becomes 0, thereby accurately measuring the ACK signal input determination time. The various times and the ACK signal input determination time are stored as time management information in the time management information storage area of the main control built-in RAM.

  Subsequent to step S76, the main control program performs a winning random number update process (step S78). In the winning random number update process, the big hit determination random number, the big hit symbol random number, and the small hit symbol random number described above are updated. Further, in addition to these random numbers, a big hit symbol initial value determining random number that is updated by the non-winning random number update process of step S50 in the main control side power-on process (main control side main process) shown in FIG. And the random number for determining the initial value for the small hit symbol is also updated. The random value for determining the initial value for the big hit symbol and the random number for determining the initial value for the small hit symbol are updated in the main control side main process and the main control side timer interrupt process, respectively, thereby improving the randomness. . On the other hand, since the big hit determination random number, the big hit symbol random number, and the small hit symbol random number are random numbers related to the winning determination (big hit determination), each time the winning random number update process is performed, each counter Counts up.

  For example, the counter for updating the jackpot determination random number is an initial value updating type counter as described above, and is a predetermined fixed numerical value range from the minimum value to the maximum value (in this embodiment, the value as the minimum value). 0 to the maximum value is updated within the value 32767), and the range from the minimum value to the maximum value is incremented by incrementing by 1 each time the main control timer interrupt processing is performed. The big hit determination initial value determination random number is counted up toward the maximum value (value 32767), and then the big hit determination initial value determination random number is counted up. When the counter for updating the big hit determination random number finishes counting up within the range from the minimum value to the maximum value of the big hit determination random number, the big hit determination initial value determination random number is updated by the winning random number update process. The big hit determination initial value determination random number can be obtained by executing an initial value lottery process for drawing one value from a fixed numerical range of a counter for updating the big hit determination random number. Note that the above-described random numbers for normal symbol determination and random numbers for determining the initial value for normal symbol determination are also updated by this winning random number update process. The random number for determining normal symbols is the same as the method for updating the random number for determining big hits, and the description thereof is omitted.

  In this embodiment, the big hit determination initial value determining random number, the big hit symbol initial value determining random number, and the small hit symbol initial value determining random number are processed on the main control side power-on processing (main control) shown in FIG. Update processing in step S50 in the main main processing) and the winning random number update processing in step S78 in the main control timer interrupt processing, which is the main routine, are updated each time the interrupt timer is generated. When the number of executions of the non-winning random number update process in step S50 is random by repeatedly executing the main process on the main control side within the remaining time until the next interrupt timer is generated after the process time becomes uneven. , The big hit determination initial value determining random number, the big hit symbol initial value determining random number, and the small hit symbol initial value determining random number in step S50 Or as a mechanism to update only in non Toraku random number update process.

  Subsequent to step S78, the main control program performs prize ball control processing (step S80). In this prize ball control process, the main control program reads out the input information from the input information storage area described above and creates a prize ball command for paying out a game ball based on this input information. A self-check command for confirming the connection state between the board and the payout control board 4110 is created. This main control program transmits the created prize ball command and self-check command to the payout control board 4110 as main payout serial data.

  Further, in the prize ball control process, the main control program executes a prize ball control program code that is a part of the program code, and is output from the count switch 2110 when the game ball is received in the big prize opening 2103, for example. Triggered by the fact that the detection information based on the detected signal has been written in the corresponding defined bit areas defined successively one bit at a time for the number of winning prize openings 2103, for example, 15 balls as prize balls A prize ball command is generated as a prize ball instruction to pay out and is sent to the payout control board 4110 (payout control means).

  In the present embodiment, since there are two large winning openings 2103 as the large winning openings, the main control program has a plurality of definition bit areas prepared in advance in the main control RAM as the above-described definition bit areas. From the inside, two definition bits for the big winning opening 2103 are used. Hereinafter, these will be referred to as “first bit area” and “second bit area” in this order. For example, in the case of a game board having one winning prize slot, one definition bit area is used. These definition bit areas to be used are, for example, one bit and are adjacent to each other. When the game ball is received in the big winning opening 2103, for example, “1” is written in the first definition bit area which is the fourth bit, for example, as detection information based on the detection signal output from the count switch 2110. Thereafter, the main control program initializes the definition bit area corresponding to the big winning opening that has identified that the game ball has been received by writing, for example, “0”, and prepares for the next game ball to be received.

  Here, the main control program also determines which definition bit area is to be checked. For example, if the main control program sets the definition bit area corresponding to the count switch 2110 of the big prize opening 2103 to the fourth bit, the main control program of the pachinko gaming machine in which only one big prize opening is provided as in this embodiment. In this case, the main control program acquires information on the fourth bit definition bit area.

  Further, the main control program performs a mask process on the detection information acquired in this way in accordance with a prize ball effective range of a special prize opening 2103 described later, creates a prize ball command, and writes it in the transmission information storage area. It is determined whether or not to output to the payout control board 4110. When it is determined that this prize ball command should not be transmitted, the main control program, for example, as a mask process for each defined bit area in which detection information based on the detection signal from the count switch 2110 is written is forcibly executed. The bit may be set to OFF (“0”), and the prize ball command may not be written in the transmission information storage area.

  In this prize ball control process, the main control program detects the detection information corresponding to the detection signal from the count switch 2110 indicating that one game ball has been received in the big prize opening 2103 in the first special game state. In response to being written in the definition bit area corresponding to the big winning opening 2103, for example, a prize ball command is created as a prize ball instruction indicating that 15 balls should be paid out, and the transmission information storage area described above Write to. At the same time, the main control program writes a winning sound command as a command to output a predetermined sound in the transmission information storage area described above, and then transmits it to the peripheral control board 4140 to be transmitted to the peripheral control MPU 4150a to the speaker, for example, “ The sound “Pokon” is output.

  On the other hand, in the first special gaming state, the main control program detects detection information based on a detection signal from the count switch 2110 indicating that one game ball has been received in the special winning opening 2103 in the special winning opening 2103. If not written in the corresponding definition bit area, for example, a prize ball command is not created as a prize ball instruction indicating that 15 balls should be paid out. Also in this case, the main control program writes a winning sound command as a command to output a predetermined sound in the transmission information storage area described above, but the winning ball command is transmitted to the payout control board 4110 (payout control means). Prevent the game ball payout operation from being executed. Thereafter, the main control program initializes the definition bit area corresponding to the special winning opening 2103 and clears the detection information based on the detection signal from the count switch 2110 to allow the game ball to be paid out. To do.

  At this time, the main control program, when paying out more than the specified number of payouts that can be paid out in accordance with the acceptance of the game balls to the big prize opening 2103, will give an excessive payout abnormality command (not shown in FIG. 36). ) In the transmission information storage area, and then transmitted to the peripheral control board 4140 in the command transmission process (step SS92). Then, the peripheral control MPU 4150a causes the speaker to perform predetermined notification.

  In this way, since a substantially illegal game ball is not paid out, damage to the game hall (game hall) can be minimized.

  On the other hand, instead of the main control program, when it is detected that a game ball has been received at the special winning opening 2103, the main control program immediately writes an excessive winning abnormality command in the transmission information storage area to control the peripheral control MPU 4150a. The speaker may be informed.

  Thereafter, the main control program reads the prize ball command from the transmission information storage area described above and transmits it to the payout control board 4110 (payout control means).

  As described above, when a game ball is received for the special winning opening 2103, it can be confirmed by hearing whether or not the corresponding count switch 2110 is functioning.

  On the other hand, if the payer ACK signal notifying the payout control board 4110 that the payout control board 4110 has successfully received the prize ball command is not input within a predetermined time, the main control program determines whether the main control board 4100 and the payout control board 4110 A self-check command for confirming the connection state between the boards is created and transmitted to the payout control board 4110.

  Subsequent to step S80, the main control program performs a frame command reception process (step S82). In the payout control board 4110, the payout control program executes various commands of 1 byte (8 bits) classified into the status display shown in FIG. Send. On the other hand, as described later, the payout control program outputs an error occurrence command when an error occurs in the payout operation, or outputs an error canceling navigation command based on a detection signal of the operation switch 952. In the frame command reception process described above, when the main control program normally receives the various commands as payer serial data, information that informs the payout control board 4110 to that effect is stored as output information in the main control built-in RAM. Store in the area. Also, the main control program reformats the command received normally as payer serial data into a 2-byte (16-bit) command (various commands classified as status display in FIG. 36 (frame status 1 command, error cancellation). The navigation command and the frame state 2 command))) are stored in the transmission information storage area described above as transmission information. The frame state 1 command here corresponds to the first error occurrence command, and the error cancellation navigation command corresponds to the first error cancellation command.

  Subsequent to step S82, the main control program performs a fraud detection process (step S84). In this fraud detection process, the abnormal state related to the prize ball is confirmed. For example, when the input information is read from the input information storage area described above and the game is not in the big hit gaming state, when the game switch is detected by the count switch 2110 to enter the big winning opening 2103, the main control program Then, a winning abnormality display command classified into the notification display shown in FIG. 36 as an abnormal state is created, and stored as transmission information in the transmission information storage area described above.

  Subsequent to step S84, the main control program performs a special symbol and special electric accessory control process (step S86). In this special symbol and special electric accessory control process, the main control program updates the above-described jackpot determination random number by +1 by the counter, and accepts the game ball to the first start port 2101 or the second start port 2102. That is, triggered by a winning award (establishment of the start condition), the value of the above-mentioned counter is taken out for each start storage information for which the start condition is satisfied, and used as a big hit random number value. It is determined whether or not it matches the jackpot determination value stored in advance in the ROM (lottery means). Hereinafter, this determination process is also expressed as “special lottery”. The main control program determines whether or not to generate a jackpot gaming state based on the lottery result, and the jackpot random number value matches the jackpot determination value (predetermined winning conditions are met) ), The normal gaming state is shifted to the big hit gaming state. The jackpot game state corresponds to a special game state, a first special game state, and a second special game state, which will be described later, and indicates a game state in which these are collectively called.

  The main control program determines, for example, the number of rounds, the opening time, the opening time, and the game as data for defining the jackpot gaming mode set in the jackpot gaming mode determination process described later when determining the jackpot gaming mode. Definition data area (not shown) which is a partial storage area of the main control built-in RAM specified by an address offset from the definition data (table) representing the ball winning limit count count according to the number of the big winning mouths. Read).

  By the way, a subroutine, which is a program module constituted by a set of program codes, is generally called after a CALL instruction included in a main routine and a program code group included in the program module is executed. The return instruction is used to return to the main routine (see the first reference above). In this case, since an instruction for calling back is required, at first glance, it seems difficult to reduce the program capacity.

  However, in this embodiment, when the main routine includes a continuous subroutine, for example, after the main routine calls and executes the first subroutine with the CALL instruction, the next subroutine is called with another CALL instruction continuously. Alternatively, the return instruction may not be arranged at the end of the program code group of the first subroutine, but may be connected to the beginning of the program code group of the next subroutine as it is. With the program module having such a configuration, the capacity of the entire program can be reduced.

  In the special symbol and special electric accessory control process described above, the main control program determines whether or not the random number for jackpot matches the probability variation hit determination value stored in advance in the main control built-in ROM. The main control program determines whether or not to shift to the probability variation state based on the lottery result, and the random number for jackpot matches the probability variation determination value (the probability variation transition condition is satisfied). In this case, the game is shifted to the probability variation state. On the other hand, if the jackpot random number value does not match the probability variation determination value (the condition after probability variation is not satisfied), the game state other than the probability variation is transitioned ( Winning probability control means). Here, the “probability variation state” refers to a state (high probability state) in which the winning probability of the special lottery described above is set relatively high compared to the normal gaming state (low probability state).

  Further, in this special symbol and special electric accessory control process, the main control program is shown in FIG. 35 when the lottery result mentioned above is triggered by the acceptance of the game ball to the first start port 2101. If the lottery result is triggered by the acceptance of a game ball at the second start port 2102, various commands related to the special figure 2 synchronization effect are generated. Create The main control program stores the command thus created in the transmission information storage area as transmission information.

  At the same time, the main control program determines a start hold display mode with reference to a preceding determination table (not shown) based on various random values acquired in response to the start winning, and displays the change after the start winning. Before disclosing the special symbol stop symbol, a command (hereinafter referred to as “reserved ball number change” as an example) is executed to imply a special lottery result (hereinafter referred to as “preceding judgment process”). Command ”), and when the preceding determination process is to be executed, it is stored in the transmission information storage area as transmission information. At this time, the main control program includes information regarding the stop symbol of the special symbol as information suggesting the type of the jackpot game, as will be described later, instead of the random value itself of the special lottery. I am doing so. Details of the preceding determination process will be described later.

  Next, the main control program sets the output of the lighting signal so that the first special symbol display 1185 is turned on according to the variation display pattern determined at the time of starting winning according to the type of the special symbol, or the second special symbol display The output of the lighting signal is set so that the device 1186 is lit, and the output information is stored in the output information storage area described above. When the main control program shifts to the jackpot gaming state, for example, the various commands classified into the jackpot relationship shown in FIG. 35 (the jackpot opening command, the big winning opening 1 opening Nth display command, the big winning opening 1 closing) Display command, winning prize 1 count display command, jackpot ending command, and jackpot symbol display command) are stored as transmission information in the transmission information storage area, and the opening / closing member 2107 is opened / closed by the attacker solenoid 2108A or the attacker The output of the drive signal to the solenoid 2108B is set and stored as output information in the output information storage area. In addition, the main control program sets two rounds so that the two-round display lamp (not shown) of the round indicator 1190 is turned on when the number of times (rounds) the grand prize winning opening 2103 is changed from the closed state to the open state is two. The output of the lighting signal to the display lamp is set and stored as output information in the output information storage area, or when the number of rounds is six, the six-round display lamp (not shown) of the round indicator 1190 is turned on. Set the lighting signal output to the 6-round display lamp and store it as output information in the output information storage area, or turn on the 12-round display lamp (not shown) of the round indicator 1190 when the round is 12 times To set the output of the lighting signal to the 12-round display lamp and store it in the output information storage area as output information, Und is stored in the output information storage area as output information to set the output of the lighting signal to the 16 rounds indicator lamp to turn on the 16 rounds indicator lamp round display 1190 (not shown) when a 16 times. Further, the main control program sets the output of the lighting signal to the gaming state indicator 1183 so as to light the presence / absence of the transition to the probability variation state with a predetermined color, and stores it in the output information storage area as output information.

  By the way, in a general pachinko gaming machine, when a winning winning of a game ball is triggered, a special symbol is started to be displayed in a variable manner, and a jackpot lottery is executed. When the condition is satisfied, the lighting state of a so-called probability variation lamp as a gaming state indicator is changed and the state changes to a probability variation state. In this probability variation state, the probability of the big hit lottery described above is set to be relatively higher than in the normal gaming state, and it is almost guaranteed that the winning condition is satisfied again and the big win is achieved (the first described above). See references). In this way, as a gaming machine that may transition to the probability variation state after the probability variation state has ended, the probability variation state is mainly continued until the next big hit, as if the jackpot game is looped. (Hereinafter referred to as a “loop machine”), and a probability variation state that continues until the special symbol fluctuation count reaches a predetermined number after the jackpot game ends (hereinafter referred to as an “ST (special time) machine”. ")" Exists. As described above, the pachinko machines of different types of the probability variation state continue to have different control of the game state display described above, and in the development stage, the control of the game state display is designed for each model one by one. It was difficult to improve development efficiency.

  Therefore, in the present embodiment, when the game ball is received at the first start port 2101 or the second start port 2102, the main control program determines whether or not the winning condition is satisfied, and the winning condition is satisfied. If the winning condition is satisfied and the probability variation transition condition is satisfied, the probability that the winning condition is satisfied is determined as the normal gaming state. The display mode of the game state display 1183 is set to the lighting state while the state is shifted to the probability variation state set relatively higher than the above. The main control program then sets the display state of the game state indicator 1183 to a specific interrupt cycle when the winning condition is satisfied again and the probability variation transition condition is satisfied, and the probability variation state is continued. The display state of the game state indicator 1183 is changed from the light-off state to the light-on state again within the same interrupt cycle as the specific interrupt cycle.

  Specifically, first, as described above, the main control program determines whether or not the winning condition is satisfied after the game ball is received at the first start port 2101 or the second start port 2102. (The lottery means), and if the winning condition is satisfied, the normal gaming state is shifted to the big hit gaming state, while if the winning condition is satisfied and the probability variation changing condition is The probability transition condition is shifted to a probability fluctuation state in which the probability that the winning condition is satisfied is set to be relatively higher than the normal gaming state (gaming state control means). While this probability control state continues, the main control program keeps the display state of the game state indicator 1183 in the lighting state, while the game state indicator 1183 displays the display state when a transition is made to a game state other than the probability change state. The mode is turned off (lighting mode control means). When the main control program turns on the display state of the game state indicator 1183 in response to the transition to the probability variation state described above, and then the winning condition is satisfied again and the probability change transition condition is further satisfied, After the probability variation state is continued, the display state of the game state indicator 1183 is temporarily changed from the lighting state to the extinguishing state within a specific interrupt cycle, and then the game is performed within the same interrupt cycle as the specific interrupt cycle. The display mode of the status indicator 1183 is changed from the extinguished state to the lit state again (lit state continuation control means). Although the player wants to visually recognize that the probability variation state continues, the display state of the game state indicator 1183 can be changed for a very short time as described above. It is possible to make it appear as if the display state of the game state display 1183 has not changed on the visual of the player.

  If it does in this way, it will be difficult to visually recognize that it turned off once, and it will be visually recognized as if the lighting state continues on the display mode of game state indicator 1183. Then, even if the pachinko gaming machine 1 according to the present embodiment is a so-called loop machine in which the probability variation state continues continuously, the probability variation state continues until the specified number of variations of the special symbol after the jackpot gaming state ends. In addition, even if it is a so-called ST (special time) machine that shifts to the probability fluctuation state again when the winning condition is satisfied within the specified fluctuation number, the program code that controls the display mode of the game state indicator 1183 between different models Can be shared. As a result, the development efficiency of different types of pachinko machines can be improved.

  Furthermore, in this special symbol and special electric accessory control process, the main control program (game control means) shifts from the normal gaming state to the jackpot gaming state when the winning condition is satisfied as described above, Further, when the probability variation transition condition as an example of the transition condition is satisfied, the state is also shifted to the probability variation gaming state as an example of the specific gaming state (gaming state control means). Here, the main control program may be shifted to the probability variation gaming state as an example of the specific gaming state without substantially paying out the game ball in the big hit gaming state. The specific game state may be a state in which the time-shortening operation condition is established as another example of the transition condition and the time-shortening function is in operation, It may be in a gaming state. This main control program manages the remaining number of times of display change of a special symbol during a period from a certain gaming state to another gaming state, and transmits gaming state information indicating the managed gaming state. By writing it in the transmission information storage area as information, it is then transmitted in the command transmission process S92 described later within the same timer interruption period (game state notification means).

  Specifically, when the above-described probability change transition condition is satisfied in this main control program, special symbols are variably displayed until the game state shifts to a game state other than the probability change game state, for example, the normal game state. Information related to the remaining number of times (hereinafter referred to as “remaining number of times information”) is included in one of the commands transmitted when the start condition is satisfied after the start condition is satisfied, for example, the change pattern command corresponding to the change pattern By writing it as transmission information in the transmission information storage area, it is then transmitted in the command transmission processing S92 described later within the same timer interruption period (remaining fluctuation number notification means). The main control program may include the above remaining number information in other commands, or may be transmitted to the peripheral control board 4140 as an independent command.

  Subsequent to step S86, the main control program performs normal symbol and normal electric accessory control processing (step S88). In this normal symbol and normal electric accessory control process, the main control program reads input information from the input information storage area described above and performs a gate winning process based on this input information. In this gate winning process, the main control program determines whether or not the detection signal from the gate switch 2352 is input to the input terminal from the input information. Based on this determination result, the main control program extracts the value of the counter for updating the above-described normal random number for determination per symbol when the detection signal is input to the input terminal, and stores the main control built-in RAM as gate information. Is stored in the gate information storage area.

  This gate information storage area is provided with 0th partition to 3rd partition (four partitions), and gate information is stored in the order of 0th partition, 1st partition, 2nd partition, and 3rd partition. It is like that. For example, when gate information is stored in the 0th to 2nd sections of the gate information storage, when the detection signal from the gate switch 2352 is input to the input terminal, the gate information is stored in the third section of the gate information storage. To do.

  The gate information stored in the 0th section of the gate information storage is set in the work area of the main control built-in RAM. When this gate information is set, the gate information of the first section of the gate information storage is in the 0th section of the gate information storage, the gate information of the second section of the gate information storage is in the first section of the gate information storage, The gate information of the third section of the information storage is shifted to the second section of the gate information storage, respectively, and the third section of the gate information storage becomes an empty area. For example, when gate information is stored in the first partition to the second partition of the gate information storage, the gate information of the first partition of the gate information storage is stored in the 0th partition of the gate information storage. The gate information of the two sections is shifted to the first section of the gate information storage, and the second section of the gate information storage and the third section of the gate information storage become empty areas. Here, when the gate information is stored in the first section to the third section of the gate information storage, the above-described gate information is turned on so that the normal symbol storage display 1188 is turned on using the total number of stored gate information as a holding ball. Based on the above, the output of the lighting signal of the normal symbol storage display 1188 is set and stored as output information in the output information storage area described above.

  Following such a gate winning process, the main control program reads the gate information set in the work area of the main control built-in RAM, and extracts the value of the random number for judgment per ordinary symbol from the read gate information. It is determined whether or not it matches the determination value per normal symbol stored in advance in the built-in ROM (referred to as “normal lottery”). The main control program determines whether or not to open / close the pair of movable pieces 2106 according to this determination result (lottery result by normal lottery). When the main control program performs the opening / closing operation by this determination, the pair of movable pieces 2106 are in an open state so that a game ball can be received in the second starting port 2102 and a game advantageous to the player Transition to the state. Furthermore, the main control program determines the normal symbol variation display pattern corresponding to the above-described determination based on the above-mentioned normal symbol variation display pattern random number value, and is classified into the general symbol synchronization effect related shown in FIG. The command is generated and stored in the transmission information storage area as transmission information, and a lighting signal is output to the normal symbol display 1189 so that the normal symbol display 1189 is lit in accordance with the determined normal symbol variation display pattern. Is stored in the output information storage area as output information. Further, when the extracted random number for normal symbol determination matches the normal symbol determination value stored in advance in the main control built-in ROM, the main control program reads the normal electric role effect shown in FIG. Various related commands are created and stored in the transmission information storage area as transmission information, and the output of the drive signal to the start-port solenoid 2105 is set so as to open and close the pair of movable pieces 2106. Store in the information storage area. On the other hand, the main control program, when the value of the random number for normal symbol determination taken out does not coincide with the normal symbol determination value stored in advance in the main control built-in ROM, the normal symbol variation display pattern random number described above. The normal symbol variation display pattern is determined based on the above, and various commands classified as related to the common-synchronization effect shown in FIG. 35 are created, stored as transmission information in the transmission information storage area described above, and the determined normal The output of the lighting signal to the normal symbol display 1189 is set so as to light the normal symbol display 1189 according to the symbol variation display pattern, and the output information is stored in the output information storage area described above.

  Subsequent to step S88, the main control program performs port output processing (step S90). In this port output process, the main control program reads output information from the output information storage area described above from the output terminals of the various output ports of the main control MPU 4100a and outputs various signals based on the output information. The main control program, for example, outputs a main payout ACK signal when the various commands from the payout control board 4110 are normally received from the output terminal of a predetermined output port of the main control MPU 4100a based on the output information. When the game is in a big hit game state, a driving signal is output to the attacking solenoids 2108A and 2108B for opening / closing the opening / closing member 2107 of the big winning opening 2103, or a starting opening solenoid for opening / closing the pair of movable pieces 2106 In addition to outputting drive signal to 2105, 2 round jackpot information output signal, 6 round jackpot information output signal, 12 round jackpot information output signal, 16 round jackpot information output signal, probability changing information output signal, special symbol display Information output signal, normal symbol display information output signal, short time medium Output information, and outputs various information (game information) signal to the payout control board 4110 regarding the game, such as start-up hole winning information output signal.

  Subsequent to step S90, the main control program performs peripheral control board command transmission processing (step S92). In this peripheral control board command transmission processing, the main control program reads transmission information such as commands and data from the transmission information storage area described above and transmits this transmission information to the peripheral control board 4140 as main peripheral serial data (command Transmission means). The transmission information includes various commands created in the main control side timer interruption process, which is this routine, shown in FIG. Various commands categorized as commands and jackpots (for example, one winning mouth count corresponding to a big winning mouth count command based on a detection signal from the count switch 2110 when a game ball entering the big winning mouth 2103 is detected) Display command), various commands classified as power-on, various commands classified as related to ordinary drawing effect, various commands classified as related to ordinary electric effect, various classified as notification display shown in FIG. Commands (door frame opening command, door frame closing command, body frame opening command, body frame closing command, etc.), various commands (frame Position 1. command, error reset navigation command and the frame state 2 command), various commands and various commands are classified into other are divided into test-related are stored. The main serial data consists of 3 bytes per packet. Specifically, the main peripheral serial data includes a status indicating a type of command having a storage capacity of 1 byte (8 bits), a mode indicating a production variation having a storage capacity of 1 byte (8 bits), and a status. And a sum value obtained by calculating the sum with the mode regarded as a numerical value, and this sum value is created at the time of transmission.

  In this peripheral control board command transmission process, when the main control program receives a frame state 1 command (first error occurrence command) from the payout control board 4110 via the RXA terminal reception port, the peripheral control board 4140 (effect control unit) ) Frame status 1 command (second error occurrence command) is transmitted (error command sending means). In this case, the main control program transfers the frame state 1 command in the form shown in FIG. 37 received from the payout control board 4110 to the peripheral control board 4140 as the frame state 1 command in the form shown in FIG.

  On the other hand, in this peripheral control board command transmission process, if the main control program receives an error release navigation command (first error release command) from the payout control board 4110 via the RXA terminal reception port, the peripheral control board 4140 An error cancellation navigation command (second error cancellation command) is transmitted to (error command sending means). In this case, the main control program transfers the error release navigation command in the form shown in FIG. 37 received from the payout control board 4110 to the peripheral control board 4140 as the error release navigation command in the form shown in FIG.

  Furthermore, in this peripheral control board command transmission process, when the main control program receives a main body frame release command (first main body frame release command) from the payout control board 4110 via the RXA terminal reception port, the peripheral control board 4140 A main body frame release command (second main body frame release command) is transmitted to the (production control unit) (main body frame command sending means, second main body frame sending means). In this case, the main control program transfers the body frame release command in the form shown in FIG. 37 received from the payout control board 4110 to the peripheral control board 4140 as the body frame release command in the form shown in FIG. On the other hand, in this peripheral control board command transmission process, when the main control program receives a main body frame close command (first main body frame close command) from the payout control board 4110 through the reception port of the RXA terminal, the peripheral control board 4140 ( A main body frame closing command (second main body frame closing command) is transmitted to the production control unit (main body frame command sending means, second main body frame command sending means, and second specific frame command sending means). In this case, the main control program transfers the main body frame closing command in the form shown in FIG. 37 received from the payout control board 4110 to the peripheral control board 4140 as the main body frame closing command in the form shown in FIG.

  In this peripheral control board command transmission process, when the main control program receives a door frame opening command (first door frame opening command) from the payout control board 4110 via the RXA terminal reception port, the peripheral control board 4140 ( A door frame opening command (second door frame opening command) is transmitted to the effect control unit (door frame command sending means, second door frame command sending means, second specific frame command sending means). In this case, the main control program transfers the door frame closing command in the form shown in FIG. 37 received from the payout control board 4110 to the peripheral control board 4140 as the door closing command in the form shown in FIG. On the other hand, in this peripheral control board command transmission process, when the main control program receives a door closing command (first door closing command) from the payout control board 4110 via the RXA terminal reception port, the peripheral control board 4140 (effect control) A door closing command (second door closing command) (door frame command sending means, second door frame command sending means, second specific frame command sending means). In this case, the main control program transfers the door closing command in the form shown in FIG. 37 received from the payout control board 4110 to the peripheral control board 4140 as the door closing command in the form shown in FIG.

  Subsequent to step S92, the main control program sets a value C in the watchdog timer clear register WCL (step S94). By setting the value C in the watchdog timer clear register WCL in step S94, the value C is set in the watchdog timer clear register WCL following the value B set in step S70. As a result, the value A, the value B, and the value C are sequentially set in the watchdog timer clear register WCL, and the watchdog timer is cleared.

  Subsequent to step S94, the main control program switches (restores) the registers (step S96) and ends this routine. Here, when the main control timer interrupt process, which is this routine, is started, the main control MPU 4100a loads the contents of the general-purpose registers on the stack and saves them. This prevents the contents of the general-purpose register used in the main process on the main control side from being destroyed. In step S96, the contents saved on the stack are read and written to the original register. Note that the main control MPU 4100a sets the interrupt permission after the return in step S96.

[5. Various control processing of peripheral control board]
Next, various processes of the peripheral control board 4140 that receives various commands from the main control board 4100 (main control MPU 4100a) will be described with reference to FIGS. FIG. 15 is a flowchart showing an example of the peripheral control unit power-on process, FIG. 16 is a flowchart showing an example of the peripheral control unit V blank interrupt process, and FIG. 17 shows an example of the peripheral control unit 1 ms timer interrupt process. FIG. 18 is a flowchart showing an example of a peripheral control unit command reception interrupt process.

  As shown in FIG. 7, the peripheral control board 4140 includes a peripheral control unit 4150, a liquid crystal and sound control unit 4160, and the like. Here, various control processes of the peripheral control unit 4150 will be described. First, the peripheral control unit power-on process will be described, followed by the peripheral control unit V blank interrupt process, the peripheral control unit 1 ms timer interrupt process, the peripheral control unit command reception interrupt process, and the peripheral control unit power failure warning signal interrupt process. . In the present embodiment, the peripheral control unit power failure warning signal interrupt processing is set as the highest priority as the interrupt processing priority, followed by the peripheral control unit 1 ms timer interrupt processing, peripheral control unit command reception interrupt processing, and peripheral control unit The order of V blank interrupt processing is set.

[5-1. Various control processes of peripheral control unit]
[5-1-1. Peripheral control unit power-on processing]
First, the peripheral control unit power-on process will be described with reference to FIG. When the pachinko gaming machine 1 is powered on, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 7 performs a peripheral control unit power-on process as shown in FIG. When the peripheral control unit power-on process is started, the effect control program performs an initial setting process under the control of the peripheral control MPU 4150a (step S1000). In this initial setting process, the production control program performs a process of initializing the peripheral control MPU 4150a itself, a hot start / cold start determination process, a process of setting a wait timer after reset, and the like. The peripheral control MPU 4150a first performs a process of initializing itself. The time required for the process of initializing the peripheral control MPU 4150a is on the order of microseconds (μs), and the peripheral control MPU 4150a is initialized in a very short time. be able to. As a result, the peripheral control MPU 4150a is output from the main control board 4100, for example, in the peripheral control unit command reception interrupt processing described later, as shown in FIG. 10 and FIG. Various commands such as commands relating to the control of game effects and commands relating to the state of the pachinko gaming machine 1 can be received. In the process of initializing the peripheral control MPU 4150a itself, the peripheral control MPU 4150a initializes the built-in VRAM by, for example, writing “0” in the storage area of the built-in VRAM in the sound source built-in VDP 4160a.

  In the hot start / cold start determination process, for the peripheral control RAM 4150c shown in FIG. 8, effect backup information (1fr) that is the contents backed up in Bank1 (1fr) and Bank2 (1fr) in the backup first area 4150cb. ) And the production backup information (1 ms), which is the contents backed up in Bank 1 (1 ms) and Bank 2 (1 ms), are compared, and Bank 3 (1 fr) and Bank 4 (1 fr) in the backup second area 4150 cc are compared. The production backup information (1fr) which is the contents backed up in the bank is compared, and the production backup information (1 fr) which is the contents backed up in Bank3 (1 ms) and Bank4 (1 ms) s), and when the compared contents match, the contents stored in Bank1 (1fr) with respect to Bank0 (1fr), which is a normally used storage area of the peripheral control RAM 4150c shown in FIG. The production backup information (1fr) and the production backup information (1ms) stored in Bank1 (1ms) with respect to Bank0 (1ms) are copied back to make a hot start, When the contents do not match (that is, when they do not match), the value 0 is forcibly written to Bank0 (1fr) and Bank0 (1 ms), which are normally used storage areas of the peripheral control RAM 4150c. And cold start.

  In the hot start / cold start determination process, the peripheral backup SRAM 4150d also compares the production backup information (SRAM), which is the contents backed up in the Bank 1 (SRAM) and Bank 2 (SRAM) in the backup first area 4150db. At the same time, the production backup information (SRAM), which is the contents backed up in the Bank 3 (SRAM) and the Bank 4 (SRAM), in the backup second area 4150 dc is compared. When the compared contents match, the production backup information (SRAM) which is the contents stored in the Bank 0 (SRAM) with respect to the Bank 0 (SRAM) which is a normally used storage area of the peripheral control SRAM 4150d (see FIG. 7). ) Is copied back to make a hot start, while when the compared contents do not match (that is, when they do not match), the value is relative to Bank0 (SRAM), which is a storage area normally used by the peripheral control SRAM 4150d. A 0 is forcibly written to make a cold start. Following such a hot start or cold start, the value 0 is forcibly written to the backup non-management target work area 4150cf of the peripheral control RAM 4150c (see FIG. 8) to clear it to zero. Then, after performing this initialization setting process, the peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e (see FIG. 7) so that the peripheral control MPU 4150a is not reset. Yes.

  Furthermore, in this peripheral control unit power-on process, the power-on contact sensitivity adjustment function built in the touch panel module 246a (contact input control means) operates as follows. That is, in this contact sensitivity adjustment function at power-on, the touch panel module 246a itself adjusts the contact sensitivity on the contact surface of the touch panel 246 when power supply is started by the power supply control unit (initial contact sensitivity adjustment means). ). Specifically, first, the control register 481a of the touch panel controller 481 stores a contact determination threshold value as a capacitance when the contact surface of the touch panel 246 is in a non-contact state. The touch panel controller 481 uses the initial value of a predetermined contact determination threshold (hereinafter referred to as “initial contact”) as the contact determination threshold stored in the control register 481a in response to the start of power supply by the power supply control unit. Also referred to as “determination threshold”.

  Subsequent to step S1000, the effect control program performs current time information acquisition processing (step S1002). In this current time information acquisition process, calendar information specifying the date and time and time information specifying the hour, minute, and second are acquired from the RTC built-in RAM 4165aa of the RTC 4165a of the RTC control unit 4165 shown in FIG. In the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. 4, the current calendar information is set in the calendar information storage unit and the current time information is set in the time information storage unit. In the current time information acquisition process, the brightness setting process of the liquid crystal display device is also performed. In the brightness setting process of the liquid crystal display device, the peripheral control MPU 4150a acquires brightness setting information from the RTC built-in RAM 4165aa of the RTC control unit 4165, and the game board is set to have the brightness of the LED included in the acquired brightness setting information. A process of turning on the backlight by adjusting the luminance of the backlight of the side liquid crystal display device 1900 is performed. As described above, the brightness setting information includes brightness adjustment information for adjusting the range of the brightness of the LED, which is the backlight of the game board side liquid crystal display device 1900, from 100% to 70% in increments of 5%, The brightness of the LED which is the backlight of the game board side liquid crystal display device 1900 that has been set is included.

  In the brightness setting process of the liquid crystal display device, specifically, the brightness of the LED included in the brightness setting information stored in the RTC built-in RAM 4165aa of the RTC control unit 4165 is 75%, and the backlight of the game board side liquid crystal display device 1900 is displayed. Is turned on by adjusting the backlight brightness of the game board side liquid crystal display device 1900 based on the brightness adjustment information included in the brightness setting information, and the brightness stored in the RTC built-in RAM 4165aa of the RTC control unit 4165. When the backlight of the game board side liquid crystal display device 1900 is turned on when the luminance of the LED included in the setting information is 80%, the backlight of the game board side liquid crystal display device 1900 is turned on based on the luminance adjustment information included in the luminance setting information. Lights with the brightness adjusted. In this liquid crystal display device luminance setting process, the same correction as the above-described luminance correction program for correcting the luminance of the game board side liquid crystal display device 1900 according to the usage time of the game board side liquid crystal display device 1900 is performed. It is not done at all. This is because the brightness setting process of the liquid crystal display device incorporates a correction program similar to the brightness correction program, so that the brightness of the LED is corrected toward 100% each time the brightness setting process of the liquid crystal display device is executed. This is to prevent it from being done.

  In the present embodiment, the peripheral control MPU 4150a acquires calendar information and time information from the RTC built-in RAM 4165aa of the RTC 4165a only once when the power is turned on. In addition, the peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e after performing this current time information acquisition processing so that the peripheral control MPU 4150a is not reset.

  Subsequent to step S1002, the effect control program sets a value 0 to the V blank signal detection flag VB-FLG (step S1006). This V blank signal detection flag VB-FLG is a flag for determining whether or not to execute a peripheral control unit steady process to be described later, and has a value of 1 when the peripheral control unit steady process is executed. Is set to 0 when not executing. The V blank signal detection flag VB-FLG, which will be described later, is executed when a V blank signal indicating that the screen data from the peripheral control MPU 4150a can be received is input from the sound source built-in VDP 4160a. The value 1 is set in the part V blank signal interrupt processing. In step S1006, the V blank signal detection flag VB-FLG is initialized once by setting the value 0 to the V blank signal detection flag VB-FLG. The peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e after setting the value 0 to the V blank signal detection flag VB-FLG so that the peripheral control MPU 4150a is not reset. Yes.

  Subsequent to step S1006, the effect control program determines whether or not the V blank signal detection flag VB-FLG is 1 (step S1008). When the V blank signal detection flag VB-FLG is not 1 (value 0), the process returns to step S1008 and it is repeatedly determined whether or not the V blank signal detection flag VB-FLG is 1. By repeating such a determination, the process waits until the peripheral control unit steady process is executed. The peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e after determining whether or not the V blank signal detection flag VB-FLG is 1, and resets to the peripheral control MPU 4150a. It is made so that it won't be applied.

  When the V blank signal detection flag VB-FLG has a value of 1 in step S1008, that is, when the peripheral control unit steady process is executed, a value 1 is first set to the steady process flag SP-FLG (step S1009). The steady processing flag SP-FLG is set to a value of 1 when the peripheral control unit steady processing is being executed, and to a value of 0 when the peripheral control unit steady processing is completed.

  Subsequent to step S1009, the effect control program performs 1 ms interrupt timer activation processing (step S1010). In this 1 ms interrupt timer starting process, a 1 ms interrupt timer for executing a later-described peripheral control unit 1 ms timer interrupt process is started, and the number of times this 1 ms interrupt timer is started and the peripheral control unit 1 ms timer interrupt process is executed. The value 1 is set in the 1 ms timer interrupt execution count STN for counting the 1 ms timer interrupt execution count STN. This 1 ms timer interrupt execution count STN is updated by the peripheral control unit 1 ms timer interrupt processing.

  Subsequent to step S1010, the effect control program performs lamp data output processing (step S1012). In this lamp data output process, the effect control program performs DMA serial continuous transmission to the lamp driving board 4170 shown in FIG. Here, serial transmission of the serial I / O port for the lamp driving board is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. When the serial transmission for the lamp drive board serial I / O port is started, the game board 4 is stored in the lamp drive board transmission data storage area 4150caa of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. A state in which game board side light emission data SL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs of various decorative boards provided is created and set in a lamp data creation process to be described later It has become.

  The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates transmission of the serial I / O port for the lamp drive board as a request factor of the peripheral control DMA controller 4150ac, and is stored at the head address of the lamp drive board side transmission data storage area 4150caa. The first 1 byte of the game board side light emission data SL-DAT is transmitted to the transmission buffer register of the serial I / O port for the lamp driving board via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer and write. As a result, the serial I / O port for the lamp driving board transfers the written data in the transmission buffer register to the transmission shift register, and synchronizes with the light emission clock signal SL-CLK on the game board side to 1 byte of the transmission shift register. The data starts to be transmitted bit by bit.

  The peripheral control DMA controller 4150ac is triggered by a transmission interrupt request for the lamp drive board serial I / O port (in this embodiment, in the transmission buffer register of the lamp drive board serial I / O port). The written 1-byte data is transferred to the transmission shift register, and the transmission buffer register is empty because the 1-byte data disappears.), The peripheral control CPU core 4150aa is using the bus. If not, the remaining game board side light emission data SL-DAT stored in the lamp drive board side transmission data storage area 4150caa is byte by byte via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transmit serial I / O port for lamp drive board By transferring and writing to the buffer register, the lamp drive board serial I / O port transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the light emission clock signal SL-CLK on the game board side. Transmission of 1-byte data of the transmission shift register is started bit by bit, and continuous transmission is performed through the serial I / O port for the lamp driving board.

  In the lamp data output process, the effect control program performs a DMA serial continuous transmission process to the frame decoration drive amplifier board 194 shown in FIG. Also here, the frame I / O port LED serial I / O port continuous transmission is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a. When the frame decoration drive amplifier board LED serial I / O port continuous transmission is started, the frame decoration drive amplifier board side LED transmission data storage area of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. In 4150cab, door side light emission data STL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs of various decorative boards provided on the door frame 5 is created by a lamp data creation process described later. Is set.

  The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates the transmission of the frame decoration drive amplifier board LED serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and transmits the frame decoration drive amplifier board side LED transmission data storage area. The first one byte of the door-side light emission data STL-DAT stored at the head address of 4150cab is serially used for the frame decoration drive amplifier board LED via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer and write to the I / O port transmit buffer register. As a result, the frame decoration drive amplifier board LED serial I / O port transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the door side light emission clock signal STL-CLK. Transmission of 1-byte data is started bit by bit.

  The peripheral control DMA controller 4150ac is triggered every time a transmission interrupt request for the serial I / O port for frame decoration drive amplifier board LED is generated (in this embodiment, the serial I / O for frame decoration drive amplifier board LED). 1 byte data written in the transmission buffer register of the port is transferred to the transmission shift register, and the transmission buffer register is empty because the 1 byte data disappears.), Peripheral control CPU core 4150aa When the bus does not use a bus, the remaining door side light emission data STL-DAT stored in the frame decoration drive amplifier board side LED transmission data storage area 4150cab is stored byte by byte in the external bus 4150h and the peripheral control bus controller 4150ad. And frame decoration via peripheral bus 4150ai By transferring and writing to the transmission buffer register of the serial amplifier I / O port for the dynamic amplifier board LED, the serial I / O port for frame decoration drive amplifier board LED writes the data of the written transmission buffer register to the transmission shift register. Transfer and start transmitting 1-byte data of the transmission shift register bit by bit in synchronization with the door side light emission clock signal STL-CLK, and perform continuous transmission by the serial I / O port for frame decoration drive amplifier board LED Yes.

  Subsequent to step S1012, the effect control program performs an operation unit monitoring process (step S1014). In this operation unit monitoring process, in the operation unit information acquisition process in the peripheral control unit 1 ms timer interruption process described later, the dial operation unit 401 is based on detection signals from various detection switches provided in the operation unit 400 shown in FIG. Rotation (rotation direction) and various information obtained by operating the pressing operation unit 405 (for example, rotation of the dial operation unit 401 created based on detection signals from various detection switches provided in the operation unit 400 (rotation direction) ) History information, operation history information of the pressing operation unit 405, etc.) Based on the operation unit information acquisition storage area 4150cai of the peripheral control RAM 4150c shown in FIG. The presence or absence of operation of the unit 405 is monitored, and the rotation direction and push of the dial operation unit 401 are monitored. The state of operation of the operation section 405 appropriately determines whether to reflect the game effects.

  Subsequent to step S1014, the effect control program performs display data output processing (step S1016). In this display data output processing, the drawing data for one screen (one frame) generated on the built-in VRAM of the sound source built-in VDP 4160a in the display data creation processing described later is sent from the channels CH1 and 2 shown in FIG. The data is output to the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 246. Thereby, various screens are drawn on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 246. In the display data output process, when the drawing exceeding the drawing capability of the sound source built-in VDP 4160a is performed, the generated drawing data for one screen (one frame) is used as the game board side liquid crystal display device 1900 and the upper plate side liquid crystal. The output to the display device 246 is canceled. Thereby, although delay of processing time can be prevented, so-called frame dropping occurs, a plurality of LEDs on various decorative boards provided on the game board 4 by the ramp data output processing in step S1012, and The speaker housed in the speaker box 920 provided in the main body frame 3 shown in FIG. 5 by the effect by the plurality of LEDs on the various decorative boards provided in the door frame 5 and the sound data output processing described later, and shown in FIG. It is a mechanism in which priority can be given to synchronization with effects produced by music, sound effects, etc. according to various effects from speakers provided on the door frame 5.

  Subsequent to step S1016, the effect control program performs sound data output processing (step S1018). In this sound data output process, the effect control program outputs to the audio data transmission IC 4160c as audio data obtained by serializing sound data such as music and sound effects set in the sound source built-in VDP 4160a in the sound data creation process described later, In addition to music and sound effects, the sound data of notification sound and notification sound is output to the audio data transmission IC 4160c as serialized audio data. When the audio data transmission IC 4160c receives the serialized audio data from the sound source built-in VDP 4160a, the audio data transmission IC 4160c is directed toward the frame decoration drive amplifier board 194 as differential serial data using the right audio data as a plus signal and a minus signal. At the same time, the left audio data is transmitted toward the frame decoration drive amplifier board 194 as differential serial data having a plus signal and a minus signal. As a result, music and sound effects adapted to various effects are reproduced in stereo from the speakers housed in the speaker box 920 provided on the main body frame 3 and the speakers provided on the door frame 5, as well as notification sounds and notification sounds. Stereo playback.

  Subsequent to step S1018, the effect control program performs scheduler update processing (step S1020). In this scheduler update process, the effect control program updates various schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. For example, in the scheduler update process, among the screen data arranged in time series constituting the screen generation schedule data set in the schedule data storage area 4150cae, what number screen data from the top screen data is stored in the sound source built-in VDP 4160a. The pointer is updated to indicate whether to output.

  Also, in the scheduler update process, among the light emission data arranged in time series constituting the light emission mode generation schedule data set in the schedule data storage area 4150cae, the number of the light emission data from the first light emission data is emitted from the various LEDs. The pointer is updated to indicate whether the mode is set.

  In the scheduler update processing, sound data such as music and sound effects, sound data of notification sound and notification sound, which are arranged in time series constituting the sound generation schedule data set in the schedule data storage area 4150cae, are instructed. Of the sound command data, the pointer is updated in order to indicate what number of sound command data from the head sound command data is to be output to the built-in sound source VDP 4160a.

  In the scheduler update process, the drive data of the electric drive sources such as motors and solenoids arranged in time series constituting the electric drive source schedule data set in the schedule data storage area 4150cae is used from the head drive data. The pointer is updated to indicate what number of drive data is to be output. The drive data of the electric drive sources such as motors and solenoids arranged in time series constituting the electric drive source schedule data is a peripheral control unit 1 ms timer interrupt which is repeatedly executed every time a 1 ms timer interrupt described later occurs. It is updated by the motor and solenoid drive process in the process. In the motor and solenoid drive processing that is repeatedly executed each time this 1 ms timer interrupt occurs, an electric drive source such as a motor or solenoid is driven according to the drive data indicated by the pointer, and the next drive specified in time series is performed. The pointer is updated to the data, and the pointer is updated every time its own processing is executed. In other words, since the drive data indicated by the pointer updated in the motor and solenoid drive processing is forcibly updated in the scheduler update processing, the pointer is originally instructed for some reason in the motor and solenoid drive processing. Even if other drive data is instructed from the drive data that is supposed to be performed, it is forcibly updated to instruct the drive data that should be instructed originally in the scheduler update processing.

  Subsequent to step S1020, the effect control program performs a received command analysis process (step S1022). In this received command analysis process, the effect control program analyzes various commands transmitted from the main control board 4100 in various commands received in a peripheral control unit command reception interrupt process (command receiving means) described later (command analysis). means). That is, in the effect control program, the command received in this peripheral control unit command reception interrupt process is, for example, a start opening prize command for instructing the start opening start effect, the number of normal symbols held (0 to 4) ), A symbol synchronization effect start command for instructing the start of a symbol synchronization effect, a symbol memory command that is output when the number of start suspension changes, and a winning ball 2103 is received by a game ball. The winning prize 1 count display command (big winning prize count command) output every time, or the frame status 1 command (second error occurrence command, full tank error occurrence command) indicating the content of the full tank shown in FIG. (Command analyzing means) to recognize which gaming state is currently in progress. In addition, after the predetermined time has elapsed from the time when the power is turned on, the effect control program is configured such that the command received by the peripheral control unit command reception interrupt process is a body frame opening command, a body frame closing command, a door frame opening command, or a door frame. Analyzes whether or not the command is a close command. Various commands from the main control board 4100 are received by the peripheral control unit command reception interrupt process and stored in the reception command storage area 4150cac of the peripheral control RAM 4150c shown in FIG. The effect control program analyzes various commands stored in the received command storage area 4150cac. The various commands shown in FIG. 35 are classified into various commands classified as related to the special figure 1 tuning effect, various commands classified as related to the special figure 2 synchronous effect, various commands classified as related to the jackpot, and power-on. , Various commands classified as related to ordinary drawing effect, various commands classified as related to ordinary electric character effect, various commands classified as notification display shown in FIG. 36, door frame opening command described above , Door frame closing command, body frame opening command and body frame closing command, error release navigation command (corresponding to the second error canceling command) and frame state 1 command (corresponding to the second error occurrence command) There are various commands that are classified, various commands that are classified as related to the test, and various commands that are classified into others.

  Subsequent to step S1022, the effect control program performs warning processing (step S1024). In this warning process, when the command analyzed by the effect control program in the received command analysis process in step S1022 as described above includes various commands classified into the notification display shown in FIG. The screen generation schedule data, the light emission mode generation schedule data, the sound generation schedule data, the electrical drive source schedule data, and the like set in the abnormality display mode for executing the abnormality notification are stored in the peripheral control unit 4150. The data is extracted from various control data copy areas 4150ce of the peripheral control ROM 4150b or the peripheral control RAM 4150c, and set to 4150cae in the schedule data storage area of the peripheral control RAM 4150c. In the warning process, when multiple abnormalities occur simultaneously, the abnormality notification is performed in the order of the priority registered in advance, and the abnormality is automatically resolved and the remaining abnormality notifications are automatically transitioned to. It is supposed to be. This allows you to monitor multiple anomalies at the same time without losing the information that an anomaly has occurred due to the occurrence of another anomaly after the occurrence of the anomaly but before resolving the anomaly Can do.

  Furthermore, in this warning process, after a predetermined time has elapsed since the power was turned on, the command analyzed by the effect control program in the received command analysis process (step S1022) described above is classified into the status display shown in FIG. In the case of various commands to be executed, for example, an error canceling navigation command (second error canceling command), by controlling the liquid crystal and sound control unit 4160 in a manner different from the normal rendering mode accompanying the rendering operation, for example, a game The panel side liquid crystal display device 1900 (production device), the upper plate side liquid crystal display device 244 (production device), and a lamp (production device) are used to visually warn the outside, or using a pair of side speakers (production device). To audibly warn the outside (error notification means). In this way, when a malicious player attempts to input an error cancellation navigation command to the main control board 4100 by operating the operation switch 952 of the payout control board 4110 despite being in a gaming state. Since the pachinko gaming machine 1 is configured to warn the outside, fraudulent acts on the main control board 4100 that may affect the progress of the game are suppressed.

  Next, following step S1024 described above, the effect control program performs main prize ball number information acquisition processing (step S1025), and then performs RCT acquisition information update processing (step S1026). In this RTC acquisition information update process, the effect control program stores in the calendar information storage unit acquired in the current time information acquisition process in step S1002 and set in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. The updated calendar information and the time information stored in the time information storage unit are updated. By this RCT acquisition information update process, the hour, minute and second as time information stored in the time information storage unit are updated, and the year and month as calendar information stored in the calendar information storage unit based on the updated time information. The day is updated.

  Subsequent to step S1026, the effect control program performs lamp data creation processing (step S1028). In this lamp data creation process, the effect control program updates the pointer in the scheduler update process in step S1020, and the pointer indicates the light emission data arranged in time series constituting the light emission mode generation schedule data. Peripheral control of game board side light emission data SL-DAT for outputting lighting signals, blinking signals, or gradation lighting signals to a plurality of LEDs of various decorative boards provided on the game board 4 based on the light emission data to be performed The peripheral control ROM 4150b of the unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c are extracted and created, set in the lamp drive board side transmission data storage area 4150caa of the peripheral control RAM 4150c shown in FIG. 5 of various decorative boards provided in 5 The door side light emission data STL-DAT for outputting a lighting signal, blinking signal or gradation lighting signal to D is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. It is created and set in the frame decoration drive amplifier board side LED transmission data storage area 4150cab of the peripheral control RAM 4150c shown in FIG.

  Subsequent to step S1028, the effect control program performs display data creation processing (step S1030). In this display data creation process, the pointer is updated in the scheduler update process in step S1020, so that the effect control program is arranged in time series in the peripheral control MPU 4150a as data constituting the screen generation schedule data. Of the screen data, the screen data indicated by the pointer is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. When the screen data is input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a extracts at least one character data from the liquid crystal and sound control ROM 4160b based on the input screen data, and the extracted at least one character data. Then, sprite data is created, and drawing data for one screen (one frame) to be displayed on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 246 is generated on a built-in VRAM (corresponding to a frame buffer).

  By the way, in the conventional pachinko gaming machine, as the game progresses, by displaying a video composed of a number of material images superimposed on the background image in each frame, an attempt is made to make it difficult for the player to run out of interest. (Refer to the first reference above.) Although it is required to execute display control so that a larger number of material images are included in each frame in order to display more various images, a large number of material images are included in each frame. At first glance, it seems that a large burden is placed on display control.

  Therefore, in the present embodiment, for the purpose of simplifying the display control of frames including a large number of material images and reducing the processing load, the effect control program is provided for each frame displayed based on the drawing data and each frame. While managing correspondence information in which correspondence relationships with a plurality of material images that can be represented are defined in advance, when the predetermined frame of each frame is to be displayed, the correspondence information is referred to and the predetermined information is referred to. At least one predetermined material image to be included in the frame is specified, and drawing data is included in the built-in sound source VDP 4160a without including the predetermined material image and excluding other material images excluding the predetermined material image. A predetermined frame based on the drawing data stored in the built-in VRAM is generated by being generated and stored in the built-in VRAM (frame buffer). Being displayed on the side the liquid crystal display device 1900 (display unit). This will be specifically described below.

  First, in the present embodiment, at least a part of background image data (hereinafter also referred to as “specific background image data”) out of a large number of background image data used for displaying a large number of background images constituting each frame, At a position where a material image (hereinafter also referred to as “specific sprite”) such as at least one sprite on the background image based on the specific background image data is to be originally arranged (hereinafter referred to as “original arrangement position”), As shown in a display mode that cannot be visually recognized (hereinafter referred to as “confidential state”), it is managed as follows.

  First, in the peripheral control board 4140, the following correspondence linking table (corresponding relationship information management means) is stored in the peripheral control ROM 4150b. Browse the table. In this correspondence linking table, each frame displayed based on each drawing data generated by the sound source built-in VDP 4160a and at least one sprite that can be represented in each frame (or a predetermined number of frame group groups). Predefined correspondence information is managed together with a concealment release command (confidential release command) for canceling the visual concealment state of the at least one sprite. In this correspondence linking table, each sprite (or each background image) can be identified using a sprite number, and as a part of the correspondence information, the coordinates of each sprite in the display range of each frame The value is managed.

  In this correspondence linking table, as such correspondence relationship information, for example, at least one material image such as a sprite that can be represented in each frame displayed based on each drawing data generated by the sound source built-in VDP 4160a, and A correspondence relationship with a secrecy cancellation command for canceling the visual secrecy state of the at least one material image is defined in advance. In the following description, the at least one material image is referred to as “desired sprite”.

  As described above, the peripheral control MPU 4150a has a function of causing the sound source built-in VDP 4160a to generate drawing data from sprite data based on the scheduler data (drawing management means). When the display control program tries to display a predetermined frame according to the result of the predetermined effect lottery executed when the start condition is satisfied, the correspondence relationship in the correspondence association table is controlled by the control of the peripheral control MPU 4150a. With reference to the information, a desired sprite to be included in the predetermined frame is specified (material image specifying means).

  Further, the production control program specifies the secrecy release command corresponding to the desired sprite by referring to the correspondence information in the correspondence linking table when the desired sprite should be represented in a predetermined frame according to the schedule data, The specified concealment release command is output to the sound source built-in VDP 4160a (concealment release instructing means). The secrecy release command includes a sprite number (hereinafter referred to as “desired sprite number”) that can identify a desired sprite whose secrecy state should be released in the predetermined frame. As a result of the output of the secrecy release command, the display state flag of the name tag information is updated to the one that was off in the initial state. The name tag information and its display state flag are prepared for each sprite that can be represented in each frame, and are referred to when the sound source built-in VDP 4160a executes the drawing process.

  Here, the effect control program operates the sound source built-in VDP 4160a (drawing control means) as follows when trying to display a predetermined frame under the control of the peripheral control MPU 4150a. That is, the sound source built-in VDP 4160a has a display mode in which a desired sprite that can be included in the predetermined frame is kept in a concealed state based on the correspondence information in the correspondence linking table when the concealment release command is not received. Drawing data to be generated in the frame buffer. Thereby, the effect control program can display the frame of the aspect which cannot see the said desired sprite on the game board side liquid crystal display device 1900 by control of peripheral control MPU4150a.

  On the other hand, when the sound source built-in VDP 4160a receives the concealment release command, it confirms that the display state flag of the name tag information corresponding to the desired sprite number included in the concealment release command is updated to ON. As a trigger, the desired sprite corresponding to the secrecy release command is specified with reference to the correspondence information in the correspondence linking table. Furthermore, the built-in sound source VDP 4160a generates rendering data in the frame buffer for canceling the concealed state of the specified desired sprite and setting the display mode so that the desired sprite can be visually recognized. As a result, the effect control program can cause the game board side liquid crystal display device 1900 to display a frame in a display mode in which the desired sprite can be visually recognized at the original arrangement position under the control of the peripheral control MPU 4150a.

  In this way, the presentation control program does not need to finely manage which sprite group can be represented in each frame when displaying the frame group of a certain scene due to the presence of the correspondence linking table. On the other hand, the sound source VDP 4160a can draw a frame representing each desired sprite by a very simple control compared to the conventional display control of whether or not to output the secrecy release command to the peripheral control MPU 4150a. It is possible to draw a frame that does not represent any sprite. Thereby, the display control of the frame including a large number of sprites can be simplified and the processing load can be reduced.

  In addition, because the correspondence relationship table described above employs a configuration in which the sprite group including the desired sprite is linked to the effect control program (the concealment release command group issued by) to manage the correspondence relationship. In addition, the creation work of sprite data and the design work of the production control program can be completely separated independently, and the design work related to display control can be simplified.

  By the way, as described above, as a detection device that can be mounted on a pachinko gaming machine, in general, sensitivity adjustment is generally performed as an initial process when the power is turned on, and then the device operates with the sensitivity (the first reference above). reference). Even if the contact sensitivity is adjusted in the initial process in this way, depending on the gaming environment thereafter, it may be considered that the sensitivity gradually becomes inappropriate at first glance.

  Therefore, in the present embodiment, in this display data creation processing, the effect control program is further controlled by the peripheral control MPU 4150a to the upper plate side liquid crystal display device 246 (second display means) and the touch panel 246 (contact type input means). The function of causing the touch panel module 246a (contact input control means) to adjust the contact sensitivity of the contact surface of the touch panel 246 while outputting the effect command (effect execution command) for executing the display operation in a mode for prompting the touch on the operation surface. A threshold setting command (sensitivity adjustment command) for enabling (contact sensitivity adjustment means) is output (command output means). In other words, the effect control program prompts the upper liquid crystal display device 246 to touch the operation surface of the touch panel 246 with a finger as an effect command (effect execution command) (to the operation surface of the contact type input means). A command for executing the display operation in the mode of prompting the contact of the user is written in the transmission information storage area, and then output to the liquid crystal and sound control unit 4160 (contact prompting command means). Next, in the liquid crystal and sound control unit 4160, when the command is received, the presentation control program (the display control program by the control thereof) is touched on the operation surface of the touch panel 246 (contact type input means) based on the command. A screen in a mode for prompting touching is displayed on the upper plate side liquid crystal display device 246.

  Next, following step S1030, the effect control program performs touch panel processing (step S1031). In this touch panel processing, mainly the effect control program detects the contact state on the operation surface of the touch panel 246 based on the contact detection signal as the detection signal received from the touch panel module 246a of the touch panel 246 under the control of the peripheral control MPU 4150a. (Contact state detection means). That is, this effect control program also has a function as a touch panel driver (contact state detecting means) that detects a contact state on the operation surface of the touch panel 246. The effect control program acquires the coordinate value of the operation surface of the touch panel 246 indicating the center of the contact portion based on the contact state, specifies the position represented by the coordinate value as a detection point (detection point acquisition means), Operation information including the initial position is acquired. In addition, this effect control program may acquire not only such coordinate values but also a range of the operation surface (hereinafter referred to as a contact range).

  In this touch panel process, in order to deal with the above-mentioned concerns, the presentation control program is controlled by the peripheral control MPU 4150a, separately from the above-described presentation command (production execution command), and then stored in the control register 481a of the touch panel controller 481. A threshold setting command (sensitivity adjustment command) for updating the stored contact determination threshold value is written in the transmission information storage area at a predetermined timing, and then output to the touch panel module 246a (contact input control means) shown in FIG. (Sensitivity adjustment command means).

  Specifically, the effect control program, as the predetermined timing described above, when the variation time of the special symbol 1 (first special symbol) has elapsed from the main control MPU 4100a (see FIG. 35) ) When the predetermined time (for example, 1 minute) has elapsed since the last time, or when the variation time of special symbol 2 (second special symbol) has elapsed, 35), the threshold setting command described above is written in the transmission information storage area and transmitted to the touch panel controller 481 of the touch panel module 246a.

  The effect control program controls the touch panel module 246a, and the touch panel 246 is touched when the touch panel controller 481 receives the threshold setting command (sensitivity adjustment command) output from the peripheral control MPU 4150a as an example of the outside. Adjust the contact sensitivity on the surface. In other words, the effect control program receives the threshold setting command from the peripheral control MPU 4150a to the touch panel controller 481 of the touch panel module 246a, and based on the threshold setting command, the touch determination stored in the control register 481a. The contact sensitivity by the touch panel 246 is adjusted by updating the threshold value for use. Specifically, touch panel controller 481 receives the threshold setting command, acquires the capacitance based on the detection signal output from touch panel sensor 482, and uses this capacitance as the contact surface of touch panel 246. Is determined as a new contact determination threshold value in the non-contact state, and the contact determination threshold value stored in the control register 481a is updated with the new contact determination threshold value.

  After that, the touch panel controller 481 compares the new threshold value for contact determination updated in the control register 481a with the detected capacitance acquired every time the contact state is detected as described above. When it is determined that the detected capacitance is less than the contact determination threshold, the contact surface is determined to be in a non-contact state, while when it is determined that the detected capacitance is equal to or greater than the contact determination threshold. It is determined that the contact surface is in contact.

  As described above, when the touch panel controller 481 determines that the contact surface is in the contact state, the touch panel controller 481 outputs contact detection information including the detection coordinate value on the contact surface to the peripheral control board 4140. In the peripheral control board 4140, when the contact detection information is received, the peripheral control MPU 4150a can grasp the contact position on the contact surface based on the detected coordinate value included in the received contact detection information.

  As described above, the touch sensitivity of the touch panel 246 is increased at a desired timing triggered by the touch panel controller 481 receiving the threshold setting command (sensitivity adjustment command) output by the peripheral control MPU 4150a of the peripheral control board 4140. Since the predetermined threshold value for contact determination is updated, the contact sensitivity of the touch panel 246 (contact type input means) is adjusted at a desired timing if the output timing of the threshold setting command by the peripheral control MPU 4150a is appropriately controlled. (Calibration) For this reason, the production control program removes the output timing that may affect the game by the player and causes the touch panel controller 481 to receive the threshold setting command, so that the game always affects the touch panel 246 without affecting the game. The detection of a contact state can be made into an appropriate operation mode.

  The timing at which this effect control program should output the threshold setting command to the touch panel controller 481 under the control of the peripheral control MPU 4150a is, for example, as shown above. There is a possibility that a predetermined time (for example, 1 minute) has elapsed since the command or the special figure 2 synchronized production end command has been received, and the player has touched the operation surface of the touch panel 246 because the game has been stopped. Low timing can be illustrated. That is, such contact sensitivity adjustment is performed as much as possible during the special symbol variation display that may be performed using the touch panel 246, and is performed when the variation display is completed. Yes.

  In addition, as a timing at which the threshold setting command should be output, in addition, the effect control program receives from the main control MPU 4100a a normal-synchronization effect end command (see FIG. 35) transmitted when the normal symbol variation time has elapsed. It may be a timing at which a predetermined time (for example, 1 minute) has passed.

  On the other hand, as described above, the touch panel 246 is a capacitance type and is provided on the upper plate 301 that can store a large number of game balls and easily generate static electricity. Sensitivity adjustment is performed at a predetermined timing accordingly, and it is erroneously detected that the capacitance has changed even if it is caused by such changes in the surrounding environment and not by the player's operation. It becomes difficult to do.

  Subsequent to step S1031, the effect control program performs sound data creation processing (step S1032). In the sound data creation process, the effect control program updates the pointer in the scheduler update process in step S1020, and the pointer indicates the sound command data arranged in time series constituting the sound generation schedule data. The sound command data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. When the sound command data is input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a extracts sound data such as music and sound effects stored in the liquid crystal and sound control ROM 4160b and controls the sound source by controlling the sound source. Sound data such as music and sound effects are incorporated according to the track number defined in the data, and an output channel to be used is set according to the output channel number.

  In the sound data creation process, each time this sound data creation process is performed (that is, every time the peripheral control unit steady process is performed), the peripheral control A / D converter 4150ak shown in FIG. The voltage divided by the resistance value at the rotation position of the knob portion of 4140a is converted into a value of 1024 steps from 0 to 1023. In this embodiment, the value of 1024 steps is divided into seven and managed as substrate volumes 0 to 6, and the sound volume is set to the substrate volume 0, the maximum volume is set to the substrate volume 6, and the substrate volume 0 to the substrate volume are set. Each volume is set to increase toward the volume 6. By controlling the liquid crystal and the built-in sound source VDP 4160a of the sound control unit 4160 so that the volume is set to the substrate volume 0 to 6, audio data is obtained as audio data obtained by serializing the sound data in the sound data output process of step S1018 described above. By outputting to the transmission IC 4160 c, music and sound effects flow from the speakers housed in the speaker box 920 provided in the main body frame 3 and the speakers provided in the door frame 5.

  In addition, the notification sound and the notification sound flow without depending on the volume adjustment based on the turning operation of the knob part, and the sound volume of the liquid crystal and sound control unit 4160 can be set by the program from the mute level to the maximum volume level. The built-in VDP 4160a can be controlled and adjusted. The volume adjusted by this program can be smoothly changed from the mute to the maximum volume, unlike the substrate volume divided into the above seven stages. For example, even if a store clerk or the like of the hall rotates the knob portion of the volume adjustment volume 4140a to set the volume to a low level, the hall and the door frame 5 are accommodated in the speaker box 920 provided in the main body frame 3. Although the production sound such as music and sound effects flowing from the provided speakers is reduced, the sound volume is high when a malfunction occurs in the pachinko gaming machine 1 or when the player is cheating (in this embodiment, the maximum The notification sound set to (volume) can be played. Therefore, even if the volume of the production sound is reduced, it is possible to prevent the hall clerk or the like from becoming difficult to notice the occurrence of a malfunction or the player's cheating due to the notification sound. Also, based on the current board volume set by volume adjustment based on the turning operation of the knob part, the volume of the advertisement sound is reduced so as not to interfere with the music and sound effects. In addition to music and sound effects, the screen displayed on the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 246 can be rendered more powerful and advantageous for the player. It is also possible to notify that there is a high possibility that the game state will be entered.

  Subsequent to step S1032, the effect control program performs a backup process (step S1034). In this backup process, the effect control program stores the contents stored in the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. 8 into the backup first area 4150cb and the backup second area 4150cc. The contents are copied and backed up, and the contents stored in the peripheral control SRAM 4150d attached to the peripheral control MPU 4150a are copied and backed up in the backup first area 4150db and the backup second area 4150dc, respectively.

  Specifically, in the backup process, the peripheral control RAM 4150c is backed up every frame (1 frame) in the backup management target work area 4150ca shown in FIG. 8, that is, every time the peripheral control unit steady process is executed. Lamp drive board side transmission data storage area 4150caa, frame decoration drive amplifier board side LED transmission data storage area 4150cab, reception command storage area 4150cac, RTC information acquisition storage area 4150cad, included in the target Bank0 (1fr) The production information (1fr), which is the content stored in the schedule data storage area 4150cae, is used as production backup information (1fr), and Bank1 (1fr) and Bank2 (1) of the backup first area 4150cb Peripheral control DMA controller 4150ac to r) is copied at high speed, and backup Bank3 second area 4150cc (1fr) and peripheral control DMA controller 4150ac to Bank4 (1FR) is copied at high speed.

  The high-speed copy of the contents stored in Bank 0 (1fr) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a shown in FIG. The content stored in Bank0 (1fr) is designated to be copied to Bank1 (1fr) in the backup first area 4150cb, and the content stored in the first address of Bank0 (1fr) is changed to the end address of Bank0 (1fr) The stored contents are all copied in order from the first address of Bank 1 (1fr) in the backup first area 4150cb in succession to a predetermined byte (for example, 1 byte), and the peripheral control CPU core 4150aa performs the peripheral control DM. The content stored in Bank0 (1fr) as the request factor of the controller 4150ac is designated to be copied to Bank2 (1fr) in the backup first area 4150cb, and Bank0 (1fr) is stored from the content stored at the first address of Bank0 (1fr). The contents stored at the end address of 1fr) are all copied in order from the start address of Bank2 (1fr) of the backup first area 4150cb in succession by a predetermined number of bytes (for example, 1 byte).

  Subsequently, the peripheral control CPU core 4150aa designates the content stored in Bank0 (1fr) as the request factor of the peripheral control DMA controller 4150ac, specifies the copy of the backup second area 4150cc to Bank3 (1fr), and Bank0 (1fr) ) To the content stored at the end address of Bank0 (1fr) to the content stored at the end address of Bank0 (1fr). The peripheral control CPU core 4150aa specifies the contents stored in Bank0 (1fr) as the request factor of the peripheral control DMA controller 4150ac, and specifies that the backup second area 4150cc is copied to Bank4 (1fr). Shi From the content stored at the beginning address of Bank0 (1fr) to the content stored at the end address of Bank0 (1fr), a predetermined byte (for example, 1 byte) is continuously stored in the backup second area 4150cc Bank4 (1fr) Copy everything starting from the first address.

  In the backup process, the peripheral control SRAM 4150d becomes a backup target for each frame (1 frame) in the backup management target work area 4150da shown in FIG. 8, that is, every time the peripheral control unit steady process is executed. The peripheral control DMA controller 4150ac is provided in the bank 1 (SRAM) and the bank 2 (SRAM) in the backup first area 4150db as the production information (SRAM), which is the content stored in the Bank 0 (SRAM). The peripheral control DMA controller 4150ac copies to the bank 3 (SRAM) and the bank 4 (SRAM) in the backup second area 4150dc at high speed.

  The high-speed copy of the contents stored in Bank 0 (SRAM) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a shown in FIG. The content stored in Bank0 (SRAM) is designated to be copied to Bank1 (SRAM) in backup first area 4150db, and the content stored at the beginning address of Bank0 (SRAM) is changed to the end address of Bank0 (SRAM). The stored contents are all copied successively from the first address of Bank 1 (SRAM) in the backup first area 4150db in order of predetermined bytes (for example, 1 byte), and the peripheral control CPU core 4150aa The content stored in Bank0 (SRAM) as the request factor of the edge control DMA controller 4150ac, the copy to Bank2 (SRAM) of the backup first area 4150db is designated, and the content stored in the first address of Bank0 (SRAM) To the contents stored at the end address of Bank 0 (SRAM) are copied in order from the start address of Bank 2 (SRAM) in the backup first area 4150 db in succession by a predetermined number of bytes (for example, 1 byte).

  Subsequently, the peripheral control CPU core 4150aa designates the contents stored in the Bank 0 (SRAM) as the request factor of the peripheral control DMA controller 4150ac, specifies the copy of the backup second area 4150dc to the Bank 3 (SRAM), and Bank 0 (SRAM). ) To the content stored at the end address of Bank0 (SRAM) to the content stored at the end address of Bank0 (SRAM) by a predetermined number of bytes (for example, 1 byte) continuously, the top address of Bank3 (SRAM) in backup second area 4150dc The peripheral control CPU core 4150aa copies the contents stored in the bank 0 (SRAM) as the request factor of the peripheral control DMA controller 4150ac to the bank 4 (SRAM) of the backup second area 4150dc. P2 is specified, and the content stored in the bank 0 (SRAM) start address to the content stored in the bank 0 (SRAM) end address is continuously backed up by a predetermined byte (for example, 1 byte) in a second backup area 4150dc. Are all copied in order from the top address of Bank 4 (SRAM).

  Subsequent to step S1034, a WDT clear process is performed (step S1036). In this WDT clear process, a clear signal is output to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e so that the peripheral control MPU 4150a is not reset.

  Subsequent to step S1036, the effect control program sets the value 0 in the steady processing flag SP-FLG as completion of execution of the peripheral control unit steady processing (step S1038), returns to step S1006 again, and V blank signal detection flag VB -FLG is initialized by setting value 0, and the determination in step S1008 is repeated until value 1 is set in V blank signal detection flag VB-FLG in the peripheral control unit V blank signal interrupt processing described later. That is, in step S1008, the process waits until the value 1 is set in the V blank signal detection flag VB-FLG. The process of S1038 is performed, and the process returns to step S1006 again. As described above, when it is determined in step S1008 that the V blank signal detection flag VB-FLG has a value of 1, processing in steps S1009 to S1038 is performed. The processing in steps S1009 to S1038 is referred to as “peripheral control unit steady processing”.

  The peripheral control unit steady process starts from the fact that the effect control program first sets the value 1 in the steady processing flag SP-FLG, assuming that the peripheral control unit steady process is being executed in step S1009, and 1 ms in step S1010. An interrupt timer activation process is performed, and each process of steps S1012, S1014,..., And step S1036 is performed. Set to to complete. The peripheral control unit steady process is executed when the V blank signal detection flag VB-FLG is 1 in step S1008. As described above, the V blank signal detection flag VB-FLG is executed when the V blank signal indicating that the screen data from the peripheral control MPU 4150a can be accepted is input from the sound source built-in VDP 4160a. The value 1 is set in the peripheral control unit V blank signal interrupt processing described later. In this embodiment, since the frame frequency (number of screen updates per second) of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 246 is set to approximately 30 fps per second as described above, V The interval at which the blank signal is input is approximately 33.3 ms (= 1000 ms ÷ 30 fps). That is, the peripheral control unit steady process is repeatedly executed about every 33.3 ms.

[5-1-2. Peripheral control unit V blank signal interrupt processing]
Next, a V blank signal indicating that the screen data from the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 7 can be received is input from the liquid crystal and sound source built-in VDP 4160a of the sound control unit 4160. The peripheral control unit V blank signal interrupt processing executed with this as an opportunity will be described. When the peripheral control unit V blank signal interrupt process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 determines whether the steady processing flag SP-FLG is 0 as shown in FIG. S1045). As described above, the steady processing flag SP-FLG has a value of 1 when the peripheral control unit steady processing in steps S1009 to S1038 in the peripheral control unit power-on processing of FIG. It is set to a value of 0 when execution of the process is completed.

  If the steady process flag SP-FLG is not 0 (value 1) in step S1045, that is, if the peripheral control unit steady process is being executed, this routine is terminated. On the other hand, when the steady processing flag SP-FLG is 0 in step S1045, that is, when the execution of the peripheral control unit steady processing is completed, the value 1 is set to the V blank signal detection flag VB-FLG (step S1050). This routine ends. As described above, the V blank signal detection flag VB-FLG is a flag for determining whether or not to execute the peripheral control unit steady process. When the part steady process is not executed, the value is set to 0.

  In this embodiment, it is determined in step S1045 whether or not the steady processing flag SP-FLG is 0, that is, whether or not the peripheral control unit steady processing has been completed, and the peripheral control unit steady processing has been completed. Sometimes the value 1 is set to the V blank signal detection flag VB-FLG in step S1050. This is because the V blank signal is input and the V blank signal is input when the peripheral control unit steady processing is being executed. When the value 1 is set to the signal detection flag VB-FLG, it is assumed that the peripheral control unit steady process is executed in step S1008 in the peripheral control unit power-on process of FIG. Since the peripheral control unit steady process is started from the beginning by forcibly canceling on the way, the peripheral control unit in FIG. 15 is turned on for the purpose of preventing this. The peripheral control unit V blank signal, which is this routine, indicates that the peripheral control unit steady processing is being executed by setting the value 1 to the steady processing flag SP-FLG in step S1009 in the processing (peripheral control unit steady processing). In addition to notifying the interrupt processing, the peripheral control unit steady state processing is completed by setting the steady processing flag SP-FLG to 0 in step S1038 in the peripheral control unit power-on processing (peripheral control unit steady state processing) of FIG. This is communicated to the peripheral control unit V blank signal interrupt process, which is this routine, so that the steady processing flag SP-FLG is 0 in the determination of step S1045 in the peripheral control unit V blank signal interrupt process, which is this routine. It is determined whether or not there is, that is, whether or not the peripheral control unit steady process has been executed. In other words, this is a measure for when the peripheral control unit steady process cannot be completed before the next V blank signal is input and the next V blank signal is input, so-called process failure.

  As a result, in the current peripheral control unit steady process, if the process cannot be completed in about 33.3 ms and the process is dropped, the next determination is made in step S1008 in the peripheral control unit power-on process of FIG. It is in a state of waiting until the V blank signal is input. That is, the time required to execute the current peripheral control unit steady process that has been dropped is about 66.6 ms. Normally, a peripheral control unit 1 ms timer interrupt process, which will be described later, is repeatedly executed every time a 1 ms interrupt timer is generated by starting the 1 ms interrupt timer in step S1010 in the peripheral control unit power-on process (peripheral control unit steady process) in FIG. Is executed only 32 times for one peripheral control unit steady process. However, if there is a current peripheral control unit steady process that has been dropped as described above, the peripheral control unit 1 ms timer interrupt process is not performed 64 times. No, it is executed only 32 times. In other words, even if the peripheral control unit steady process has failed, the consistency between the presentation progress state by the peripheral control unit steady process and the presentation progress state by the peripheral control unit 1 ms timer interrupt process, which is timer interrupt control, is consistent. It is designed not to collapse. Therefore, even if the peripheral control unit steady process is lost, the progress state of the performance can be reliably matched.

[5-1-3. Peripheral control unit 1ms timer interrupt processing]
Next, the peripheral control unit 1 ms timer interrupt process that is repeatedly executed every time the 1 ms interrupt timer is generated by starting the 1 ms interrupt timer in step S1010 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. 15 will be described. . When the peripheral control unit 1 ms timer interrupt process is started, the peripheral control unit 4150 shown in FIG. 7 performs the 1 ms timer interrupt execution count STN as shown in FIG. 17 under the control of the peripheral control MPU 4150a. Is less than 33 times (step S1100). As described above, the 1 ms timer interrupt execution count STN is determined by this routine when the 1 ms interrupt timer is activated in the 1 ms interrupt timer activation process in step S1010 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. It is a counter that counts the number of times a peripheral control unit 1 ms timer interrupt process is executed. In this embodiment, since the frame frequency (number of screen updates per second) of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 246 is set to approximately 30 fps per second as described above, V The interval at which the blank signal is input is approximately 33.3 ms (= 1000 ms ÷ 30 fps). That is, since the peripheral control unit steady process is repeatedly executed about every 33.3 ms, after starting the 1 ms interrupt timer in step S1010 in the peripheral control unit steady process, the next peripheral control unit steady process is performed. The peripheral control unit 1 ms timer interrupt process is executed only 32 times before. Specifically, when the 1 ms interrupt timer is started in step S1010 in the peripheral control unit steady process, the first 1 ms timer interrupt is generated first, then the second,... Will occur.

  When the 1 ms timer interrupt execution count STN is not smaller than 33 times in step S1100, that is, when the 1 ms timer interrupt for the 33rd time is generated and the peripheral control unit 1 ms timer interrupt processing is started, the effect control program is directly executed by this routine. Exit. In the present embodiment, when the 33rd 1 ms timer interrupt occurs accidentally before the next generation of the V blank signal, in the present embodiment, the peripheral control unit 1 ms timer interrupt process is the peripheral control unit V as the priority of interrupt processing. Although set higher than the blank interrupt process, the start of the peripheral control unit 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. In other words, in the present embodiment, the V blank signal is a signal that dominates the entire system of the peripheral control board 4140. Therefore, when the occurrence of the 1st timer interrupt for the 33rd time happens to precede the generation of the next V blank signal. In order to execute the peripheral control unit V blank interrupt process, the start of the peripheral control unit 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. Then, after the 1 ms interrupt timer is started again in step S1010 in the peripheral control unit steady process due to the generation of the V blank signal, the peripheral control unit 1 ms timer interrupt process is newly started by the first 1 ms timer interrupt generation. ing.

  On the other hand, when the 1 ms timer interrupt execution count STN is smaller than 33 in step S1100, the value 1 is added to the 1 ms timer interrupt execution count STN (increment, step S1102). By adding 1 to the 1 ms timer interrupt execution count STN, the 1 ms interrupt timer is activated in the 1 ms interrupt timer activation process of step S1010 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. The number of times that the peripheral control unit 1 ms timer interrupt process, which is this routine, is executed is increased by one.

  Subsequent to step S1102, the effect control program performs motor and solenoid drive processing (step S1104). In this motor and solenoid drive processing, the electric drive source schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. 8 is arranged in time series. In accordance with the drive data indicated by the pointer among the drive data of the electrical drive sources such as the motor and the solenoid, the effect control program determines the electrical drive sources such as the motor and the solenoid of the frame decoration drive amplifier board 194 and the motor drive board 4180. While driving, the pointer is updated to the next drive data defined in time series, and the pointer is updated every time the motor and solenoid drive processing is executed.

  Specifically, in the motor and solenoid drive processing, the effect control program performs DMA serial continuous transmission processing to the frame decoration drive amplifier board 194. Here, the effect control program uses the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a to continuously transmit the frame decoration drive amplifier board motor serial I / O port. When this frame decoration drive amplifier board motor serial I / O port continuous transmission starts, first, the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the externally attached peripheral control RAM 4150c is stored. A drive signal to the dial drive motor 414 of the operation unit 400 shown in FIG. 7 based on drive data indicated by a pointer among drive data of electric drive sources such as motors and solenoids arranged in time series. 8 is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and the peripheral control RAM 4150c shown in FIG. Frame decoration Set in the transmission data storage area 4150caf amplifier substrate side motor. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates transmission of the frame decoration drive amplifier board motor serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and stores frame decoration drive amplifier board side motor transmission data. Frame decoration drive amplifier board motor via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai with the first byte of the door side motor drive data STM-DAT stored in the head address of the area 4150caf Transfer and write to the transmission buffer register of the serial I / O port. As a result, the frame decoration drive amplifier board motor serial I / O port transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the door side motor drive clock signal STM-CLK. The 1-byte data starts to be transmitted bit by bit.

  The peripheral control DMA controller 4150ac is triggered every time a transmission interrupt request for the frame decoration drive amplifier board motor serial I / O port is generated (in this embodiment, the frame decoration drive amplifier board motor serial I / O 1 byte data written in the transmission buffer register of the port is transferred to the transmission shift register, and the transmission buffer register is empty because the 1 byte data disappears.), Peripheral control CPU core 4150aa When the bus does not use the bus, the remaining door side motor drive data STM-DAT stored in the frame decoration drive amplifier board side motor transmission data storage area 4150caf is stored byte by byte, external bus 4150h, peripheral control bus controller 4150ad, and via peripheral bus 4150ai, By transferring and writing to the transmission buffer register of the decorative drive amplifier board motor serial I / O port, the frame decoration drive amplifier board motor serial I / O port transmits the data of the written transmission buffer register to the transmission shift register. 1 byte data of the transmission shift register is started bit by bit in synchronization with the door side motor drive clock signal STM-CLK, and the frame decoration drive amplifier board motor serial I / O port continuously transmits. Is going.

  In the motor and solenoid drive processing, DMA serial continuous transmission processing to the motor drive board 4180 is performed. Also here, serial transmission of the motor drive board serial I / O port is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. When the serial I / O port continuous transmission for the motor drive board is started, first, when configuring the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the peripheral control RAM 4150c attached externally Drive to motors and solenoids for moving various movable bodies provided in the game board 4 based on drive data indicated by the pointer among drive data of electric drive sources such as motors and solenoids arranged in series The game board side motor drive data SM-DAT for outputting signals is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c, and the peripherals shown in FIG. Motor drive of control RAM 4150c Set on the substrate side transmission data storage area 4150Cag. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates transmission of the motor drive board serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and stores it in the head address of the motor drive board side transmission data storage area 4150cag. The first 1 byte of the game board side motor drive data SM-DAT thus obtained is transmitted to the serial I / O port for the motor drive board via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer and write to register. As a result, the serial I / O port for the motor drive board transfers the written data of the transmission buffer register to the transmission shift register, and 1 of the transmission shift register is synchronized with the game board side motor drive clock signal SM-CLK. Start transmitting byte data bit by bit.

  The peripheral control DMA controller 4150ac is triggered by the transmission interrupt request for the motor drive board serial I / O port (in this embodiment, in the transmission buffer register of the motor drive board serial I / O port). The written 1-byte data is transferred to the transmission shift register, and the transmission buffer register is empty because the 1-byte data disappears.), The peripheral control CPU core 4150aa is using the bus. If not, the remaining game board side motor drive data SM-DAT stored in the motor drive board side transmission data storage area 4150cag is transferred byte by byte via the external bus 4150h, peripheral control bus controller 4150ad, and peripheral bus 4150ai. , Serial I / O port for motor drive board By transferring and writing to the transmission buffer register, the motor drive board serial I / O port transfers the written data of the transmission buffer register to the transmission shift register, and the game board side motor drive clock signal SM-CLK and Synchronously, transmission of 1-byte data of the transmission shift register is started bit by bit, and continuous transmission is performed by the serial I / O port for the motor drive board.

  Following step S1104, movable body information acquisition processing is performed (step S1106). In this movable body information acquisition process, it is determined whether or not detection signals from various detection switches provided on the game board 4 are input, thereby history information (for example, original position history information) of detection signals from the various detection switches. , Movable position history information, etc.) is created and set in the movable body information acquisition storage area 4150cah of the peripheral control MPU 4150a and the peripheral control RAM 4150c externally shown in FIG. From the history information of the detection signals from the various detection switches set in the movable body information acquisition storage area 4150cah, the original positions and the movable positions of the various movable bodies provided on the game board 4 can be acquired.

  Subsequent to step S1106, an operation unit information acquisition process is performed (step S1108). In this operation unit information acquisition process, it is determined whether or not detection signals from various detection switches provided in the operation unit 400 are input, whereby history information of detection signals from various detection switches (for example, a dial operation unit) Rotation (rotation direction) history information 401, operation history information of the pressing operation unit 405, etc.) is created, and the operation unit information acquisition storage area of the peripheral control MPU 4150a and the externally attached peripheral control RAM 4150c shown in FIG. Set to 4150cai. The rotation direction of the dial operation unit 401 and the presence / absence of the operation of the pressing operation unit 405 can be acquired from the history information of detection signals from various detection switches set in the operation unit information acquisition storage area 4150cai.

  Subsequent to step S1108, the effect control program performs a drawing state acquisition process (S1110) and a main prize ball number information output process (S1112), and subsequently performs a backup process (step S1114), and ends this routine. In this backup processing, the contents stored in the peripheral control MPU 4150a and the externally attached peripheral control RAM 4150c shown in FIG. 8 are copied to the backup first area 4150cb and the backup second area 4150cc for backup. At the same time, the contents stored in the peripheral control MPU 4150a and the externally attached peripheral control SRAM 4150d are copied to the backup first area 4150db and the backup second area 4150dc for backup.

  More specifically, in the backup process, the peripheral control RAM 4150c performs the peripheral control unit 1ms timer interrupt process, which is this routine, every time the 1ms interrupt timer is generated in the backup management target work area 4150ca shown in FIG. Each time it is executed, frame decoration drive amplifier board side motor transmission data storage area 4150caf, motor drive board side transmission data storage area 4150cag, movable body information acquisition storage area included in Bank 0 (1 ms) to be backed up Production information (1 ms), which is the content stored in 4150 cah and the operation unit information acquisition storage area 4150 cai, is used as production backup information (1 ms), and Bank 1 (1 ms) and Bank 2 (in the backup first area 4150 cb) Peripheral control DMA controller 4150ac in ms) is copied at high speed, and backup Bank3 second area 4150cc (1ms) and Bank4 (1 ms) to the peripheral control DMA controller 4150ac copies at high speed.

  The high-speed copy of the contents stored in Bank 0 (1 ms) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a shown in FIG. The content stored in Bank0 (1 ms) is designated to be copied to Bank1 (1 ms) in backup first area 4150cb, and the content stored at the beginning address of Bank0 (1 ms) is changed to the end address of Bank0 (1 ms). The stored contents are all copied in sequence starting from the first address of Bank 1 (1 ms) in the backup first area 4150cb in succession by a predetermined number of bytes (for example, 1 byte), and the peripheral control CPU core 4150aa performs the peripheral control DM. The contents stored in Bank0 (1 ms) as the request factor of the controller 4150ac are designated to be copied to Bank2 (1 ms) in the backup first area 4150cb, and the contents stored in the first address of Bank0 (1ms) are used to determine Bank0 ( The contents stored at the end address of 1 ms) are all copied in order from the first address of Bank 2 (1 ms) in the backup first area 4150cb in succession by a predetermined number of bytes (for example, 1 byte).

  Subsequently, the peripheral control CPU core 4150aa designates the contents stored in Bank0 (1 ms) as the request factor of the peripheral control DMA controller 4150ac, specifies the copy of the backup second area 4150cc to Bank3 (1 ms), and Bank0 (1 ms) ) To the content stored at the end address of Bank 0 (1 ms) from the content stored at the head address of) in the backup second area 4150 cc of bank 3 (1 ms) The peripheral control CPU core 4150aa specifies the contents stored in Bank0 (1ms) as the request factor of the peripheral control DMA controller 4150ac, and specifies that the backup second area 4150cc is copied to Bank4 (1ms). Shi From the content stored at the beginning address of Bank0 (1 ms) to the content stored at the end address of Bank0 (1 ms), bank 4 (1 ms) in the backup second area 4150 cc continuously by a predetermined byte (for example, 1 byte) Copy everything starting from the first address.

  As described above, in the peripheral control unit 1 ms timer interruption process, various processes related to the effects in steps S1104 to S1108 are executed as the progress of the effects within a period of 1 ms. On the other hand, in the peripheral control unit steady process in the power-on process of the peripheral control unit in FIG. 15, various processes related to the effects in steps S1012 to S1032 described above are performed as the progress of effects within a period of about 33.3 ms. doing. In the peripheral control unit 1 ms timer interrupt process, when the 1 ms timer interrupt execution count STN is not smaller than the value 33 in step S1100, that is, when the first 1 ms timer interrupt is generated and the peripheral control unit 1 ms timer interrupt process is started. Since this routine is ended as it is, even if the occurrence of the 33rd 1 ms timer interrupt happens to happen before the next V blank signal, the peripheral control unit by this 33rd 1 ms timer interrupt. The start of the 1 ms timer interrupt process is forcibly canceled, and after the 1 ms interrupt timer is started again in step S1010 in the peripheral control unit steady process due to the generation of the V blank signal, the peripheral control is newly performed by the first 1 ms timer interrupt. 1ms timer division It is adapted to start the actual processing. That is, the consistency between the progress state of the effect by the peripheral control unit steady process and the progress state of the effect by the peripheral control unit 1 ms timer interrupt process which is the timer interrupt control is not lost. Therefore, it is possible to reliably match the progress of the production.

  Further, as described above, the interval at which the V blank signal is output varies somewhat depending on the liquid crystal sizes of the game board side liquid crystal display device 1900 and the upper plate side liquid crystal display device 246, and the peripheral control MPU 4150a and the sound source built-in VDP 4160a Even in the manufacturing lot of the mounted peripheral control board 4140, the interval at which the V blank signal is output may change somewhat. In this embodiment, since the V blank signal is a signal that dominates the entire system of the peripheral control board 4140, if the occurrence of the first 1 ms timer interrupt happens to precede the next generation of the V blank signal, the peripheral control is performed. In order to execute the part V blank interrupt process, the start of the peripheral control part 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. In other words, in the present embodiment, even if the interval at which the V blank signal is output changes slightly, by forcibly canceling the start of the peripheral control unit 1 ms timer interrupt process by the 33rd 1 ms timer interrupt, A time shift due to a slight change in the interval at which the V blank signal is output can be absorbed.

[5-1-4. Peripheral control unit command reception interrupt processing]
Next, the peripheral control unit command reception interrupt process for receiving various commands from the main control board 4100 will be described. The peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 7 starts the transmission of various commands from the main control board 4100 as serial data, and this causes the main peripheral serial data to be built into the peripheral control MPU 4150a. One byte (8 bits) of information is taken into the reception buffer at the board serial I / O port, and when this fetching is completed, an interrupt is generated as a trigger, and peripheral control unit command reception interrupt processing is performed. The main circumference serial data is composed of 3 bytes per packet, the status is assigned as the first byte, the mode is assigned as the second byte, and the status and mode are regarded as numerical values as the third byte and the total The sum value that is calculated is assigned.

  When the peripheral control unit command reception interrupt process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 determines whether or not the 1-byte reception period timer has timed out as shown in FIG. 7 (step S1200). The 1-byte reception period timer sets a period during which 1-byte (8-bit) information can be received from the main peripheral serial data transmitted from the main control board 4100.

  When the 1-byte reception period timer has not timed out in step S1200, that is, when it is within a period in which 1-byte (8-bit) information can be received from the main peripheral serial data transmitted from the main control board 4100, the peripheral The 1-byte information received from the reception buffer of the main I / O port for the main control board built in the control MPU 4150a is fetched (step S1202), and the value 1 is added to the reception counter SRXC (increment, step S1204). This reception counter SRXC is a counter indicating the number of times the data has been extracted from the reception buffer. When the status, which is the first byte of the main peripheral serial data, is extracted from the reception buffer, the value is 1, and the mode is the second byte of the main peripheral serial data. The value is 2 when extracted from the reception buffer, and the value is 3 when the sum value, which is the third byte of the main serial data, is extracted from the reception buffer. The reception counter SRXC is set to an initial value 0 when the power is turned on.

  Subsequent to step S1204, it is determined whether or not the reception counter SRXC has a value of 3, that is, whether or not the sum value that is the third byte of the main peripheral serial data has been extracted from the reception buffer (step S1206). In this determination, following the status that is the first byte of the main peripheral serial data, the mode that is the second byte of the main peripheral serial data and the sum value that is the third byte of the main peripheral serial data are sequentially received from the reception buffer. It is determined whether or not it has been taken out.

  When the reception counter SRXC is not 3 in step S1206, that is, following the status that is the first byte of the main peripheral serial data, the mode that is still the second byte of the main peripheral serial data, and the third byte of the main peripheral serial data When the sum values are not sequentially taken out from the reception buffer, the 1-byte reception period timer is set (step S1208), and this routine is terminated. By setting the 1-byte reception period timer in step S1208, the mode that is the second byte of the main circumference serial data or the period during which the sum value that is the third byte of the main circumference serial data can be received is set.

  On the other hand, when the reception counter SRXC has a value of 3 in step S1206, that is, following the status that is the first byte of the main peripheral serial data, the mode that is the second byte of the main peripheral serial data, and the main peripheral serial data 3 When the sum value which is the byte is taken out from the reception buffer in order, the initial value 0 is set in the reception counter SRXC (step S1210), and the sum value is calculated (step S1212). In this calculation, the status that is the first byte of the main circumference serial data and the mode that is the second byte of the main circumference serial data, which have already been extracted from the reception buffer in step S1202, are regarded as numerical values and the sum (sum value). ) Is calculated.

  Subsequent to step S1212, it is determined whether or not the sum value, which is the third byte of the main serial data already extracted from the reception buffer in step S1202, matches the sum value calculated in step S1212 (step S1212). S1214). The sum value that is the third byte of the main circumference serial data already extracted from the reception buffer in step S1202 is the sum value allocated as the third byte of the main circumference serial data from the main circumference serial data from the main control board 4100. Therefore, it should match the sum value calculated in step S1212. However, the pachinko gaming machine 1 is supplied with game balls from the pachinko island facility, and when the game balls rub against each other and are charged, electrostatic discharge is generated to generate noise, so the pachinko gaming machine 1 is affected by noise. The environment is susceptible. Therefore, in this embodiment, the peripheral controller 4150 side regards the status assigned as the first byte of the received main circumference serial data and the mode assigned as the second byte of the main circumference serial data as numerical values. The sum (sum value) is calculated, and the calculated sum value matches the sum value allocated as the third byte of the main circumference serial data among the main circumference serial data from the main control board 4100. It is determined whether or not. As a result, the peripheral control MPU 4150a determines whether or not the main peripheral serial data is changed to the main peripheral serial data different from the normal due to the influence of noise between the main control board 4100 and the peripheral control board 4140. be able to.

  In step S1214, if the sum value that is the third byte of the main circumference serial data already extracted from the reception buffer in step S1202 matches the sum value calculated in step S1212, the received main circumference serial data is received. 8 shows the status allocated as the first byte and the mode allocated as the second byte of the main peripheral serial data, as shown in FIG. (Step S1216), and this routine is terminated. The reception command storage area 4150cac is used as a ring buffer, and the status allocated as the first byte of the main circumference serial data and the mode allocated as the second byte of the main circumference serial data are: It is stored in the peripheral control unit reception ring buffer of 4150cac. This "peripheral control unit reception ring buffer" is a buffer that is used so that the end and the top of the buffer are connected. Data is sequentially stored from the beginning of the buffer, and when it reaches the end of the buffer, it returns to the beginning. Remember. When storing the peripheral control MPU 4150a in the peripheral control unit reception ring buffer in step S1216, the peripheral control MPU 4150a is allocated as the received status of the main peripheral serial data as the first byte and the main peripheral serial data as the second byte. Are stored in association with each other, and the sum value allocated as the third byte is discarded.

  On the other hand, when the 1-byte reception period timer has not timed out in step S1200, that is, it exceeds the period in which 1-byte (8-bit) information can be received from the main peripheral serial data transmitted from the main control board 4100. Sometimes, or in step S1214, if the sum value that is the third byte of the main peripheral serial data already extracted from the reception buffer in step S1202 and the sum value calculated in step S1212 do not match, this routine is directly executed. finish.

[5-2. Processing by graphic chip (VDP with built-in sound source)]
Next, processing by the graphic chip (VDP 4160a with built-in sound source) will be described with reference to FIGS. 6 and 7 as appropriate. In general, the peripheral control board 4140 receives a command output from the main control board 4100, and causes the liquid crystal display device 1900 to display the decorative design in a variable manner over the change time of the special design in accordance with the received command. After that, it has a function of displaying a decoration stop symbol corresponding to the result of the big hit lottery.

[5-2-1. Control data]
In this embodiment, the liquid crystal and sound control unit 4160 can store the above-described image data (material image data), the liquid crystal and sound control ROM 4160b (video data storage unit), the sound source built-in VDP 4160a, and the peripheral for controlling the sound source built-in VDP 4160a. A control MPU 4150a (control unit) and a frame buffer with a built-in sound source VDP 4160a are provided. Further, the liquid crystal and sound control ROM 4160b stores in advance a plurality of control data including attribute information for controlling each of the plurality of non-video effect execution units in a specific manner.

  FIG. 19A is a diagram showing an example of the storage state of the control data strings 2635A, 2635B, and 2635C prepared in advance in the liquid crystal and sound control ROM 4160b as described above. In the liquid crystal and sound control ROM 4160b, schedule data (corresponding to schedule data for non-video to be described later) including these control data strings 2635A, 2635B, and 2635C is provided separately from the schedule data for video display that defines the display order of frames. Stored. Control data strings 2635A, 2635B, and 2635C are stored in advance in the liquid crystal and sound control ROM 4160b in a compressed state using the following specific compression method. It is decompressed when read by the built-in VDP 4160a.

  The control data strings 2635A, 2635B, and 2635C are stored as a single combination for each frame, for example, in a state of being arranged in time series along the rendering time t. In this embodiment, the aggregate of the control data sequences 2635A, 2635B, and 2635C arranged in time series along the production time t is also collectively referred to as “non-video schedule data”. Since these control data strings 2635A, 2635B, and 2635C have the same data size, when the head address of the control data string 2635A is designated, the built-in sound source VDP 4160a easily specifies the storage positions of the remaining control data strings 2635B and 2632C. can do.

  FIG. 19B illustrates an example of a data format indicating details of the control data string 2635A illustrated in FIG. As shown in FIG. 19B, the control data string 2635A includes, for example, a 2-bit type code, 24-bit (3-byte) first control data, second control data, third control data,. 100th control data is included.

  As the above-described 2-bit type code, for example, “00” is set for light output control using a lamp or LED, and “01” is set for sound control using a speaker. “10” is set for the accessory control using the motor.

  On the other hand, when the type code is “00 (light output control)”, the 24-bit control data is, for example, attribute information for defining the light luminance, the duty ratio, etc. of each pixel. Can be mentioned. Specifically, for example, when the control target is an LED, each control data is red (8 bits: 1 byte), green (8 bits: 1 byte), and blue (8 bits: 8 bits: depending on the three primary colors of light. 1 dot) is data for outputting one dot composed of three pixels as light of a specific mode. That is, each control data is used as attribute information for driving each corresponding LED in a desired mode, for example, a mode of luminance and duty ratio.

  When the type code is “01 (sound output control)”, the 24-bit control data includes, for example, a 16-bit frequency for designating sound frequencies covering the audible range (approximately 20 to 20000 Hz). A designation portion and an 8-bit amplitude designation portion for designating the amplitude of sound in 256 levels are included.

  When the type code is “10 (motor control)”, as the 24-bit control data, for example, if the motor to be controlled is a four-phase stepping motor, it corresponds to four values for every 6 bits. Excitation current over energization time is given to each phase.

  Here, in FIG. 7 described above, the liquid crystal and sound control unit 4160 employs a configuration independent of the peripheral control unit 4150. The function of the liquid crystal and sound control unit 4160 is the peripheral control board 4140 (effect control). Part).

  In the peripheral control board 4140, a correspondence management table 2611 is stored in advance in the peripheral control ROM 4150b. This correspondence management table 2611 can be referenced not only from the peripheral control MPU 4150a of the peripheral control board 4140 but also from the built-in sound source VDP 4160a. The correspondence management table 2611 may be stored in the built-in ROM of the peripheral control MPU 4150a of the liquid crystal and sound control unit 4160.

  The sound source built-in VDP 4160a (production image forming unit) generates frame data used for frame display using the material image data read from the liquid crystal and the sound control ROM 4160b in the order according to the video display schedule data. In addition, a plurality of pixel data are generated as described later based on a plurality of controls included in a plurality of control data strings read from the sound control ROM 4160b.

  FIG. 20 shows a configuration example of the storage area of the frame buffer. As shown in FIG. 20, the frame buffer includes a display area storage area 2631 and a display area storage area 2632. The display area storage area 2631 is a storage area for storing the frame data generated by the sound source built-in VDP 4160a. On the other hand, the storage area outside display area 2632 is a storage area for storing a plurality of pixel data generated by the sound source built-in VDP 4160a. In addition, the storage area outside display area 2632 includes a specific number of pixel areas corresponding to the number of non-video effect execution units.

  In the storage area 2632 outside the display area, for example, control for controlling the number of types of non-video effect execution units (in this embodiment, for example, three types of lamps, LEDs, speakers, and motors) in a specific manner. Storage areas for storing data strings 2635A, 2635B, and 2635C are formed. In this embodiment, for example, the control data string 2635A is used for lamp or LED control, the control data string 2635B is used for speaker control, and the control data string 2635C is set for a motor.

  Control data string 2635A stores control data for controlling the lamp or LED group, control data string 2635B stores control data for controlling the speaker, and control data string 2635C stores the speaker. Control data for controlling is stored.

  FIG. 21 is a diagram showing an example of the contents of the correspondence management table 2611. As shown in FIG. This correspondence management table 2611 is stored in advance in the built-in ROM of the peripheral control MPU 4150a of the liquid crystal and sound control unit 4160, for example. The sound source built-in VDP 4160a stores the generated frame data in the display area storage area 2631 while the generated pixel data is stored in the storage area 2632 outside the display area specified based on the correspondence management table 2611. Store in the pixel area.

  In the correspondence management table 2611, the type of the non-video effect execution unit described above is distinguished and managed by the type code. In the present embodiment, since a plurality of non-video effect execution units of the same type are provided, the plurality of non-video effect execution units of the same type are each managed with a system number as an independent system. Has been.

  In the present embodiment, for example, since 100 lamps or LEDs corresponding to the type code “00” are mounted, there are 100 systems. In the correspondence management table 2611, a plurality of the same type System numbers of “1” to “100” are assigned to the non-video effect execution unit. The pixel area numbers of the pixel areas corresponding to these system numbers are “A-1” to “A-100”. These pixel area numbers correspond to the pixel area numbers A-1 to A-100 shown in FIG.

  Since there are four speakers corresponding to the type code “01”, there are four systems. In the correspondence management table 2611, the plurality of non-video effect execution units of the same type include: System numbers “1” to “4” are assigned. The pixel area numbers of the respective pixel areas corresponding to these system numbers are “B-1” to “B-4”. Here, the pixel areas corresponding to the pixel area numbers “B-5” to “B-100” are not used because there is no speaker to be controlled. In this case, the speaker is activated. Stores data to prevent this from happening. These pixel area numbers correspond to the pixel area numbers B-1 to B-100 shown in FIG.

  Since 30 motors corresponding to the type code “10” are mounted, there are 30 systems, and the correspondence management table 2611 includes a plurality of non-video effect execution units of the same type. System numbers “1” to “30” are assigned. The pixel area numbers of the respective pixel areas corresponding to these system numbers are “C-1” to “C-30”. Here, the pixel areas corresponding to the pixel area numbers “C-31” to “C-100” are not used because there is no motor to be controlled. In this case, each of the motor areas Stores data to prevent excitation of phases. These pixel area numbers correspond to the pixel area numbers C-1 to C-100 shown in FIG.

[5-2-2. Control data extraction process]
FIG. 22 is a flowchart illustrating an example of the control data extraction process. In the control data extraction process, the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160 extracts each control data for each type code from the control data sequence 2635A, 2635B, 2635C. The sound source built-in VDP 4160a executes this control data extraction process together with the normal display data creation process (S1030) liquid crystal display control process as part of the timer interrupt process executed approximately every 33 ms.

  First, the sound source built-in VDP 4160a checks whether or not an extraction instruction command from the peripheral control board 4140 is stored in a command buffer (not shown) (step S1301). If no extraction instruction command is stored in the command buffer, the built-in tone generator VDP 4160a ends the control data extraction process and executes the above-described timer interrupt process.

  On the other hand, when the extraction instruction command is stored in the command buffer, the built-in sound source VDP 4160a initializes the type number variable m as the variable of the number of types of the plurality of non-video effect execution units and sets it to “0”. (Step S1302).

  Next, when the sound source built-in VDP 4160a reads the drawing data (corresponding to the video effect data) for one frame from the storage area 2631 in the display area of the frame buffer, the storage area outside the display area corresponding to the same frame at the same time. All the control data strings 2635A, 2635B,. 2835C is extracted (step S1303).

  First, the sound source built-in VDP 4160a adds “1” to the current type number variable m (here “0”) (step S1304), and sets the type type variable m to “1”. Next, the sound source built-in VDP 4160a acquires the type of the m-th (here, the first) control data string 2635A in the same frame (step S1305). After that, the sound source built-in VDP 4160a extracts 100 pieces of control data of the control data string 2635A (step S1306), from the first control data (first system) to the last control data (100th system). , “1” to “100” are assigned as system numbers.

  Next, the built-in sound source VDP 4160a refers to the correspondence management table 2611 and identifies each pixel area number corresponding to each system related to the control data string 2635A. Here, in the present embodiment, as shown in FIG. 20, each of the pixel areas A-1 to A-100 is formed for the control data string 2635A in the non-display target storage area 2632 of the frame buffer. The pixel areas B-1 to B-100 are formed for the control data string 2635B, and the pixel areas C-1 to C-100 are formed for the control data string 2635C. Therefore, the sound source built-in VDP 4160a can specify A-1 to A-100 as the pixel area numbers corresponding to the systems “1” to “100” with respect to the control data string 2635A. Finally, the sound source built-in VDP 4160a stores each control data of each system in each pixel area A-1 to A-100 (step S1308).

  Next, the built-in sound source VDP 4160a determines whether the type number variable m is 3 or more (step S1309). In this embodiment, whether or not the number of types is 3 or more is confirmed in this embodiment in that the types of the plurality of non-video effect execution units are three types of lamps, LEDs, speakers, and motors. This is because it is set to be. The built-in sound source VDP 4160a ends the control data extraction process when the type / type number variable m is 3 or more, and repeats the above-described steps S1305 to S1309 when the type / type number variable m is not 3 or more. Similarly, in the data strings 2635B and 2635C, the control data of each system is stored in the corresponding pixel areas B-1 to B-100 and the pixel areas C-1 to C-100.

  As described above, the built-in sound source VDP 4160a completes the storage of each control data in each pixel area in the same frame and completes the control pattern synthesis by associating each control data in each pixel area with the type code. The data is transferred to the peripheral control MPU 4150a of the control board 4140 and stored in a specific area of the RAM built in the peripheral control MPU 4150a.

[5-2-3. Production control processing]
This effect control process is a process executed as a part of the timer interruption process every 2 ms by the peripheral control MPU 4150a of the peripheral control board 4140.

  First, the peripheral control MPU 4150a determines whether or not it is currently in the production proxy mode. Next, if the peripheral control MPU 4150a determines that it is not currently in the production proxy mode, it ends the production control process. On the other hand, if it is currently in the production substitution mode, each control is performed for each type code from the specific area of the built-in RAM. Acquire data for the number of all systems (acquisition means).

  Next, the peripheral control MPU 4150a refers to a type code corresponding to each control data, and specifies a non-video effect execution unit as a control target corresponding to each type code (control unit).

  Next, the peripheral control MPU 4150a passes through the serial input / output port to at least one of the door frame decoration lamp 2624 and the LEDs 2020, 2122, and 2124 (a plurality of non-video effect execution units) of each system specified as described above. On the other hand, by outputting each corresponding control data instead of the lamp driving board command, at least one of the door frame decoration lamp 2624 and the LEDs 2020, 2122, and 2124 in each specific mode based on the attribute information included in each control data. One is driven (control means).

  At the same time, the peripheral control MPU 4150a outputs the corresponding control data to the control register of the sound source built-in VDP 4160a instead of the sound output command, and writes it to the sound source built-in VDP 4160a in the attribute information included in each control data. The speaker of each system is driven in each specific mode based on (control means).

  In step S1204, the peripheral control MPU 4150a of the peripheral control board 4140 outputs each control data to the motor drive board 4180 via the serial input / output port in place of a predetermined motor drive command, thereby converting the control data into each control data. A motor such as the door lower right drive motor 272 is driven in each specific mode based on the included attribute information (control means).

  In this way, the built-in sound source VDP 4160a generates a control pattern that should have been generated by the peripheral control MPU 4150a instead of the peripheral control MPU 4150a, and stores it in each pixel area of the storage area outside display area 2632 in the frame buffer. Storing. Here, the sound source built-in VDP 4160a is not particularly conscious, and when generating normal frame data (corresponding to the video effect data) in the drawing process, at the same time, at least one control data (non-video effect data). The control pattern including the equivalent) is generated.

  That is, since the sound source built-in VDP 4160a can generate a control pattern as if it is a simple drawing process by using the remaining power, the control pattern generation by the peripheral control MPU 4150a that should originally have generated this control pattern. Processing can be omitted. For this reason, the peripheral control MPU 4150a reduces the processing load for generating this control pattern. Therefore, in the peripheral control board 4140, since the peripheral control MPU 4150a can devote resources to other processes as much as the processing load is greatly reduced, more various effects can be realized.

  Moreover, the VDP 4160a with built-in sound source develops drawing data (corresponding to video effect data) for each frame used when displaying the same frame in the frame buffer, and at the same time, transmits the light from the decoration lamp or LED in the same frame. Since a control pattern including each control data for output control, sound output control by a speaker, and drive control for the center moving motor 2214 and the like is developed together, a special mechanism is required when performing these synchronous controls. Rather, the development period of the pachinko gaming machine 1 can be shortened compared to the case where a mechanism for synchronous control must be incorporated as in the prior art.

[5-2-4. Control data compression method]
By the way, in the conventional gaming machine, as the game progresses, a variety of images including a large number of material images are displayed, or light and sound are output using a lamp or a speaker to execute various effects. The player's interest is hardly exhausted (see Reference 1 above). In recent years, the data size of presentation control data used for controlling such various presentation operations has been increasing, and the capacity of a non-volatile memory such as a so-called character ROM has been under pressure.

  In view of this, the present embodiment employs a configuration as described later for the purpose of greatly reducing the data capacity of presentation control data for controlling regular presentation operations. First, at least the control data sequence 2635B (light output control data) of the control data sequences 2635A, 2635B, and 2635C described above is an output of light to be output to at least one lamp or LED (hereinafter, “lamp” is exemplified). Output mode information representing a mode is set repeatedly at least three times along the elapsed time. This output mode information corresponds to at least one of the control data strings 2635A, 2635B, and 2635C synchronized in each frame. In the present embodiment, for example, the control data string 2635B will be described. In this embodiment, the control data strings 2635A and 2635C have the same description as that of the control data string 2635B, and the same effect can be obtained even if they are processed as follows.

  The control data sequence 2635B (light output control data) having such a configuration is stored in advance in the peripheral control ROM 4150b (production control storage means). Using the “regularity” of the difference between temporally continuous output mode information among the output mode information, the data of the control data string 2635B with the original data size in a state where these at least three output mode information are compressed It is the aspect made smaller than the size. Hereinafter, first, a specific example of the contents of the control data string 2635B will be described.

  First, in the present embodiment, instead of assuming that the control data string 2635B is 24 bits and the lamps are 100 systems (100) as described above, for example, the control data string 2635B is 3 bits. A description will be given assuming that there are five lamps (five).

  In the present embodiment, for example, the light output mode of the five lamps based on the control data string 2635B as control data for controlling a specific effect using five lamps, An effect mode is assumed that changes evenly at a constant rate each time a predetermined period is displayed (in this embodiment, the light output from the lamp gradually decreases and darkens).

  For example, the control data sequence 2635B (type code 2633 is omitted) shown in FIG. 23 includes first control data to fifth control data (one output mode information) in the (N−1) th frame, the Nth frame, and the (N + 1) th frame, respectively. Equivalent). The first control data to the fifth control data for each frame define output modes of five types of lamps when each frame is displayed. For example, FIG. 23 shows a control data string 2635B (corresponding to one output mode information) that defines the output mode of light to be output from the five lamps when the N-1th frame is displayed. Represents.

  In the illustrated (N-1) th frame, when the control data string 2635B is represented by 3 bits, for example, the first control data “111 (luminance 7)” and the second control data “110 (luminance 6)” are displayed. Control data, third control data “100 (luminance 4)”, fourth control data “101 (luminance 5)”, and fifth control data “011 (luminance 3)” Is included. The first control data defines the light output mode by the first lamp among the five lamps, and the second control data defines the light output mode by the second lamp among the five lamps. In the third control data, the light output mode by the third lamp among the five lamps is defined, and the fourth control data is the light output by the fourth lamp among the five lamps. The output mode is defined, and the fifth control data defines the light output mode of the fifth lamp among the five lamps.

  In the illustrated Nth frame, when the control data string 2635B is expressed by 3 bits, for example, the first control data “110 (luminance 6: luminance difference“ −1 ”)” and “101 (luminance 5) : The second control data “luminance difference“ −1 ”)”, the third control data “011 (luminance 3)”, and the fourth control data “100 (luminance 4: luminance difference“ −1 ”)”. Control data and five types of control data called fifth control data “010 (luminance 2: luminance difference“ −1 ”)” are included. The first control data defines the light output mode by the first lamp among the five lamps, and the second control data defines the light output mode by the second lamp among the five lamps. In the third control data, the light output mode by the third lamp among the five lamps is defined, and the fourth control data is the light output by the fourth lamp among the five lamps. The output mode is defined, and the fifth control data defines the light output mode of the fifth lamp among the five lamps.

  In the illustrated (N + 1) th frame, when the control data string 2635B is represented by 3 bits, for example, the first control data “101 (luminance 5: luminance difference“ −1 ”)” and “100 (luminance 4) : Brightness difference “−1”) ”, third control data“ 010 (luminance 2: luminance difference “−1”) ”, and“ 011 (luminance 3: luminance difference “ -1 ")" and fifth control data "001 (luminance 1: luminance difference" -1 ")" are included. The first control data defines the light output mode by the first lamp among the five lamps, and the second control data defines the light output mode by the second lamp among the five lamps. In the third control data, the light output mode by the third lamp among the five lamps is defined, and the fourth control data is the light output by the fourth lamp among the five lamps. The output mode is defined, and the fifth control data defines the light output mode of the fifth lamp among the five lamps.

  As described above, in the present embodiment, for example, the light output mode of the five lamps based on the effect control data sequence 2635B for controlling a specific effect using five lamps is set to each frame. Since the regularity that the “difference” of the brightness of each lamp is equal to “−1” is held every time is displayed every predetermined period, it seems to change evenly at a constant rate. (In this embodiment, the light output from the lamp gradually decreases and darkens).

  In the present embodiment, since the control data string 2635B has a difference in luminance of light represented by the three first control data in each frame of “−1” (corresponding to the regularity), for example, in the N−1th frame. Only the first control data (“111”) and data configuration information (hereinafter also referred to as “compression control data string 2635B”) that the luminance difference is “−1” for the next two frames are stored in the peripheral control ROM 4150b. As a result, the first control data of the control data sequence 2635B is supposed to be 9 bits “111”, “110” “101” in the (N−1) th frame to the (N + 1) th frame, The data size is small information like the compression control data string 2635B. For this reason, the storage capacity of the peripheral control ROM 4150b in which such a compression control data string 2635B should be prepared in advance can be greatly suppressed. In addition, when the control data string 2635B is not 3 bits as in this example but 24 bits as described above, the larger the number of bits handled, the greater the suppression of the data size by such a compression method. I can plan.

[5-2-5. Control data expansion method]
On the other hand, in the peripheral control board 4140, the effect control program compresses at least three output mode information in, for example, the sound source built-in VDP 4160a (data control means) instead of the peripheral control MPU 4150a in the peripheral control ROM 4150b (effect control storage means). With respect to the control data sequence (light output control data) 2635B stored in the stored state (hereinafter also referred to as “compression control data sequence 2635B”), the “regularity” of the difference between the time-sequential output mode information is set. The decompression is performed by restoring the at least three output mode information.

  By the way, in the peripheral control board 4140, a regularity management table for managing the regularity of the difference of such output mode information is prepared in advance in the peripheral control ROM 4150b. In this regularity management table, for each identifier of each frame, the “regularity” of the difference between the output mode information represented by each control data string in a certain frame and the next output mode information represented by each control data string in the next frame Is managed. Therefore, when the effect control program searches this regularity management table using the identifier of the frame to be displayed as a search key, the “regularity” of the difference in the output mode information corresponding to this frame can be acquired.

  Specifically, when the presentation control program reads the compression control data string 2635B from the peripheral control ROM 4150b, the presentation control program uses the regularity managed for each frame in the regularity management table, for example, the (N-1) th. Based on the first control data “111” in the frame and the regularity that the luminance difference is “−1”, the first control data in the Nth frame is restored to “110”, and the N−1th The first control data in the frame can be restored to “101”.

  This effect control program, under the control of the peripheral control MPU 4150a, stores the sprite data (material image data) to be synchronized with each other in accordance with the schedule data in the sound source built-in VDP 4160a (drawing control means). Or read from the built-in RAM if it has already been developed in the built-in RAM (effect control storage means), and then each predetermined period from each sprite data read from the peripheral control ROM 4150b. Drawing data is generated and stored in the frame buffer, and a frame based on the drawing data stored in the frame buffer is repeatedly displayed on the game board side liquid crystal display device 1900 (display means) (frame control means).

  As described above, in the present embodiment, the effect control program is stored in the sound source built-in VDP 4160a under the control of the peripheral control MPU 4150a in a state where at least three pieces of output mode information are compressed in the peripheral control ROM 4150b as described above. The control data string 2635B (light output control data) is decompressed by restoring at least three pieces of output mode information as follows. In other words, the production control program is synchronized with each frame repeatedly displayed on the game board side liquid crystal display device 1900 (display means) as described above on the sound source built-in VDP 4160a under the control of the peripheral control MPU 4150a. The at least three pieces of output mode information are decompressed by using the “regularity” of the difference between the output mode information (data decompression control means).

  Further, on the peripheral control board 4140, the effect control program sends at least one light of each output mode corresponding to each of the restored three types of output mode information to the built-in sound source VDP 4160a under the control of the peripheral control MPU 4150a. The lamp (light output means) outputs light in synchronization with the generated frame (light output control means). In the peripheral control board 4140, the effect control program may cause the peripheral control MPU 4150a (data control means) to perform the same processing as described above.

  In this way, as an example of the effect control data for controlling the regular effect operation, for example, the data capacity of the control data string 2635B (light output control data) for regularly changing the light output mode is greatly increased. Can be reduced.

  In the above embodiment, as an effect mode using the compression / expansion method as described above, the output of the light from the lamp gradually decreases, causing the player to feel the darkness and giving a sense of tension. Although the mode has been illustrated, the present invention is not limited to this, and conversely, by setting the regularity of the difference between the output mode information corresponding to each frame to “+1”, the light output by the lamp is gradually increased, and the game You may apply to the production aspect which can raise a person's feelings and can have expectation. Of course, the same effect can be obtained even if the output of the sound is changed instead of the output of the light from the lamp.

[6. Restriction on reading of production information]
FIG. 24 is a block diagram of a peripheral control board for explaining a configuration for releasing the concealment of effect information based on an instruction from the peripheral control MPU 4150a in the present embodiment.

  The main control board 4100 transmits a command instructing the start of the production to the peripheral control board 4140. The command for instructing the start of the production is, for example, the special figure 1 synchronized production start command or the special figure 2 synchronized production start command shown in FIG.

  The peripheral control MPU 4150a of the peripheral control board 4140 obtains effect configuration information for executing the specified effect from the peripheral control ROM 4150b based on the command for instructing the start of the effect received from the main control board 4100. The effect composition information includes, for example, schedule data for each scene in the effect. After that, the peripheral control MPU 4150a outputs a display command (execution instruction command, effect control information) of effects based on the effect configuration information to the sound source built-in VDP 4160a.

  Based on the display command output from the peripheral control MPU 4150a, the sound source built-in VDP 4160a converts the image data such as the character and the background and the effect data such as the sound data and sound data of the character output from the speaker into the liquid crystal and sound. Obtained from the control ROM 4160b. Based on the input display command, the image data and sound data acquired from the liquid crystal and sound control ROM 4160b are output to a liquid crystal display device and a speaker.

  In the present embodiment, some or all of the effect data stored in the liquid crystal and sound control ROM 4160b is concealed (encrypted), and the concealment is released based on the concealment release information 4201. Even if the effect data stored in the liquid crystal and sound control ROM 4160b is extracted without releasing the concealment, the extracted effect data cannot be normally output.

  Note that the concealment may be released based on the display command, or the concealment is released when the release command for releasing the concealment of the effect data transmitted together with the display command is received. Also good. For example, the release command may be transmitted together with the display command by including information on whether or not the image data is concealed in the effect composition information.

  The effect data is concealed by, for example, encrypting the effect data with the common key based on the common key encryption method, storing it in the liquid crystal and sound control ROM 4160b, and encrypting the common key with a predetermined public key. At this time, the secret release information 4201 corresponds to the common key encrypted with the public key. Then, the sound source built-in VDP 4160a holds the secret key corresponding to the public key together with the public key.

  In the decryption of the effect data, first, the secret release information 4201 corresponding to the effect data to be decrypted is acquired, and the common key is acquired by decrypting with the public key and the secret key held in the sound source built-in VDP 4160a. Finally, the effect data encrypted with the acquired common key may be decrypted.

  Also, instead of accepting the release command every time the presentation data is acquired, it is also possible to accept the input of the release command when the gaming machine is turned on, and thereafter permit the release of concealment until the power is turned off. Good. In addition, when acquiring concealment effect data at the time of execution of a special effect (for example, when change display based on a predetermined change pattern is executed), at the time of execution of the special effect (for example, change) The release command may be transmitted from the peripheral control MPU 4150a to the sound source built-in VDP 4160a at the start or at the start of the big hit game.

  Furthermore, instead of releasing the concealment by the release command transmitted from the peripheral control MPU 4150a, it is determined whether the sound source built-in VDP 4160a independently releases the concealment, and the effect data is released from concealment. Also good. Here, an example in which the sound source built-in VDP 4160a independently releases concealment when the power is turned on will be described. FIG. 25 is a block diagram of a peripheral control board for explaining a configuration in which the sound source built-in VDP 4160a independently releases the concealment of effect information.

  When the power of the gaming machine is turned on, drive power (main control drive power, peripheral control drive power) for each control board is supplied from the power supply board 851 to the main control board 4100 and the peripheral control board 4140 (power supply board) The power supply from is not limited to the main control board and the peripheral control board, but the drive power is supplied to other control boards (for example, the payout control board), but the description thereof is omitted. ).

  When the supply of power is started, the start signal output unit 4401 detects the start of power supply and outputs a reset signal (start signal) to the peripheral control CPU 4150a and the liquid crystal and sound source control unit (VDP) 4160a. The liquid crystal and sound source control unit (VDP) 4160a determines whether to hide the concealment of the effect data based on the input of the reset signal (activation signal).

  Whether or not to conceal the effect data may be determined based on whether or not the received activation signal is valid, for example. Alternatively, the determination may be made based on whether or not the transmission source of the received activation signal is valid. That is, if the transmission source of the activation signal is from the peripheral control MPU 4150a, it may be determined that the effect data is properly acquired, and the concealment of the effect data may be released.

  Further, whether or not to conceal the effect data based on the fact that initialization setting information (which does not include information for instructing deciphering) is input from the peripheral control MPU 4150a to the sound source built-in VDP 4160a when the power is turned on. You may make it determine.

  Further, when the display command is input from the peripheral control MPU 4150a, when the display command is a command related to reading of the image data, it is determined whether or not to hide the concealment of the effect data (image data). You may do it. At this time, first, it may be determined whether or not the effect data is concealed, and then it may be determined whether or not the concealment of the effect data is cancelled. When reading the production data that is not concealed, the data reading may be permitted without determining whether or not the production data is to be concealed. The determination as to whether or not the effect data is concealed may be performed by analyzing the effect data or may hold information indicating whether or not the effect data is concealed.

  Further, the effect data may be encrypted only in the case of special data. The special data may be limited to, for example, an original scene not included in the original in which the character appears when the image data is a character having a copyright. By constituting in this way, the act of illegally extracting a scene that can be seen only during the game from the storage medium (liquid crystal and sound control ROM 4160b) and releasing it to the outside is prevented, and the copyright is protected. Can do. As for audio data, only copyrighted data may be concealed. For example, the concealment of audio data is limited to a song or BGM output from a speaker at the time of production, and the notification sound or warning sound may not be concealed.

  Next, the details of the processing in the sound source built-in VDP 4160a will be described. Here, a case where image data is processed will be described, but sound data may be processed similarly.

  The sound source built-in VDP 4160a includes a secret cancellation information determination unit 4301, a secret image data conversion unit 4302, a video RAM (VRAM) 4303, a display image configuration unit 4304, a frame buffer 4305, and a display image data output unit 4306.

  When receiving the input of the display command transmitted from the peripheral control MPU 4150a, the confidentiality cancellation information determination unit 4301 acquires the confidentiality cancellation information 4201 corresponding to the image data acquired from the liquid crystal and sound control ROM 4160b (the confidentiality cancellation information acquisition unit). Then, it is determined whether or not the acquired confidentiality cancellation information 4201 is valid (concealment cancellation information determination means). If the acquired confidentiality cancellation information 4201 is not valid, the image reading is stopped and an error is notified to the peripheral control MPU 4150a.

  Further, when the peripheral control MPU 4150a receives the notification of the occurrence of the error from the sound source built-in VDP 4160a, the peripheral control MPU 4150a analyzes the content of the notification and specifies the type of error. Then, schedule data for executing error notification screen display and sound (notification sound) output corresponding to the specified error type is selected and acquired from the peripheral control ROM 4150c. Subsequently, a display command is created based on the acquired schedule data and transmitted to the sound source built-in VDP 4160a.

  When receiving the error notification display command from the peripheral control MPU 4150a, the sound source built-in VDP 4160a displays a screen for error notification on the liquid crystal display device 1900 according to the received display command, and outputs sound (notification sound) from the speaker. Note that the screen displayed for error notification (especially failure notification for deconcealment) and the sound to be output are stored in the liquid crystal and sound control ROM 4160b without being concealed. In this case, concealment is not performed. You may perform error alerting | reporting, without determining whether it cancels | releases. In addition to the error notification screen, data may be stored in the liquid crystal and sound control ROM 4160b without concealing the initial screen (power-on screen), the demonstration screen, and the like. In this manner, by removing data such as an error notification screen and an initial screen from the target of concealment, it is possible to prevent the notification of the gaming state and the like from being disabled when the concealment release fails.

  On the other hand, if the acquired secret release information 4201 is valid, the secret image data conversion unit 4302 acquires the secret image data 4202 from the liquid crystal and sound control ROM 4160b, and releases the concealment by the acquired secret release information 4201. Display image data (image data that is not concealed (encrypted)) is acquired.

  If the image data to be acquired is not concealed, the concealed image data 4202 designated from the liquid crystal and sound control ROM 4160b may be acquired as it is. When the image data that has been concealed and the image data that has not been concealed are mixed and stored in the liquid crystal and sound control ROM 4160b, whether or not the image data to be acquired is concealment information is displayed in the display command. Information to be shown may be included.

  Further, the concealment of the image data may be canceled in units of data buses connecting the liquid crystal and sound control ROM 4160b and the sound source built-in VDP 4160a, or may be canceled in units of a predetermined data capacity. Furthermore, it may be released for each character, may be released in units of frames (time), or may be released in units of a plurality of frames. At this time, the secrecy release information 4201 may be set in units of releasing the secrecy.

  Subsequently, the secret image data conversion unit 4302 temporarily stores the acquired display image data in a video RAM (VRAM) 4303 included in the sound source built-in VDP 4160a. The VRAM 4303 may be connected to the outside of the sound source built-in VDP 4160a.

  Further, the display image configuration unit 4304 processes the display image data stored in the VRAM 4303 to generate image data constituting the display screen (display screen data), and stores the display screen data in the frame buffer 4305. The display image data is, for example, a character or a background, and the display screen data is an image obtained by combining display image data (for example, an image obtained by combining (compositing) a background and a character).

  Finally, the display image data output unit 4306 outputs the display screen data stored in the frame buffer 4305 to the liquid crystal display device 1900 based on the control information.

  The secrecy cancellation information determination unit 4301, the secrecy image data conversion unit 4302, and the display image configuration unit 4304 may be configured by software that functions by executing a predetermined program, or by hardware. Also good.

  In the present embodiment, image data and sound data are stored in the liquid crystal and sound control ROM 4160b, but may be stored in separate storage media as an image ROM and a sound source ROM. For example, the image data and the sound data may be stored in different storage media, or the confidentiality release information may be stored in different storage media. Further, in the case where the liquid crystal and sound control ROM 4160b is configured by a plurality of memory modules, the secrecy release information may be set for each module (device).

  Further, the liquid crystal and sound control ROM 4160b and the sound source built-in VDP 4160a may be connected by a dedicated connector. The memory module (liquid crystal and sound control ROM 4160b) is not provided directly on the control board, but is provided as a separate board by connector connection, so that the control block and the memory block can be separated and the memory capacity and the like can be changed for each model. This is because it becomes possible. Further, by connecting with a dedicated connector instead of a general-purpose connector, it is physically difficult to extract image data and sound data from the outside, and security can be further improved.

  Further, the storage medium for storing the image data and the sound data may be configured by a board separate from the peripheral control board 4140. At this time, the storage medium may be configured to be connectable to the peripheral control board 4140 without using a harness. At this time, by setting the shape of the connection terminal to a dedicated shape, it is possible to improve security as in the case where the connection terminal is connected by a dedicated connector.

  Further, as described above, the peripheral control board 4140 is stored in a dedicated case having caulking, but a storage medium for storing image data and sound data may also be stored in a separate dedicated case. .

  Further, the effect data for which the concealment is released may be stored in a volatile storage medium and held until the power is turned off. By comprising in this way, the process which cancels | releases concealment at the time of reading of subsequent production data can be abbreviate | omitted. In this case, when the power of the gaming machine is cut off, the effect data whose concealment is released is erased. However, after the power is turned on again, the concealment may be released again at the timing when the image data is read.

[7. Others]
The present invention has been described with reference to preferred embodiments. However, the present invention is not limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention as described below. And design changes are possible.

  That is, although the said embodiment has mainly shown the case where it applies to a ball-type game machine (pachinko game machine), it is not limited to this, The rotation type game machine (pachislot game machine) mentioned later is used. Can also be applied. Alternatively, the present embodiment may be applied to a gaming machine in which a pachinko gaming machine and a pachislot gaming machine are fused. In either case, the same operational effects as those described above can be obtained.

  As a basic configuration of such a rotating type gaming machine or a gaming machine formed by combining the rotating type gaming machine, for example, a rotating display body (rotating display means) including a plurality of reels (rotating bodies) with a plurality of types of symbols, A housing provided with the rotating display, an operating lever (first operating means) provided outside the housing, and a plurality of devices provided outside the housing corresponding to the plurality of reels, respectively. And a stop button (second operation means), wherein the plurality of reels are rotated by the operation of the operation lever (corresponding to the establishment of the start condition) as a trigger. Rotating body control means for stopping the rotation of each corresponding reel according to the operation sequence of the buttons, and an internal lottery for determining whether or not a predetermined winning condition is satisfied when the start lever is operated Run Game control means (main control board described above) having lottery means and game state control means for shifting from the normal game state to the special game state advantageous to the player after the predetermined winning condition is satisfied 4100) and production control means for controlling the production operation according to the establishment condition of the predetermined winning condition by the control of the game control means (substantially equivalent to the function of the peripheral control board 4140 described above) The display control means performs display operation as a part of the effect operation (substantially equivalent to the function of the liquid crystal display device 1900 described above), and is attached to the plurality of reels under the control of the game control means. A payout device (payout hand) for performing a game medium payout operation according to a combination mode of a plurality of symbols stopped in a symbol display area in which a variation mode of the plurality of symbols is visually recognized ) And it includes a.

1 Pachinko machine (game machine)
DESCRIPTION OF SYMBOLS 2 Outer frame 3 Main body frame 4 Game board 5 Door frame 244 Top plate side liquid crystal display device 1100 Game area 1170 Main control board box 1900 Game board side liquid crystal display device 1910 Peripheral control board box 4100 Main control board (game control means)
4110 Dispensing control board (dispensing control means)
4140 Peripheral control board (production control means)
4150 Peripheral control unit 4150a Peripheral control MPU
4150b Peripheral control ROM
4150c Peripheral control RAM
4160 Liquid crystal and sound control unit 4160a VDP with built-in sound source (production execution means, read restriction means, read restriction release means)
4160b Liquid crystal and sound control ROM (effect information storage means)
4160c Audio data transmission IC
4201 Concealment release information 4202 Concealment image data 4301 Concealment release information determination unit 4302 Concealment image data conversion unit 4303 Video RAM (VRAM)
4304 Display image composition unit 4305 Frame buffer 4306 Display image data output means

Claims (2)

Main control means for controlling the game;
Effect control means for executing a game effect based on an execution instruction from the main control means;
In a gaming machine comprising: production information storage means for storing production information for executing the production,
The production control means includes
Production execution means for executing the production;
Read restriction means for restricting reading of the production information from the production information storage means;
A read restriction releasing means for releasing the restriction of reading the production information,
The production execution means
Effect information read restriction determination means for determining at a predetermined timing whether or not to restrict the reading of the effect information stored in the effect information storage means;
When it is determined by the effect information read restriction determining means that normal reading of the effect information stored in the effect information storage means is restricted, the effect information stored in the effect information storage means by the read restricting means is normal. And an effect information acquisition means that enables normal reading of the effect information stored in the effect information storage means by the read restriction release means when it is determined that the read restriction is not restricted. Machine. Main control means for controlling the game;
Effect control means for executing a game effect based on an execution instruction from the main control means;
In a gaming machine comprising: production information storage means for concealing and storing production information for executing the production,
The production control means includes
Production execution means for executing the production;
Anonymization releasing means for releasing the effect information from anonymization,
The production execution means
Anonymity cancellation determination unit that determines at a predetermined timing whether or not to cancel the concealment of the effect information stored in the effect information storage unit;
When it is determined that the concealment of the production information stored in the production information storage unit is not released by the anonymity release determination unit, when it is determined to release without concealing the production information, A game machine comprising: production information obtaining means that makes it possible to obtain the production information by releasing the concealment of the production information by the concealment release means.