JP6421971B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine.

  2. Description of the Related Art Conventionally, a gaming machine on which a display control board that performs display control of a plurality of display means with separate VDPs has been proposed (for example, Patent Document 1).

  When displaying an image with a large image size that cannot be accommodated in the transmission band of one signal transmission line by the single link method in the output of the conventional VDP, the second signal transmission line is used. A dual link method in which data is simultaneously transmitted to the first signal transmission path and the second signal transmission path has been adopted.

JP 2010-279799 A (paragraph [0102], FIG. 1 and FIG. 3)

  By the way, when the display control is performed for each of the plurality of display means with different VDPs, it is difficult to synchronize the display control with each VDP as the number of display means increases. There was a problem that the synchronism of the progress of images was lost. Further, in the conventional VDP dual link system, output is only performed for one display means.

  The present invention has been made in view of such circumstances, and an object of the present invention is to output a single dual link system without breaking the synchronism of the progress of the effect image by the plurality of display means. Accordingly, an object of the present invention is to provide a gaming machine that can display effect images on a plurality of display means by associating a plurality of display means.

  Effective solutions for achieving the above-described object will be described below. In addition, the effect | action etc. are demonstrated as needed. In addition, for easy understanding, the corresponding configuration in the embodiment of the invention is also shown as appropriate, but is not limited at all.

(Solution 1)
An gaming machine comprising a plurality of display means capable of displaying an image, wherein the gaming machine generates an image and stores it in a storage means, and outputs the stored image by a dual link method Generating means, wherein the image generation means generates first distraction drawing data corresponding to a first distraction image obtained by extending an image to be displayed on one display means among the plurality of display means ; An image extension means for generating second extension drawing data corresponding to a second extension image obtained by extending an image to be displayed on another display means other than one display means, and masking the image on the first extension image. The slit-like odd-numbered mask pattern used to generate the first elongated drawing data for the remaining even columns and the second elongated drawing data for the remaining odd-numbered columns masked on the second elongated image. Mask pattern generation means for generating a slit-shaped even-column mask pattern used for generating the first extension drawing data for the even-numbered columns in the even-numbered address of the storage means, and second for the odd-numbered columns an image storage means for storing a distraction drawing data to the odd address of the memory means, the output of the first distraction drawing data of the even row content stored in an even address before term memory unit, an odd pre-term memory means has the output of the second distraction drawing data of the odd column fraction is then stored in the address, and at the same time line cormorant simultaneous output means, wherein the mask pattern generation means is stretched odd dot row mask pattern predetermined The slit-shaped even-numbered mask pattern is generated by generating the slit-shaped odd-numbered-mask pattern and extending a predetermined even-numbered dot-mask pattern. Generates, the one of the display means is arranged to be fixed to a predetermined position, the other display means is arranged movable by electric driving means, a game machine, characterized in that.

This gaming machine is provided with a plurality of display means. This display means is capable of displaying an image.

This gaming machine further includes image generation means. The image generation means generates an image and stores it in the storage means, and can output the stored effect image by the dual link method.

The image generation means has an image extension means, a mask pattern generation means, an image storage means, and a simultaneous output means. The image extension means can generate first extension drawing data corresponding to a first extension image obtained by extending an image to be displayed on one display means among the plurality of display means, and the one display means. It is possible to generate second distraction drawing data corresponding to the second distraction image obtained by extending the image to be displayed on the other display means except for. The mask pattern generation unit masks the slit-like odd-numbered mask pattern used to generate the first stretched drawing data for the even-numbered columns remaining on the first stretched image and the second stretched image. It is possible to generate the slit-shaped even-column mask pattern used for generating the second elongated drawing data for the remaining odd-numbered columns. The image storage means can store the first extended drawing data for even columns in the even addresses of the storage means, and can store the second extended drawing data for odd columns in the odd addresses of the storage means. It can be done. The simultaneous output means outputs the first extended drawing data for the even number columns stored in the even address of the storage means, and the output of the second extended drawing data for the odd number columns stored in the odd address of the storage means. It can be done at the same time. The mask pattern generation means can generate a slit-like odd-numbered mask pattern by extending a predetermined odd-numbered-dot mask pattern, and can also generate a slit-shaped even-numbered-mask pattern by extending a predetermined even-numbered dot-mask pattern. can do.
The image generation means outputs the first extended drawing data for the even number columns stored in the even address of the storage means for one display means and the storage for the other display means other than the one display means by the dual link method. Since the second extension drawing data for the odd number column stored in the odd address of the means can be output simultaneously, the dual link method that has been used for displaying one display means in the past is used. The present invention can be applied to a gaming machine as an unprecedented novel method for displaying an image on a display means. Therefore, it is possible to display the effect images on the plurality of display means by associating the plurality of display means with one dual link output.

In this embodiment, for example, the liquid crystal and sound source built-in VDP 4160a of the peripheral control board 4140 in FIG. 31 corresponds to the image generation means, and the game board side liquid crystal display device 1900 in FIG. 10 corresponds to one display means. The movable liquid crystal display devices 1925a to 1925d in FIG. 10 correspond to other display means. Although not shown, the movable devices 1925aa to 1925da correspond to electrical drive means.

(Solution 2)
A gaming machine comprising effect control means for controlling the progress of effects by a plurality of display means capable of displaying an effect image based on a command from a main control means for controlling the progress of the game, wherein the gaming machine is Further, the rendering data of the effect image is generated and stored in the storage means, and the stored rendering data of the effect image is simultaneously output to the first signal transmission path and the second signal transmission path by the dual link method. The production control means generates drawing data of the production image to be displayed on at least the display means included in the first system among the plurality of display means and sets the even-numbered address of the storage means. Control to be stored is performed on the image generation means, and included in the remaining second system excluding the display means included in the first system among the plurality of display means The drawing data generation control means for controlling the image generation means to generate drawing data of the effect image to be displayed on the display means and store it in the odd address of the storage means, and the image by the drawing data generation control means The rendering image rendering data to be displayed on the display unit included in the first system stored in the even address of the storage unit generated by the generation unit is output from the first signal transmission path and included in the first system. The display means controls the image generating means to display the effect image stored at the even address of the storage means, and at the odd address of the storage means generated by the image generating means by the drawing data generation control means. The drawing data of the effect image displayed on the display means included in the stored second system is output from the second signal transmission path, and the second system Gaming machine, characterized in a control to display an effect image stored in the odd address of the storage means comprise a drawing data output control means for performing on the image generating unit on a display unit included in the.

  This gaming machine is provided with production control means. The effect control means is capable of controlling the progress of the effects by a plurality of display means capable of displaying the effect image based on a command from the main control means for controlling the progress of the game.

  This gaming machine further includes image generation means. The image generation means generates rendering data for the effect image and stores it in the storage means, and also stores the rendering data for the effect image stored in the first signal transmission path and the second signal transmission path by a dual link method. It can output simultaneously.

  The effect control means includes at least drawing data generation control means and drawing data output control means. The drawing data generation control means controls the image generation means to generate drawing data of the effect image to be displayed on the display means included in the first system among the plurality of display means and to store it in the even address of the storage means. In addition, it is possible to generate rendering data of effect images to be displayed on the display means included in the remaining second system, excluding the display means included in the first system among the plurality of display means, and store it in odd addresses of the storage means This control can be performed on the image generation means. The drawing data output control means outputs drawing data of the effect image displayed on the display means included in the first system stored in the even address of the storage means generated by the image generation means by the drawing data generation control means. The image generation means can control the image generation means to display the effect image output to the display means included in the first system and stored in the even address of the storage means. The drawing data of the effect image displayed on the display means included in the second system stored in the odd address of the generated storage means is output from the second signal transmission path and the odd number of the storage means is displayed on the display means included in the second system. Control for displaying the effect image stored in the address can be performed on the image generating means.

  In this way, rendering data for effect images displayed on the display means included in the first system can be generated and stored in the even addresses in one storage means, and the odd addresses in one storage means can be stored in the odd addresses. Since the rendering data of the effect image displayed on the display means included in the two systems can be generated and stored, the image generation means can store the rendering data of the effect image stored at the even address of the storage means by the dual link method. By outputting from the first signal transmission path, the effect image stored at the even address of the storage means can be displayed on the display means included in the first system, and the effect image stored at the odd address of the storage means is 2 The effect image stored in the odd address of the storage means is displayed on the display means included in the second system by outputting from the first signal transmission path. (In other words, the image generation means outputs the rendering data of the rendering image stored in the even address of the storage means for the display means included in the first system, and the The drawing data of the effect image stored in the odd address of the storage means for the display means included in the two systems can be simultaneously output). As a result, the synchronism of the progress of the effect images of the plurality of display means by the display means included in the first system and the display means included in the second system is not lost, and one conventional display means is provided. The dual link method that has been used for display is an unprecedented novel method for displaying effect images on a plurality of display means including display means included in the first system and display means included in the second system. Can be applied to gaming machines. Accordingly, the effect images can be displayed on the plurality of display means by associating the plurality of display means with one dual link method output without breaking the synchronism of the progress of the effect images by the plurality of display means. Can do.

  In this embodiment, for example, the main control MPU 4100a in the main control board 4100 in FIG. 12 corresponds to the main control means, and various commands transmitted from the main control board 4100 to the peripheral control board 4140 in FIG. 41 and FIG. The game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d in FIG. 10 correspond to a plurality of display means, and the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 in FIG. 1 corresponds to the gaming machine, the liquid crystal on the peripheral control board 4140 of FIG. 31 and the built-in VRAM of the sound source built-in VDP 4160a of the sound control unit 4160 correspond to the storage means, and the peripheral of FIG. In the VDP 4160a with built-in sound source of the liquid crystal and sound control unit 4160 in the control board 4140 The even channel of channel CH1 corresponds to the first signal transmission path, and the odd channel of channel CH1 in the liquid crystal and sound source built-in VDP 4160a of the peripheral control board 4140 in FIG. 31 corresponds to the second signal transmission path. 31, the liquid crystal and sound source built-in VDP 4160a of the peripheral control board 4140 in FIG. 31 corresponds to the image generation means, and the game board side liquid crystal display device 1900 in FIG. 10 corresponds to the “display means included in the first system”. The movable liquid crystal display devices 1925a to 1925d in FIG. 10 correspond to “display means included in the second system”, and the display data creation process in step S1030 in the power-on process of the peripheral control unit in FIG. 64 is the drawing data generation control. It corresponds to the means and corresponds to the even dot row that can be specified by the even address in FIG. The grid-like processed image MVD2 processed into a grid shape so that only a plurality of strip-like images of the part remains is “drawing effect image displayed on the display means included in the first system stored in the even address of the storage means” The grid-like processed image SVD2 (SVDA2 to SVDA2) that corresponds to “data” and is processed so as to leave only a plurality of strip-like images corresponding to the odd-numbered dot rows that can be specified by the odd-numbered addresses in FIG. 64 is equivalent to the “drawing data of the rendering image displayed on the display means included in the second system stored in the odd address of the storage means”, and the peripheral control unit in FIG. The display data output process in step S1016 in the power-on process corresponds to the drawing data output control means.

(Solution 3)
A gaming machine comprising: first display means capable of displaying an effect image; and second display means provided separately from the first display means and capable of displaying an effect image. The gaming machine further includes an image generating unit that generates an effect image and stores the generated effect image in a storage unit and outputs the stored effect image by a dual link method, and the image generation unit includes at least the image generating unit. After rendering the rendering data of the effect image to be displayed on the first display means to the even address of the storage means, and storing the rendering data of the effect image to be displayed on the second display means to the odd address of the storage means In addition, the output of the rendering data of the effect image stored at the even address of the storage means for the first display means, and the odd number of the storage means for the second display means. Gaming machine and performs the output of the drawing data of the effect image stored in less, at the same time.

  This gaming machine includes a plurality of display means, a first display means and a second display means. The first display means can display the effect image. The second display means is provided separately from the first display means and can display the effect image.

  This gaming machine further includes image generation means. The image generation means generates an effect image and stores it in the storage means, and can output the stored effect image by a dual link method.

  The image generation means stores at least the rendering data of the effect image displayed on the first display means at the even address of the storage means, and the rendering data of the effect image displayed on the second display means at the odd address of the storage means. Output of the rendering data of the effect image stored in the even address of the storage means for the first display means and the output of the rendering data of the effect image stored in the odd address of the storage means for the second display means Can be performed at the same time.

  As described above, the image generation means outputs the rendering data of the rendering image stored in the even address of the storage means for the first display means and the odd address of the storage means for the second display means by the dual link method. Since it is possible to simultaneously output the rendering data of the produced effect image, the conventional dual link method used for displaying one display means is used to display the effect image on a plurality of display means. It can be applied to gaming machines as a novel method that is not present. Therefore, it is possible to display the effect images on the plurality of display means by associating the plurality of display means with one dual link output.

  In the present embodiment, for example, the game board side liquid crystal display device 1900 of FIG. 10 corresponds to the first display means, the movable liquid crystal display devices 1925a to 1925d of FIG. 10 correspond to the second display means, and FIG. The built-in sound source VDP 4160a of the liquid crystal and sound control unit 4160 in the peripheral control board 4140 corresponds to an image generation unit, and the built-in VRAM of the sound source VDP 4160a in the peripheral control board 4140 in FIG. 31 corresponds to a storage unit. 32C, a grid-like processed image MVD2 processed into a grid so that only a plurality of strip-like images corresponding to the even-numbered dot rows that can be specified by the even-numbered addresses in FIG. Is an odd number that can be designated by an odd address in FIG. 32 (g). A grid-like processed image SVD2 (lattice-like processed image SVD2 made up of SVDA2 to SVDD2) processed into a grid shape so that only a plurality of strip-like images corresponding to a row of columns remains is “the second display Corresponds to the rendering data of the effect image stored in the odd address of the storage means for the means.

(Solution 4)
A gaming machine comprising a plurality of display means capable of displaying an effect image, wherein the gaming machine further generates effect image drawing data and stores it in the storage means and stores the stored effect image drawing data Can be output simultaneously to the first signal transmission path and the second signal transmission path by the dual link method, and the rendering data of the effect image from the image generation means can be divided and output. Division output means, and the image generation means includes at least rendering image rendering data displayed on a display means included in a first system among the plurality of display means or the first of the plurality of display means. One of the rendering data of the effect image displayed on the display means included in the remaining second system excluding the display means included in one system is stored in an even address of the storage means. And storing the other in the odd address of the storage means, and then outputting the rendering data of the effect image stored in the even address of the storage means to the first signal transmission path and the odd address of the storage means. Simultaneously outputting the drawing data of the stored effect image to the second signal transmission path, and the divided output means is at least one of the first signal transmission path or the second signal transmission path. When the drawing data of the effect image transmitted from one side is input, and the drawing data of the input effect image is for the display means included in the first system, the drawing data of the input effect image is While being divided so as to correspond to the effect images displayed on the display means included in one system and outputting them to the display means included in the first system, the input effects When the drawing data of the image is for the display means included in the second system, the input rendering data of the effect image is divided so as to correspond to the effect image displayed on the display means included in the second system. And outputting to the display means included in the second system.

  This gaming machine includes a plurality of display means capable of displaying effect images. This gaming machine further includes image generation means and division output means. The image generating means generates rendering data of the effect image and stores it in the storage means, and simultaneously stores the stored rendering data of the rendering image on the first signal transmission path and the second signal transmission path by the dual link method. It can be output. The division output means can divide and output the rendering data of the effect image from the image generation means.

  The image generation means includes at least the rendering data of the effect image displayed on the display means included in the first system among the plurality of display means or the remaining second except for the display means included in the first system among the plurality of display means. One of the rendering data of the effect image displayed on the display means included in the system is stored in the even address of the storage means, and the other is stored in the odd address of the storage means and then stored in the even address of the storage means. The output of the rendered image drawing data to the first signal transmission path and the output of the rendering image rendering data stored in the odd address of the storage means to the second signal transmission path can be performed simultaneously. It has become.

  The division output means receives at least drawing data of the effect image transmitted from either the first signal transmission path or the second signal transmission path, and the input drawing data of the effect image is the first system. Display means included in the first system by dividing the drawing data of the input effect image so as to correspond to the effect image displayed on the display means included in the first system. On the other hand, when the drawing data of the input effect image is for the display means included in the second system, the drawing data of the input effect image is used as the second drawing data. Each can be divided so as to correspond to the effect image displayed on the display means included in the system, and can be output to the display means included in the second system.

  In this way, the image generating means is the rendering data to be displayed on the display means included in the first system among the plurality of display means, or the rest other than the display means included in the first system among the plurality of display means. One of the rendering data of the effect image displayed on the display means included in the second system can be stored in the even address of the storage means, and the other can be stored in the odd address of the storage means. . The image generation means outputs the rendering data of the rendering image stored at the even address of the storage means to the first signal transmission path and the rendering data of the rendering image stored at the odd address of the storage means by the dual link method. Since the output to the second signal transmission path can be performed simultaneously, the effect image of the plurality of display means by the display means included in the first system and the display means included in the second system The dual link method that has been used to display one display means in the past and the display means included in the first system and the display included in the second system The present invention can be applied to a gaming machine as an unprecedented novel method for displaying an effect image on a plurality of display means. Accordingly, the effect images can be displayed on the plurality of display means by associating the plurality of display means with one dual link method output without breaking the synchronism of the progress of the effect images by the plurality of display means. Can do.

  The divided output means receives drawing data of the effect image transmitted from either the first signal transmission path or the second signal transmission path, and the input drawing data of the effect image is the first system. When the display means is included in the display means, the drawing data of the input effect image can be divided so as to correspond to the effect image displayed on the display means included in the first system. Therefore, while it is possible to display the effect images corresponding to the display means included in the first system, when the drawing data of the input effect image is for the display means included in the second system, this input The rendered data of the rendered effect image can be divided so as to correspond to the rendered image displayed on the display means included in the second system. Therefore, it is possible to display an effect image corresponding to the display means included in the second system, respectively.

  In the present embodiment, for example, the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d in FIG. 10 correspond to a plurality of display means, the pachinko gaming machine 1 in FIG. 1 corresponds to a gaming machine, and FIG. In the peripheral control board 4140 of FIG. 31, the even channel of the channel CH1 in the liquid crystal and sound control unit 4160 with built-in sound source 4160a corresponds to the first signal transmission path, and the liquid crystal and sound control unit 4160 with built-in sound source in the peripheral control board 4140 of FIG. The odd-numbered channel CH1 in the VDP 4160a corresponds to the second signal transmission path, the liquid crystal and sound source built-in VDP 4160a in the peripheral control board 4140 in FIG. 31 corresponds to the image generation means, and the peripheral control board in FIG. VDP with built-in sound source of liquid crystal and sound control unit 4160 in 4140 The internal VRAM 160a corresponds to the storage means, the signal division circuits 3420y and 3420z of the liquid crystal output board 3420 in FIG. 31 correspond to the division output means, and the game board side liquid crystal display device 1900 in FIG. The movable liquid crystal display devices 1925a to 1925d in FIG. 10 correspond to “display means included in the second system” and correspond to even dot rows that can be specified by even addresses in FIG. 32 (c). The grid-processed image MVD2 processed in a grid pattern so that only a plurality of strip-shaped images remain is equivalent to “drawing data of the rendering image stored at the even address of the storage means”, and FIG. Grid processed image SVD2 (SVDA2 to SVD) processed into a grid so that only a plurality of strip-shaped images corresponding to odd dot rows that can be specified by odd addresses remain. Lattice-like processed image composed of 2 SVD2) corresponds to the "drawing data of the effect image stored in odd address of the storage unit".

(Solution 5)
When a predetermined starting condition is satisfied, it is then determined whether or not a predetermined winning condition is satisfied. After that, when the winning condition is satisfied, it is advantageous to the player from the normal gaming state. A game control means for shifting to a special game state, an effect control means for controlling an effect operation according to the established condition of the winning condition by the control of the game control means after the start condition is satisfied, and the effect control means First display means for displaying a first effect image by control, and second display means for displaying a second effect image by control of the effect control means, wherein the effect control means displays a video. Production control storage means in which a plurality of material image data used for displaying a plurality of material images to be configured is stored in advance, and whether the necessary material image data out of the plurality of material image data An image generating unit that generates drawing data and stores it in a storage unit and then outputs the image by a dual link method, and a frame that controls each of the image generating units and includes each effect image based on the drawing data for each preset period And a rendering operation control means for repeatedly displaying the first display means and the second display means, wherein the drawing control means corresponds to the first extended effect image obtained by extending the first effect image. Effect image extension means for generating first extension drawing data to be generated and generating second extension drawing data corresponding to a second extension effect image obtained by extending the second effect image, and the first extension The first extended drawing data for the even number of columns remaining by masking the predetermined slit-like odd-numbered mask pattern on the effect image is generated, while the second extended effect image is already displayed. Mask processing control means for generating second extended drawing data for odd columns remaining masked by overlapping the slit-shaped even-numbered mask patterns, and output of the first extended drawing data for the even columns, Simultaneous output control means for simultaneously executing output of second extended drawing data for odd-numbered columns, and the mask based on the even-numbered basic dot row mask pattern prepared in advance in the effect control storage means The predetermined slit-shaped even-numbered mask pattern is generated by extending a predetermined even-numbered dot-mask pattern generated by arranging a combination of dots and the blank dots in a row over a predetermined number of times, while the effect control storage means A combination of the mask dot and the blank dot is determined based on the even basic dot row mask pattern prepared in advance. The predetermined odd-numbered dot row mask pattern generated by arranging in a row over a predetermined number of times is extended to generate the predetermined slit-like odd-numbered row mask pattern.

  From the even basic dot row mask pattern (basic dot row mask pattern) having the minimum dot configuration prepared in advance in the effect control storage means as described above, not only the odd basic dot row mask pattern but also a predetermined lattice shape When the even-numbered mask pattern and the default odd-numbered mask pattern are generated, the production control storage means prepares the default grid-like odd-numbered mask pattern and the default grid-like even-numbered mask pattern in advance. The default odd-numbered mask pattern and the default even-numbered mask pattern are extended from the even-numbered basic dot-row mask pattern (basic dot-row mask pattern) with the minimum dot configuration as needed. I will do it. Therefore, the amount of data that should be prepared in advance in the production control storage means that is a non-volatile memory can be extremely suppressed, so that more production material image data can be prepared in the production control storage means accordingly. As a result, it becomes possible to realize even more diverse images.

(Solution 6)
When a predetermined starting condition is satisfied, it is then determined whether or not a predetermined winning condition is satisfied. After that, when the winning condition is satisfied, it is advantageous to the player from the normal gaming state. A game control means for shifting to a special game state, an effect control means for controlling an effect operation according to the established condition of the winning condition by the control of the game control means after the start condition is satisfied, and the effect control means First display means for displaying a first effect image by control, and second display means for displaying a second effect image by control of the effect control means, wherein the effect control means displays a video. Production control storage means in which a plurality of material image data used for displaying a plurality of material images to be configured is stored in advance, and whether the necessary material image data out of the plurality of material image data An image generating unit that generates drawing data and stores it in a storage unit and then outputs the image by a dual link method, and a frame that controls each of the image generating units and includes each effect image based on the drawing data for each preset period Reproducible operation control means for repeatedly displaying the first display means and the second display means, and the effect control storage means can be specified by an even-numbered address of the previous storage means and is in a grid pattern A mask dot for masking an even unit region that is one of each even strip region to be arranged includes an even basic dot row mask pattern configured by alternately arranging blank dots, and the drawing control means includes The first effect drawing image corresponding to the first extension effect image obtained by extending the first effect image is generated, and the second effect image is extended. An effect image extension means for generating second extension drawing data corresponding to the second extension effect image, and an even number left by masking a predetermined slit-like odd-numbered mask pattern on the first extension effect image. First decompression drawing data for a row is generated and stored in each even strip area of the storage means, while a predetermined slit-like even row mask pattern is overlaid on the second stretched effect image and masked. The mask processing control means for generating the second extended drawing data for the odd-numbered columns and storing them in each odd strip area of the storage means and the even-numbered address of the storage means for the first display means can be designated. The output of the first extended drawing data for the even-numbered columns stored in each even-numbered strip area, and each of the odd-numbered shorts that can be designated by an odd address among the storage means for the second display means. Simultaneous output control means for simultaneously executing the output of the second decompressed drawing data for the odd-numbered columns stored in the booklet area, and further comprising the even basics prepared in advance in the effect control storage means An even dot row mask pattern generating means for generating a predetermined even dot row mask pattern by arranging a combination of the mask dots and the blank dots in a row over a predetermined number of times based on a dot row mask pattern, and the generated Based on the even-numbered basic dot row mask pattern prepared in advance in the even-numbered row mask pattern generating means for extending the predetermined even-numbered dot row mask pattern to generate the predetermined slit-shaped even-numbered row mask pattern. The mask dots and blank dot combinations are arranged in a line over a predetermined number of times. An odd dot row mask pattern generating means for generating a predetermined odd dot row mask pattern, and an odd row mask for generating the predetermined slit-like odd row mask pattern by extending the generated default odd dot row mask pattern And a pattern generation means.

  From the even basic dot row mask pattern (basic dot row mask pattern) having the minimum dot configuration prepared in advance in the effect control storage means as described above, not only the odd basic dot row mask pattern but also a predetermined lattice shape When the even-numbered mask pattern and the default odd-numbered mask pattern are generated, the production control storage means prepares the default grid-like odd-numbered mask pattern and the default grid-like even-numbered mask pattern in advance. The default odd-numbered mask pattern and the default even-numbered mask pattern are extended from the even-numbered basic dot-row mask pattern (basic dot-row mask pattern) with the minimum dot configuration as needed. I will do it. Therefore, the amount of data that should be prepared in advance in the production control storage means that is a non-volatile memory can be extremely suppressed, so that more production material image data can be prepared in the production control storage means accordingly. As a result, it becomes possible to realize even more diverse images.

(Solution 7)
The gaming machine according to any one of the solving means 1 to 6, wherein the gaming machine is a revolving type gaming machine.

  In the gaming machine of the present invention, since the gaming machine is a spinning-type gaming machine, the operational effects described in any of the solving means 1 to 6 can be obtained in the spinning-type gaming machine. As a basic configuration of the spinning machine, after a symbol information string (for example, a plurality of reel columns with a plurality of symbol information) composed of a plurality of symbol information is variably displayed, the display result of the symbol information is stopped and displayed. In addition to the fluctuation display means, the fluctuation display of the symbol information is started based on the operation of the start operation means (for example, the start lever), and based on the operation of the stop operation means (for example, the stop button) or the elapse of a predetermined time. Stop changing the symbol information. And it is provided with a profit granting state generating means for generating a profit granting state (big hit gaming state) on the condition that the symbol information becomes a predetermined specific display mode, and a medal is used as a game medium, and a profit granting state is generated. It is structured so that a large amount of medals are sometimes paid out.

(Solution 8)
The gaming machine according to any one of the solving means 1 to 6, wherein the gaming machine is a fusion gaming machine in which a pachinko gaming machine and a revolving gaming machine are fused.

  In the gaming machine of the present invention, since the gaming machine is a fusion gaming machine in which a pachinko gaming machine and a spinning-type gaming machine are fused, The effects described in any one of the solving means 1 to 6 can be obtained. As a basic configuration of a fusion gaming machine in which a pachinko gaming machine and a spinning-type gaming machine are merged, a symbol information string composed of a plurality of symbol information (for example, a plurality of reel strings with a plurality of symbols) is variably displayed. Later, it is provided with a fluctuation display means for stopping and displaying the display result of the symbol information, and starts the fluctuation display of the symbol information based on the operation of the start operation means (for example, the start lever), and the stop operation means (for example, stop) Button) or the change display of the symbol information is stopped based on the passage of a predetermined time. And it is provided with the profit grant state generation means which generates a profit grant state (big hit game state) on condition that the symbol information becomes a predetermined specific display mode, and a game ball is used as a game medium, A large amount of game balls are paid out when they are generated.

  In the gaming machine of the present invention, it is possible to produce a plurality of display means by associating a plurality of display means with one dual link system output without breaking the synchronism of the progress of the effect images by the plurality of display means. Each image can be displayed.

It is a perspective view which shows the state which open | released the main body frame with respect to the outer frame of a pachinko gaming machine, and opened the door frame with respect to the main body frame. It is a front view of a pachinko gaming machine. It is a rear view of a pachinko gaming machine. It is a front perspective view of an outer frame. It is a front perspective view of a main body frame. It is a back surface perspective view of the board | substrate unit in a main body frame. It is a perspective view of a door frame. It is a front view of a game board. It is the disassembled perspective view which decomposed | disassembled the game board of FIG. 8 and was seen from the front. It is a figure which shows the outline of the aspect which a movable liquid crystal display device moves to an up-down and left-right direction. It is a front view which expands and shows the function display unit in a game board in the state attached to the pachinko gaming machine. It is a block diagram of a main control board, a payout control board, and a peripheral control board. FIG. 13 is a block diagram illustrating the continuation of FIG. 12. It is the schematic of the various detection signals input / output to lending device connection terminal boards, such as a game ball which relays the electrical connection of the payout control board which comprises a main board, CR unit, and a frequency display board. FIG. 13 is a block diagram illustrating the continuation of FIG. 12. It is a block diagram which shows the outline of peripheral control MPU. It is a block diagram around VDP with a built-in sound source in the liquid crystal and the sound control unit. It is a block diagram which shows the power supply system of a pachinko gaming machine. FIG. 4A is a block diagram showing a power generation circuit, and FIG. 2B is a diagram showing a relationship between power consumption and a power consumption suppression level accompanying the power consumption. FIG. 19 is a block diagram showing a continuation of FIG. 18. It is a circuit diagram which shows the circuit of a main control board. It is a circuit diagram which shows a power failure monitoring circuit. It is a circuit diagram which shows the interface circuit for communication between the board | substrates of a main control board and a peripheral control board. It is a circuit diagram which shows the circuit etc. of a payout control part. It is a circuit diagram which shows the payout control input circuit. FIG. 26 is a circuit diagram illustrating a continuation of FIG. 25. It is a circuit diagram which shows a payout motor drive circuit. It is a circuit diagram which shows CR unit input / output circuit. It is an input / output diagram showing various input / output signals to / from the main control board and various output signals to the external terminal board. It is a figure which shows the arrangement | sequence of the output terminal of an external terminal board. It is a block diagram which shows the circuit structure of a liquid crystal output board. It is a figure which shows an example of the production method of drawing data. It is a conceptual diagram which shows the structural example of each mask pattern. It is a figure which shows an example of the production example of a game board side liquid crystal display device and a movable liquid crystal display device. FIG. 35 is a diagram showing a continuation of an example of the effect example in FIG. 34. It is a circuit diagram which shows the liquid crystal module circuit which draws the display area of an upper plate side liquid crystal display device. It is a block diagram of the touch panel circuit which performs detection control of the contact state of a touch panel. It is the schematic which detects the position where the finger is touching the touch panel. It is the schematic which shows the continuation of FIG. It is a table which shows an example of the various commands transmitted to the payout control board from the main control board. It is a table which shows an example of the various commands transmitted to a peripheral control board from a main control board. 42 is a table showing a continuation of various commands transmitted from the main control board to the peripheral control board in FIG. 41. It is a table which shows an example of the various commands from the payout control board which a main control board receives. It is a flowchart which shows an example of the main control side power-on process. FIG. 45 is a flowchart showing a continuation of main-control-side power-on processing in FIG. 44. FIG. It is a flowchart which shows an example of the main control side timer interruption process. It is a flowchart which shows an example of the process at the time of power-on of a payout control part. It is a flowchart which shows a continuation of the process at the time of power-on of the payout control part of FIG. FIG. 49 is a flowchart showing a continuation of the payout control unit power-on process following FIG. 48. FIG. It is a flowchart which shows an example of a payout control part timer interruption process. It is a flowchart which shows an example of a rotation angle switch log | history production process. It is a flowchart which shows an example of a sprocket fixed position determination skip process. It is a flowchart which shows an example of a spherical collision determination process. It is a flowchart which shows an example of the prize ball stock number addition process for prize balls. It is a flowchart which shows an example of the number-of-use prize ball stock number addition process. It is a flowchart which shows an example of a stock monitoring process. It is a flowchart which shows an example of a pay-out ball engagement operation determination setting process. It is a flowchart which shows an example of a payout setting process. It is a flowchart which shows an example of a sphere ball movement setting process. It is a flowchart which shows an example of a retry operation | movement monitoring process. It is a flowchart which shows an example of a mismatch counter reset determination process. It is a flowchart which shows an example of an error cancellation operation determination process. It is a timing chart which shows the signal process (a) at the time of paying-out operation by ball lending, and the input signal confirmation process (a) from CR unit. It is a flowchart which shows an example of a peripheral control part power-on process. It is a flowchart which shows an example of the peripheral control part V blank interruption process. It is a flowchart which shows an example of a peripheral control part 1ms timer interruption process. It is a flowchart which shows an example of a peripheral control part command reception interruption process. It is a flowchart which shows an example of a peripheral control part power failure warning signal interruption process. It is a flowchart which shows an example of a power saving power saving mode transition determination process. It is a flowchart which shows an example of a power consumption monitoring process. The figure which shows the relationship between the value set as a master volume value for power suppression, and a power consumption suppression stage, The figure which shows the relationship between the brightness | luminance set as a brightness | luminance for power suppression, and a power consumption suppression stage (b) ). It is a flowchart which shows an example of a LOCKN signal log | history creation process. It is a flowchart which shows an example of a connection malfunction determination process. It is a flowchart which shows an example of a connection recovery process. It is a timing chart explaining the timing which outputs a connection confirmation signal with respect to the INIT terminal of the transmitter IC for upper plate side liquid crystals. It is a figure which shows an example of the display content of a maintenance screen. It is a figure which shows the display content which should call a salesclerk during jackpot. It is a figure which shows an example of the display content of a service mode screen. It is a figure which shows an example of the display content of a break timer setting screen. It is a figure which shows an example of the display content of the screen during a break. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example in which the title of the selection display thing was displayed. It is a figure which shows an example in which the title of the selection display thing was displayed. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of an operation menu screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of a volume adjustment screen. It is a figure which shows an example of the variable display effect displayed on the display area of a game board side liquid crystal display device. It is a figure which shows an example of the launch operation malfunction notification effect displayed on the display area of the game board side liquid crystal display device. It is a block diagram which shows the circuit structure of the liquid crystal output board in case eight movable liquid crystal display devices are provided in a game board. It is a schematic perspective view of a slot machine.

[1. Overall configuration of pachinko machine]
Hereinafter, a pachinko gaming machine as a gaming machine of the present invention will be described with reference to the drawings. First, the entire pachinko gaming machine according to the embodiment will be described with reference to FIGS. FIG. 1 is a perspective view showing a state in which a main body frame is opened with respect to an outer frame of the pachinko gaming machine according to the embodiment and a door frame is opened with respect to the main body frame, and FIG. 2 is a front view of the pachinko gaming machine. FIG. 3 is a rear view of the pachinko gaming machine.

  As shown in FIG. 1 to FIG. 3, the pachinko gaming machine 1 includes an outer frame 2 installed in an island facility (not shown) of a game hall, and a box that is pivotally supported by the outer frame 2 so as to be opened and closed and opened on the front side. A game board 4 having a frame-shaped main body frame 3, a game area 1100 in which a game ball as a game medium is inserted and fixed to the main body frame 3 from the front side, and the front face of the main body frame 3 and the game board 4 are on the player side And a door frame 5 pivotally supported so as to be openable and closable with respect to the main body frame 3. The door frame 5 of the pachinko gaming machine 1 stores a gaming window 101 formed so that the gaming area 1100 of the gaming board 4 can be viewed from the player side, and a gaming ball disposed below the gaming window 101. A dish-shaped upper plate 301 and lower plate 302 (see FIG. 7), and a handle device 500 that a player operates to drive game balls stored in the upper plate 301 into the game area 1100 of the game board 4 It is equipped with.

  Also, in the pachinko gaming machine 1, the outer frame 2, the main body frame 3, and the door frame 5 are each formed in a vertically long rectangular shape extending in the vertical direction in the front view, and the horizontal widths in the horizontal directions are substantially the same. The size of the main body frame 3 and the door frame 5 is slightly shorter than that of the outer frame 2. A decorative cover 23 is attached to the front surface of the outer frame 2 at a position below the main body frame 3 and the door frame 5, and the front surface of the outer frame 2 is completely closed by the door frame 5 and the decorative cover 23. It has become so. The outer frame 2, the main body frame 3, and the door frame 5 are arranged so that their upper ends are substantially aligned, and the main body frame 3 and the door frame 5 can be rotated at a position on the left end front side of the outer frame 2. The right end of the main body frame 3 and the door frame 5 moves to the front side with respect to the outer frame 2 so as to be in an open state.

  Further, the pachinko gaming machine 1 has a game area 1100 into which a game ball is driven through a substantially circular game window 101 in front view, and projects forward to the lower side of the game window 101. In this way, two upper plates 301 and lower plates 302 are arranged vertically. In addition, a handle device 500 for the player to operate is disposed at the lower right corner of the front surface of the door frame 5, and the player holds the handle device 500 in a state where game balls are stored in the upper plate 301. When the rotation operation is performed, the game ball in the upper plate 301 is driven into the game area 1100 of the game board 4 with a hitting strength corresponding to the rotation angle, and a game can be played.

  The game window 101 of the door frame 5 is closed by a transparent glass unit 590 so that the player can visually recognize the inside of the game area 1100, but the player inserts a hand or the like into the game area 1100 to play the game. The game balls and obstacle nails in the area 1100, various winning holes and bonuses cannot be touched.

[2. Overall structure of outer frame]
Next, the outer frame 2 installed in the island facility of the game hall will be described with reference to FIG. FIG. 4 is a front perspective view of the outer frame. As shown in FIG. 4, the outer frame 2 includes upper and lower upper and lower frame plates 10 and 11 that extend in the horizontal direction, left and right side frame plates 12 and 13 that extend in the vertical (vertical) direction, and respective frame plates. And four connecting members 14 that connect the end portions of 10, 11, 12, and 13 and connecting the frame plates 10, 11, 12, and 13 with the connecting member 14 to form a vertically long rectangular shape ( (Square shape). The upper frame plate 10 and the lower frame plate 11 in the outer frame 2 are formed of a solid material (for example, wood, plywood, etc.) having a predetermined thickness. Note that an upper support fitting 20 described later is attached to the upper surface and the front surface of the left end portion of the upper frame plate 10.

  On the other hand, the side frame plates 12 and 13 are light metal molds (for example, aluminum alloys) having a constant cross-sectional shape. In addition, a plurality of grooves extending in the vertical direction are formed on the outer side surface and the inner side surface of the side frame plates 12 and 13, and work is performed when the pachinko gaming machine 1 is installed in the pachinko island facility of the game hall. The pachinko gaming machine 1 can be easily held by a person's finger and the design of the appearance can be enhanced.

  The outer frame 2 is arranged so as to face the upper support fitting 20 fixed to the upper surface of the left end of the upper frame plate 10 and the lower support plate 20 and is fixed to a predetermined position inside the lower portion of the left side frame plate 12. A support bracket 21, a reinforcement bracket 22 arranged to support the lower surface of the lower support bracket 21 and fixed to connect the left and right side frame plates 12 and 13, and a decorative cover fixed to the front surface of the reinforcement bracket 22 23. The upper support fitting 20 and the lower support fitting 21 are for pivotally supporting the main body frame 3 and the door frame 5 so as to be opened and closed. A shaft support pin 633 (see FIG. 5) of an upper shaft support bracket 630 in the main body frame 3 to be described later is detachably engaged with the support hole 20c in the upper support bracket 20. A main body frame shaft support formed on a main body frame shaft support bracket 644 of the main body frame 3, which will be described later, is inserted into the support protrusion 21d of the lower support bracket 21. After the main body frame 3 is inserted into the support hole of the main body frame shaft support bracket 644, the main body frame 3 can be simply mounted by locking the shaft support pin 633 of the upper shaft support bracket 630 of the main body frame 3 in the support hole 20c. It can be pivotally supported so that it can be opened and closed.

  Further, the outer frame 2 has two closing plates 24 and 25 (see FIG. 1) attached and fixed inside the right side frame plate 13 with a predetermined distance apart in the vertical direction. These closing plates 24 and 25 are formed in a substantially L shape in plan view. The closing plates 24 and 25 are hook portions 1054 and 1065 (see FIG. 1) of a locking device 1000 (locking device) attached along the open side of the main body frame 3 when the main body frame 3 is closed with respect to the outer frame 2. As will be described in detail later, by inserting a key into the cylinder lock 1010 of the lock device 1000 and rotating it to one side, the hook portions 1054 and 1065 and the closing plates 24 and 25 are connected to each other. The engagement is released and the closed state of the main body frame 3 with respect to the outer frame 2 can be released.

[3. Overall structure of main frame]
Next, the main body frame 3 provided on the front side of the outer frame 2 so as to be freely opened and closed will be described with reference to FIGS. 5 and 6. FIG. 5 is a front perspective view of the main body frame, and FIG. 6 is a rear perspective view of the substrate unit in the main body frame. As shown in FIG. 5, the main body frame 3 forms a skeleton of the main body frame 3 and penetrates in the front-rear direction and has a main body frame base 600 having a rectangular game board holding port 601 for holding the game board 4. An upper shaft support bracket 630 and a lower shaft support bracket 640 that are respectively attached to the upper and lower ends of the left end of the main body frame base 600 and are pivotally supported by the outer frame 2 and pivotally support the door frame 5; A hitting device 650 for driving a game ball into a game area 1100 of the game board 4 attached to the lower front surface of the main body frame base 600, and a game to the upper plate 301 of the tray unit 300 attached to the rear side of the main body frame base 600. A prize ball unit 700 for paying out a ball, and when the door frame 5 is attached to the front surface of the main body frame base 600 and the door frame 5 is opened with respect to the main body frame 3, the prize ball unit 700 is moved to the dish unit 300 of the door frame 5. It includes a ball outlet opening and closing unit 790 to shut off the flow of skill sphere, the.

  The main body frame 3 is attached to the lower rear surface of the main body frame base 600, and includes various control boards and power supply boards 851 for controlling electrical components provided in the door frame 5 and the main body frame 3 except the game board 4. Are combined into a unit board unit 800, a back cover 900 that covers the rear opening of the game board holding port 601 in the main body frame base 600, and a side security plate 950 that covers the left end of the main body frame base 600 when viewed from the front. And a locking device 1000 that is attached to the right end portion of the main body frame base when viewed from the front and that locks the main body frame 3 with respect to the outer frame 2 and opens and closes the door frame 5 with respect to the main body frame 3.

[3-1. Body frame base]
Next, the main body frame base 600 will be described. The main body frame base 600 is integrally formed of a synthetic resin, and the outer shape in front view is a vertically long rectangular shape along the outer shape of the door frame 5, and is formed to have a predetermined amount of depth in the front-rear direction. Has been. The main body frame base 600 has a game board holding port 601 through which the inside of about 3/4 of the whole from the upper part to the lower part penetrates in a rectangular shape in the front-rear direction and can fit and hold the outer periphery of the game board 4, and the main body frame A U-shaped front end frame portion 602 that forms the outer periphery of the front end excluding the left side of the base 600 when viewed from the front, and is recessed backward from the front surface of the front end frame portion 602, and from the lower end of the door frame base body 110 in the door frame 5 to the rear. The protruding door frame protruding piece 110c (see FIG. 1), the upper bent protruding piece 167 (see FIG. 1) protruding to the rear of the upper reinforcing sheet metal 151 in the reinforcing unit 150 of the door frame 5, and the open side reinforcing sheet metal 153. And an engaging groove 603 into which an open-side outer bent protruding piece 164 (see FIG. 1) protruding rearward is inserted and engaged.

  Further, the main body frame base 600 extends from the lower side of the game board holding port 601 to the lower end of the main body frame base 600 and is recessed from the front end of the front end frame portion 602 to the rear side by a predetermined amount and spread in a plate shape in the left-right direction. 604 and a peripheral wall portion 605 that protrudes rearward inside the front end frame portion 602 and forms an inner peripheral wall of the game board holding port 601. The peripheral wall portion 605 connects the free end portions (upper and lower left end portions in front view) of the U-shaped front end frame portion 602 so that the outer shape of the main body frame base 600 has a frame shape. It has become.

  In addition, the main body frame base 600 forms a lower side of the game board holding port 601 at the upper end of the lower rear wall part 604, and a game board placement part 606 on which the game board 4 is placed, and the game board placement part 606. A positioning protrusion 607 that protrudes upward from substantially the center in the left-right direction and engages with the out-ball discharge groove of the game panel 1150 in the game board 4, and is formed at a predetermined position on the right inner wall when viewed from the front in the peripheral wall portion 605. A game board locking portion to which the tool 1120 is fastened, and a plurality of upper end regulating ribs 609 arranged in the left-right direction in a plate shape that hangs downward from the upper inner wall of the peripheral wall portion 605 and whose lower ends can come into contact with the upper end of the game board 4 And. The positioning protrusion 607 of the main body frame base 600 can be engaged with the out-ball discharge groove of the game board 4 to restrict the lower end of the game board 4 from moving in the left-right direction and the rear direction. Yes. Further, the game board locking portion can restrict the right side of the game board 4 from moving in the front-rear direction when the game board stopper 1120 of the game board 4 is locked. . Although the details of the left side of the game board 4 when viewed from the front will be described later, the movement in the front-rear direction is restricted by the positioning member 956 of the side security plate 950.

  In addition, the main body frame base 600 is formed at a position where the lower rear wall portion 604 is recessed one step further to the rear side than the front surface of the front end frame portion 602. The ball striking device 650 is attached from the front side so that the firing solenoid 654 of 650 is housed in the solenoid housing recess. In a state in which the ball hitting device 650 is attached to the front surface of the lower rear wall portion 604, a foul space 626 that extends leftward and downward is formed on the left side of the front view of the ball hitting device 650 from the upper end of the shot rail 660. It is like that. In the present embodiment, when the door frame 5 is closed with respect to the main body frame 3, the foul ball inlet 542e (see FIG. 1) in the foul cover unit 540 is positioned below the foul space 626. The game ball descending the foul space 626 is received by the foul ball inlet 542e of the foul cover unit 540 and discharged to the lower plate 302 (see FIG. 7) in the plate unit 300.

  Further, the main body frame base 600 is formed in a plurality of openings in a rectangular shape in the front-rear direction on the left side of the left and right center of the lower rear wall 604 in the front view, and a plurality of openings on the upper side of the opening and the left and right sides in the front view. And a through hole 615 penetrating the through hole. The opening portion of the main body frame base 600 is closed from the front side by a relay terminal plate cover 692, and the board unit attached to the rear surface of the lower rear wall portion 604 through the opening 692 a of the relay terminal plate cover 692. The 800 main door relay terminal plate 880 and the peripheral door relay terminal plate 882 face the front side.

  Further, the main body frame base 600 detects the opening of the door frame 5 with respect to the main body frame 3 on the lower front surface of the substantially circular cylinder lock through hole 611 penetrating in the front-rear direction at the upper right end of the lower rear wall 604 in front view. A door frame opening switch 618 is attached, and when the door frame 5 is opened (opened) with respect to the main body frame 3, the pressing is released and the opening of the door frame 5 can be detected. It is like that. Further, the main body frame base 600 is provided with a main body frame opening switch 619 for detecting the opening of the main body frame 3 with respect to the outer frame 2 on the lower rear surface from the position where the door frame opening switch 618 is attached. When the main body frame 3 is opened (opened) with respect to the outer frame 2, the pressing is released and the opening of the main body frame 3 can be detected.

[3-2. Upper shaft support bracket and lower shaft support bracket]
Next, the upper shaft bracket 630 and the lower shaft bracket 640 will be described. The upper shaft support bracket 630 and the lower shaft support bracket 640 are respectively attached to the bracket mounting portions on the upper left and lower rear ends of the main body frame base 600 using a predetermined screw to attach the door frame 5 to the main body frame 3. The main frame 3 can be pivotally supported with respect to the outer frame 2 so as to be openable and closable.

  The upper shaft support bracket 630 is attached to the upper bracket attachment portion of the main body frame base 600 and has a plate-like attachment portion 631 extending in the vertical and horizontal directions, and a plate-like front extension extending forward from the upper end of the attachment portion 631. Portion 632, a shaft support pin 633 projecting upward from the vicinity of the front end of the front extension portion 632, and a shaft pin 155 of the door frame 5 disposed on the left side of the shaft support pin 633 in front view (FIG. 7). And the door frame shaft support hole 634 penetrating in the up-down direction, and the front end of the front extension 632 hangs downward from the front end and restricts the rotation end of the door frame 5 toward the open side. And a stopper. In the upper shaft support 630, the attachment portion 631, the front extension portion 632, and the stopper are integrally formed by bending a single metal plate.

  The lower shaft support bracket 640 is disposed below the door frame shaft support bracket 642 for supporting the door frame 5 and supports the main body frame 3 with respect to the outer frame 2. The main body frame shaft support bracket 644 is provided. The door frame shaft support bracket 642 in the lower shaft support bracket 640 is attached to the lower bracket mounting portion of the main body frame base 600 and extends forward from the lower end of the mounting portion. A plate-like front extension 642b, a door frame shaft support hole 642c through which a shaft pin 157 (see FIG. 7) of the door frame 5 is inserted in the vertical direction near the front end of the front extension 642b, and the front And a stopper 642d that is erected upward from the left end portion of the extension portion 642b when viewed from the front and restricts the rotation end of the door frame 5 toward the open side. The door frame shaft support 642 is integrally formed with a mounting portion, a front extension 642b, and a stopper 642d by bending a single metal plate.

  Further, the main body frame shaft support bracket 644 in the lower shaft support bracket 640 is attached to the lower bracket mounting portion of the main body frame base 600 and extends forward and downward from the lower end of the mounting portion. A front extending portion 644b that protrudes, and a main body frame shaft support hole that penetrates in the vertical direction in the vicinity of the front end of the front extending portion 644b are provided. The main body frame shaft support 644 is also integrally formed with an attachment portion and a front extension portion 644b by bending a single metal plate.

  The lower shaft bracket 640 is in a state where the mounting portion of the door frame shaft bracket 642 and the mounting portion of the main body frame shaft bracket 644 are overlapped (contacted) in the front-rear direction. The front extension part 642b and the front extension part 644b of the main body frame shaft support metal 644 are attached to the lower metal attachment part of the main body frame base 600 in a state of being separated by a predetermined distance in the vertical direction.

  The upper shaft support 630 and the lower shaft support 640 are attached to the main body frame base 600, and the shaft support pin 633 of the upper shaft support 630 and the main body frame shaft support hole of the lower shaft support 640 are coaxial. The body frame shaft support hole of the body frame shaft support bracket 644 in the lower shaft support bracket 640 is fitted to the support protrusion 21d (see FIG. 4) of the lower support bracket 21 in the outer frame 2. The front extension portion 644b of the main body frame shaft support bracket 644 is placed on the support protruding piece 21c (see FIG. 4) of the lower support bracket 21, so that the shaft of the upper shaft support bracket 630 is inserted. By inserting the support pin 633 into the support hole 20c (see FIG. 4) of the upper support fitting 20 in the outer frame 2, the main body frame 3 can be pivotally supported with respect to the outer frame 2 so as to be opened and closed. It is like that.

  Further, the upper shaft support bracket 630 and the lower shaft support bracket 640 are attached to the main body frame base 600, and the door frame shaft support hole 634 of the upper shaft support bracket 630 and the door frame shaft support hole of the lower shaft support bracket 640. 642c is positioned coaxially with the door frame so that the shaft pin 157 of the door frame 5 is inserted into the door frame shaft support hole 642c of the door frame shaft support bracket 642 in the lower shaft support bracket 640. 5 is mounted on the front extension 642b of the door frame shaft bracket 642, and the shaft pin 155 of the door frame 5 is placed on the door frame of the upper shaft bracket 630. The door frame 5 can be pivotally supported with respect to the main body frame 3 so as to be openable and closable by being inserted into the pivotal support hole 634. In the present embodiment, the shaft pin 155 on the upper side of the door frame 5 is slidable in the vertical direction. When the shaft pin 155 is inserted into the door frame shaft support hole 634 of the upper shaft support 630, the shaft pin 155 is inserted. Is once slid downward so that the upper shaft support portion 156 of the door frame 5 and the front extension portion 632 of the upper shaft support fitting 630 overlap vertically, and then the shaft pin 155 is slid upward. It can be inserted into the door frame shaft support hole 634.

[3-3. Hitting ball launcher]
Next, the hit ball launching device 650 will be described. The hitting ball launching device 650 is mounted so that the metal plate launch base 652 is mounted at a predetermined position on the front surface of the lower rear wall portion 604 in the main body frame base 600, and the rotary drive shaft 654a projects forward from the lower rear surface of the launch base 652. Firing solenoid 654, a hitting ball 656 fixed to the rotation drive shaft 654a of the firing solenoid 654 so as to be integrally rotatable, a tip 658 fixed to the tip of the hitting ball 656, and a predetermined movement path of the tip 658 A firing rail 660 extending diagonally to the upper left when viewed from the front and attached to the front surface of the firing base 652, and a tip 658 at the tip of the hitting ball 656 passes between the firing rail 660 and the top of the firing rail 660. A ball stopper that holds the game ball at the base end of the firing rail 660 while forming a gap through which the game ball cannot pass at the same time. 662 and a stopper for restricting the ball hitting ball 656 (tip 658) from rotating toward the shooting rail 660 from the hitting position where the game ball held at the base end of the shooting rail 660 by the ball stopper piece 662 can be hit. 664.

  The firing solenoid 654 of the ball striking device 650 is not shown in detail, but the rotational drive shaft 654a reciprocates with a strength (speed) corresponding to the rotational operation angle of the handle device 500. . Further, the hitting ball basket 656 of the hitting ball launching device 650 has a fixed portion 656a fixed to the rotation drive shaft 654a of the launch solenoid 654, and a gentle arc extending from the fixed portion 656a, and the tip is centered on the rotation drive shaft 654a. On the other hand, a hook portion 656b with the hook tip 658 fixed to the tip at a normal direction, a stopper portion 656c extending to the opposite side of the hook portion 656b with the fixing portion 656a interposed therebetween, and a stopper portion 656c capable of contacting the stopper 664 It has. When the stopper portion 656c of the hitting ball basket 656 is in contact with the stopper 664, the tip of the tip 658 is rotated to the firing rail 660 side from the hitting position (the rotation end in the counterclockwise direction when viewed from the front). Being regulated.

  When the hitting ball launcher 650 is attached to the lower rear wall portion 604 of the main body frame base 600, the upper end of the firing rail 660 is substantially the center in the left-right direction, that is, the upper end of the lower rear wall portion 604, that is, the game board mounting portion. 606 (the lower side of the game board holding port 601) is located below and has a predetermined width in the left-right direction between the lower end of the outer rail 1111 in the game board 4 held by the game board holding port 601. Thus, a foul space 626 extending downward is formed. The hit ball launching device 650 can hit the game ball into the game area 1100 of the game board 4 by firing the game ball so as to jump over the foul space 626 on the left side of the front view from the launch rail 660. It has become. In a state where the door frame 5 is closed with respect to the main body frame 3, the foul ball inlet 542e of the foul cover unit 540 attached to the door frame 5 is positioned below the foul space 626. A game ball that has become a foul ball without being driven into the area 1100 falls in the foul space 626, is received by the foul ball inlet 542 e, and is discharged to the lower plate 302.

[3-4. Prize ball unit]
Next, the prize ball unit 700 will be described. In the pachinko island facility in the hall where the pachinko gaming machine 1 is installed, the game balls supplied from the pachinko island facility side to the pachinko gaming machine 1 are stored, and the upper plate 301 of the pachinko gaming machine 1 is based on a predetermined payout instruction. To pay out. The prize ball unit 700 has a prize ball base 710 attached to the rear surface of the main body frame base 600 and a prize ball tank attached to the upper rear surface of the prize ball base 710 and receiving and storing game balls supplied from the Pachinko island equipment side. 720, a tank rail unit 730 arranged below the prize ball tank 720 and arranged to send the game balls stored in the prize ball tank 720 to the downstream side, and the game balls arranged by the tank rail unit 730 The prize ball device 740 to be paid out based on the payout instruction, and the game balls paid out by the prize ball device 740 can be guided to the upper plate 301 of the tray unit and are paid out when the upper plate 301 is full of game balls. And a full tank branching unit 770 capable of branching and guiding the game ball to the lower plate 302 side.

  The prize ball unit 700 includes an external terminal board 784 attached to the rear surface of the prize ball base 710 and an external terminal board cover 786 that covers the rear side of the external terminal board 784.

[3-4-1. Prize ball tank]
In the prize ball tank 720, the outer periphery of the bottom wall portion 721 is surrounded by an outer peripheral wall portion 722, and a predetermined amount of game balls can be stored on the bottom wall portion 721. The prize ball tank 720 is inclined so that the upper surface of the bottom wall portion 721 is lowered toward the discharge port 723 so that the game ball on the bottom wall portion 721 rolls toward the discharge port 723. It has become.

  The prize ball tank 720 includes two ball leveling members 727 that are pivotally supported by the shaft portion 725. One end side of the ball leveling member 727 is pivotally supported by the shaft portion 725 and holds a weight inside, and the other end side is suspended by its own weight. The ball leveling member 727 hangs down in a tank rail unit 730, which will be described later, so that game balls circulating in the tank rail unit 730 can be leveled and aligned.

[3-4-2. Tank rail unit]
The tank rail unit 730 includes a tank rail 731 disposed below the prize ball tank 720 and extending long in the left-right direction. The tank rail 731 has a bowl-like shape with a predetermined depth opened upward, and has a width (depth) in which the game balls can be aligned in two lines in the front-rear direction. The bottom is inclined so as to be low.

  The tank rail unit 730 is connected to the alignment gear 732 rotatably supported on the upper portion of the discharge port of the tank rail 731, the gear cover 733 covering the upper portion of the alignment gear 732, and the right end of the gear cover 733 as viewed from the front, A ball retainer plate 734 that closes the upper portion of the rail 731; a ball stop piece 735 that can move forward and backward in the tank rail 731 and stop the game ball in the tank rail 731 from rolling toward the outlet; It is equipped with. Two alignment gears 732 are provided side by side in the front-rear direction so as to correspond to the two flow paths of the game balls partitioned in two rows by the partition wall of the tank rail 731.

[3-4-3. Prize ball device]
The prize ball device 740 is for paying out the game balls discharged and supplied from the discharge port of the tank rail unit 730 to the upper plate 301 of the plate unit 300 based on a predetermined payout instruction. The prize ball device 740 has a predetermined width that communicates with a supply passage that opens to the upper end and extends to a position slightly lower than the center in the vertical direction with a width that is slightly wider than the outer shape of the game ball. A distribution space having a space, a prize ball passage that opens into the left side of the rear view when bent in a substantially square shape and communicates with the lower left side (open side) of the rear side of the distribution space, and the right side of the rear side of the distribution space (Axis support side) It has a ball passage that communicates with the lower end and extends downward and opens at the lower end. The supply passage, the distribution space, the prize ball passage, and the ball removal passage are formed in a state opened rearward.

  The prize ball device 740 is meshed with the first gear fixed to the rotating shaft of the payout motor 744 and disposed behind the motor support plate, the second gear meshing with the first gear, and the second gear. The third gear that rotates together with the third gear and the dispensing rotator as a sprocket disposed in the distribution space and the dispensing rotator are fixed to the opposite side so as to be integrally rotatable with the third gear interposed therebetween. A rotation detecting board having a plurality of (three in the present embodiment) detection slits formed at equal intervals in the direction, and a ball break switch 750 for detecting the presence or absence of a game ball in the supply passage; A counting switch 751 for detecting a game ball flowing down in the prize ball passage, a rotation angle switch 752 for detecting a detection slit formed in a rotation detection board that rotates integrally with the payout rotating body, and a rotation angle switch 752 Hold A rotational angle switch substrate 753 includes payout motor 744, burn out switch 750, a counting switch 751, and the rotation angle prize balls casing substrate 754 that relays the connection between dispensing the below-described control board and the switch 752, the.

  The payout rotator as a sprocket has three recesses each having a size capable of accommodating one game ball at equal intervals in the circumferential direction. The balls are housed in the recesses one by one and can be paid out to the prize ball passage or the ball passage passage side. Further, the three detection slits formed on the rotation detecting board that rotates integrally with the payout rotating body are equally formed (every 120 degrees) on the outer periphery of the rotation detecting board, and correspond to between the recesses of the payout rotating body. The rotation position of the payout rotating body can be detected by detecting the detection slit with the rotation angle switch 752. In the present embodiment, the rotation between the detection slits (120 degrees) of the rotation detection board (dispensing rotary body) is designed to correspond to the 18-step rotation of the dispensing motor 744.

  The award ball device 740 is configured such that when the payout rotating body is rotated counterclockwise by the payout motor 744, the game ball in the supply passage is paid out to the award ball passage. The game balls paid out to the prize ball passage by the rotation of the body are counted by the counting switch 751 one by one and then delivered to the prize ball passage. On the other hand, when the ball removal operation member is operated by a hall clerk or the like, the game balls in the supply passage are paid out to the ball removal passage. The pachinko gaming machine 1 can be discharged from the lower end of the passage to the rear outside of the pachinko gaming machine 1 through a full tank branching unit 770 described later.

[3-4-4. Full tank branch unit]
The full tank branching unit 770 is formed in a box shape that becomes lower as it goes from the rear end to the front end. The full branching unit 770 opens upward substantially at the center in the left-right direction at the upper end of the rear end, and the award of the prize ball device 740 is obtained. A prize ball receiving hole for a game ball flowing down the ball passage, a branching space that is arranged below the prize ball receiving hole and extends in the left-right direction, and a game from directly under the prize ball receiving hole in the branching space to the front side A normal path for guiding the ball, a normal ball outlet 774 that releases the game ball flowing through the normal path to the front and opened at the front right end of the front view, and the right side in the rear view rather than just below the prize ball receiving opening in the branch space A full tank passage that guides the game ball from the raised position to the front side, and a full ball exit 776 that discharges the game ball that has circulated through the full tank passage to the front and opens to the left in front of the normal ball outlet 774. ing.

  In addition, the full tank branching unit 770 includes a ball receiving port that receives a game ball that opens upward at the left end portion of the rear end upper portion when viewed from the front and flows down the ball passage of the prize ball device 740, and a ball receiving portion. A ball passage that guides the game ball received in the mouth to the front side, and a game ball that has circulated through the ball passage is released forward and at the left end of the front view at a position behind the normal ball outlet 774 and the full ball exit 776 And an open ball outlet.

  When the full tank branching unit 770 is in a state in which the door frame 5 is closed with respect to the main body frame 3, the normal ball outlet 774 and the full tank outlet 776 are respectively connected to the first ball inlet 542 a of the foul cover unit 540 in the door frame 5. And the second ball inlet 542c (see FIG. 1) and communicates with each other, and the game ball released from the normal ball outlet 774 passes through the first ball inlet 542a of the foul cover unit 540, The game balls supplied to the upper plate 301 of the unit 300 and released from the full ball outlet 776 are supplied to the lower plate 302 of the plate unit 300 through the second ball inlet 542c of the foul cover unit 540. ing. The ball outlet is formed so as to communicate with the upper right side upper end of the main body frame base ball passage in the main body frame base 600, and the game ball discharged from the ball outlet is the main body frame of the main body frame base 600. It is to be delivered to the base ball passage.

  When a game ball is further paid out from the prize ball unit 700 (prize ball device 740) in a state where the upper plate 301 of the dish unit 300 is full of game balls, the upper ball ball is raised from the first ball exit of the foul cover unit 540. The game balls that can no longer come out to the side of the tray 301 stagnate in the first ball passage of the foul cover unit 540, and eventually fill up the normal passage upstream through the normal ball outlet 774 in the full tank branching unit 770. In this state, the game ball that has entered the branch space from the prize ball receiving port cannot normally enter the passage, and starts moving in the lateral direction in the branch space, and the game ball that has moved in the horizontal direction is full. So as to enter the tongue passage and be supplied from the full bulb exit to the lower plate 302 of the dish unit 300 through the second bulb inlet 542c, the second bulb passage, and the second bulb outlet of the foul cover unit 540. It has become.

[3-5. Substrate unit]
Next, the substrate unit 800 will be described. As shown in FIG. 6, the substrate unit 800 includes a substrate unit base 810 attached to the rear surface of the lower rear wall portion of the main body frame base 600, a speaker box 820 attached to the rear left side of the substrate unit base 810, and a substrate. A power supply board box holder 840 attached to the rear face of the unit base 810, and a power supply board box attached to the rear face of the power supply board box holder 840 and having a rear end substantially flush with the rear end of the speaker box 820 850, a payout control board box 860 attached to the rear face of the power supply board box 850 and the speaker box 820, and a terminal board box 870 attached to the rear face of the speaker box 820 so as to cover the left end of the payout control board box 860 when viewed from the front. And board unit base A main door relay terminal plate 880 and the peripheral door relay terminal plate 882 is attached to the front surface 10, and a.

  The power supply board box holder 840 has a discharge ball receiving portion 841 that receives a game ball that is opened upward and discharged from the out ball discharge portion of the game board 4 downward from the left and right front in front view, A discharge passage 842 that guides and discharges the game ball received by the discharge ball receiving portion 841 downward and the front of the discharge passage 842 and the side of the discharge ball receiving portion 841 (right side in front view) is opened forward and upward. A power supply board box holder 840 is formed so that the entire rear surface of the power supply board box holder 840 is recessed to the front side, and a box housing portion capable of housing the front end of the power board board box 850 is provided.

  The power supply board box holder 840 is configured such that the open front end side of the discharge passage 842 is closed by the rear surface of the substrate unit base 810 and the opening of the substrate unit base 810 faces the discharge passage 842. The main body frame base 600 is circulated through the main body frame base ball passage formed on the rear surface of the lower rear wall portion of the main body frame base 600 and flows down to the rear side of the substrate unit base 810 through the opening of the substrate unit base 810. The game ball and the game ball discharged from the out ball discharge portion of the game board 4 and received by the discharge ball receiving portion 841 can be discharged to the lower rear side of the pachinko gaming machine 1 through the discharge passage 842. It has become.

  The power supply board box 850 is formed in a horizontally long box shape with the front open, and includes a power supply board 851 attached so as to close the front end opening. The power supply board box 850 accommodates various electronic components attached to the power supply board 851, and externally transfers heat from the electronic parts and the like through a plurality of slits 850a formed on the upper surface and the lower surface. Can be released. A power switch 852 attached to the power supply board 851 faces the rear surface of the power supply board box 850.

  The payout control board box 860 includes a thin box-shaped box base 861 that is horizontally long and opened at the rear, a thin box-shaped cover 862 that is fitted into the box base 861 from the rear side and opened at the front, and a box base 861. And a payout control board 4110 attached to the rear surface and covered by the cover 862. Further, the payout control board box 860 includes a plurality of separation cutting portions 863 that protrude outward from the left end in the rear view and are formed on both the box base 861 and the cover 862, and are provided at one location of the plurality of separation cutting portions 863. The box base 861 and the cover 862 are fixed by caulking. Thus, in order to separate the box base 861 and the cover 862, the separation and cutting portion 863 must be cut so that the box base 861 and the cover 862 cannot be separated. When the dispensing control board box 860 is opened, the trace remains. . Therefore, it can be determined whether or not the dispensing control board box 860 has been opened and closed illegally. In the present embodiment, the payout control board box 860 can be opened and closed only once for inspection or the like.

  Further, the payout control board box 860 is configured such that an operation switch 860a (error release unit) attached to the payout control board 4110, an inspection output terminal 860c, and the like face rearward through the cover 862. The payout control board box 860 has various connection terminals for connecting to the main control board 4100 and the like facing rearward through the cover 862. The operation switch 860a is operated when clearing the RAM built in the microprocessor of the payout control board 4110 and the RAM built in the microprocessor of the main control board 4100 when the power is turned on, or after the power is turned on. When an error is reported, it is operated to cancel the error, and the RAM clearing function at power-on and the power-on (time period for functioning as RAM clearing have elapsed) And a function of canceling an error in (after). A detailed description of this point will be described later.

  The terminal board box 870 includes a board base 871 attached to the rear face of the speaker box 820, a frame peripheral relay terminal board 868 attached to the rear face of the board base 871 and fixed with a peripheral panel relay terminal 872 toward the rear, and a board base. A board for lending device connection terminal plate 869 such as a game ball attached to the rear surface of 871 and having CR unit relay terminal 873 fixed to the rear, so that peripheral panel relay terminal 872 and CR unit relay terminal 873 face the rear side. And a substrate cover 874 that covers the rear side of the base 871. The peripheral panel relay terminal 872 is for connecting to a frequency indicator for displaying the operating state of the pachinko gaming machine 1 provided on the pachinko island facility side where the pachinko gaming machine 1 is installed. The terminal 873 is for connection with a CR unit installed adjacent to the pachinko gaming machine 1.

  The main door relay terminal plate 880 and the peripheral door relay terminal plate 882 are provided in the door frame 5, the peripheral control board 4140 provided in the game board 4 attached to the main body frame 3, the payout control board 4110 of the board unit 800, and the like. The connection to the handle device 500, various decorative boards, the operation unit 400, and the like is relayed. The main door relay terminal plate 880 and the peripheral door relay terminal plate 882 are attached to the board mounting portion formed on the front surface of the board unit base 810 so as to face the front side of the main body frame base 600, Wiring extending from the door frame 5 can be connected.

  The main door relay terminal plate 880 and the peripheral door relay terminal plate 882 are covered with a relay terminal plate cover 692 attached to the front surface of the main body frame base 600, and the front side of the relay terminal plate cover 692 is also covered. Only the connection terminal faces the front side through the opening 692a, so that the front surface of the main body frame 3 has a clean appearance.

  Further, the main door relay terminal plate 880 includes a ball rental button 361, a return button 362, a remaining rental display portion 363, a potentiometer 512 of the handle device 500, and a touch in the tray unit 300 arranged on the door frame 5 side. This is for relaying the connection between the switch 516, the firing stop switch 518, and the full tank switch 550 of the foul cover unit 540 and the payout control board 4110 disposed on the main body frame 3 side. It should be noted that the ball rental button 361, the return button 362, the remaining rental display unit 363, the potentiometer 512 of the handle device 500, the touch switch 516, the firing stop switch 518, and the full switch 550 of the foul cover unit 540 are provided. The description will be described later.

  In addition, the peripheral door relay terminal plate 882 is provided in the decorative units 200, 240, and 280 arranged on the door frame 5 side, various decorative boards provided in the dish unit 300 and the operation unit 400, and the operation unit 400. , For relaying the connection between the dial drive motor 414, various switches for detecting the operation of the dial operation unit 401 and the pressing operation unit 405, and the peripheral control board 4140 of the game board 4 arranged on the main body frame 3 side It is. The decorative units 200, 240, and 280 arranged on the door frame 5 side, the various decorative boards provided in the dish unit 300 and the operation unit 400, the dial drive motor 414 provided in the operation unit 400, and the dial operation. The various switches that detect the operation of the unit 401 and the pressing operation unit 405 will be described later.

[4. Overall structure of door frame]
Next, the door frame 5 that can be freely opened and closed on the front side of the main body frame 3 will be described with reference to FIG. FIG. 7 is a perspective view of the door frame. As shown in FIG. 7, the door frame 5 includes a door frame base unit 100 having a gaming window 101 whose outer shape is formed in a vertically long rectangular shape and whose inner peripheral shape is a slightly vertically long circular shape (elliptical shape), A right side decoration unit 200 attached to the right outer periphery of the gaming window 101 on the front surface of the frame base unit 100, and a left side facing the right side decoration unit 200 and attached to the left outer periphery of the gaming window 101 on the front surface of the door frame base unit 100. The decoration unit 240, the upper decoration unit 280 attached to the upper outer periphery of the gaming window 101 in front of the door frame base unit 100, and the door frame base unit disposed below the lower ends of the right side decoration unit 200 and the left side decoration unit 240. And a pair of side speaker covers 290 attached to the front surface of 100.

  The door frame 5 is attached to the front side of the door frame base unit 100 at the lower part of the gaming window 101, the operation unit 400 attached to the upper center of the dish unit 300, and the right side of the dish unit 300. An upper platen side liquid crystal display device 470, and a capacitance type liquid crystal display device 470 which is provided so as to cover the display area of the upper platen side liquid crystal display device 470 (second display device) and has a contact surface capable of detecting the contact state. The door frame base unit 100 is sandwiched between the touch panel 480 (contact type input device), the handle unit 500 that is attached to the lower right corner of the door frame base unit 100 through the dish unit 300, and performs a game ball driving operation. A foul cover unit 540 which is disposed on the rear side of the dish unit 300 and is attached to the rear surface of the door frame base unit 100; A ball feeding unit 580 attached to the rear surface of the door frame base unit 100 on the right side of the handle cover unit 540, and a glass unit 590 attached to the rear side of the door frame base unit 100 so as to close the game window 101. ing. In this embodiment, the touch panel 480 is 4.3 inches and has a resolution of 10 × 20. A touch panel drive substrate 450 that performs detection control of the contact state of the touch panel 480 is disposed near the lower side of the upper dish side liquid crystal display device 470 and is accommodated in the dish unit 300.

[4-1. Door frame base unit]
Next, the door frame base unit 100 will be described. The door frame base unit 100 has a door frame base main body 110 having a gaming window 101 having an outer shape formed in a vertically long rectangular shape and penetrating in the front-rear direction and having an inner periphery formed in a substantially elliptical shape. An upper bracket 120 that is attached to the upper center of the gaming window 101 on the front surface of the base body 110 and fixes the upper decorative unit, and a pair of sides that are attached to the lower left and right outer sides of the gaming window 101 on the front surface of the door frame base body 110. The speaker 130 and a handle bracket for supporting the handle device 500 attached to the lower right corner when viewed from the front on the front surface of the door frame base main body 110 are provided.

  The door frame base unit 100 includes a metal frame-shaped reinforcing unit 150 (see FIG. 1) fixed to the rear side of the door frame base main body 110, and the gaming window 101 on the rear surface of the door frame base main body 110. A security cover 180 (see FIG. 1) attached so as to cover the lower part, and a glass unit locking member 190 (see FIG. 1) attached to a predetermined position on the outer periphery of the gaming window 101 on the rear surface of the door frame base body 110. 1), and a launch cover 191 (see FIG. 1) that is disposed on the left side (open side) from the center in the left-right direction in rear view and is attached to the rear surface of the door frame base body 110 along the lower end of the gaming window 101. A main control board mounted on the rear surface of the door frame base body 110 below the launch cover 191 and provided in a potentiometer 512 of the handle device 500 described later and a game board 4 described later. A handle relay terminal plate 192 (see FIG. 1) that relays the connection to the 100, a handle relay terminal plate cover 193 (see FIG. 1) that covers the rear side of the handle relay terminal plate 192, and a center in the left-right direction. A frame decoration drive amplifier board 194 that is disposed on the opposite side to the launch cover 191 and the handle relay terminal plate 192 (on the right side (axial support side) from the center in the left-right direction in rear view) and attached to the rear surface of the door frame base body. (See FIG. 1) and a frame decoration drive amplifier board cover 195 (see FIG. 1) covering the rear side of the frame decoration drive amplifier board 194.

  The frame decoration drive amplifier board 194 is electrically connected to the side speakers 130 and the upper speakers of the left and right side decoration units 200 and 240, and is also electrically connected to a peripheral control board 4140 provided in the game board 4 described later. And an amplification circuit that amplifies the acoustic signal sent from the peripheral control board 4140 and outputs the amplified signal to each speaker 130. Although not specifically shown, in the present embodiment, the decorative units 200, 240, 280, various decorative boards provided in the dish unit 300 and the operation unit 400, and the dial drive motor provided in the operation unit 400. In addition, the wiring for electrically connecting the switch, the handle relay terminal plate 192, the ball rental unit 360 of the dish unit 300, etc., and the payout control board 4110, the peripheral control board 4140, etc. After being bundled together at the right side (axial support side) position, it extends rearward and is connected to the main door relay terminal plate 880 and the peripheral door relay terminal plate 882 of the main body frame 3. In addition, a plurality of various LEDs are mounted on the various decorative boards provided in the decorative units 200, 240, 280, the dish unit 300, and the operation unit 400 as light emitting decorative LEDs.

[4-1-1. Door frame base body]
The door frame base body 110 is formed in a vertically long frame shape with a synthetic resin, and is formed in such a manner that the gaming window 101 having a vertically long and substantially elliptical shape penetrating in the front-rear direction is offset upward as a whole. Has been. The gaming window 101 is formed in a smooth curved shape in which the left and right side and upper inner peripheral edges are continuous, whereas the lower inner peripheral edge is formed in a straight line extending left and right. In addition, a rectangular notch that allows insertion of the first ball outlet of the foul cover unit 540 is formed on the shaft support side (left side in front view) on the inner peripheral edge of the lower side of the game window 101 in the door frame base body 110. A speaker mounting portion for mounting and fixing the side speaker 130 disposed on the left and right outer sides of the lower side of the gaming window 101, a right side (open side) end of the front surface disposed at the lower right corner portion in front view and bulging forward The handle mounting portion for tilting the handle bracket to tilt backward, the wiring passage opening through which the wiring from the handle device 500 can pass through at a predetermined position of the handle mounting portion, and the upper side of the handle mounting portion. Thus, a lock hole 116 is formed which is formed in a cylindrical shape extending short forward and into which a cylinder lock 1010 described later can be inserted. The door frame base body 110 has an upper side formed by the game window 101 and widths on the left and right sides of an upper reinforcing sheet metal 151, a pivot supporting side reinforcing sheet metal 152, and an open side reinforcing sheet metal 153 of a reinforcing unit 150 described later. The gaming window 101 is formed as large as possible with respect to the size of the door frame base body in a front view.

[4-1-2. Reinforcement unit]
The reinforcing unit 150 includes an upper reinforcing sheet metal 151 (see FIG. 1) attached along the back side of the upper side of the door frame base body 110 and a shaft support attached along the back side of the side of the shaft support side of the door frame base body 110. Side reinforcing sheet metal 152 (see FIG. 1), an open side reinforcing sheet metal 153 (see FIG. 1) attached along the back side of the open side of the door frame base body 110, and the gaming window 101 of the door frame base body 110 And a lower reinforcing metal plate 154 (see FIG. 1) attached along the back surface of the lower side, and they are fastened to each other with screws, rivets or the like to form a square shape.

  An upper shaft support portion 156 having a shaft pin 155 slidably provided in an upper and lower direction on an upper surface and a lower shaft support portion 158 having a shaft pin 157 on its lower surface at upper and lower ends of the shaft support side reinforcing sheet metal 152. Integrated. The upper and lower shaft pins 155 and 157 are pivotally supported by the upper shaft bracket 630 and the lower shaft bracket 640 formed on the upper and lower sides of the body frame 3, so that the door frame 5 is attached to the body frame 3. So that it can be freely opened and closed.

  In addition, a hook cover 165 that contacts the door frame hook portion 1041 of the locking device 1000 is provided at the lower rear side of the opening-side reinforcing sheet metal 153. The hook cover 165 engages with the door frame hook portion 1041 of the lock device 1000 (locking device) attached along the open side of the main body frame 3 when the door frame 5 is closed with respect to the main body frame 3. By inserting a key into the cylinder lock 1010 of the lock device 1000 and rotating it in one direction (rotating in the direction opposite to the direction in which the main body frame 3 is opened with respect to the outer frame 2), the door frame hook portion 1041 and the hook cover 165 are disengaged, and the closed state of the door frame 5 with respect to the main body frame 3 can be released.

[4-2. Dish unit]
Next, the dish unit 300 will be described. The tray unit 300 includes an upper plate 301 and a lower plate 302 for storing the game balls paid out from the prize ball device 740, and the game balls stored in the upper plate 301 are shot through the ball feeding unit. Can be supplied to the device 650.

  The shape of the upper dish upper panel 314 of the dish unit 300 is formed in a curved shape so as to protrude forward from the left to the center in a front view, and forward straightly from the center to the right. Protrusively formed. An operation unit attachment portion to which the operation unit 400 is attached is formed at the upper center of the dish unit 300, and a liquid crystal attachment portion 314d for attaching the upper plate side liquid crystal display device 470 is formed on the right side of the operation unit attachment portion. . The shape of the upper plate upper panel 314 on which the liquid crystal mounting portion 314d is formed is formed in a plate shape, and for example, when a player presses the portion downward with a hand, the upper plate 314d bends downward. When the pressing force exceeds a predetermined force, the upper plate upper panel 314 is broken. This is because the upper plate side liquid crystal display device 470 is expensive, and when the player presses the hand on the screen of the upper plate side liquid crystal display device 470, the force is received by the upper plate upper panel 314. The upper plate side liquid crystal display device 470 is prevented from being damaged by bending the upper plate upper panel 314. That is, a structure is adopted in which the upper plate upper panel 314 is damaged before the upper plate side liquid crystal display device 470 is damaged. In addition, when the upper plate upper panel 314 is damaged, the plate unit 300 is replaced. In this case, the upper plate side liquid crystal display device 470 is removed from the broken upper plate upper panel 314 and attached to the upper plate upper panel 314 of the plate unit 300 to be replaced for reuse.

  Further, the dish unit 300 includes an upper dish ball removal mechanism 340 for removing game balls stored in the upper dish 301 to the lower dish 302 in response to an operation of the upper dish ball removal button 341, and a lower dish ball removal button 354. The lower tray ball removing mechanism 350 for pulling down the game balls stored in the lower tray 302 in accordance with the operation of the lower tray ball through the lower tray ball removing hole 324b and the pachinko gaming machine 1 are not shown. A ball rental unit 360 for operating the CR unit.

[4-2-1. Operation unit]
The operation unit 400 is disposed on the front surface of the upper plate 301 at a substantially center in the left-right direction when viewed from the front. Operation part), and can accept the player's operation according to the gaming state, or the dial operation part 401 can be moved, not only the game ball driving operation to the player It is intended to be able to participate in production during the game. The rotation (rotation direction) of the dial operation unit 401 is detected by a rotation detection switch provided in the operation unit 400, and the operation of the pressing operation unit 405 is detected by a press detection switch provided in the operation unit 400.

  Further, the operation unit 400 can rotate the dial operation unit 401 in the clockwise direction or the counterclockwise direction by the driving force of the dial drive motor 414. Further, the operation unit 400 rotates the dial operation unit 401 step by step by the driving force of the dial drive motor 414 using a stepping motor, or when the player rotates the dial operation unit 401, Rotation can be assisted, it can be prevented from turning on purpose, or a click can be added to the rotation. Further, the operation unit 400 can vibrate the dial operation unit 401 by alternately repeating a rotation for rotating the dial drive motor 414 in small increments and a rotation for rotating in reverse.

[4-2-2. Rental unit]
The lending unit 360 includes a lending button 361 and a return button 362 that can be pressed backward, and a lending remaining display portion 363 between the lending button 361 and the return button 362. When the ball rental button 361 is operated, it is detected by the ball rental switch 365a, and when the return button 362 is operated, it is detected by the return switch 365b. The display content of the remaining frequency indicator 365c can be visually recognized through the rental remaining display portion 363. A CR unit lamp 365d is disposed adjacent to the remaining frequency indicator 365c so that the light emission mode of the CR unit lamp 365d can be visually recognized through the rental remaining display portion 363. The ball lending switch 365a, the return switch 365b, the remaining frequency indicator 365c, and the CR unit lamp 365d are mounted on the frequency display plate 365, and the frequency display plate 365 is attached to the inside of the ball rental unit 360. . When the ball rental unit 360 is pushed into the ball lending machine provided adjacent to the pachinko gaming machine 1 with a cash or prepaid card and the ball lending button 361 is pressed, a predetermined number of game balls are transferred to the dish unit. 300 can be lent out (paid out) into the top plate 301, and when the return button 362 is pressed, the balance of the loaned portion is drawn and the remaining cash or prepaid card is returned. ing. In addition, the remaining lending display section 363 displays the number of cash and prepaid cards remaining in the ball lending machine.

[4-3. Ball transport unit]
Next, the ball feeding unit 580 will be described. The ball feeding unit 580 can supply the game balls supplied from the upper plate 301 in the plate unit 300 one by one to the hitting ball launching device 650, and the game balls stored in the upper plate 301 are supplied to the upper plate ball. It can be pulled out to the lower pan 302 by operating the upper pan ball release button 341 of the pulling mechanism 340.

  The ball feeding unit 580 is an intrusion port in which game balls stored in the upper plate 301 of the plate unit 300 are supplied through the upper plate ball discharge port of the upper plate 301 and the ball opening of the door frame base body 110 and penetrate in the front-rear direction. And a box-shaped front cover that has a ball opening that opens below the intrusion opening and is open at the rear, and a box-like shape that closes the rear end of the front cover and opens the front, and penetrates in the front-rear direction The rear cover having a hitting ball supply port 582a for supplying the game ball that has entered from the intrusion port of the front cover to the hitting ball launcher 650, and the axis extending in the front-rear direction between the rear cover and the front cover. A ball removing member that is pivotally supported and has a partitioning portion for partitioning between the entrance and the ball outlet on the rear side of the front cover, and the game balls on the partitioning portion of the ball removing member are hit one by one on the rear cover. Up and down between the front cover and the rear cover before feeding to the supply port 582a And Tamaoku member rotatably supported around an axis extending to, and a Tamaoku solenoid 585 to rotate the Tamaoku member.

  When the ball feeding solenoid 585 is driven (ON state), the ball feeding member accepts one game ball, while when the ball feeding solenoid 585 is released (OFF state), the ball feeding member accepts it. The game ball is sent (supplied) to the hitting ball launching device 650 side.

[4-4. Handle device]
Next, the handle device 500 will be described. The handle device 500 is fixed to a handle bracket attached to the front surface of the door frame base main body 110, is cylindrical, and has a handle base whose front end bulges out in a direction perpendicular to the axis, and a handle base that is rotatable relative to the handle base. Arranged at the front of the front of the rotary handle main body 506, the front of the rotary handle main body 506, the front of the rotary handle main body 506 fixed to the front of the rear of the rotary handle main body and being rotatable integrally with the rear of the rotary handle main body. And a front end cover 508 that is fixed to the handle base and rotatably supports the front of the rotary handle main body 506 and the rear of the rotary handle main body in cooperation with the handle base.

  In addition, the handle device 500 is attached and fixed to the center of rotation in front of the rotary handle body so as to protrude from the front side to the rear side, and has a non-circular bearing portion at the rear end, and the shaft member bearing portion is fitted. A potentiometer 512 that has a detection shaft portion that can be rotated together and is non-rotatably fitted to the front surface of the handle base, and is fixed to the front surface of the handle base so that the potentiometer 512 is sandwiched between the handle base and the detection of the potentiometer 512 A switch support member having a through-hole through which the shaft portion can pass, a touch switch 516 attached to the rear surface of the switch support member, and a firing stop switch 518 attached to the touch switch 516 at a different position on the rear surface of the switch support member; A single-shot button that is pivotally supported with respect to the switch support member and operates the firing stop switch 518. And a handle that is arranged so as to cover the outer periphery of the shaft member and urges the front of the rotary handle body 506 and the rear of the rotary handle body to return to the original rotation position (rotation end in the counterclockwise direction when viewed from the front). And a return spring. The potentiometer 512 is for electrically adjusting the strength of launching the game ball toward the game area 1100 according to the rotational position of the front 506 of the rotary handle. In addition, after the rotary handle main body 506 and after the rotary handle main body, it is rotated from the original rotational position to the limit rotational position (rotation end in the clockwise direction when viewed from the front) that is the maximum rotational position in the clockwise direction when viewed from the front To do.

  Further, in the handle device 500, the potentiometer 512 is a variable resistor. When the front part 506 of the rotary handle and the rear part of the rotary handle body are rotated, the detection shaft portion of the potentiometer 512 is rotated via the shaft member. . Then, the internal resistance of the potentiometer 512 changes according to the rotational position (rotation angle) of the detection shaft portion, and the driving force of the firing solenoid 654 in the ball hitting device 650 changes according to the internal resistance of the potentiometer 512, so that the rotary handle A game ball is driven into the game area 1100 with a launch intensity corresponding to (a match with) the rotation angle of the front of the main body 506 and the rear of the rotary handle, that is, the rotation position of the front of the rotary handle main body 506 and the rear of the rotary handle. Yes.

[4-5. Foul cover unit]
Next, the foul cover unit 540 will be described. The foul cover unit 540 is attached to the rear surface below the game window 101 in the door frame base unit 100 and is played by a game ball paid out from the prize ball unit 700 or a hitting ball launcher 650. A game ball (foul ball) that has not reached the area 1100 is guided to the upper plate 301 or the lower plate 302 of the plate unit 300. The foul cover unit 540 includes a cover base that is open on the front side and has a plurality of game ball passages therein, and a front cover that closes the front end of the cover base.

  The cover base of the foul cover unit 540 has a first sphere inlet 542a that is disposed in the upper right corner when viewed from the rear and penetrates in the front-rear direction, and a first base that communicates with the first sphere inlet and expands to the right in the front view toward the front end of the cover base 542. One ball passage, a second ball inlet 542c arranged outside the first ball inlet 542a (on the right side in the rear view) and having a larger opening than the first ball inlet 542a, and communicated with the second ball passage and inside the cover base And a second sphere inlet 542c that extends downward and is inclined toward the lower right corner when viewed from the front. The first ball inlet 542a and the second ball inlet 542c are the normal ball outlet 774 and the full ball outlet 776 of the full tank branching unit 770 in the prize ball unit 700 in a state where the door frame 5 is closed with respect to the main body frame 3. Are formed at positions facing each other. In the second ball passage in the cover base, the height of the portion extending in the left-right direction along the lower end is about three times as high as the outer diameter of the game ball. An accommodating space that can be accommodated is formed.

  Further, the cover base 542 is arranged at a substantially upper center in the left-right direction and has a foul ball inlet 542e that opens upward, and a foul that communicates with the foul ball inlet 542e and can guide the game ball to the upper portion near the downstream of the second ball passage. And a ball passage. In addition, the cover base includes an opening / closing operation piece for operating the opening / closing shutter 792 of the bulb outlet opening / closing unit 790 on the lower rear surface of the second bulb entrance. When the door frame 5 is closed with respect to the main body frame 3, the opening / closing operation piece contacts the spherical contact portion of the opening / closing crank in the ball outlet opening / closing unit 790, thereby rotating the opening / closing crank and opening / closing the shutter 792. It can be in an open state.

  The front cover of the foul cover unit 540 is formed in a substantially plate shape that closes the front surface of the cover base. An outlet, and a second ball outlet that is disposed in the lower right corner of the front view and communicates with the downstream end of the second ball passage of the cover base 542 and penetrates in the front-rear direction. A first ball outlet of the front cover is connected to an upper plate ball supply port of the plate unit 300 through a notch portion of the door frame base unit 100. Further, the rear end of the lower tray ball supply bowl in the tray unit 300 is connected to the second ball outlet through the ball passage opening of the door frame base main body 110.

  The foul cover unit 540 transfers the game balls supplied from the normal ball outlet 774 of the full tank branching unit 770 in the prize ball unit 700 to the first ball inlet 542a from the first ball outlet to the dish unit 300 through the first ball passage. It can supply to the upper plate 301 through the upper plate ball supply port. Further, the foul cover unit 540 passes the game ball supplied from the full tank outlet 776 of the full tank branch unit 770 in the prize ball unit 700 to the second ball inlet 542c from the second ball outlet through the second ball passage. The plate unit 300 can be supplied to the lower plate 302 via the lower plate ball supply basket and the lower plate ball supply port.

  Further, in the foul cover unit 540, when the door frame 5 is closed with respect to the main body frame 3, the foul ball inlet 542e is positioned below the foul space 626 of the main body frame 3, and the ball hitting device When the game ball launched by 650 does not reach the game area 1100 and becomes a foul ball and falls in the foul space 626, the game ball is received by the foul ball inlet 542e. The foul cover unit 540 can discharge (supply) the game balls received at the foul ball inlet 542e from the second ball outlet to the lower plate 302 of the dish unit 300 through the foul ball passage and the second ball passage. It can be done.

  Further, the foul cover unit 540 forms an upstream (left side in front view) side surface of the accommodation space in the second ball passage and is pivotally supported by the cover base so as to be swingable by a game ball stored in the accommodation space. A member, a full tank switch 550 that detects the swing of the swing member, and a spring that biases the swing member in a non-detection state by the full switch 550. The swinging member is pivotally supported at the lower end with respect to the cover base, and the upper end is rotated to the left when viewed from the front. It comes to form. Further, the swing member is biased to a position where the swing member is in a substantially vertical state by a spring. Further, the swinging member is formed with a detection piece projecting outward on the side surface opposite to the accommodation space side, and this detection piece is detected by the full switch 550. That is, based on the detection signal from the full tank switch 550, it can be determined whether or not the game ball in which the accommodation space is stored is full.

[5. Overall configuration of game board]
Next, the overall configuration of the game board 4 will be described with reference to FIGS. FIG. 8 is a front view of the game board, and FIG. 9 is an exploded perspective view of the game board of FIG. As shown in FIGS. 8 and 9, the game board 4 has an outer rail 1111 and an inner rail 1112, and a game area 1100 in which a game ball as a game medium is driven when the player operates the handle device 500. A frame-shaped front component member 1110 that defines an outer periphery, and a position that is visible from the game window 101 of the door frame 5 to the player side when attached to the pachinko gaming machine 1 at the lower right corner of the front component member 1110 when viewed from the front. And a plurality of openings 1158 penetrating in the front-rear direction in a predetermined shape at positions corresponding to the game area 1100 and attached to the rear side of the front component member 1110 so as to close the game area 1100. A plate-like gaming panel 1150, a front unit 2000 attached from the front side to the opening 1158 of the gaming panel 1150, and a gaming panel A back unit 3000 is attached to the rear surface 150, and a.

  Further, the game board 4 is disposed between the game panel 1150 and the back unit 3000, and is inserted from the rear side of the game panel 1150 into a plurality of light-emitting decorative holes that penetrate the game panel 1150. A panel lens member 2500, a liquid crystal display device that is detachably attached to the rear side of the back unit 3000 and that can display a predetermined effect image that is visible from the player side according to the gaming state, and a lower part of the back unit 3000 Is provided with a board holder 1160 attached to the lower part of the rear surface of the game panel 1150 and a main control board box 1170 attached to the rear surface of the board holder 1160.

[5-1. Previous component]
Next, the front component member 1110 will be described. The front component member 1110 has a substantially rectangular shape whose outer shape can be inserted into the game board holding port 601 of the main body frame 3, and has an inner shape that penetrates in a front-rear direction in a substantially circular shape. The outer periphery of the region 1100 is partitioned. The front component member 1110 has an outer rail 1111 that extends in an arc shape from the lower left end toward the left side from the center in the left-right direction in a front view and extends to the upper right side through the center upper end in the left-right direction in the front view. An inner rail 1112 that is arranged substantially inside the outer rail 1111 along the outer rail 1111 and extends in an arc shape from the center lower part in the left-right direction in front view to the upper left part in the front view so as to smoothly continue from the lower end of the inner rail 1112 An inner peripheral rail 1113 extending in an arc shape to a position below the end (upper end) of the outer rail 1111 along the counterclockwise circumferential direction when viewed from the front, and the end (upper end) of the inner peripheral rail 1113 and the outer rail 1111 , The inner rail 1112 and the inner peripheral rail 1113, which can be contacted with the game ball rolling along the outer rail 1111. Is located at the lowermost end of the game area 1100 at the boundary of the outer area, and is supported by the upper end of the inner rail 1112 so as to be rotatable, and closes between the outer rail 1111. In this way, it is possible to rotate only between a closed position that extends upward from the upper end of the inner rail 1112 and an open position that rotates clockwise from the front and opens the outer rail 1111. And a backflow preventing member 1116 biased by a spring so as to return to the closed position side.

  When the front component member 1110 is in a state where the game board 4 is attached to the main body frame 3, the lower end opening between the outer rail 1111 and the inner rail 1112 is a launch rail 660 in the hitting ball launcher 650 of the main body frame 3 (FIG. 1). )). Between the lower end of the outer rail 1111 and the upper end of the launch rail 660, a space extending in the left-right direction and downward is formed, and the game ball launched along the launch rail 660 of the hit ball launcher 650 is Then, it jumps over the space and is driven between the outer rail 1111 and the inner rail 1112 from the lower end opening between the outer rail 1111 and the inner rail 1112. The game ball driven between the outer rail 1111 and the inner rail 1112 rolls upward along the outer rail 1111 according to the momentum, and the backflow prevention member 1116 pivotally supported on the upper end of the inner rail 1112 is used. The player can enter the game area 1100 by rotating it toward the open position against the biasing force.

  In addition, when the game ball is strongly hit by the hit ball launching device 650, the game ball that rolls along the outer rail 1111 in the game area 1100 comes into contact with the stop portion 1114 provided at the end of the outer rail 1111. The rolling direction of the game ball can be forcibly changed by the game ball coming into contact with the stop 1114, and the game ball rolls continuously from the outer rail 1111 to the inner rail 1113. It can be prevented from moving. Note that even if a game ball that has entered (injected into) the game area 1100 returns to between the outer rail 1111 and the inner rail 1112, the backflow prevention member 1116 returns to the closed position by the biasing force before that. Thus, the backflow prevention member 1116 prevents the backflow of the game ball.

  In addition, if the game ball that has been driven into the game area 1100 is not received by the start opening 2101, 2102 or the winning opening 2103, 2104, 2201, etc. of the table unit 2000, it flows down to the lower end of the game area 1100, The out-port guide surface 1115 at the boundary between the inner rail 1112 and the inner peripheral rail 1113 is guided to the out-port 1151 of the game panel 1150 and discharged from the out-port 1151 downward to the rear side of the game board 4. .

  On the other hand, if the game ball launched from the hitting ball launcher 650 cannot enter the game area 1100 beyond the backflow prevention member 1116 at the tip of the inner rail 1112, the outer rail 1111 and the inner rail 1112 A foul space 626 formed between the upper end of the firing rail 660 and the lower end of the outer rail 1111 from the lower end opening between the outer rail 1111 and the inner rail 1112. 1 (see FIG. 1) is dropped and is received by the foul ball inlet 542e (see FIG. 1) of the foul cover unit 540 attached to the door frame 5 located below the foul space 626. It is discharged to the lower plate 302 (see FIG. 7).

  Note that the outer rail 1111 in the front component member 1110 has a metal plate attached to the surface thereof, so that the wear resistance due to rolling of the game ball is enhanced and the game ball rolls smoothly. ing. In addition, the stopper 1114 has an elastic body such as rubber or synthetic resin on the surface, and even if the game ball rolls vigorously along the outer rail 1111 and collides, the impact is reduced. The game ball can be repelled inward.

  In addition, the front component member 1110 is spaced apart in the vertical direction at the left end when viewed from the front, is recessed from the front to the rear and is opened at the left end, and is spaced apart from the right end when viewed from the front in the vertical direction. A pair of game board stoppers 1120 arranged, a fixed recess 1121 which is disposed on the left side of the front view of the outer rail 1111 and opened downward and opened downward, and has an arcuate upper side and recessed from the front side, and a lower end of the front view And a ball passage cutout 1122 that is cut out in a rectangular shape extending in the left-right direction upward from the lower end. The positioning concave portion 1119 of the front component member 1110 is fitted with a positioning member 956 (see FIG. 5) attached to the inside of the side crime prevention plate 950 in the main body frame 3, thereby allowing the game board holding port 601 (see FIG. 5). It is possible to restrict the left end of the game board 4 inserted in the front view from moving in the front-rear direction. The game board stopper 1120 can be detachably locked to the game board locking portion of the main body frame base 600 in the main body frame 3, and the game board stopper 1120 is connected to the game board. By locking to the stop portion, the right end of the game board 4 inserted into the game board holding port 601 of the main body frame 3 can be restricted from moving in the front-rear direction.

  Further, the fixing recess 1121 of the front component member 1110 has a game board fixture 690 (see FIG. 5) pivotally supported on the front surface of the main body frame 3 in a state where the game board 4 is inserted into the game board holding port 601 of the main body frame 3. (See FIG. 5) is inserted into the game board fixing tool 690, and the game board fixing tool 690 allows the game board 4 to be inserted. The lower end of the head is restricted from moving forward. Further, the ball passage cutout portion 1122 of the front component member 1110 is formed with the same ball passage cutout portion 1152 at the same position of the game panel 1150, and the game board 4 is connected to the game board holding port 601 of the main body frame 3. In the inserted state, the front end of the full tank branching unit 770 (see FIG. 5) is inserted into the notches 1122 and 1152 for the ball passage.

  A function display unit 1180, which will be described later, is arranged at the lower right of the front component member 1110 when viewed from the front.

[5-2. Table unit]
Next, the front unit 2000 of the game board 4 will be described. The front unit 200 includes an attacker unit 2100 that is disposed at a substantially lower center in the left-right direction in the game area 1100 and above the out port 1151 and is supported by the front surface of the game panel 1150. And a side prize opening member 2200 supported along the front surface of the gaming panel 1150 and a frame-shaped center accessory 2300 disposed approximately at the center of the gaming area 1100 and supported by the gaming panel 1150. Yes.

  The front unit 2000 is inserted from the front side into the opening 1158 formed at a position corresponding to the gaming area 1100 in the gaming panel 1150, and is attached to the front surface of the gaming panel 1150. A portion protruding forward from the game panel 1150 is located in the game area 1100. As a result, the front unit 2000 comes into contact with the game ball that has been driven into the game area 1100 at an appropriate position, and together with the obstacle nail implanted on the front surface of the game panel 1150, Can be changed. The table unit 2000 can decorate the game area 1100.

[5-2-1. Attacker unit]
Next, the attacker unit 2100 of the table unit 2000 will be described. The attacker unit 2100 has a plurality of entrances (winning entrances) through which game balls driven into the game area 1100 can be received. Specifically, the attacker unit 2100 is arranged at a substantially central position in the left-right direction. A start port 2101, a lower start port 2102 disposed below the upper start port 2101, and a rectangular disposed below the lower start port 2102 and extending more in the left-right direction than the upper start port 2101 and the lower start port 2102 A large winning opening 2103 having a shape, and a general winning opening 2104 arranged slightly on the left and right sides of the large winning opening 2103 are provided. The game balls received in the upper start opening 2101, the lower start opening 2102, the big winning opening 2103, and the general winning opening 2104 are guided from the front side of the game panel 1150 to the rear side.

  The upper start port 2101 of the attacker unit 2100 is open on the upper side, so that game balls can always be received (winning). On the other hand, a pair of movable pieces 2106 that can be expanded by a start port solenoid 2105 (see FIG. 12) is disposed between the lower start port 2102 disposed below the upper start port 2101 and the upper start port 2101. In the state where the pair of movable pieces 2106 rises substantially vertically, the upper starting port 2101 and the pair of movable pieces 2106 make it impossible to receive the game ball into the lower starting port 2102, whereas the pair of movable pieces 2106 In a state where the piece 2106 is expanded in the left-right direction, a game ball can be received in the lower start port 2102. That is, the lower start opening 2102 is a variable winning opening by the pair of movable pieces 2106. It should be noted that the pair of movable pieces 2106 corresponds to a normal lottery result that is drawn based on detection of the passing of a game ball by the gate switch 2352 of the gate unit 2350 in the center accessory 2300 described later (the result of the normal lottery is “winning” ”) And is opened and closed by driving the start-up solenoid 2105.

  Further, the special winning opening 2103 of the attacker unit 2100 can be opened and closed by a horizontally-long rectangular opening / closing member 2107 that can close the opening. The opening / closing member 2107 is pivotally supported so that the lower side can be pivoted. In a substantially vertical state, the prize winning opening 2103 can be closed to make it difficult to receive a game ball, and the upper side can move forward. When it is rotated, the special winning opening 2103 is opened to make it easier to accept the game ball. The opening / closing member 2107 is in a state in which the big prize opening 2103 is closed in a normal gaming state, and a special lottery is drawn when a game ball is received (starts winning) into the upper start opening 2101 or the lower start opening 2102. Depending on the lottery result (when the result of the special lottery is “big hit” or “small hit”), the attacker solenoid 2108 (see FIG. 12) is driven to open and close.

  Furthermore, the general winning opening 2104 of the attacker unit 2100 is opened upward so that game balls can be received (winned) at all times.

  Although not shown in detail, the attacker unit 2100 has a lower start port switch 2109 for detecting a game ball received in the lower start port 2102 and a count switch for detecting a game ball received in the big winning port 2103. The game ball detected by the lower start port switch 2109 and the count switch 2110 is discharged onto the bottom wall portion of the substrate holder 1160. The back unit 3000 includes an upper start port switch 3022 for detecting a game ball received in the upper start port 2101 and a general winning port switch 3020 for detecting a game ball received in the general winning port 2104. .

[5-2-2. Side prize opening member]
Next, the side prize opening member 2200 of the front unit 2000 will be described. The side winning opening member 2200 is inserted from the front side with respect to the opening 1158 formed on the left side of the opening 1158 in which the attacker unit 2100 is inserted and fixed at the lower left side from the center in the left-right direction of the game panel 1150. Above, two fixed to the front surface of the gaming panel 1150 and facing each other along the outer periphery of the gaming area 1100 so as to line up with the general winning port 2104 on the left side of the front view in the attacker unit 2100 A general winning opening 2201 is provided. These two general winning holes 2201 are opened upward so that game balls can be received (winning) at all times, and the game balls received in the general winning holes 2201 are guided from the front side of the game panel 1150 to the rear side. Then, it is detected by a general prize opening switch 3020 provided in the back unit 3000 described later.

  Further, the side prize opening member 2200 is arranged at a position where the left end is substantially in contact with the outer periphery of the game area 1100 at the upper left end of the side prize opening member 2200, and is inclined so as to become lower toward the right end. The shelf portion 2202 and the first shelf portion 2202 are arranged on the opposite side and the lower side with the two general winning holes 2201 sandwiched therebetween, and the center side in the left-right direction of the game area 1100 (the lower start opening 2102 and the big winning opening of the attacker unit 2100) A second shelf 2203 that becomes lower toward the game area 1100), and the first shelf 2202 can bring the game balls that have flowed down along the outer periphery of the game area 1100 toward the center of the game area 1100. It can be done.

  Note that the two general winning ports 2201 are arranged on the right side of the right end of the first shelf 2202, and even if the game balls are brought closer to the center of the game area 1100 by the first shelf 2202, There is a possibility of winning a prize in the general winning opening 2201. A third shelf 2204 that is inclined so as to become lower toward the center side of the game area 1100 is also provided on the upper side between the two general winning ports 2201.

  The side prize port member 2200 is formed so as to have a light-transmitting property as a whole, and although detailed illustration is omitted, a side prize port decoration board is provided on the rear side of the second shelf 2203. At the same time, a side lamp decorative board 3014 in a back unit 3000, which will be described later, is arranged on the rear side of the side prize opening member 2200. Can be decorated with light emission.

[5-2-3. Center character]
Next, the center accessory 2300 of the table unit 2000 will be described. The center accessory 2300 is inserted from the front side into an opening 1158 that is formed so as to penetrate substantially the center of the game panel 1150, and is fixed to the front surface of the game panel 1150. It is formed in a frame shape with a size that occupies most of the area 1100, and the outer peripheral surface on the right side when viewed from the front is in an arc shape so that a gap slightly larger than the outer diameter of the game ball is formed between the outer periphery of the game area 1100 The left outer peripheral surface is formed on a substantially straight line that hangs down so that a region having a predetermined width is formed between the outer peripheral surface of the game region 1100 and the outer periphery.

  The center accessory 2300 is an upper shelf portion 2301 that is inclined so as to become lower toward the left side from the position slightly on the right side in the center in the left-right direction on the outer peripheral surface on the upper side of the front wall portion located on the front surface of the game panel 1150. When a game ball driven into the upper part of the game area 1100 flows down to the upper shelf 2301, it flows down to the left of the center accessory 2300, and on the right side of the upper shelf 2301. The game balls that have flowed down (invaded) flow down to the lower part of the game area 1100 through the right side of the center bonus 2300. In other words, when a game ball is driven so that the game ball enters the right side of the upper shelf 2301 in the center accessory 2300, the chance of enjoying the flow of the game ball is reduced. It is possible to appropriately adjust the length, and to maintain a sense of tension and to suppress a loose game.

  Further, the center accessory 2300 has entered a warp inlet 2302 in which a game ball flowing down the game area 1100 can enter the outer peripheral surface on the left side of the front wall portion located on the front side of the game panel 1150 and the warp inlet 2302. A warp exit (not shown) that releases the game ball into the frame, and a game ball released from the warp exit rolls in the left-right direction, and then releases it into the game area 1100 above the attacker unit 2100. And a stage 2310 formed on the upper surface of the lower side in the frame in 2300.

  Although the detailed illustration of the stage 2310 in the center accessory 2300 is omitted, the game ball released from the warp outlet is supplied, and the game ball is placed from the first stage on the front side of the first stage. And a second stage that is capable of releasing a game ball into the game area 1100. This stage 2310 is formed in a curved surface shape such that the approximate center in the left-right direction is lowered. Further, a chance entrance 2313 into which a game ball can enter is formed at the rear side of the center of the first stage in the left-right direction. The game is discharged from the exit 2314 into the game area 1100. The chance exit 2314 is disposed immediately above the upper start opening 2101 in the attacker unit 2100, and the game ball released from the chance exit 2314 is received (wins) by the upper start opening 2101 with a high probability. ing.

  The stage 2310 in the center accessory 2300 is formed of a transparent member, and through this stage 2310, the decorative body arranged below the stage 2310 in the back unit 3000 is visible from the player side. It has become.

  Further, the center accessory 2300 is a transparent member extending leftward so as to be substantially in contact with the inner rail 1112 above the warp entrance 2302 on the left outer peripheral surface of the front wall portion located on the front side of the game panel 1150. An arch portion 2315 is further provided. The arch portion 2315 extends in a thin plate shape from a substantially front end of the front wall portion, and forms a space through which a game ball can pass between the arch portion 2315 and the front surface of the game panel 1150. Thereby, the game ball that is driven into the upper part of the game area 1100 and guided to the left of the center accessory 2300 by the upper shelf 2301 flows down to the downstream side through the rear side of the arch part 2315. .

  Further, the center accessory 2300 includes a gate portion 2350 that detects the passage of a game ball in the vicinity of the arch portion 2315 on the outer peripheral surface on the left side of the front wall portion located on the front side of the game panel 1150. The gate portion 2350 detects the game entrance that has entered the gate entrance and the gate entrance that allows the game ball flowing down the game area 1100 to be intruded on the outer peripheral surface of the left side of the front wall portion and above the arch portion 2315. A gate switch 2352 for discharging the game ball detected by the gate switch 2352 from the outer peripheral surface of the front wall portion to the game area 1100. In the present embodiment, although detailed illustration is omitted, the gate outlet of the gate portion 2350 is formed at the same height as the arch portion 2315, and the game ball detected by the gate switch 2352 is The portion 2315 can be seen as if diving.

[5-3. Panel lens member]
Next, the panel lens member 2500 of the game board 4 will be described. The panel lens member 2500 has a plurality of light emitting elements formed so as to penetrate in the front-rear direction in a circular or X shape at a position outside the opening 1158 in which the center accessory 2300 is inserted in the gaming area 1100 of the gaming panel 1150. The decorative hole is used for luminescent decoration. The panel lens member 2500 includes a transparent upper panel lens 2510 corresponding to a plurality of light emitting decoration holes formed on the upper left side of the outer periphery of the center accessory 2300, and a plurality of light emitting decoration holes disposed on the rear side of the upper panel lens 2510. An upper panel lens substrate on which the LED is mounted, a transparent lower panel lens 2520 corresponding to a plurality of light emitting decoration holes formed on the lower left side of the outer periphery of the center accessory 2300, and a rear side of the lower panel lens 2520. And a lower panel lens substrate on which a plurality of LEDs are mounted.

  The upper panel lens 2510 and the lower panel lens 2520 in the panel lens member 2500 protrude forward from the plate-like lens base portion, and have a plurality of rod-shaped insertion light guides that have substantially the same shape as the light emitting decoration hole to be inserted. Department. In a state where the insertion light guide portion is inserted into the light emitting decoration hole of the game panel 1150 from the rear side, the tip is formed so as to substantially coincide with the front surface of the game panel 1150, and the game flows down the front surface of the game panel 1150. The ball is not affected as much as possible.

  The panel lens member 2500 can illuminate and decorate the area where the game ball flows even if an opaque game panel 1150 such as a veneer plywood is used by appropriately emitting the LEDs of the upper panel lens substrate and the lower panel lens substrate. In addition to being able to show the player the decoration of the gaming panel 1150 that has never been seen before, the pachinko gaming machine 1 can be conspicuous and differentiated from other pachinko gaming machines.

[5-4. Back unit]
Next, the back unit 3000 of the game board 4 will be described. The back unit 3000 is attached and fixed to the rear surface of the gaming panel 1150, and is a 12-inch (image size 800 × 600 dots) liquid crystal display device 1900 (hereinafter referred to as “the back of the gaming panel 1150”). 4.3 inches (image size 480 ×), which is supported at the upper left, lower left, lower right and upper right of the front side of the liquid crystal display device 1900. 272 dots) four movable liquid crystal display devices 1925a to 1925d are supported on the upper and lower left sides of the liquid crystal display device 1900 in the back box 3001. The upper portion disposed on the front side of the movable liquid crystal display device 1925a to be moved and the movable liquid crystal display device 1925d disposed on the upper right side. Character unit arranged on the front side of unit 3100 and movable liquid crystal display device 1925c arranged on the lower right side and movable liquid crystal display device 1925d arranged on the right side of liquid crystal display device 1900 in back box 3001 3400 and a gear decoration body unit disposed on the front side of the movable liquid crystal display device 1925a disposed on the left and upper left of the liquid crystal display device 1900 in the back box 3001 and the movable liquid crystal display device 1925b disposed on the lower left. 3500.

  Further, the back unit 3000 is disposed at a position corresponding to the side prize opening member 2200 in the front unit 2000 attached to the front surface of the game panel 1150 near the lower left front end of the back box 3001, and a plurality of LEDs are mounted on the surface. A side lamp decoration board 3014 and a game ball attached to the lower front end of the back box 3001 and received in the general winning port 2201 of the side winning port member 2200, and a game received in the left general winning port 2104 in the attacker unit 2100 A left guiding member 3016 for guiding the ball downward, and a right guiding the game ball disposed on the right side of the left guiding member 3016 and received in the upper start port 2101 and the right general winning port 2104 on the attacker unit 2100. A guiding member 3018.

  Further, although not shown in detail, the back unit 3000 is disposed in the lower rear portion of the back box 3001 and has a horizontally-long rectangular lamp drive board box 3423 that accommodates the lamp drive board 4170, and a lower part of the lamp drive board box 3423. The motor drive board box 3430 having a horizontally long rectangular shape that is disposed on the side and accommodates the motor drive board 4180 and the lamp drive board box 3423 and the motor drive board box 3430 fixed to the rear side of the back box 3001 are arranged on the left side when viewed from the rear. A panel relay terminal plate 4161, a horizontally-long rectangular upper resistance substrate disposed at the upper rear side of the back box 3001, and a lock member attached to the rear side of the back box 3001 for detachably holding the liquid crystal display device 1900. It is equipped with.

  The back unit 3000 is not illustrated in detail, but the movable liquid crystal display devices 1925a to 1925d are respectively arranged in the vertical and horizontal directions on the rear upper left, rear lower left, rear lower right, and rear upper right of the back box 3001. Movable devices 1925aa, 1925ba, 1925ca, and 1925da that can move are provided. Each of these movable devices 1925aa to 1925da is provided with two stepping motors and a conversion mechanism that converts the rotational motion of the output shafts of the two stepping motors into linear motion, and each of the movable devices 1925aa to 1925da is provided with each. By driving two stepping motors (a total of eight stepping motors), the movable liquid crystal display devices 1925a to 1925d can be independently moved in the vertical and horizontal directions.

  In this embodiment, the back unit 3000 can be viewed from the player side through the frame of the center accessory 2300 in the front unit 2000, and each unit 3100, 3400 shaped into a predetermined shape. , 3500, etc., the concept of the pachinko gaming machine 1 can be characterized. Further, the back unit 3000 is configured such that each of the units 3100, 3400, 3500 and the movable liquid crystal display devices 1925a to 1925d can be moved independently or in conjunction with each other depending on the game state. It is possible to suggest a change in the gaming state or the arrival of a chance to the player, and the player can be entertained.

[5-4-1. Back box]
Next, the back box 3001 of the back unit 3000 will be described. The back box 3001 is formed in a box shape with the front side open, and is provided with a plurality of flange-like fixing parts 3001a projecting outward at the front end, and on the rear side of the game panel 1150 through the fixing parts 3001a. It is supposed to be fixed. Further, the back box 3001 is formed with a rectangular opening substantially at the center of the rear wall, and the liquid crystal display device 1900 supported on the rear side through this opening can be viewed from the player side. Further, the back box 3001 is for attaching and fixing the units 3100, 3400, 3500, the movable liquid crystal display devices 1925a to 1925d in the vertical and horizontal directions, the movable devices 1925aa to 1925da, the substrates 3014, and the like. The attachment portion is formed at an appropriate position.

  Although not shown, the back box 3001 inserts and locks one fixing piece 1902 that protrudes outward from the left and right sides of the liquid crystal display device 1900 to the right of the opening in the rear view (right side in the rear view). A liquid crystal support portion is provided, and a lock member is attached to the left side of the opening in the rear view. The other fixing piece 1902 (left side in the rear view) of the liquid crystal display device 1900 is supported by the lock member. A display device 1900 is detachably attached to the rear side of the back box 3001.

[5-4-2. Guide member]
Next, the left guide member 3016 and the right guide member 3018 will be described. The left guiding member 3016 guides and discharges the game balls received in the general winning port 2201 of the side winning port member 2200 and the general winning port 2104 on the left side of the attacker unit 2100 downward through different flow paths. Each of the flow paths is provided with a general winning opening switch 3020 for detecting the passage of a game ball. On the other hand, the right guiding member 3018 guides and discharges the game balls received in the upper start opening 2101 and the right general winning opening 2104 on the attacker unit 2100 downward through different flow paths to the vicinity of the lower end. The upper start opening switch 3022 is provided in the flow path corresponding to the upper start opening 2101, and the general winning opening switch 3020 is provided in the flow path corresponding to the right general winning opening 2104. The right guide member 3018 is provided with a magnetic detection switch 3024 that can detect magnetism.

  The game balls guided downward by the left guide member 3016 and the right guide member 3018 are discharged onto the bottom wall portion of the substrate holder 1160 and are discharged downward from the game board 4 from the out ball discharge portion 1161 of the substrate holder 1160. It has become so.

[5-4-3. Upper unit]
Next, the upper unit 3100 will be described. The upper unit 3100 is formed to be horizontally long as a whole, and is attached and fixed to the upper side of the opening facing the liquid crystal display device 1900 in the back box 3001. The upper unit 3100 is disposed on the front surface at a substantially central position in the left-right direction and is circular in a front view, and a lifting mechanism that moves up and down the rotational decoration body unit 3200. 3250, a swing decorative body unit 3300 disposed substantially at the center in the left-right direction on the rear side of the lifting mechanism 3250, and a movable ceiling unit 3350 disposed on the left and right sides of the swing decorative body unit 3300. ing.

  The rotating ornament body unit 3200 can be moved up and down by an elevating mechanism 3250 between a raised position located above the liquid crystal display device 1900 and a lowered position located substantially in the center of the liquid crystal display device 1900. It has become. The rotating decorative body unit 3200 is configured such that a rotating decorative body formed in the shape of a shuriken arranged on the front surface is rotated, and the rotation radius of the rotating decorative body is increased by the centrifugal force by rotating. It is like that.

  In addition, the rotating ornament body unit 3200 not only rotates at the end but also protrudes outward in the radial direction, so that the rotation radius of the entire rotating ornament body expands and the appearance changes greatly. It is possible to make it possible to give a strong impact on the player, to delight the player and to suppress the interest in the game, and to attract the player's interest strongly Therefore, the pachinko gaming machine 1 can be easily selected as a pachinko gaming machine that is greatly differentiated from other pachinko gaming machines.

  The swing ornament body unit 3300 includes swing ornament bodies disposed on the left and right sides of the swing ornament body unit 3200 adjacent to the rotational ornament body unit 3200 located at the ascending position. The body can be swung to the left and right at the same time.

  The movable ceiling unit 3350 is provided with plate-like ceiling decoration bodies that extend in the horizontal direction at the left and right ends of the upper unit 3100. This ceiling decoration body is formed so as to be rotatable around an axis extending in the left-right direction with the front end side as a center, so that the rear end side of the ceiling decoration body is lowered in a descending direction according to the gaming state. It has become.

[5-4-4. Character unit]
Next, the character unit 3400 of the back unit 3000 will be described. The character unit 3400 includes a character body that is shaped like a ninja and is three-dimensionally shaped, and the character body moves in the left-right direction from the right end position toward the center side according to the gaming state. Can be done. Further, when the character body of the character unit 3400 moves in the left-right direction, the character body 3400 is rotated by a predetermined angle around an axis extending in the up-down direction along with the movement.

  Further, the character body of the character unit 3400 can reciprocate around an axis in which the head extends in the left-right direction, and can reciprocate around the axis in which the right arm extends in the up-down direction. Can be done. Thus, by reciprocating the head, it is possible to perform an action as if the character is scolding. Further, by reciprocating the right arm in the horizontal direction, it is possible to perform an action as if the character is throwing a shuriken.

[5-4-5. Gear decoration body unit]
Next, the gear decoration body unit 3500 of the back unit 3000 will be described. The gear decoration body unit 3500 includes a gear-shaped gear decoration body that can be rotated around an axis extending in the left-right direction and is arranged in a plurality of vertical directions. It is designed to rotate.

[5-4-6. Liquid crystal display device]
Next, the liquid crystal display device 1900 of the game board 4 will be described. The liquid crystal display device 1900 is detachably attached to the rear surface of the back box 3001 of the back unit 3000, and can display a predetermined effect image according to the gaming state. The liquid crystal display device 1900 includes a fixed piece 1902 that protrudes outward from the left and right sides, and is attached to the back box 3001 via the fixed piece 1902.

  Although not shown in detail, the liquid crystal display device 1900 includes a peripheral board box 1905 that houses a peripheral control board 4140 and a liquid crystal output board 3420, which will be described later, on the rear side.

[5-4-7. Movable liquid crystal display]
Next, the movable liquid crystal display devices 1925a to 1925d of the game board 4 will be described with reference to FIG. FIG. 10 is a diagram showing an outline of a mode in which the movable liquid crystal display device is movable in the vertical and horizontal directions. The movable liquid crystal display devices 1925a to 1925d are in positions that are difficult to see when the pachinko gaming machine 1 is viewed from the front side in the standby state at the original positions (the movable liquid crystal display devices 1925a and 1925b have gear decorations). The body unit 3500 is in a standby state with the rear left upper side and the rear lower left side as the original positions, and the movable liquid crystal display devices 1925c and 1925d are in the standby state with the rear right lower side and the rear upper right side of the character unit 3400 as the original positions. )

  As described above, the movable liquid crystal display devices 1925a to 1925d are arranged in the vertical and horizontal directions by the movable devices 1925aa, 1925ba, 1925ca, and 1925da provided on the rear upper left, the rear lower left, the rear lower right, and the rear upper right. It is configured to be independently movable in each direction. Among a plurality of modes in which the movable liquid crystal display devices 1925a to 1925d are moved, as an example, the front surface of the liquid crystal display device 1900 is moved from each original position toward the center of the display area of the liquid crystal display device 1900. A mode in which the entire display area of the liquid crystal display device 1900 is covered by appearing in FIG.

  The movable liquid crystal display devices 1925a to 1925d start to move from the respective original positions toward the center of the display area of the liquid crystal display device 1900 by the movable devices 1925aa, 1925ba, 1925ca, and 1925da, as shown in FIG. As shown in FIG. 10B, the liquid crystal display device 1900 emerges from the four corners on the front surface of the liquid crystal display device 1900, and as shown in FIG. A single liquid crystal display device is combined to cover the entire display area of the liquid crystal display device 1900.

  Thereafter, the movable liquid crystal display devices 1925a to 1925d are combined as one liquid crystal display device at the center of the display area of the liquid crystal display device 1900 by the movable devices 1925aa, 1925ba, 1925ca, and 1925da as shown in FIG. As shown in FIG. 10 (b), the liquid crystal display device 1900 passes through the four corners, and returns to the original position and waits as shown in FIG. 10 (a). It becomes a state.

[6. Function display unit]
Next, the function display unit 1180 in the game board 4 will be described with reference to FIG. This function display unit 1180 is mounted and disposed at a predetermined position of the front component member 1110. FIG. 11 is an enlarged front view showing the function display unit in the game board in a state of being attached to the pachinko gaming machine.

  As shown in an enlarged view in FIG. 11, the function display unit 1180 is a game state display composed of one LED for displaying a game state that is changed by a game ball driven into the game area 1100 at the left end when viewed from the front. An upper special symbol memory display 1184 for displaying the number of holdings relating to the reception of the game ball to the upper start port 2101, which consists of two LEDs arranged vertically on the right side of the game machine 1183 and the game status indicator 1183, Upper special symbol comprising one 7-segment LED for displaying the first special lottery result arranged as the first special symbol, which is arranged on the right side of the special symbol memory display 1184 and is drawn by receiving the game ball into the upper start port 2101 Display 1185 and the second special symbol placed on the upper right of the upper special symbol display 1185 and drawn by receiving a game ball into the lower start port 2102 Lower start indicator 1186 composed of one lower 7-segment LED for displaying the separate lottery result as a second special symbol, and two LEDs arranged in the vertical direction on the right side of the lower special symbol display 1186 And a lower special symbol memory display 1187 for displaying the number of holdings relating to the reception of the game ball in 2102.

  The display unit 1181 of the function display unit 1180 displays the number of suspensions related to the passage of the gate unit 2350 by the game balls that are arranged in a circular arc substantially along the inner peripheral rail 1113 from directly above the lower special symbol display 1186. The normal symbol memory display 1188 composed of the four LEDs and the normal lottery result which is placed under the normal symbol memory display and the game ball passes through the gate portion 2350 is displayed as a normal symbol. The normal symbol display 1189 made of one LED and the normal symbol memory display 1188 are arranged side by side diagonally to the upper right, and the first prize lottery result or the second special lottery result is “big hit”, and the opening / closing of the big prize opening 2103 A round indicator 1190 composed of two LEDs for displaying the number of repetitions of the pattern (number of rounds).

  The gaming status indicator 1183 is a full-color LED that can change the emission color of red, green, and orange, and various gaming statuses (in combination with lighting / flashing) For example, a normal state, a probability variation state, a time shortening state, a probability variation short state, a big hit gaming state, a small hit gaming state, etc.) can be displayed.

  When the upper special symbol display 1184 cannot display the first special symbol in the upper special symbol display 1185 in a variable manner, when the game ball is received in the upper start port 2101, the start of the variable display is suspended ( The number of stored first special symbols (stored) is displayed. In addition, the special symbol memory display 1184 has a first special symbol memory lamp 1184a and a first special symbol memory lamp 1184b made of predetermined LEDs. The first special symbol memory lamps 1184a and 1184b are turned on / off. The number of holds can be displayed by the blinking pattern. Specifically, for example, the first special symbol memory lamp 1184a is turned on and the first special symbol memory lamp 1184b is turned off when the number of holdings is one, and the first special symbol memory lamps 1184a and 1184b when the number of holdings is two. When the number of holds is 3, the first special symbol memory lamp 1184a blinks and the first special symbol memory lamp 1184b is lit. When the number of held is 4, the first special symbol memory lamps 1184a and 1184b are both It is blinking. In the present embodiment, up to four are reserved.

  When the lower special symbol display 1187 cannot display the second special symbol in the lower special symbol display 1186 variably, if the game ball is received at the lower start port 2102, the start of the variable display is suspended ( The number of stored second special symbols (stored) is displayed. The lower special symbol memory indicator 1187 has a second special symbol memory lamp 1187a and a second special symbol memory lamp 1187b made of predetermined LEDs. The number of holds can be displayed by the blinking pattern. Specifically, for example, the second special symbol memory lamp 1187a is turned on and the second special symbol memory lamp 1187b is turned off when the number of reserved is 1, and the second special symbol memory display lamp 1187a, When the number of holdings is three, the second special symbol memory lamp 1187a blinks and the second special symbol memory lamp 1187b is lit. When the number of holdings is four, the second special symbol memory lamps 1187a and 1187b are turned on. Both are blinking. In the present embodiment, up to four are reserved.

  The upper special symbol display 1185 and the lower special symbol display 1186 display the first special lottery result and the second special lottery result which are drawn by receiving the game balls to the upper start port 2101 and the lower start port 2102. The 7-segment LED stops after it fluctuates for a predetermined time according to the special lottery result, and the first special lottery result and the second special lottery result are played according to the light emission pattern (special symbol) of the stopped 7-segment LED. It can be made to recognize the person side.

  The normal symbol display 1189 is a full-color LED that can change the emission color of red, green, and orange, and the gate portion 2350 is played by a combination of the emission color and lighting / flashing. A normal lottery result drawn by passing a ball can be displayed. In addition, the display of the normal symbol by the normal symbol display 1189 is also stopped and displayed with the light emission pattern corresponding to the normal lottery result after being displayed for a predetermined period of time, like the special symbol.

  The normal symbol memory display 1188 is a normal symbol whose start of variable display is suspended (stored) when a game ball passes through the gate part 2350 when the normal symbol display 1189 cannot display the normal symbol in a variable manner. The number of hold (number of storage) is displayed. The normal symbol memory display 1188 includes four normal symbol memory lamps 1188a to 1188d arranged side by side from below, each of which is a predetermined LED, and the normal symbol memory lamp 1188a from the bottom according to the number of holds. By sequentially lighting up to 1188d, it is possible to display the number of reserved normal symbols. In the present embodiment, up to four normal symbol fluctuation displays are held (stored).

  The round indicator 1190 includes a two-round display lamp 1190a made of predetermined LEDs and a 15-round display lamp 1190b, and can display the number of rounds in a “hit” game by lighting each lamp. It is like that.

  Further, as shown in FIG. 11, the function display unit 1180 can be viewed from the player side through the game window 101 of the door frame 5 with the game board 4 attached to the pachinko gaming machine 1. Yes. Game status indicator 1183, upper special symbol memory display 1184, upper special symbol indicator 1185, lower special symbol indicator 1186, lower special symbol memory indicator 1187, normal symbol memory indicator 1188, normal symbol indicator 1189, and The round indicator 1190 is attached to the front surface of the function display board 1191. A connection terminal for connecting the function display board 1191 and the main control board 4100 is attached to the rear end of the rearward projecting portion of the function display unit 1180.

  In this embodiment, since the function display unit 1180 is provided in the front component member 1110 of the game board 4, as compared with the case where it is provided in the front unit 2000 and the back unit 3000 attached to the game panel 1150, The function display unit 1180 can be used as the basic configuration of the game board 4, the configuration related to the pachinko gaming machine 1 can be simplified to prevent an increase in cost, and the model of the pachinko gaming machine 1 (table The position of the function display unit 1180 does not change even if the detailed configuration of the game board 4 that is embodied by the unit 2000 or the back unit 3000 and can characterize the model of the pachinko gaming machine 1 is different. Let the hall clerk recognize the position of the function display unit 1180 without confusion. So that the can.

[7. Main control board, payout control board and peripheral control board]
Next, a control board for performing various controls of the pachinko gaming machine 1 will be described with reference to FIGS. 12 is a block diagram of the main control board, the payout control board, and the peripheral control board, FIG. 13 is a block diagram showing the continuation of FIG. 12, and FIG. 14 is a payout control board, CR unit and frequency constituting the main board. FIG. 15 is a schematic diagram of various detection signals input / output to / from a lending device connection terminal board such as a game ball that relays electrical connection with the display board, FIG. 15 is a block diagram showing a continuation of FIG. 12, and FIG. FIG. 17 is a block diagram showing an outline of the peripheral control MPU, and FIG. 17 is a block diagram around the sound source built-in VDP in the liquid crystal and sound control unit.

  As shown in FIG. 12, the control configuration of the pachinko gaming machine 1 is mainly configured by a main control board 4100, a payout control board 4110, and a peripheral control board 4140, and various controls are shared. First, the main control board will be described, and then the payout control board, the power supply board, and the peripheral control board will be described.

[7-1. Main control board]
As shown in FIG. 12, the main control board 4100 that controls the progress of the game controls the power-on process that is executed when the power is turned on, and is executed after a predetermined time has elapsed since the power is turned on, and performs the game operation. Various control programs such as a main control program to be controlled, a ROM for storing various commands, a RAM for temporarily storing data, and the like are input to the main control MPU 4100a, which is a microprocessor, and detection signals from various detection switches. Main control input circuit 4100b, main control output circuit 4100c for outputting various signals to an external substrate, etc., main control solenoid drive circuit 4100d for driving various solenoids, power failure or instantaneous And a power failure monitoring circuit 4100e for monitoring signs of a stop.

  The main control MPU 4100a includes a built-in RAM (hereinafter referred to as “main control built-in RAM”) and a built-in ROM (hereinafter referred to as “main control built-in ROM”). Further, a watchdog timer 4100af (hereinafter referred to as “main control built-in WDT 4100af”) for monitoring the operation (system), a function for preventing fraud, and the like are also incorporated.

  The main control MPU 4100a has a built-in nonvolatile RAM. In this non-volatile RAM, a unique ID code with a unique code (a code that exists only in the world) for identifying an individual by the manufacturer that manufactured the main control MPU 4100a is stored in advance. Since the ID code once attached is stored in the nonvolatile RAM, it cannot be rewritten using an external device. The main control MPU 4100a can take out and refer to the ID code from the nonvolatile RAM.

  The main control MPU 4100a also uses a hardware random number circuit 4100an (hereinafter referred to as "built-in main control") to update a big hit determination random number for use in determining whether or not to generate a big hit gaming state among various random numbers related to the game. A hard random number circuit 4100an ”). The main random number circuit 4100an with built-in main control generates a random number within a predetermined numerical range (in this embodiment, a numerical range of a value 0 to a maximum value 32767 is preset as a minimum value), A predetermined value as the initial value is not fixed (that is, the initial value is not fixed), and the circuit configuration is such that a different value is set each time the main control MPU 4100a is reset. Specifically, when the main control MPU 4100a is reset, the hard random number circuit 4100an with built-in main control first sets a clock signal (input to the main control MPU 4100a as an initial value within a predetermined numerical range). Based on the clock signal output from the main control crystal oscillator (to be described later), other values within the predetermined numerical range are extracted one after another without duplication, and all values within the predetermined numerical range are extracted. Then, again, one value in the predetermined numerical range is extracted, and other values in the predetermined numerical range are not duplicated at high speed based on the clock signal input to the main control MPU 4100a. Extract one after another. The main control built-in hard random number circuit 4100an repeats such a high-speed lottery, and the main control MPU 4100a wins the value extracted by the main control built-in hard random number circuit 4100an at the time of acquiring a value from the main control built-in hard random number circuit 4100an. It is set as a random number for judgment.

  The main control input circuit 4100b is not provided with a reset terminal for forcibly resetting information whose detection signals from various detection switches are input to the various input terminals, and does not have a reset function. Therefore, the main control input circuit 4100b is configured as a circuit to which a system reset signal from a main control system reset described later is not input. That is, the main control input circuit 4100b does not reset the information based on the detection signals from the various detection switches input to the various input terminals by a main control system reset to be described later. The circuit is configured to be output from the output terminal.

  The main control output circuit 4100c is configured as an open collector output type in which an emitter terminal is grounded with a ground (GND), and various signals for outputting various signals to an external substrate or the like are input to the various input terminals. Main control output circuit 4100ca with a reset function having a reset function in which a reset terminal for forcibly resetting the received information is provided, and a main control output circuit 4100cb without reset function without a reset function in which no reset terminal is provided. And is composed of. The main control output circuit 4100ca with a reset function is configured as a circuit to which a system reset signal from a main control system reset described later is input. That is, the main control output circuit 4100ca with a reset function is reset when information for outputting various signals input to the various input terminals to an external board or the like is reset by a main control system reset described later. Is configured as a circuit that does not output any signal from the various output terminals. On the other hand, the main control output circuit 4100cb without a reset function is configured as a circuit to which a system reset signal from a main control system reset described later is not input. That is, the main control output circuit 4100cb having no reset function does not reset the information for outputting various signals input to the various input terminals to an external board or the like by a main control system reset described later. The signal based on this is comprised as a circuit from which the various output terminals are output.

  As shown in FIG. 8, the upper start port switch 3022 for detecting the game ball that has entered the upper start port 2101, the lower start port switch 2109 for detecting the game ball that has entered the lower start port 2102, and the general winning port 2104 A detection signal from the general winning opening switch 3020 for detecting a game ball that has entered and a signal from the power failure monitoring circuit 4100e are input to the input terminal of a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b. Yes. In addition, as shown in FIG. 8, the gate switch 2352 that detects the game ball that has passed through the gate portion 2350, the general winning port switch 3020 that detects the gaming ball that has entered the general winning port 2201, and the big winning port 2103 are entered. A detection signal from a count switch 2110 that detects a game ball and a magnetic detection switch 3024 that is attached to the back unit 3000 shown in FIG. The signal is inputted to the input terminal of a predetermined input port of the main control MPU 4100a through the terminal board 4161 and the main control input circuit 4100b.

  The main control MPU 4100a outputs a drive signal from the output terminal of the predetermined output port to the main control output circuit 4100ca with reset function based on the detection signals from these switches, so that the main control output circuit with reset function is output. 4100ca outputs a control signal to the main control solenoid drive circuit 4100d, and outputs a drive signal from the main control solenoid drive circuit 4100d to the start port solenoid 2105 and the attacker solenoid 2108 via the panel relay terminal plate 4161, or a predetermined output thereof. By outputting a drive signal from the output terminal of the port to the main control output circuit 4100ca with reset function, the upper special symbol display from the main control output circuit 4100ca with reset function via the panel relay terminal board 4161 and the function display board 1191 1185, Drive signals to the special symbol display 1186, the upper special symbol storage display 1184, the lower special symbol storage display 1187, the normal symbol display 1189, the normal symbol storage display 1188, the game state display 1183, and the round display 1190 Or output.

  Further, the main control MPU 4100a outputs various information (game information) relating to the game from the output terminal of the predetermined output port to the main control output circuit 4100ca with reset function, so that payout control is performed from the main control output circuit 4100ca with reset function. Various information about the game (game information) is output to the substrate 4110, or a signal (power failure clear signal) is output from the output terminal of the predetermined output port to the main control output circuit 4100ca with reset function. A signal (power failure clear signal) is output from the control output circuit 4100ca to the power failure monitoring circuit 4100e.

  In this embodiment, the upper start port switch 3022, the lower start port switch 2109, the gate switch 2352, and the count switch 2110 use non-contact type electromagnetic proximity switches, whereas Contact type ON / OFF operation type mechanical switches are used for the prize opening switches 3020 and 3020. This is because game balls frequently enter the upper start opening 2101 and the lower start opening 2102 and frequently pass through the gate portion 2350, so the upper start opening switch 3022, the lower start opening switch 2109, and the gate switch 2352 Detection of game balls also occurs frequently. Therefore, long-life proximity switches are used as the upper start port 3022, the lower start port switch 2109, and the gate switch 2352. In addition, when a big hit gaming state that is advantageous to the player occurs, the game winning balls 2103 are opened and game balls are frequently entered, so that the game balls are frequently detected by the count switch 2110. For this reason, a proximity switch having a long life is also used as the count switch 2110. On the other hand, detection by the general winning opening switches 3020 and 3020 does not occur frequently in the general winning opening 2104 and 2201 where game balls do not enter frequently. For this reason, mechanical switches having a shorter lifetime than the proximity switches are used as the general winning award opening switches 3020 and 3020.

  Further, the main control MPU 4100a transmits various commands related to payout as serial data from the output terminal of the predetermined serial output port to the main control output circuit 4100cb without reset function, thereby performing payout control from the main control output circuit 4100cb without reset function. Various commands are transmitted to the substrate 4110 as serial data. When the payout control board 4110 completes normal reception of various commands from the main control board 4100 as serial data, the payout control board 4110 outputs a signal to that effect (payer ACK signal) to the main control board 4100. This signal (payer ACK signal) is input to an input terminal of a predetermined input port of the main control MPU 4100a through the main control input circuit 4100b.

  Also, the main control MPU 4100a receives various commands related to the state of the pachinko gaming machine 1 from the payout control board 4110 as serial data by the main control input circuit 4100b, so that the main control input circuit 4100b receives the predetermined serial input port. Receives various commands as serial data at the input terminal. When the main control MPU 4100a completes normal reception of various commands from the payout control board 4110 as serial data, a main control output with a reset function is sent from the output terminal of the predetermined output port to that effect (main payout ACK signal). The signal is output to the circuit 4100ca, and a signal (main payment ACK signal) is output from the main control output circuit 4100ca with reset function to the payout control board 4110.

  Further, the main control MPU 4100a transmits, as serial data, various commands relating to control of game effects and various commands relating to the state of the pachinko gaming machine 1 to the main control output circuit 4100cb having no reset function from the output terminal of the predetermined serial output port. Thus, various commands are transmitted as serial data from the main control output circuit 4100cb having no reset function to the peripheral control board 4140.

  Here, a main peripheral serial transmission port for transmitting various commands as serial data to the peripheral control board 4140 will be briefly described. The main control MPU 4100a is configured with a main control CPU core 4100aa as the center. In addition to the main control built-in RAM, a main peripheral serial transmission port 4100ae, which is one of various main control serial I / O ports, is connected to the bus 4100ah. Circuit connection (see FIG. 23). The main peripheral serial transmission port 4100ae transmits various commands as main peripheral serial data to the peripheral control board 4140, and mainly includes a transmission shift register 4100aea, a transmission buffer register 4100aeb, a serial management unit 4100aec, and the like (FIG. 23). When the main control CPU core 4100aa sets a command in the transmission buffer register 4100aeb and outputs a transmission start signal to the serial management unit 4100aec, the serial management unit 4100aec sends the command set in the transmission buffer register 4100aeb from the transmission buffer register 4100aeb. The data is transferred to the transmission shift register 4100aea, and transmission to the peripheral control board 4140 is started as main peripheral serial data. In the present embodiment, the transmission buffer register 4100aeb has a storage capacity of 32 bytes. The main control CPU core 4100aa continuously sends a plurality of commands to the peripheral control board 4140 by setting a plurality of commands in the transmission buffer register 4100aeb and then outputting a transmission start signal to the serial management unit 4100aec.

  Note that the power supply board 851 for supplying various voltages to the main control board 4100 is an electric power source as a backup power supply for supplying power to the main control board 4100 for a predetermined time (3 hours in the present embodiment) even when the power is shut off. A multilayer capacitor (hereinafter simply referred to as “capacitor”) BC0 (see FIG. 18) is provided. The capacitor BC0 allows the main control MPU 4100a to store various types of information in the main control built-in RAM even when the power is turned off. Various kinds of information stored in the main control built-in RAM are stored in the operation signal (RAM clear signal) from the operation switch 860a when an operation switch 860a of a payout control board 4110 (to be described later) is operated within a predetermined period from when the power is turned on. Is output from the payout control board 4110 and input to an input terminal of a predetermined input port of the main control MPU 4100a via the main control input circuit 4100b, and triggered by this, the main control MPU 4100a completely erases from the main control built-in RAM. (Clear).

[7-2. Dispensing control board]
As shown in FIG. 13, a payout control board 4110 for performing game ball launch control, ball feed control, and the like in addition to game ball payout control performs various controls relating to payout and controls game ball launch control and ball feed control. A payout control unit 4120 for performing the above-described operations, an operation switch 860a also having various functions, and an error LED display 860b for displaying the state of the pachinko gaming machine 1. Further, the operation switch 860a having a function as a RAM clear switch is described as a RAM (hereinafter referred to as “main control built-in RAM”) built in the main control MPU 4100a based on a detection signal output by being operated. A RAM clear signal for completely erasing the information stored in.

[7-2-1. Dispensing control unit]
As shown in FIG. 13, a payout control unit 4120 that performs various controls relating to payout and controls game ball launch control and ball transport control controls power-on processing that is executed when the power is turned on, and is predetermined after the power is turned on. Dispensing is a microprocessor with a built-in various control programs including a payout control program for controlling a payout operation of game media executed after a lapse of time, a ROM for storing various commands, a RAM for temporarily storing data, and the like Control MPU 4120a, payout control input circuit 4120b to which detection signals from various detection switches relating to payout and detection signals from various detection switches relating to the launch of game balls are input, and payout for outputting various signals to an external substrate or the like The control output circuit 4120c and the payout motor 744 of the prize ball device 740 shown in FIG. It includes a payout motor drive circuit 4120d for outputting a signal, and a CR unit output circuit 4120e for exchanging various signals between the CR unit 6. The payout control MPU 4120a includes a launch ball feed control circuit 4120ag that performs launch control by the launch solenoid 654 of the hit ball launcher 650 shown in FIG. 5 and ball feed control by the ball feed solenoid 585 of the ball feed unit 580 shown in FIG. A launching ball feed failure monitoring circuit 4120ah for monitoring whether or not a failure has occurred in the launching ball feed control circuit 4120ag is incorporated. The payout control MPU 4120a has a built-in RAM (hereinafter referred to as “payout control built-in RAM”), a built-in ROM (hereinafter referred to as “payout control built-in ROM”), A watchdog timer for monitoring the operation (system) and a function for preventing fraud are also incorporated.

  The discharge ball feeding control circuit 4120ag built in the dispensing control MPU 4120a that performs the firing control by the firing solenoid 654 and the ball feeding control by the ball feeding solenoid 585 corresponds to the rotational position of the front 506 of the rotating handle body shown in FIG. And a touch switch for detecting whether or not a palm or a finger is touching the front 506 of the rotary handle body, and an operation signal from the potentiometer 512 that electrically adjusts the strength (launch strength) of launching the game ball toward the game area 1100. A detection signal from 516 and a detection signal from a firing stop switch 518 that detects whether or not the launching (launching) of the game ball is forcibly stopped according to the player's will are a handle relay terminal plate 192, a power supply board 851 and the payout control input circuit 4120b of the payout control board 4110. In addition, when the CR unit 6 and the game ball lending device connection terminal plate 869 are electrically connected, the launch ball feed control circuit 4120ag transmits a CR connection signal to that effect to the CR unit input / output of the payout control board 4110. It is input via the circuit 4120e.

  The shot ball feed control circuit 4120ag adjusts a drive current for launching (shooting) the game ball toward the game area 1100 based on an operation signal from the potentiometer 512, and a payout control output circuit 4120c (with a reset function to be described later) A discharge control output circuit 4120c (a payout control with a reset function, which will be described later) is performed on the power supply board 851 (a launch solenoid drive circuit 858 which will be described later) via the payout control output circuit 4120ca) and a firing control by the firing solenoid 654 is performed. The ball of the ball feeding unit 580 is output to the power supply board 851 (ball feeding solenoid drive circuit 859 described later) via the output circuit 4120ca) and a constant current is outputted to the ball feeding solenoid 585 via the handle relay terminal plate 192. The feeding member is the upper plate 30 of the plate unit 300 shown in FIG. Receiving 1 ball the accumulated game balls, control is performed to send the game ball Tamaoku member accepts the hitting launcher 650 side.

  The firing ball feed control circuit 4120ag operates in accordance with the payout control program. When the firing operation permission is set, the game ball 1905 is played in the game area 1100 according to the rotational position of the front 506 of the rotary handle shown in FIG. An operation signal from a potentiometer 512 that electrically adjusts the strength (firing strength) to be launched toward the head, a detection signal from a touch switch 516 that detects whether a palm or finger is touching the front 506 of the rotating handle, The detection signal from the firing stop switch 518 for detecting whether or not the launching (launching) of the game ball is forcibly stopped at the will of the player, and the CR unit 6 and the game ball lending device connection terminal plate 869 are electrically connected. Control of the game ball is performed based on the CR connection signal indicating that the connection is established. On the other hand, when the launch operation prohibition is set, the above-described launch control of the game ball is forcibly stopped.

  The game ball launch control by the shot ball feed control circuit 4120ag is 99.93 to 99.95 as the number of game balls that can be launched (launched) toward the game area 1100 per minute. It is preset so that it does not exceed 100 balls. This is realized by a PWM circuit (not shown) for generating a PWM (abbreviation of Pulse Width Modulation) signal (not shown) built in the payout control MPU 4120a. The pulse width of the PWM signal output from this circuit is such that the number of game balls that can be launched (launched) toward the game area 1100 per minute is 99.93 to 99.95. The PWM signal is set in advance, and the circuit is connected so that the PWM signal is input to the shot ball feed control circuit 4120ag. The shot ball feed control circuit 4120ag measures the launch timing of the game ball based on the input PWM signal.

  As described above, the firing ball feed failure monitoring circuit 4120ah monitors whether or not a failure has occurred in the firing ball feed control circuit 4120ag, and stores the monitoring result (whether or not a failure has occurred) as status information. It can be held. When the payout control program obtains status information from the launching ball feed failure monitoring circuit 4120ah and determines that a failure has occurred in the launching ball feed control circuit 4120ag, it controls the launching of the game ball by the launching ball feed control circuit 4120ag. In order to forcibly stop, the firing operation prohibition is set to the firing ball feed control circuit 4120ag.

  The payout control program sets the launching operation prohibition to the launching ball feed control circuit 4120ag as an initial state (default) when an instantaneous power failure or power failure occurs and the power is restored after the power is turned on. After that, when the status information is acquired from the shooting ball feeding failure monitoring circuit 4120ah and it is determined that the shooting ball feeding control circuit 4120ag is not defective, the shooting ball sending control circuit 4120ag starts the launch control of the game ball. The launching operation permission is set for the launching ball feed control circuit 4120ag, while the status information is acquired from the launching ball feed failure monitoring circuit 4120ah and it is determined that the launching ball feed control circuit 4120ag is malfunctioning. Launch to maintain the state where the launch control of the game ball by the ball feed control circuit 4120ag is stopped Setting the firing operation prohibition against sending control circuit 4120ag.

  Here, as a problem in the shot ball feed control circuit 4120ag, it is difficult to adjust the drive current for launching (shooting) the game ball toward the game area 1100 based on the operation signal from the potentiometer 512. If the operation signal from the potentiometer 512 is affected by noise, it becomes a highly distorted signal, and the drive current for launching (launching) the game ball toward the game area 1100 cannot be specified. Is difficult to adjust, the detection signal from the touch switch 516 turns into a very distorted signal due to the influence of noise, and whether the player's palm or finger is touching the front 506 of the rotary handle If it is difficult to identify the detection signal, the detection signal from the firing stop switch 518 is affected by noise. In addition to the case where it becomes difficult to specify whether or not the launching (launching) of the game ball has been forcibly stopped by the player's will due to the distorted signal, When 4120ag itself is destroyed for some reason and cannot be used, or when the number of game balls launched (launched) toward the game area 1100 per predetermined time exceeds a predetermined number (this embodiment) In this case, the number of game balls shot (launched) toward the game area 1100 per minute may exceed 100).

  Under the control of the payout control MPU 4120a, the payout control program converts various information related to games (game information) and various commands related to payout from the main control board 4100 as payer serial data transmission signals via the payout control I / O port 4120b. Receive serial data by serial method. Also, the payout control program generates a frame state 1 command (corresponding to the first error occurrence command) when an error occurs in the game ball payout operation, or operates the operation switch 860a as an error release unit. Based on the signal (detection signal), a 16-bit (2 bytes) error cancellation navigation command (corresponding to the first error cancellation command) is created, and the error occurrence command and the error cancellation navigation command are respectively transmitted to the payer serial data As a serial signal, a signal is output to the reception port of the main control board 4100 via the payout control I / O port 4120b (command transmission means). In addition, the payout control program is provided after a predetermined time has elapsed since the power was turned on, that is, after the payout control unit main process is executed or the payout control unit timer interrupt process is executed to start payout control. When an error occurs in the operation, the error is canceled based on a detection signal generated in response to the operation of the operation switch 860a, and output of warning information corresponding to the error is stopped (error cancellation control means).

  The payout control program outputs a door frame opening command (first door opening command) when a detection signal (door frame opening detection signal) associated with the opening operation is input from the door frame opening switch 618. When a detection signal (body frame opening detection signal) accompanying the opening operation is input from the body frame opening switch 619, a body frame opening command (first body frame opening command) is output. On the other hand, when the detection signal (door frame closing detection signal) accompanying the closing operation is input from the door frame opening switch 618, the payout control program receives a door frame closing command (first door frame closing command). When a detection signal (main body frame closing detection signal) accompanying the closing operation is input from the main body frame opening switch 619, a main body frame closing command (first main body frame closing command) is output.

  In addition, when the payout control program obtains status information from the launching ball feed failure monitoring circuit 4120ah and determines that there is no malfunction in the launching ball feed control circuit 4120ag, the payout control program 4120ag determines the game balls. In order to start the launch control, the launching operation permission is set for the launching ball feed control circuit 4120ag. On the other hand, when it is determined that the launching ball feed control circuit 4120ag is defective, a game by the launching ball feed control circuit 4120ag is performed. In order to forcibly stop the launch control of the sphere, the launch operation prohibition is set to the launch ball feed control circuit 4120ag.

  The payout control input circuit 4120b is not provided with a reset terminal for forcibly resetting information whose detection signals from the various detection switches are input to the various input terminals, and does not have a reset function. Therefore, the payout control input circuit 4120b is configured as a circuit to which a system reset signal from a payout control system reset described later is not input. In other words, the payout control input circuit 4120b does not reset the information based on the detection signals from the various detection switches inputted to the various input terminals by a payout control system reset to be described later. The circuit is configured to be output from the output terminal.

  The payout control output circuit 4120c is configured as an open collector output type in which the emitter terminal is grounded with the ground (GND), and various signals for outputting various signals to an external substrate or the like are input to the various input terminals. Payout control output circuit 4120ca with a reset function having a reset function in which a reset terminal for forcibly resetting the received information is provided, and a payout control output circuit 4120cb without reset function having no reset function in which no reset terminal is provided And is composed of. The payout control output circuit 4120ca with a reset function is configured as a circuit to which a system reset signal from a payout control system reset described later is input. That is, the payout control output circuit 4120ca with a reset function resets the information for outputting various signals input to the various input terminals to an external substrate or the like by a payout control system reset described later, and the information Is configured as a circuit that does not output any signal from the various output terminals. In contrast, the payout control output circuit 4120cb without a reset function is configured as a circuit to which a system reset signal from a payout control system reset described later is not input. In other words, the payout control output circuit 4120cb without the reset function does not reset the information for outputting the various signals input to the various input terminals to an external substrate or the like by the payout control system reset described later. The signal based on this is comprised as a circuit from which the various output terminals are output.

  A detection signal from a ball break switch 750 that detects the presence or absence of a game ball in the supply passage of the prize ball device 740 and a count switch 751 that detects a game ball flowing down in the prize ball device 740 is first a prize. It is input to the input terminal of a predetermined input port of the payout control MPU 4120a through the prize ball case substrate 754 of the ball device 740 and the payout control input circuit 4120b. The detection signals from the rotation angle switch 752 for detecting the detection slit formed on the rotation detection board of the prize ball device 740 are first a rotation angle switch board 753 of the prize ball device 740, a prize ball case inner board 754, and It is input to an input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

  The detection signals from the door frame opening switch 618 for detecting the opening of the door frame 5 with respect to the main body frame 3 and the main body frame opening switch 619 for detecting the opening of the main body frame 3 with respect to the outer frame 2 are sent to the payout control input circuit 4120b. To the input terminal of a predetermined input port of the payout control MPU 4120a.

  Further, the detection signal from the full switch 550 for detecting whether or not the storage space of the foul cover unit 540 shown in FIG. 1 is full is stored in the handle relay terminal plate 192, the power supply board. 851 and the input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

  The payout control MPU 4120a receives various commands related to payout from the main control board 4100 via the payout control input circuit 4120b in the serial data mode at the input terminal of the serial input port, or the operation signal (detection) of the operation switch 860a. Signal) is output to the main control board 4100 via the payout control input circuit 4120b. When the payout control MPU 4120a completes the normal reception of various commands from the main control board 4100 as serial data, a payout control output with a reset function is sent from the output terminal of the predetermined output port. By outputting to the circuit 4120ca, a signal (payer ACK signal) is output from the payout control output circuit with reset function 4120ca to the main control board 4100.

  Also, the payout control MPU 4120a sends out various commands for indicating the state of the pachinko gaming machine 1 from the output terminal of the serial output port as serial data to the payout control output circuit 4120cb without the reset function, thereby giving out the payout without the reset function. Various commands are transmitted as serial data from the control output circuit 4120cb to the main control board 4100. When the main control board 4100 completes normal reception of various commands from the payout control board 4110 as serial data, the main control board 4100 outputs a signal (main payment ACK signal) to that effect to the payout control board 4110. This signal (main payment ACK signal) is input to an input terminal of a predetermined input port of the payout control MPU 4120a via the payout control input circuit 4120b.

  Also, the payout control MPU 4120a outputs a drive signal for driving the payout motor 744 from the output terminal of the predetermined output port to the payout control output circuit 4120ca with reset function, so that the payout control output circuit 4120ca with reset function is output. Is output to the payout motor drive circuit 4120d, and the drive signal is output from the payout motor drive circuit 4120d to the payout motor 744 via the prize ball case substrate 754, or from the output terminal of the predetermined output port. By outputting a drive signal for displaying the state of the gaming machine 1 on the error LED indicator 860b to the payout control output circuit 4120ca with reset function, the drive signal is output from the error LED indicator 860b with the reset function payout control output circuit 4120ca. Or output to

  The error LED display 860b is a segment display, and displays the state of the pachinko gaming machine 1 by displaying alphanumeric characters and figures. The contents displayed and notified by the error LED display 860b include the following. For example, when the figure “-” is displayed, it is notified that it is “normal”, and when the numeral “0” is displayed, it indicates that it is “connection abnormality” (specifically, with the main control board 4100). The fact that there is an abnormality in electrical connection between the board and the payout control board 4110) is notified, and when the number “1” is displayed, it is “out of ball” (specifically, out of ball) Based on the detection signal from the switch 750, it is notified that there is no game ball in the supply passage of the prize ball device 740, and when the number “2” is displayed, it means that “the ball is clear” (specifically, Is based on the detection signal from the rotation angle switch 752, and the payout rotator and the game ball are meshed in the vicinity of the entrance at the entrance of the distribution space communicating with the supply passage of the prize ball device 740, and the payout rotator is difficult to rotate. Number) When “3” is displayed, the fact that it is a “counter switch error” (specifically, that a malfunction has occurred in the count switch 751 based on a detection signal from the count switch 751) is notified, and the number “ When “5” is displayed, it is informed that it is a “retry error” (specifically, that the number of retries of the payout operation has reached a preset upper limit value), and the number “6” is displayed. When it is, it is informed that it is “full” (specifically, based on the detection signal from the full tank switch 550, the game ball in which the accommodation space of the foul cover unit 540 is stored is full) When the number “7” is displayed, it is reported that “CR is not connected” (electrical connection is cut off from either the payout control board 4110 to the CR unit 6). However, when the number “9” is displayed, it is “in stock (awarded ball stock (unpaid) is present)” (specifically, the number of game balls that have not yet been paid out is a predetermined number of balls) To that effect).

  Further, the payout control MPU 4120a outputs the number of game balls actually paid out as prize balls from the output terminal of the predetermined output port to the payout control output circuit 4120ca with reset function, thereby providing payout control with reset function. The number of game balls actually paid out as prize balls is output from the output circuit 4120ca to the external terminal board 784 via a resistor (not shown).

  Also, the payout control board 4110 outputs various information (game information) related to the game from the main control board 4100 to the external terminal board 784 via a resistor (not shown). In addition to the payout control board 4110, various information from the peripheral control board 4140 (number of game balls to be paid out as prize balls, etc.) is also input to the external terminal board 784. The external terminal board 784 is provided with a plurality of photocouplers (not shown) (infrared LEDs and photo ICs are built in), and a game hall (hole) is provided via the plurality of photocouplers. ), The number of game balls, and various information (game information, content of error relating to game ball payout operation, or the fact that there was an error) are transmitted to the hall computer installed in (1). The external terminal board 784 and the hall computer are electrically insulated by a plurality of photocouplers, and an abnormal voltage is applied to the hall computer via the external terminal board 784 of the pachinko gaming machine 1. The hall computer does not malfunction or break down, and the main control board 4100 that advances the game from the hall computer via the external terminal board 784 of the pachinko gaming machine 1, the payout control board that controls the payout etc. An abnormal voltage is applied to 4110 and the peripheral control board 4140 that controls the progress of the production, so that malfunction or failure does not occur. The hall computer includes the number of game balls actually paid out as a winning ball by the pachinko gaming machine 1, game information of the pachinko gaming machine 1, and the number of game balls scheduled to be paid out as the winning ball by the pachinko gaming machine 1. By grasping this, the player's game and game ball payout information (so-called play information) by the payout operation of the pachinko gaming machine 1 are monitored.

  The ball lending request signal for the game ball from the ball lending switch 365a of the ball lending unit 360 and the return request signal for the prepaid card from the return switch 365b shown in FIG. And, it is input to the CR unit 6 through a lending device connection terminal board 869 such as a game ball. The CR unit 6 transmits a signal designating the number of game balls to be lent according to the ball lending request signal to the payout control board 4110 via the gaming ball lending device connection terminal board 869 in a serial manner, and this signal is transmitted to the CR unit. It is input to an input terminal of a predetermined input port of the payout control MPU 4120a via the input / output circuit 4120e. In addition, the CR unit 6 updates the remaining degree of the prepaid card inserted according to the number of rented game balls, and displays a signal for displaying the remaining degree on the remaining number display 365c, such as a game sphere. The signal is output to the lending device connection terminal plate 869, the main door relay terminal plate 880, and the frequency display plate 365, and this signal is input to the remaining frequency display 365c. In addition, the CR unit lamp 365d adjacent to the remaining frequency indicator 365c is supplied with the supply voltage from the CR unit 6 via the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880. Yes.

  The power supply board 851 for supplying various voltages to the payout control board 4110 is a capacitor BC1 as a backup power supply for supplying power to the payout control board 4110 for a predetermined time (1 hour in the present embodiment) even when the power is shut off. (See FIG. 18). With this capacitor BC1, the payout control MPU 4120a can store various types of information in the payout control built-in RAM (payout storage unit) even when the power is shut off. Various types of information stored in the payout control built-in RAM are stored in the payout control MPU 4120a via the payout control input circuit 4120b when the operation switch 860a is operated within a predetermined period from when the power is turned on. The payout control MPU 4120a input to the input terminal of the input port determines as a RAM clear signal for completely erasing the information stored in the payout control built-in RAM, and triggered by this from the payout control built-in RAM by the payout control MPU 4120a. It is completely erased (cleared). This operation signal (RAM clear signal) is output to the payout control output circuit 4120cb without reset function, and is output to the main control board 4100 from the payout control output circuit 4120cb without reset function.

[7-2-2. Exchange of various signals with game ball rental device connection terminal board]
Here, the exchange of various signals between the payout control unit 4120 and the CR unit 6 and the exchange of various signals between the CR unit 6 and the frequency display board 365 will be described with reference to FIG. As shown in FIG. 14, the game ball lending device connection terminal plate 869 relays the electrical connection between the CR unit 6 and the payout control board 4110, as well as the CR unit 6 and the frequency display board 365. (To be precise, the game ball rental device connection terminal plate 869 is electrically connected to the frequency display plate 365 via the main door relay terminal plate 880. The CR unit 6 and the game ball lending device connection terminal plate 869 are electrically connected, the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880 are electrically connected, and the main door relay Terminal board 880 and frequency display board 365 are electrically connected). Between the board of CR unit 6 and gaming ball lending device connection terminal plate 869, between the gaming ball lending device connection terminal plate 869 and payout control board 4110, gaming ball lending device connection terminal plate 869 and main door relay. The board between the terminal board 880 and the board between the game ball lending device connection terminal board 869 and the frequency display board 365 are electrically connected by wiring (harness), respectively. In addition, AC24V, which will be described later, from the power supply board 851 is supplied to the CR unit 6 via a game ball rental device connecting terminal plate 869. The CR unit 6 generates a predetermined voltage VL (in this embodiment, DC +12 V (DC +12 V, hereinafter referred to as “+12 V”)) from the supplied AC 24 V by a built-in voltage generation circuit (not shown) together with the ground LG. The game ball lending device connection terminal plate 869 is supplied to the payout control board 4110, while the game ball lending device connection terminal plate 869 and the main door relay terminal plate 880 are supplied to the frequency display plate 365. .

  The frequency display board 365 has a ball lending switch 365a, which is a push button switch, mounted on the component surface at a position corresponding to the lending button 361 of the lending unit 360 shown in FIG. A return switch 365b, which is a push button switch, is mounted at a position corresponding to the button 362, and a remaining frequency display 365c, which is a segment display, is mounted at a position corresponding to the remaining lending display section 363 of the rental unit 360.

  The ball rental switch 365a and the return switch 365b are electrically connected to the ground LG from the CR unit 6 via a game ball rental device connection terminal plate 869 and a main door relay terminal plate 880. When the ball lending button 361 is pressed, the ball lending switch 365a is turned on (the ball lending switch 365a is turned on), and the ball lending operation signal TDS from the ball lending switch 365a is transmitted to the main door relay terminal plate 880 and the game. It is inputted to the CR unit 6 through a ball lending device connection terminal board 869. When the return button 365b is pressed, the return switch 365b is turned on (turned on), and the return operation signal RES from the return switch 365b is connected to the main door relay terminal plate 880 and a rental device such as a game ball. The signal is input to the CR unit 6 through the terminal board 869.

  The remaining frequency indicator 365c is composed of three segment indicators arranged in a line. Of these three digit segment indicators, one digit segment indicator is sequentially driven, so-called dynamic lighting system is used for three digits. The segment display is controlled to be lit. By such lighting control, the remaining frequency indicator 365c displays the remaining amount of the prepaid card inserted into the CR unit 6 or displays an error of the CR unit 6. The remaining frequency indicator 365c includes digit signals DG0 to DG2 (three signals in total) for designating one-digit segment indicator among the three-digit segment indicator, and the designated one-digit segment indicator. Segment drive signals SEG-A to SEG-G (a total of 7 signals) for designating the contents to be lit and displayed are connected from the CR unit 6 to the lending device connection terminal board 869 such as a game ball and the main door relay terminal board When input via the 880, a one-digit segment indicator is sequentially emitted according to the input digit signals DG0 to DG2 and segment drive signals SEG-A to SEG-G, and these three-digit segment indicators The contents due to the light emission can be visually recognized through the lending remaining display portion 363.

  A CR unit lamp 365d is mounted on the frequency display board 365 adjacent to the remaining frequency display 365c. The CR unit lamp 365d is supplied with a predetermined voltage VL from the CR unit 6 via a game ball lending device connection terminal plate 869 and a main door relay terminal plate 880. The predetermined voltage VL is input to the CR unit 6 as a ball lending available signal TDL through a current limiting resistor mounted on the gaming ball lending device connection terminal plate 869 via the CR unit lamp 365d. The CR unit 6 creates a predetermined voltage VL from the AC 24 V supplied from the power supply board 851 by the built-in voltage creation circuit, and the ball rental switch 365a and the return switch 365b are in a valid ball rental state. Controls the logic of the ball lending available signal TDL to cause the CR unit lamp 365d to emit light, and this light emission can be visually recognized through the lending remaining display portion 363. Further, the segment drive signals SEG-A to SEG-G are input to the remaining frequency indicator 365c through a current limiting resistor mounted on the gaming ball lending device connection terminal board 869.

  In the CR unit 6, the ball lending button 361 is pressed, and the ball lending operation signal TDS from the ball lending switch 365a is transmitted from the frequency display plate 365 via the main door relay terminal plate 880 and the game ball lending device connection terminal plate 869. When inputted, the ball rental request signal BRDY is output to the payout control board 4110 (payout control MPU 4120a) via the game ball lending device connecting terminal board 869. The CR unit 6 performs a single payout operation start request signal for paying out a predetermined number of rented balls (in this embodiment, 25 balls, corresponding to 100 yen as an amount) in one payout operation. Is output to the payout control board 4110 (the payout control MPU 4120a) via the gaming ball rental device connecting terminal board 869. The payout control board 4110 (payout control MPU 4120a) to which BRDY and BRQ are input, sends EXS, which is a signal for notifying that the one payout operation has been started or ended, to the lending device connection terminal board 869 such as a game ball. Through the terminal, the PRDY, which is a signal for outputting to the CR unit 6 or notifying that the payout operation for paying out the ball is possible or impossible, is connected to a lending device connection terminal board such as a game ball. Or output to the CR unit 6 via 869. In addition, for example, when a hall clerk or the like is preset in the CR unit 6 so that a game ball of 200 yen is paid out when the ball rental button 361 is pressed, one payout operation is performed. Is performed twice in succession, and when 25 balls for 100 yen are paid out, 25 balls for 100 yen are paid out, and 50 balls for a total of 200 yen are paid out. Become.

  In the CR unit 6, the return button 362 is pressed, and a return operation signal RES from the return switch 365 b is input from the frequency display board 365 via the main door relay terminal board 880 and the game ball lending device connection terminal board 869. The prepaid card is discharged from an insertion slot (not shown) and returned. The returned prepaid card stores a remaining amount obtained by subtracting an amount corresponding to the number of game balls paid out as a result of the ball rental button 361 being pressed.

[7-3. Power supply board]
Next, the power supply board 851 will be briefly described. The power supply board 851 is supplied from the Pachinko Island facility, and can be electrically connected to or disconnected from AC 24 volts (AC24V), and a power supply control unit 855 that generates various power supplies. 5, a launch solenoid drive circuit 858 for driving the launch solenoid 654 of the hit ball launcher 650 shown in FIG. 5, and a ball feed solenoid drive circuit for driving the ball feed solenoid 585 of the ball feed unit 580 shown in FIG. 859. The launch solenoid drive circuit 858 is controlled by a launch ball feed control circuit 4120ag built in the payout control MPU 4120a of the payout control board 4110 and launches a game ball toward the game area 1100 based on an operation signal from the potentiometer 512 (launch). The drive current to the firing solenoid 654 is adjusted so that it can be The ball feeding solenoid drive circuit 859 is controlled by the launch ball feeding control circuit 4120ag built in the dispensing control MPU 4120a of the dispensing control board 4110, and the ball feeding member of the ball feeding unit 580 is the upper plate of the dish unit 300 shown in FIG. One game ball stored in 301 is received, and the driving current to the ball feeding solenoid 585 is adjusted to be a constant current so that the game ball received by the ball feeding member can be sent to the ball hitting device 650 side. It has become so.

[7-3-1. Power control unit]
The power control unit 855 operates the power switch 852 to improve the power factor of the power rectified by the synchronous rectifier circuit 855a that rectifies the AC 24 volts (AC 24V) supplied from the pachinko island facility and the synchronous rectifier circuit 855a. Power factor correction circuit 855b, smoothing circuit 855c for smoothing the power whose power factor has been improved by power factor improvement circuit 855b, and various direct currents for supplying power smoothed by smoothing circuit 855c to various substrates A power generation circuit 855d for generating a power supply.

[7-4. Peripheral control board]
As shown in FIG. 15, the peripheral control board 4140 performs effect control based on various commands from the main control board 4100, and covers the display area of the upper plate side liquid crystal display device 470 shown in FIG. The touch panel drive substrate 450 that performs detection control of the touch state of the capacitance type touch panel 480 provided and draws the display area of the upper-plate-side liquid crystal display device 470 and the periphery for exchanging control commands and various information (various data) The controller 4150, the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925 a to 1925 d, and the upper plate side liquid crystal display device 470 are controlled for drawing, while the speaker box 820 shown in FIG. Liquid crystal and sound control unit 4 for controlling sound such as music and sound effects flowing from the speaker housed in the speaker and the speaker 130 provided on the door frame 5 60, a real-time clock (hereinafter referred to as “RTC”) control unit 4165 holding calendar information for specifying the date and time and time information for specifying the hour, minute, second, and a speaker box provided in the main body frame 3 And a volume adjustment volume 4140a for adjusting the volume of music, sound effects and the like flowing from the speaker housed in 820 and the speaker 130 provided on the door frame 5 by rotating the knob.

[7-4-1. Peripheral control unit]
As shown in FIG. 15, the peripheral control unit 4150 for effect control controls the peripheral control MPU 4150a as a microprocessor and the power-on process executed when the power is turned on, and after a predetermined time has elapsed since the power was turned on. Various control programs such as a sub-control program that is executed and controls the production operation, a peripheral control ROM 4150b that stores various data, various control data, and various schedule data, and a VDP 4160a with a built-in sound source of the liquid crystal and sound control unit 4160 described later. Various information continued across the peripheral control unit steady process executed each time a V blank signal is input (for example, schedule data defining a screen to be drawn on the game board side liquid crystal display device 1900, light emission of various LEDs, etc. Manage schedule data that defines aspects Peripheral control RAM 4150c for storing information for the purpose) and various information continued across days (for example, information for managing a history of occurrence of a big hit gaming state, information for managing special performance flags, etc.) ), A peripheral control external watchdog timer 4150e (hereinafter referred to as “peripheral control external WDT 4150e”) for monitoring whether the peripheral control MPU 4150a is operating normally, and a power source. A value transmitted by the power consumption suppression signal from the board 851 (power consumption suppression stage described later) is sampled at a predetermined cycle via the frame peripheral relay terminal board 868 (in the peripheral control unit 1 ms timer interrupt processing described later). In the power consumption status history information creation process), the power consumption status history information is stored and retained sequentially. A power consumption status history RAM 4150f, a battery 4150g for supplying backup power to the power consumption status history storage unit 4150f so that the power consumption status history information of the power consumption status history storage unit 4150f is stored when the power is cut off, and power consumption Based on the power consumption status history information stored and held in the status history RAM 4150f, the power status consumed by the pachinko gaming machine 1 at the time of power-off (immediately before power-off) is grasped at the time of power recovery and the pachinko gaming machine 1 A power saving mode transition notification LED 4150k for notifying a transition state to the power saving mode at the time of power recovery for suppressing power consumption.

  Peripheral control RAM 4150c can retain the stored content only for the time when power is restored immediately after an instantaneous power failure, and power is cut off for a long time (when a long-time power interruption occurs) The peripheral control SRAM 4150d is supplied with backup power by a large-capacity electrolytic capacitor (not shown) provided on the power supply board 851 (hereinafter referred to as “electrolytic capacitor for SRAM”). Thus, the stored contents can be held for about 50 hours. By providing the electrolytic capacitor for SRAM on the power supply board 851, when the game board 4 is detached from the pachinko gaming machine 1, backup power is not supplied to the peripheral control SRAM 4150d. Therefore, the peripheral control SRAM 4150d stores the stored contents. Loses its contents because it can no longer hold.

  The peripheral control external WDT 4150e is a timer for monitoring whether or not the system of the peripheral control MPU 4150a is running out of control. When this timer expires, a hardware reset is performed. That is, the peripheral control MPU 4150a is reset when a clear signal for clearing the timer of the peripheral control external WDT 4150e is not output to the peripheral control external WDT 4150e within a certain period (until the timer expires). When the peripheral control MPU 4150a outputs a clear signal to the peripheral control external WDT 4150e within a certain period, the peripheral control external WDT 4150e can restart the timer count of the peripheral control external WDT 4150e, and therefore no reset is applied.

  The peripheral control MPU 4150a incorporates a plurality of parallel I / O ports, serial I / O ports, and the like. When various commands are received from the main control board 4100, the peripheral control MPU 4150a is provided on the game board 4 based on the various commands. The game balls to be paid out as prize balls based on the game balls entered in the various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning opening 2104, 2201, and the large winning opening 2103 shown in FIG. Each time the number of balls reaches a predetermined number of balls (in this embodiment, it is set to 10), a main prize ball number information output signal for notifying the fact from the parallel I / O port When the power is cut off based on the power consumption status history information output to the external terminal board 784 via the control output circuit or stored in the power consumption status history RAM 4150f Power saving mode to convey the state of transition to the power saving mode during power recovery by grasping the power status consumed by the pachinko gaming machine 1 at the time of power recovery and suppressing the power consumed by the pachinko machine 1 immediately before the power is turned off An information output signal is output from the parallel I / O port to the external terminal board 784 via a peripheral control output circuit (not shown), or a lighting signal, a flashing signal, or the like for a plurality of LEDs provided on various decorative boards of the game board 4 The game board side emission data for outputting the gradation lighting signal is transmitted from the serial I / O port for the lamp driving board to the lamp driving board 4170 via a peripheral control output circuit (not shown), or various kinds of data provided on the gaming board 4 The game board side motor drive data for outputting a drive signal to an electric drive source such as a motor or solenoid for operating the movable body is used as a serial I / O port for the motor drive board. The door side motor drive data for transmitting the drive signal to the electric drive source such as the dial drive motor 414 provided on the door frame 5 from the door to the motor drive board 4180 via the peripheral control output circuit is frame decorated. Transmission from the drive amplifier board motor serial I / O port to the frame decoration drive amplifier board 194 via the peripheral control output circuit, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882, and various decorations of the door frame 5 The door side light emission data for outputting lighting signals, blinking signals or gradation lighting signals to a plurality of LEDs etc. provided on the board is sent from the frame decoration drive amplifier board LED serial I / O port to the peripheral control output circuit, frame periphery Transmission to the frame decoration drive amplifier board 194 via the relay terminal board 868 and the peripheral door relay terminal board 882, and detection control of the touch state of the touch panel 480 are performed. Control commands (for example, a detection control start command for starting detection control of the touch state of the touch panel 480, a contact position data request command for requesting a position where the finger touches the touch panel 480 (contact position data), Power saving mode transition command for shifting to power saving mode. ) From the serial I / O port for the touch panel drive board to the touch panel drive board 450 via the peripheral control output circuit, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882.

  Various commands from the main control board 4100 are input to the serial I / O port for main control board of the peripheral control MPU 4150a via a peripheral control input circuit (not shown). In addition, a detection signal from a rotation detection switch for detecting the rotation (rotation direction) of the dial operation unit 401 and a pressure detection switch for detecting the operation of the pressing operation unit 405 provided in the operation unit 400. The detection signal is serialized by a door-side serial transmission circuit (not shown) provided on the frame decoration drive amplifier board 194, and the serialized operation unit detection data is transmitted from the door-side serial transmission circuit to the peripheral door relay terminal plate 882, the frame. The signal is input to the operation unit detection serial I / O port of the peripheral control MPU 4150a via the peripheral relay terminal plate 868 and the peripheral control input circuit. Further, a position where a finger touches the touch panel 480 from the touch panel drive board 450 that performs detection control of the touch state of the touch panel 480 via the peripheral door relay terminal board 882, the frame peripheral relay terminal board 868, and the peripheral control input circuit. (Contact position data) is serialized and input to the serial I / O port for touch panel drive board of the peripheral control MPU 4150a.

  Detection signals from various detection switches (for example, photosensors) for detecting the original positions and movable positions of various movable bodies provided on the game board 4 are on the game board side (not shown) provided on the motor drive board 4180. Serialized by the serial transmission circuit, and this serialized movable body detection data is input to the serial I / O port for the motor drive board of the peripheral control MPU 4150a from the serial transmission circuit on the game board via the peripheral control input circuit. Yes. The peripheral control MPU 4150a exchanges various data between the peripheral control board 4140 and the motor drive board 4180 by switching the input / output of the serial I / O port for the motor drive board.

  Peripheral control MPU 4150a has a built-in watchdog timer (hereinafter referred to as “peripheral control built-in WDT”). It is diagnosed whether or not.

[7-4-1a. Peripheral control MPU]
Next, the peripheral control MPU 4150a which is a microcomputer will be described. As shown in FIG. 16, the peripheral control MPU 4150a has a peripheral control built-in RAM 4150ab, a peripheral control DMA (Direct Memory Access) controller 4150ac, a peripheral control bus controller 4150ad, and various peripheral control serial I's. / O port 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O ports 4150ag, peripheral control analog / digital converter (hereinafter referred to as peripheral control A / D converter) 4150ak, and the like.

  Peripheral control CPU core 4150aa reads / writes various data to / from peripheral control built-in RAM 4150ab and peripheral control DMA controller 4150ac via internal bus 4150ah, while peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT 4150af, Various data are read from and written to the various peripheral control parallel I / O ports 4150ag and the peripheral control A / D converter 4150ak via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai.

  The peripheral control CPU core 4150aa reads various data from the peripheral control ROM 4150b via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h, while the peripheral control RAM 4150c, the peripheral control SRAM 4150d, and the power Various data are read from and written to the consumption status history RAM 4150f via the internal bus 4150ah, the peripheral control bus controller 4150ad, and the external bus 4150h.

  The peripheral control DMA controller 4150ac includes storage devices such as a peripheral control built-in RAM 4150ab, a peripheral control ROM 4150b, a peripheral control RAM 4150c, and a peripheral control SRAM 4150d, peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O port 4150ag and a dedicated controller that transfers data independently between the input / output devices such as the peripheral control A / D converter 4150ak without using the peripheral control CPU core 4150aa. ~ It has four channels called DMA3.

  Specifically, the peripheral control DMA controller 4150ac includes a storage device of a peripheral control built-in RAM 4150ab incorporated in the peripheral control MPU 4150a, various peripheral control serial I / O ports 4150ae and peripheral control built-in WDT 4150af incorporated in the peripheral control MPU 4150a. In order to transfer data independently between the peripheral control various parallel I / O ports 4150ag and the input / output devices such as the peripheral control A / D converter 4150ak without the peripheral control CPU core 4150aa. The peripheral control built-in RAM 4150ab reads / writes data from / to the storage device via the internal bus 4150ah, while the peripheral control serial I / O port 4150ae, the peripheral control built-in WDT 4150af, and the peripheral control various parallel I / O port 4150. g, and the peripheral control A / D converter input and output devices such as 4150Ak, via the peripheral control bus controller 4150ad and peripheral bus 4150Ai, reading and writing.

  The peripheral control DMA controller 4150ac is a storage device such as a peripheral control ROM 4150b, a peripheral control RAM 4150c, and a peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a, and various peripheral control serial I / Os built in the peripheral control MPU 4150a. Without the peripheral control CPU core 4150aa between the input / output devices such as the O port 4150ae, the peripheral control built-in WDT 4150af, the peripheral control various parallel I / O ports 4150ag, and the peripheral control A / D converter 4150ak. In order to perform data transfer independently, peripheral control bus controller 4150ad and external bus 4150h are connected to storage devices such as peripheral control ROM 4150b, peripheral control RAM 4150c, and peripheral control SRAM 4150d. The peripheral control I / O port 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O port 4150ag, peripheral control A / D converter 4150ak, etc. Reading and writing are performed via the control bus controller 4150ad and the peripheral bus 4150ai.

  The peripheral control bus controller 4150ad controls the internal bus 4150ah, peripheral bus 4150ai, and external bus 4150h to control the central processing unit of the peripheral control MPU core 4150aa, peripheral control built-in RAM 4150ab, peripheral control ROM 4150b, peripheral control RAM 4150c, and peripheral control Various devices such as storage devices such as SRAM 4150d, peripheral control various serial I / O ports 4150ae, peripheral control built-in WDT 4150af, peripheral control various parallel I / O ports 4150ag, and peripheral control A / D converter 4150ak It is a dedicated controller that exchanges various data between them.

  Peripheral control various serial I / O ports 4150ae are: lamp drive board serial I / O port, motor drive board serial I / O port, frame decoration drive amplifier board motor serial I / O port, frame decoration drive amplifier board LED Serial I / O port, frame decoration drive amplifier board motor serial I / O port, main control board serial I / O port, operation unit information acquisition serial I / O port, and touch panel drive board serial I / O Has a port.

  Peripheral control built-in watchdog timer (peripheral control built-in WDT) 4150af is a timer for monitoring whether the system of the peripheral control MPU 4150a is running out of control, and when this timer is up, the hardware reset is performed. It has become. In other words, when the watchdog timer is started, the peripheral control CPU core 4150aa resets when the clear signal for clearing the timer is not output to the peripheral control built-in WDT 4150af within a certain period (until the timer is up). Will take. When the peripheral CPU core 4150aa starts the watchdog timer and outputs a clear signal to the peripheral control built-in WDT 4150af within a certain period, the peripheral count CPU core 4150aa can restart the timer count and is not reset.

  The peripheral control various parallel I / O port 4150ag outputs various latch signals such as a game board side motor drive latch signal and a door side motor drive light emission latch signal, and also outputs a clear signal to the peripheral control external WDT 4150e, As the winning balls are paid out based on game balls entered in various winning ports such as the upper starting port 2101, the lower starting port 2102, the general winning ports 2104, 2201 and the big winning port 2103 shown in FIG. Each time the number of game balls to be played reaches a predetermined number of balls (in this embodiment, 10 is set), the main prize ball number information is used as main prize ball number information for notifying that effect. An output signal is output to the external terminal board 784, or when the power is turned off based on the power consumption status history information stored in the power consumption status history RAM 4150f ) To save power as power-saving mode information for grasping the power state consumed by the pachinko gaming machine 1 at the time of power recovery and transferring the power-saving mode at the time of power recovery to suppress the power consumed by the pachinko gaming machine 1 The motor drive board 4180 is provided with detection signals from various detection switches for outputting mode information output signals to the external terminal board 784 and detecting the original positions and movable positions of various movable bodies provided on the game board 4. Movable body for serialization by a game board side serial transmission circuit (not shown) and receiving the serialized movable body detection data from the game board side serial transmission circuit at the serial I / O port for the motor drive board of the peripheral control MPU 4150a An information acquisition latch signal is output, or a lighting signal of an LED mounted on the upper decorative board of the upper decorative unit 280 in the door frame 5 Output to or. This LED is a high-intensity white LED and serves as a confirmation notification lamp for informing that the occurrence of the big hit gaming state has been confirmed. In this embodiment, by adopting a configuration in which the LED and the peripheral control various parallel I / O ports 4150ag are directly connected electrically, the path between the LED and the peripheral control various parallel I / O ports 4150ag is shortened. Therefore, it is possible to take noise countermeasures for lighting control of the LED having a significant meaning in games. Note that the output control of the main prize ball number information output signal, the output control of the power saving mode information output signal, and the lighting control of the LED are executed in a peripheral control unit 1 ms timer interrupt process described later. In addition, lighting control of other LEDs other than LEDs that are controlled to be lighted in a peripheral control unit 1 ms timer interrupt process described later is executed in a peripheral control unit steady process described later.

  The peripheral control A / D converter 4150ak is electrically connected to the volume adjustment volume 4140a, and the resistance value is changed by rotating the knob portion of the volume adjustment volume 4140a, and the resistance at the rotation position of the knob portion is changed. The voltage divided by the value is converted from an analog value to a digital value, and converted to a value in 1024 steps from a value 0 to a value 1023. In the present embodiment, the values of 1024 levels are divided into seven and managed as substrate volumes 0-6. The substrate volume 0 is set to mute, the substrate volume 6 is set to the maximum volume, and the volume is set to increase from the substrate volume 0 toward the substrate volume 6. The liquid crystal and sound control unit 4160 (a sound source built-in VDP 4160a to be described later) is controlled so that the volume is set to the substrate volume 0 to 6 and the speaker and door frame 5 housed in the speaker box 820 provided in the main body frame 3 Music and sound effects flow from the provided speaker 130. In this way, music and sound effects flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 by volume adjustment based on the turning operation of the knob portion. .

  In the present embodiment, in addition to music and sound effects, notification sounds for notifying a hall clerk or the like of the occurrence of a malfunction of the pachinko gaming machine 1 or fraudulent acts on the pachinko gaming machine 1, contents relating to game effects, etc. (For example, the screen spread on the game board side liquid crystal display device 1900 is rendered more powerful, or the game state is likely to shift to a game state advantageous to the player). ) Also flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the notification sound and the notification sound are adjusted in volume based on the turning operation of the knob portion. The sound volume flows from the mute to the maximum volume by a liquid crystal and sound control unit 4160 (a sound source built-in VDP 416 described later). So that the it can be adjusted by controlling the a). The volume adjusted by this program can be smoothly changed from the mute to the maximum volume, unlike the substrate volume divided into the above seven stages. Thus, for example, even when a hall clerk or the like rotates the knob portion of the volume adjustment volume 4140a to set the volume to a low level, the speakers and doors housed in the speaker box 820 provided in the main body frame 3 Although the production sound such as music and sound effects flowing from the speaker 130 provided in the frame 5 is reduced, the sound volume is increased when a malfunction occurs in the pachinko gaming machine 1 or when the player is cheating. In the embodiment, the notification sound set to the maximum volume) can be played. Therefore, even if the volume of the production sound is reduced, it is possible to prevent the hall clerk or the like from becoming difficult to notice the occurrence of a malfunction or the player's cheating due to the notification sound. Also, based on the current board volume set by volume adjustment based on the turning operation of the knob part, the volume of the advertisement sound is reduced so as not to interfere with the music and sound effects. In addition to music and sound effects, there is a possibility that the screen unfolded on the game board side liquid crystal display device 1900 will be rendered more powerful, or the game state may be shifted to an advantageous game state. You can also announce that it is expensive.

[7-4-1b. Peripheral control ROM]
The peripheral control ROM 4150b stores in advance various control programs, various data, various control data, and various schedule data for controlling the peripheral control unit 4150, the liquid crystal and sound control unit 4160, the RTC control unit 4165, and the like. The various schedule data includes screen generation schedule data for generating a screen to be drawn on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470, and light emission modes of various LEDs. Disbursement as emission mode generation schedule data, sound generation schedule data for generating music, sound effects, etc., electric drive source schedule data for generating drive modes of electric drive sources such as motors and solenoids, and prize balls A main prize for generating a main prize ball information output signal for notifying the hall computer as main prize ball information that the number of scheduled game balls has reached a predetermined number (10 balls in this embodiment). Sphere information output signal schedule data and the like. The screen generation schedule data is configured by arranging screen data defining the screen configuration in time series. The game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. The order of screens to be drawn is defined. The light emission mode generation schedule data is configured by arranging light emission data defining the light emission modes of various LEDs in time series. The sound generation schedule data is configured by arranging sound command data in time series, and defines the order in which music and sound effects flow. The sound command data includes an output channel number for instructing which output channel to use among a plurality of output channels in a built-in sound source of the sound source built-in VDP 4160a of the liquid crystal and sound control unit 4160, and a sound source built-in VDP 4160a. A track number for instructing which track to incorporate sound data such as music and sound effects out of a plurality of tracks in the built-in sound source is defined. The electrical drive source schedule data is configured by arranging drive data of electrical drive sources such as motors and solenoids in time series, and defines the operation of electrical drive sources such as motors and solenoids. The main award ball information output signal schedule data is a hall with main award ball information indicating that the number of game balls to be paid out as a prize ball has reached a predetermined number (10 balls in this embodiment). Output waveform data for generating a main prize ball information output signal to be transmitted to the computer is arranged in time series, and an output waveform of the main prize ball information output signal is defined.

  Various control programs stored in the peripheral control ROM 4150b may be read out and executed directly from the peripheral control ROM 4150b, or copied to various control program copy areas of the peripheral control RAM 4150c described later when the power is turned on. Some are read and executed. In addition, various data, various control data, and various schedule data stored in the peripheral control ROM 4150b may be directly read from the peripheral control ROM 4150b, or when various power control data copy areas of the peripheral control RAM 4150c described later are turned on. Some of which are copied in the above are read out.

  Further, the peripheral control ROM 4150b is one of various control programs for controlling the RTC control unit 4165 to correct the luminance of the game board side liquid crystal display device 1900 according to the usage time of the game board side liquid crystal display device 1900. A brightness correction program is included. This brightness correction program corrects a decrease in brightness due to aging of the game board side liquid crystal display device 1900 when the backlight of the game board side liquid crystal display device 1900 is mounted with an LED type. The date and time when the game board side liquid crystal display device 1900 is first turned on, the current date and time, the luminance setting information, and the like are acquired from the built-in RAM of the RTC control unit 4165 described later, and the acquired luminance setting information is based on the correction information. To correct. This correction information is stored in advance in the peripheral control ROM 4150b. As will be described later, the brightness setting information includes brightness adjustment information for adjusting the range of the brightness of the LED, which is the backlight of the game board side liquid crystal display device 1900, from 100% to 70% in increments of 5%, The brightness of the LED that is the backlight of the game board side liquid crystal display device 1900 that is set is included. For example, the date and time when the game board side liquid crystal display device 1900 was first turned on and the current date and time From the date when the game board side liquid crystal display device 1900 is first powered on, when six months have already passed, the corresponding correction information (for example, 5%) is obtained from the peripheral control ROM 4150b, and the brightness When the brightness of the LED included in the setting information is 75% and the backlight of the game board side liquid crystal display device 1900 is turned on, the correction information acquired for this 75% is used. On the game board side, the brightness of the backlight of the game board side liquid crystal display device 1900 is adjusted based on the brightness adjustment information included in the brightness setting information so that the brightness is further increased by 5%. If December has already passed since the date when the liquid crystal display device 1900 was first turned on, the corresponding correction information (for example, 10%) is acquired from the peripheral control ROM 4150b, and the LED included in the luminance setting information When the backlight of the game board side liquid crystal display device 1900 is turned on with the brightness of 75%, the brightness setting is set so that the brightness is further increased by 10%, which is the correction information acquired with respect to 75%, to 85%. Based on the brightness adjustment information included in the information, the brightness of the backlight of the game board side liquid crystal display device 1900 is adjusted to light up.

[7-4-1c. Peripheral control RAM]
A peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a, as shown in FIG. 16, is a backup that exclusively stores information to be backed up among various information updated by executing various control programs. A management target work area 4150ca, a backup first area 4150cb and a backup second area 4150cc for storing a copy of various information stored in the backup management target work area 4150ca, and a peripheral control ROM 4150b. Various control program copy area 4150cd for storing a copy of the various control programs exclusively, and various data, various control data, various schedule data, etc. stored in peripheral control ROM 4150b, etc. Various control data copy area 4150ce for storing the copied data exclusively, and backup non-management target for storing the information not updated for backup among the various information updated by executing various control programs And a work area 4150cf.

  When the pachinko gaming machine 1 is turned on (including when power is restored due to a momentary power failure or a power failure), the value 0 is forcibly written to the backup unmanaged work area 4150cf and cleared to zero. For the backup management target work area 4150ca, the backup first area 4150cb, and the backup second area 4150cc, the power-on state command (see FIG. 41) from the main control board 4100 is cleared to RAM when the pachinko gaming machine 1 is powered on. The start of the effect and the game state are instructed (for example, the start of the effect is instructed when the operation switch 860a shown in FIG. 12 is operated within a predetermined period from when the power is turned on) Is cleared to zero.

  The backup management target work area 4150ca is effect information (various information updated in the peripheral control unit steady process executed each time a V blank signal from the VDP 4160a with built-in sound source of the liquid crystal and sound control unit 4160 described later is input) Bank 0 (1fr) for storing 1fr) exclusively as a backup target, and production information (1ms) which is various information updated in the peripheral control unit 1ms timer interrupt process executed every time a 1ms timer interrupt described later occurs. Bank 0 (1 ms) that is stored exclusively as a backup target. Here, the names of Bank0 (1fr) and Bank0 (1 ms) will be briefly described. “Bank” is a minimum management unit representing the size of a storage area for storing various information. The subsequent “0” means that the storage area is normally used for storing various information updated by executing various control programs. That is, “Bank 0” means that the size of the storage area that is normally used is the minimum management unit. In addition, “Bank1,” “Bank2,” “Bank3,” and “Bank4” provided in an area extending from a backup first area 4150cb to a backup second area 4150cc, which will be described later, are stored in the same storage area as “Bank0”. It means having a size. As will be described later, “(1fr)” indicates that the sound source built-in VDP 4160a draws drawing data for one screen (one frame) on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device. When the V blank signal is inputted to the peripheral control MPU 4150a, the V blank signal indicating that the screen data from the peripheral control MPU 4150a can be received is output to the peripheral control MPU 4150a. In other words, since the peripheral control unit steady process is executed for each frame (1 frame), “Bank0”, “Bank1”, “Bank2”, “Bank3”, and “Bank4” are respectively appended ( The same applies to effect information (1fr) and effect backup information (1fr) described later. Used in the meaning). As described later, “(1 ms)” indicates that “Bank0”, “Bank1”, “Bank2”, “Bank3”, “Bank0”, “Bank1”, “Bank3”, and the like are executed every time a 1 ms timer interrupt occurs. And “Bank 4”, respectively (the effect information (1 ms) and the effect backup information (1 ms) described later are also used in the same meaning).

  Bank0 (1fr) includes a lamp drive board side transmission data storage area 4150caa, a frame decoration drive amplifier board side LED transmission data storage area 4150cab, a reception command storage area 4150cac, an RTC information acquisition storage area 4150cad, and a schedule data storage area 4150cae. Etc. are provided. In the lamp drive board side transmission data storage area 4150caa, the game board side light emission data SL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs provided on various decoration boards of the game board 4 is provided. Is set in the frame decoration drive amplifier board side LED transmission data storage area 4150cab, which is a lighting signal, blinking signal, or gradation lighting to a plurality of LEDs provided on various decoration boards of the door frame 5. This is a storage area in which door side light emission data STL-DAT for outputting a signal is set. In the reception command storage area 4150cac, various commands transmitted from the main control board 4100 are received and the received various commands are stored. The RTC information acquisition storage area 4150cad has an RTC control unit 4165 (RTC 4165 described later). This is a storage area in which various types of information acquired from the RTC built-in RAM 4165aa) are set. The schedule data storage area 4150cae includes the received command based on the command received from the main control board 4100 (main control MPU 4100a). This is a storage area in which various corresponding schedule data are set. In the schedule data storage area 4150cae, some schedule data copied from the peripheral control ROM 4150b to the various control data copy areas 4150ce are read and set, and various schedule data are directly read from the peripheral control ROM 4150b. Some are set.

  Bank 0 (1 ms) includes a frame decoration drive amplifier board side motor transmission data storage area 4150 caf, a motor drive board side transmission data storage area 4150 cag, a movable body information acquisition storage area 4150 cah, an operation unit information acquisition storage area 4150 cai, and a drawing. A state information acquisition storage area 4150cak and the like are provided. In the frame decoration drive amplifier board side motor transmission data storage area 4150caf, door side motor drive data STM-DAT for outputting a drive signal to an electric drive source such as a dial drive motor 414 provided in the door frame 5 is stored. This is a storage area to be set, and a motor drive board side transmission data storage area 4150cag is used to output a drive signal to an electric drive source such as a motor or solenoid for operating various movable bodies provided in the game board 4. This is a storage area where the game board side motor drive data SM-DAT is set. The movable body information acquisition storage area 4150cah is provided in the game board 4 based on detection signals from various detection switches provided in the game board 4. This is a storage area in which various information obtained by acquiring the original position and the movable position of various movable bodies is set, and an operation unit information acquisition storage area 4150ca. Includes various information (for example, in the operation unit 400) obtained from the rotation (rotation direction) of the dial operation unit 401 and the operation of the pressing operation unit 405 based on detection signals from various detection switches provided in the operation unit 400. The rotation (rotation direction) history information of the dial operation unit 401, the operation history information of the pressing operation unit 405, and the like created based on detection signals from the various detection switches provided. In the state information acquisition storage area 4150cak, when the touch panel drive board 450 receives drawing data from the sound source built-in VDP 4160a of the peripheral control board 4140 and determines that the received drawing data is abnormal data, it notifies that fact. The peripheral control board 4140 and the touch panel drive based on the LOCKN signal described later outputted to Various information acquired defect frequency and bug occurrence between connection of the substrate 450 is a storage area is set.

  The bank 0 (1fr) lamp drive board side transmission data storage area 4150caa and the frame decoration drive amplifier board side LED transmission data storage area 4150cab, and the Bank 0 (1 ms) frame decoration drive amplifier board side motor transmission data storage area 4150caf. The motor drive board side transmission data storage area 4150cag is divided into two areas, a first area and a second area, respectively.

  In the lamp drive board side transmission data storage area 4150caa, when the peripheral control unit steady process described later is executed, the game board side light emission data SL-DAT is set in the first area of the lamp drive board side transmission data storage area 4150caa. When the next peripheral control unit steady process is executed, the game board side light emission data SL-DAT is set in the second area of the lamp drive board side transmission data storage area 4150caa. Each time the process is executed, the game board side light emission data SL-DAT are alternately set in the first area and the second area of the lamp drive board side transmission data storage area 4150caa. For example, when the game board side light emission data SL-DAT is set in the second area of the lamp drive board side transmission data storage area 4150caa in the current peripheral control part steady process, When the control unit steady process is executed, the process proceeds based on the game board side light emission data SL-DAT set in the first area of the lamp drive board side transmission data storage area 4150caa.

  When the peripheral control unit steady process is executed, the frame decoration drive amplifier board side LED transmission data storage area 4150cab has the door side light emission data STL in the first area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. -DAT is set, and when the next peripheral control unit steady process is executed, the door side light emission data STL-DAT is set in the second area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. Each time the peripheral control unit steady process is executed, the door side light emission data STL-DAT is alternately set in the first area and the second area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. The For example, when the door side light emission data STL-DAT is set in the second area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab in the current peripheral control part steady process, When the previous peripheral control unit steady process is executed, the process proceeds based on the door side light emission data STL-DAT set in the first area of the frame decoration drive amplifier board side LED transmission data storage area 4150cab. It has become.

  The frame decoration drive amplifier board side motor transmission data storage area 4150caf has a door in the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf when a later-described peripheral control unit 1 ms timer interrupt process is executed. When the side motor drive data STM-DAT is set and the next peripheral control unit 1 ms timer interrupt process is executed, the door side motor drive data STM is stored in the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. -DAT is set, and each time the peripheral control unit 1 ms timer interrupt process is executed, the door side is connected to the first area and the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. Motor drive data STM-DAT is set alternately. The peripheral control unit 1 ms timer interrupt process is executed. For example, in this peripheral control unit 1 ms timer interrupt process, the door side motor drive data STM-DAT is stored in the second area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf. When set, the door side motor drive data STM-DAT set in the first area of the frame decoration drive amplifier board side motor transmission data storage area 4150caf when the previous peripheral control unit 1 ms timer interrupt process was executed. The process is based on this.

  When the peripheral control unit 1 ms timer interrupt process is executed, the motor drive board side transmission data storage area 4150cag is set with the game board side motor drive data SM-DAT in the first area of the motor drive board side transmission data storage area 4150cag. When the next peripheral control unit 1 ms timer interrupt process is executed, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150cag, Each time the peripheral control unit 1 ms timer interrupt process is executed, the game board side motor drive data SM-DAT are alternately set in the first area and the second area of the motor drive board side transmission data storage area 4150cag. The peripheral control unit 1 ms timer interrupt process is executed. For example, in the current peripheral control unit 1 ms timer interrupt process, the game board side motor drive data SM-DAT is set in the second area of the motor drive board side transmission data storage area 4150cag. Sometimes, when the previous peripheral control unit 1 ms timer interrupt process is executed, the process proceeds based on the game board side motor drive data SM-DAT set in the first area of the motor drive board side transmission data storage area 4150cag. It is like that.

  Next, the backup first area 4150cb and backup second area 4150cc that store specially copied production information, which is various information stored in the backup management target work area 4150ca, will be described. In the backup first area 4150cb and the backup second area 4150cc, two pairs each having two banks as one pair are managed as one page. Production information (1fr), which is the content stored in Bank0 (1fr), which is a storage area that is normally used, is produced as production backup information (1fr) every time the peripheral control unit steady process is executed for each frame (1frame). In addition, the production information (1 ms) which is the content stored in Bank0 (1 ms), which is a storage area normally used, is copied to the backup first area 4150 cb and the backup second area 4150 cc at high speed by the peripheral control DMA controller 4150ac. As the production backup information (1 ms), the peripheral control DMA controller 41 is assigned to the backup first area 4150 cb and the backup second area 4150 cc each time the peripheral control unit 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. It is copied to the high speed by 0ac. The consistency of one page is determined by whether or not the contents of two banks constituting the page match.

  Specifically, the backup first area 4150cb is managed as a pair of Bank1 (1fr) and Bank2 (1fr) as one pair, and Bank1 (1ms) and Bank2 (1ms) as one pair. ing. The contents stored in Bank0 (1fr), which is a storage area that is normally used, are the peripheral control DMA in Bank1 (1fr) and Bank2 (1fr) each time the peripheral control unit steady process is executed for each frame (1frame). The memory that is copied at a high speed by the controller 4150ac and stored in Bank0 (1 ms), which is a storage area that is normally used, is stored every time a peripheral control unit 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. The peripheral control DMA controller 4150ac copies the data to Bank1 (1ms) and Bank2 (1ms) at high speed. The consistency of this page is determined by whether or not the contents of Bank1 (1fr) and Bank2 (1fr) match. Bank1 (1ms) and Bank2 ( It carried out by whether or not the contents of the ms) are the same.

  The backup second area 4150cc is managed as one page with a total of two pairs, with Bank3 (1fr) and Bank4 (1fr) as one pair and Bank3 (1ms) and Bank4 (1ms) as one pair. The contents stored in Bank0 (1fr), which is a storage area that is normally used, are the peripheral control DMA in Bank3 (1fr) and Bank4 (1fr) each time the peripheral control unit steady process is executed for each frame (1frame). The memory that is copied at a high speed by the controller 4150ac and stored in Bank0 (1 ms), which is a storage area that is normally used, is stored every time a peripheral control unit 1 ms timer interrupt process is executed every time a 1 ms timer interrupt occurs. It is copied to Bank 3 (1 ms) and Bank 4 (1 ms) at high speed by the peripheral control DMA controller 4150ac. The consistency of this page is determined by whether or not the contents of Bank 3 (1 fr) and Bank 4 (1 fr) match, Bank3 (1 ms) and Bank4 ( It carried out by whether or not the contents of the ms) are the same.

  As described above, in this embodiment, the backup first area 4150cb has one pair of Bank1 (1fr) and Bank2 (1fr), and one pair of Bank1 (1ms) and Bank2 (1ms). It is an area to manage as a page, and the backup second area 4150 cc has a total of 2 pairs, with Bank 3 (1 fr) and Bank 4 (1 fr) as one pair, Bank 3 (1 ms) and Bank 4 (1 ms) as one pair This is an area for management as one page. Different ID codes are stored at the beginning and end of each page, that is, at the beginning and end of the backup first area 4150cb and backup second area 4150cc.

  In the present embodiment, the production information (1fr) that is the content stored in Bank0 (1fr) that is a storage area that is normally used is the production control information (1fr), and the peripheral control unit for each frame (1frame). Every time the steady process is executed, the contents are copied to the backup first area 4150cb and the backup second area 4150cc at high speed by the peripheral control DMA controller 4150ac and stored in Bank0 (1 ms) which is a storage area used normally. The production information (1 ms) is, as production backup information (1 ms), every time the 1 ms timer interrupt is generated, the backup first area 4150 cb and the backup second area 4150 cc are executed each time the peripheral control unit 1 ms timer interruption process is executed. Peripheral control Although designed to be copied at a high speed by the MA controller 4150Ac, a program for executing a fast copy from these peripheral control DMA controller 4150Ac are common. That is, in this embodiment, the production information (1fr) and the production information (1 ms) are managed by a common management method (execution of a common program).

[7-4-1d. Peripheral control SRAM]
A peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a includes a backup management target work area 4150da that exclusively stores information to be backed up among various information updated by executing various control programs. A backup first area 4150db and a backup second area 4150dc are provided for storing a copy of various information stored in the backup management target work area 4150da. The contents stored in the peripheral control SRAM 4150d are the power-on state commands (see FIG. 41) from the main control board 4100 when the pachinko gaming machine 1 is turned on (including when power is restored due to an instantaneous power failure or power failure). ) Instructs the start of the RAM clear effect and the gaming state (for example, instructs the start of the effect when the operation switch 860a shown in FIG. 12 is operated within a predetermined period from when the power is turned on. Is not cleared to zero. This is completely different from the point that the backup management target work area 4150ca, the backup first area 4150cb, and the backup second area 4150cc of the peripheral control RAM 4150c described above are cleared to zero. Further, when the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the power of the pachinko gaming machine 1 is turned on, a screen for performing the setting mode is displayed on the game board side liquid crystal display device 1900. It has come to be. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the setting mode screen, each content (item) stored in the peripheral control SRAM 4150d (for example, a history of occurrence of a big hit gaming state, etc.) On the other hand, the contents (items) stored in the peripheral control RAM 4150c are not displayed at all and cannot be cleared in the setting mode. This point is also completely different between the peripheral control RAM 4150c and the peripheral control SRAM 4150d.

  The backup management target work area 4150da is production information (SRAM) which is various information continued across days (for example, information for managing the history of occurrence of the big hit gaming state and special production flag management) Information) and the like are stored in a dedicated manner as a backup target. Here, the name of Bank 0 (SRAM) will be briefly described. As described above, “Bank” is a minimum management unit indicating the size of a storage area for storing various types of information. The subsequent “0” means a storage area that is normally used for storing various information updated by executing various control programs. That is, “Bank 0” means that the size of the storage area that is normally used is the minimum management unit. “Bank1,” “Bank2,” “Bank3,” and “Bank4” provided in an area extending from a backup first area 4150db to a backup second area 4150dc, which will be described later, are in the same storage area as “Bank0”. It means having a size. Since “(SRAM)” is a backup target of various information stored in the peripheral control SRAM 4150d externally attached to the peripheral control MPU 4150a, “Bank0”, “Bank1”, “Bank2”, “Bank3” , And “Bank 4”, respectively (effect information (SRAM) and effect backup information (SRAM) to be described later are also used in the same meaning).

  Next, the backup first area 4150db and backup second area 4150dc that store specially copied production information (SRAM), which is various information stored in the backup management target work area 4150da, will be described. The backup first area 4150db and the backup second area 4150dc are managed with one pair of two banks, and one pair as one page. Production information (SRAM), which is the content stored in Bank0 (SRAM), which is a storage area used normally, is production backup information (SRAM) each time the peripheral control unit steady process is executed for each frame (1 frame). The peripheral control DMA controller 4150ac copies the backup first area 4150db and the backup second area 4150dc at high speed. The consistency of one page is determined by whether or not the contents of two banks constituting the page match.

  Specifically, in the backup first area 4150db, Bank1 (SRAM) and Bank2 (SRAM) are managed as one pair, and this one pair is managed as one page. The contents stored in Bank0 (SRAM), which is a storage area that is normally used, are stored in the peripheral control DMA in Bank1 (SRAM) and Bank2 (SRAM) each time the peripheral control unit steady process is executed for each frame (1 frame). This page is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank1 (SRAM) and Bank2 (SRAM) match.

  In the backup second area 4150dc, Bank3 (SRAM) and Bank4 (SRAM) are managed as one pair, and this one pair is managed as one page. The contents stored in Bank0 (SRAM), which is a storage area that is normally used, are stored in the peripheral control DMA in Bank3 (SRAM) and Bank4 (SRAM) each time the peripheral control unit steady process is executed for each frame (1 frame). This page is copied at high speed by the controller 4150ac, and the consistency of this page is determined by whether or not the contents of Bank3 (SRAM) and Bank4 (SRAM) match.

  As described above, in this embodiment, the backup first area 4150db is an area for managing Bank 1 (SRAM) and Bank 2 (SRAM) as one pair, and managing this one pair as one page. Reference numeral 4150 dc is an area for managing Bank 1 (SRAM) and Bank 4 (SRAM) as one pair, and managing this one pair as one page. Different ID codes are stored at the beginning and end of each page, that is, at the beginning and end of the backup first area 4150db and backup second area 4150dc.

[7-4-1e. Power consumption status history RAM]
The power consumption status history RAM 4150f externally attached to the peripheral control MPU 4150a samples the value (power consumption suppression step) transmitted by the power consumption suppression signal from the power supply board 851 at a predetermined cycle (peripheral to be described later) This is stored and held as power consumption status history information (in the power consumption status history information creation processing in the control unit 1 ms timer interrupt processing). Specifically, the peripheral control MPU 4150a executes a peripheral control unit 1ms timer interrupt process every time a 1ms timer interrupt described later occurs, and in this peripheral control unit 1ms timer interrupt process, a power consumption suppression signal from the power supply board 851 is executed. Is sampled and stored in the power consumption status history RAM 4150f as power consumption status history information. In this embodiment, the power consumption status history information can store and hold the value (power consumption suppression stage) transmitted by the power consumption suppression signal for 3000 times as the number of samplings. When the transmitted value (power consumption suppression stage) is stored and held, the values (power consumption suppression stage) transmitted by the power consumption suppression signal already sampled up to the previous time are shifted one by one so that they are arranged in time series. The value (power consumption suppression stage) that is sampled and transmitted by the power consumption suppression signal is stored and held, and when the number of sampling reaches 3000 times, the value that is sampled and transmitted by the power consumption suppression signal (power consumption) Each time the suppression stage is stored, the value that the oldest sampled power consumption suppression signal conveys ( Power consumption inhibiting step) is adapted to be discarded one by one in sequence. In other words, the power consumption status history information includes the value (power consumption suppression stage) conveyed by the power consumption suppression signal sampled this time for the most recent 3000 times (in other words, the peripheral control MPU 4150a executes the peripheral control unit 1 ms timer interrupt process). Each time the value (power consumption suppression stage) transmitted by the power consumption suppression signal from the power supply board 851 is sampled and sequentially stored in the power consumption status history RAM 4150f as power consumption status history information, the peripheral control unit 1 ms timer interrupt processing Is executed 3000 times so that values (power consumption suppression steps) transmitted by the power consumption suppression signal for 3 seconds (= 1 ms × 3000 times) are arranged in time series.

[7-4-1f. Power saving mode transition notification LED]
The power saving mode transition notification LED 4150k indicates the power status consumed by the pachinko gaming machine 1 when the power is turned off (immediately before the power is turned off) based on the power consumption status history information stored in the power consumption status history RAM 4150f. This is to notify the state of transition to the power saving mode at the time of power recovery that suppresses the power consumed by the pachinko gaming machine 1 by grasping in FIG. The power saving mode transition notification LED 4150k is not electrically connected to the peripheral control board 4140 via a signal wiring, but is directly mounted on the peripheral control board 4140 so that the light emission mode is controlled by the peripheral control MPU 4150a. Has been. In this embodiment, the power-saving mode transition notification LED 4150k is a surface-mount type, which employs a high-luminance single color light emitting in green, and a staff such as a hall clerk shows the lock device shown in FIGS. When the main body frame 3 is opened with respect to the outer frame 2 by releasing the closed state of the main body frame 3 with respect to the outer frame 2 by inserting a key into the 1000 cylinder lock 1010 and rotating, The power saving mode transition notification LED 4150k is directly soldered to the peripheral control board 4140 at the position where the main frame 3 is attached to the back side of the pachinko gaming machine 1 (that is, the back side of the game board 4) and the outer frame 2. A staff member such as a clerk in the hall can see the issue mode of the power saving mode transition notification LED 4150k from the open side of the main body frame 3 when opened.

  Specifically, the peripheral control MPU 4150a stores the power consumption status history information stored and held in the power consumption status history RAM 4150f in the power saving power saving mode transition determination process in the power-on process of the peripheral control unit described later that is executed at the time of power recovery. Based on the above, it is determined whether or not to shift to the power saving mode at the time of power recovery by identifying the power status (power consumption suppression stage described later) consumed by the pachinko gaming machine 1 at the time of power-off (immediately before power-off). The peripheral control MPU 4150a sets the light emission mode of the power saving mode transition notification LED 4150k to the non-power saving notification mode (lighting state) when the determination result does not shift to the power saving power saving mode, while the determination result is the power saving power saving mode. When switching to the power saving mode, the light emission mode of the power saving mode transition notification LED 4150k is set to the power saving notification mode (light-off state). A staff member such as a store clerk of the hall rotates whether the pachinko machine 1 is in a state where it has shifted to the power saving mode after power recovery by inserting a key into the cylinder lock 1010 of the lock device 1000, By releasing the closed state of the main body frame 3 with respect to the outer frame 2 and opening the main body frame 3 with respect to the outer frame 2, it can be confirmed by visually observing the issue mode of the power saving mode transition notification LED 4150k.

  Here, the reason for adopting the surface mounting type that is directly soldered to the peripheral control board 4140 as the power saving mode transition notification LED 4150k will be briefly described. When the power saving mode transition notification LED 4150k is arranged away from the peripheral control board 4140 and is electrically connected to the peripheral control board 4140 through the signal wiring, for example, a staff member such as a hall clerk is working. When the signal wiring connector is disconnected from the peripheral control board 4140 or the main body frame 3 is opened with respect to the outer frame 2, the signal wiring is placed in the gap on the closing side of the main body frame 3. If the gap between the outer frame 2 and the outer frame 2 is closed to narrow the gap and the signal wiring is disconnected, it becomes difficult for the peripheral control MPU 4150a to control the light emission mode of the power saving mode transition notification LED 4150k. Because. In this embodiment, as the power saving mode transition notification LED 4150k, a surface mount type that is soldered directly to the peripheral control board 4140 is adopted, but a lead type that can be soldered directly to the peripheral control board 4140 is used. Also good.

[7-4-2. Liquid crystal and sound control unit]
Drawing control of the game board side liquid crystal display device 1900, movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470, and the speaker housed in the speaker box 820 provided in the main body frame 3 and the door frame 5 are provided. As shown in FIG. 15, the liquid crystal and sound control unit 4160 that performs sound control such as music and sound effects flowing from the speaker 130 has a built-in sound source for sound control such as music and sound effects (hereinafter referred to as “ VDP (Video Display Processor) with built-in sound source that performs drawing control on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. 4160a, game board side liquid crystal display device 1900, movable liquid crystal display devices 1925a to 1925d, and upper plate side liquid crystal display device 47. A liquid crystal and sound control ROM 4160b for storing various sound data such as music and sound effects in addition to various character data displayed on the screen, and a frame decoration driving amplifier board using the serialized music and sound effects as audio data The audio data transmission IC 4160c that transmits toward the 194 and the drawing data serialized to the upper plate side liquid crystal display device 470 below the upper plate side liquid crystal display device 470 attached to the right side of the plate unit 300 of the door frame 5 Transmitter IC4160d for upper plate side liquid crystal that transmits to the touch panel drive substrate 450 disposed in the vicinity and accommodated in the plate unit 300, and serial I / O for touch panel drive substrate built in the peripheral control MPU 4150a of the peripheral control unit 4150 LOCKN, which is serial data output from the O port In addition to the signal output from the differential circuit 4160e that differentiates the signal output request data into a plus signal and a minus signal and the transmitter IC 4160d for the upper plate side liquid crystal, the signal from the difference circuit 4160e is input. When the signal from the differential circuit 4160e is input, the circuit is connected so as to transmit the signal. On the other hand, when the signal from the differential circuit 4160e is not input, the upper plate side liquid crystal And a forced switching circuit 4160f for circuit connection so as to transmit a signal output from the transmitter IC 4160d. The liquid crystal and sound control ROM 4160b displays, for example, annular image data used for displaying a ring-shaped display object (annular display object), and an operation menu background image described later, as sprite data used for displaying a screen or an image described later. Operation menu background image data to be used, selection display object image data used for displaying at least one selection display object described later, tone adjustment background image data used for displaying a volume adjustment screen including a volume scale described later, and a volume adjustment icon described later In addition to volume setting icon image data used for display, display of main body frame rear surface image data and service mode screen used for display of main body frame rear image in which the position of each part on the rear surface of main body frame 3 can be viewed when viewed from the player Service mode screen image data used for breaks, breaks used to display break timer setting screens Timer setting screen image data, and, during breaks screen image data used for displaying the break in the screen is stored. Note that the liquid crystal and sound control ROM 4160b also stores suggestion display object image data used to display an suggestion display object for prompting that the pressing operation unit 405 (operation unit) of the operation unit 400 should be operated.

  The peripheral control MPU 4150a of the peripheral control unit 4150 extracts the screen generation schedule data corresponding to the command from the main control board 4100 from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. It is set in the schedule data storage area 4150cae of the peripheral control RAM 4150c, and the first screen data of the screen generation schedule data set in the schedule data storage area 4150cae is used as the various controls of the peripheral control ROM 4150b or the peripheral control RAM 4150c of the peripheral control unit 4150. After being extracted from the data copy area 4150ce and output to the sound source built-in VDP 4160a, the schedule data is triggered by the input of a V blank signal described later. The next screen data following the first screen data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c in accordance with the screen generation schedule data set in the storage area 4150cae and has a built-in sound source. Output to the VDP 4160a. As described above, the peripheral control MPU 4150a converts the screen data arranged in time series into the screen generation schedule data according to the screen generation schedule data set in the schedule data storage area 4150cae every time the V blank signal is input. In addition, the first screen data is output to the built-in sound source VDP 4160a one by one.

  Also, the peripheral control MPU 4150a receives the sound command data at the head of the sound generation schedule data corresponding to the command from the main control board 4100 from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. Extracted and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c, the head sound command data of the sound generation schedule data set in the schedule data storage area 4150cae is the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral control The schedule data storage is triggered by the input of the V blank signal after extracting from the various control data copy area 4150ce of the RAM 4150c and outputting it to the VDP 4160a with built-in sound source. In accordance with the sound generation schedule data set in the area 4150cae, the next sound command data following the head sound command data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c, and the sound source Output to built-in VDP 4160a. As described above, the peripheral control MPU 4150a receives the sound command data arranged in time series in the sound generation schedule data according to the sound generation schedule data set in the schedule data storage area 4150cae, and the V blank signal is input. Each time, the head sound command data is output to the built-in sound source VDP 4160a one by one.

[7-4-2a. Sound source built-in VDP]
When the screen data is input from the peripheral control MPU 4150a in addition to the above-described built-in sound source, the sound source built-in VDP 4160a receives a game board from the liquid crystal and sound control ROM 4160b based on the input screen data as shown in FIG. Sprite data is extracted by extracting the side character data and the upper plate character data and displayed on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. A VRAM for generating drawing data for one frame is also built in (hereinafter referred to as “built-in VRAM”). The built-in sound source VDP 4160a draws drawing data for the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d among the drawing data generated on the built-in VRAM from the channel CH1 via the liquid crystal output board 3420. In addition to outputting to the display device 1900 and the movable liquid crystal display devices 1925a to 1925d, drawing data for the upper plate side liquid crystal display device 470 is output from the channel CH2 to a peripheral control output circuit, frame peripheral relay terminal plate 868, peripheral door relay terminal (not shown). The game board side liquid crystal display device 1900 and the movable liquid crystal are output (transmitted) to the upper plate side liquid crystal display device 470 via the plate 882 and the touch panel drive substrate 450 housed in the plate unit 300 of the door frame 5. Display devices 1925a to 1925d and an upper plate side liquid crystal display device 470; Thereby achieving synchronization. Note that the screen data from the peripheral control MPU 4150a includes the game board side based on the position (contact position data) where the finger touches the touch panel 480 (that is, the image is reflected in the position touched by the finger). In some cases, the order of screens drawn on the liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper-side liquid crystal display device 470 is defined.

  The drawing data output from the channel CH1 is output from the peripheral control board 4140 to the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d, whereas the drawing data output from the channel CH2 is From the peripheral control board 4140, the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the plate placed near the lower side of the upper plate side liquid crystal display device 470 attached to the right side of the plate unit 300 of the door frame 5 It is output (transmitted) to the upper dish side liquid crystal display device 470 via the touch panel drive substrate 450 housed in the unit 300. As described above, the drawing data output from the channel CH1 is output from the peripheral control board 4140 to the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d as described above. Since the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d are respectively attached to the game board 4, from the channel CH1 to the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d. Although the wiring length required for the route is short, the drawing data output from the channel CH2 is transmitted from the peripheral control board 4140 via the touch panel drive board 450 accommodated in the dish unit 300 of the door frame 5 as described above. Since it is output to the upper plate side liquid crystal display device 470, peripheral control While the plate 4140 is attached to the game board 4, the touch panel drive substrate 450 is housed in the dish unit 300 of the door frame 5, so that the frame peripheral relay terminal plate 868, the peripheral door relay terminal from the channel CH 2. Since the length of the wiring required for the path to the plate 882 and the touch panel drive substrate 450 is extremely longer than that of the channel CH1, it is extremely susceptible to noise. For this reason, for the channel CH2 in which the length of the wiring for sending the drawing data is extremely longer than that of the channel CH1, "V-by-One ( By adopting a differential communication called “registered trademark”, the system is less susceptible to noise.

  The channel CH1 uses a serial differential interface called LVDS (Low Voltage Differential Signaling). In the present embodiment, a dual link method is adopted as the LVDS. The single link method uses one signal transmission line, whereas the dual link method uses two signal transmission lines. In the dual link system, when displaying an image with a large image size that cannot be supported by the transmission band of one signal transmission path by the single link system, the second signal transmission path is used, Data is transmitted simultaneously through the first signal transmission path and the second signal transmission path.

  In this embodiment, the game board side liquid crystal display device 1900 employs 12 inches having an image size of 800 × 600 dots, and the four movable liquid crystal display devices 1925a to 1925d have an image size of 480 × 272 dots, 4.3. Inch is adopted. That is, since the game board side liquid crystal display device 1900 and the four movable liquid crystal display devices 1925a to 1925d are not large in image size, the image size can be sufficiently displayed by a single link method if used alone. is there.

  In the present embodiment, the sound source built-in VDP 4160a has two channels, CH1 and CH2, for drawing data generated on the built-in VRAM. Therefore, when drawing data is transmitted by the single link method, the game board A total of six channels of the side liquid crystal display device 1900, the four movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 are required, and there are not enough channels for transmitting drawing data by the single link method.

  Therefore, in this embodiment, the dual link method is adopted. The first signal transmission path is an even channel, the second signal transmission path is an odd channel, and drawing data for the game board side liquid crystal display device 1900 is transmitted from the even channel to the liquid crystal output board 3420, while the odd channel has four channels. Drawing data for the movable liquid crystal display devices 1925a to 1925d is transmitted to the liquid crystal output substrate 3420. Drawing data is transmitted simultaneously for even and odd addresses by the dual link method.

  When the drawing data transmitted simultaneously to the even address and the odd address are received by the liquid crystal output board 3420, the drawing data of the even address is transmitted to the game board side liquid crystal display device 1900, and the drawing data of the odd address is four. It is transmitted to the movable liquid crystal display devices 1925a to 1925d.

  The channel CH2 uses a parallel interface for the channel CH1. The drawing data output from the channel CH2 is composed of three video signals, a red video signal, a green video signal, and a blue video signal, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. Serialized by the upper plate side liquid crystal transmitter IC 4610d and accommodated in a peripheral control output circuit (not shown), a frame peripheral relay terminal plate 868, a peripheral door relay terminal plate 882, and the tray unit 300 of the door frame 5. It is transmitted to the touch panel drive substrate 450. The various serialized signals are restored to parallel signals in the touch panel drive substrate 450 and output to the upper plate side liquid crystal display device 470.

  As described above, the peripheral control MPU 4150a displays the screen data for one screen (one frame) displayed on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 by the built-in sound source VDP 4160a. The sound source built-in VDP 4160a extracts the character data from the liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data, and the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925a. Drawing data for one screen (one frame) to be displayed on the 1925d and the upper plate side liquid crystal display device 470 is generated on the built-in VRAM, and among the generated drawing data, the game board side liquid crystal display device 1900 and the movable liquid crystal display are displayed. Drawing data for the devices 1925a to 1925d is sent to channel C. 1 to the liquid crystal output board 3420, and image data for the upper plate side liquid crystal display device 470 is transmitted from the channel CH2 to a peripheral control output circuit (not shown), a frame peripheral relay terminal plate 868, a peripheral door relay terminal plate 882, and the door frame 5 Is output (transmitted) to the upper dish side liquid crystal display device 470 via the touch panel drive substrate 450 housed in the dish unit 300. That is, “screen data for one screen (one frame)” means one screen (1) displayed on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. This is data for generating (frame) drawing data on the built-in VRAM.

  The sound source built-in VDP 4160a transmits drawing data for one screen (one frame) from the channel CH1 to the liquid crystal output board 3420, and image data for the upper plate side liquid crystal display device 470 from the channel CH2 is not shown in the peripheral control. When outputting (transmitting) to the upper dish side liquid crystal display device 470 via the output circuit, the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the touch panel drive substrate 450 housed in the dish unit 300 of the door frame 5. Then, a V blank signal indicating that the screen data from the peripheral control MPU 4150a can be received is output to the peripheral control MPU 4150a. In the present embodiment, the frame frequency (the number of screen updates per second) of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 is set to approximately 30 fps per second. Therefore, the interval at which the V blank signal is output is about 33.3 ms (= 1000 ms ÷ 30 fps). The peripheral control MPU 4150a executes a peripheral control unit V blank signal interrupt process to be described later when this V blank signal is input. Here, the interval at which the V blank signal is output varies somewhat depending on the liquid crystal sizes of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. In addition, even in the manufacturing lot of the peripheral control board 4140 on which the peripheral control MPU 4150a and the built-in sound source VDP 4160a are mounted, the interval at which the V blank signal is output may change somewhat.

  The sound source built-in VDP 4160a employs a frame buffer method. In this “frame buffer system”, drawing data for one screen (one frame) to be drawn on the screen of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. The drawing data for one screen (one frame) held in the frame buffer (built-in VRAM) is stored on the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d. This is a method of outputting to the dish side liquid crystal display device 470. A frame buffer for holding drawing data for one screen (one frame) to be drawn on the screens of the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d, and the screen of the upper plate side liquid crystal display device 470 And a frame buffer for holding drawing data for one screen (one frame) to be drawn on the built-in VRAM of the sound source built-in VDP 4160a, and each frame buffer has another frame buffer having the same storage capacity. Is provided. That is, two frame buffers having the same storage capacity as frame buffers for holding drawing data for one screen (one frame) to be drawn on the screens of the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d. (Double buffer) is provided in the built-in VRAM of the sound source built-in VDP 4160a, and is stored as a frame buffer for holding drawing data for one screen (one frame) to be drawn on the screen of the upper plate side liquid crystal display device 470. Two frame buffers (double buffers) having the same capacity are provided in the built-in VRAM of the sound source built-in VDP 4160a. In this embodiment, by adopting such a double buffer, drawing data for one screen (one frame) to be drawn on the screen of the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d is generated. When writing to one frame buffer, one screen is drawn on the screen of the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d already written (held) in the other frame buffer. The drawing data of (one frame) is read and output to the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d, and one screen portion is drawn on the screen of the upper plate side liquid crystal display device 470. When drawing data for (one frame) is generated and written to one frame buffer, the other The drawing data for one screen (one frame) to be drawn on the screen of the upper plate side liquid crystal display device 470 already written (held) in the video buffer is read and output to the upper plate side liquid crystal display device 470. .

  When the sound command data described above is input from the peripheral control MPU 4150a based on a command from the main control board 4100, the built-in sound source VDP 4160a receives music stored in the liquid crystal and sound control ROM 4160b as shown in FIG. By extracting sound data such as sound and sound effects and controlling the built-in sound source, sound data such as music and sound effects are incorporated into the track according to the track number specified in the sound command data and used according to the output channel number The output channel is set and the music accommodated in the speaker box 820 provided in the main body frame 3 and the speaker, the sound effect, etc. flowing from the speaker 130 provided in the door frame 5 are serialized and output as audio data to the audio data transmission IC 4160c. .

  Note that the sound command data also includes a sub-volume value for adjusting the volume of the track in which the sound data is incorporated, and a plurality of tracks in the built-in sound source of the sound source built-in VDP 4160a include effect sounds such as music and sound effects. In addition to the sound data and the sub-volume value for adjusting the sound volume, the sound data of the notification sound and the sound volume for notifying the clerk of the hall of the occurrence of the malfunction of the pachinko gaming machine 1 and the illegal act on the pachinko gaming machine 1 Incorporates a sub-volume value that adjusts. Specifically, for the production sound, the substrate volume adjusted by rotating the knob portion of the volume adjustment volume 4140a described above is set as the sub volume value, and for the notification sound, the volume adjustment is performed. The maximum volume is set as the sub-volume value without depending on the volume adjustment based on the turning operation of the knob portion of the volume 4140a. The sub-volume value of the effect sound can be adjusted by shifting to a setting mode to be described later by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400.

  The sound command data also includes a master volume value for adjusting the volume of the output channel, and a plurality of output channels in the built-in sound source of the built-in sound source VDP 4160a include a plurality of sound sources in the built-in sound source of the sound source built-in VDP 4160a. Of the tracks, the sound data of the production sound built into the track to be used is combined with the sub-volume value that adjusts the volume of the production sound built into the track to be used. Actually, it amplifies the master volume value that is the volume that flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, and serializes the amplified effect sound as audio data. The data is output to the audio data transmission IC 4160c.

  In the present embodiment, the master volume value is set to a constant value excluding the master volume value for power suppression, and when the volume of the combined effect sound is the maximum volume, it is amplified to the master volume value. The sound volume flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is set to an allowable maximum sound volume. Specifically, for the production sound, among the multiple tracks, the sound data of the production sound incorporated in the track to be used and the sub-volume value that adjusts the volume of the production sound incorporated in the track to be used The volume of the set sound adjustment volume 4140a is synthesized with the substrate volume adjusted by rotating the knob, and the volume of the synthesized performance sound is actually applied to the speaker box 820 provided in the main body frame 3. It amplifies up to the master volume value that is the volume that flows from the speaker to be accommodated and the speaker 130 provided on the door frame 5, serializes the amplified effect sound, and outputs it as audio data to the audio data transmission IC 4160c. Indicates the sound data of the notification sound incorporated in the track used and the sound of the notification sound incorporated in the track used. Is combined with the maximum volume without depending on the volume adjustment based on the turning operation of the knob portion of the volume adjustment volume 4140a set as the sub volume value for adjusting the volume, and the volume of the synthesized notification sound is actually Amplification is performed up to a master volume value which is a volume flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, and the amplified notification sound is serialized to be audio data as audio data The data is output to the transmission IC 4160c.

  Here, when the production sound is flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the occurrence of the malfunction of the pachinko gaming machine 1 or the pachinko gaming machine 1 To briefly explain the control of playing a notification sound in order to notify the store clerk etc. of fraudulent behavior, the sub-volume value of the track in which the production sound is incorporated is forcibly set to mute, and this production sound is incorporated. The track sound data, the sub-volume value set for the mute, the sound data of the track in which the notification sound is incorporated, and the sub-volume value where the notification sound volume is set to the maximum volume are synthesized. The volume of the produced effect sound and the volume of the notification sound are actually set to the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5. Amplified to a master volume value as the volume flowing from 130, and outputs the amplified effect sound and alarm sound as an audio data to the audio data transmission IC4160c Serialize.

  In other words, the sound that flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is only the notification sound of the maximum volume. At this time, since the production sound is muted, the production sound does not flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, but the production sound is used for the sound generation described above. Progressing according to schedule data. In the present embodiment, the notification sound flows from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 for a predetermined period (for example, 90 seconds). When the period of time elapses, the volume of the effect sound that has been progressing according to the sound generation schedule data that has been forcibly set to mute so far has been adjusted by rotating the knob portion of the volume adjustment volume 4140a. It is set again as the volume value (at this time, when the adjustment is made by moving to the setting mode by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400, the adjusted effect sound is sub- Set to the volume value) and the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5. So that the flow from mosquitoes 130.

  Thus, when the production sound is flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the occurrence of a malfunction of the pachinko gaming machine 1 or the pachinko gaming machine 1 When a notification sound flows in order to notify a store clerk or the like of a fraudulent act to the hall, the volume of the effect sound is muted and the notification sound is provided in the speaker and door frame 5 housed in the speaker box 820 provided in the main body frame 3. Although the silenced effect sound flows from the speaker 130 and proceeds in accordance with the sound generation schedule data, the speaker is accommodated in the speaker box 820 provided in the main body frame 3 after a predetermined period of time. When the speaker 130 provided on the door frame 5 stops flowing, the production sound does not start to flow again from where the notification sound starts to flow. So that the start flowing again from where the notification sound is beginning to flow to proceed according to the schedule data for generating sound until after the lapse of a predetermined period of time.

[7-4-2b. Liquid crystal and sound control ROM]
As shown in FIG. 17, the liquid crystal and sound control ROM 4160b includes game board side character data to be drawn in the display area of the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display. The upper plate character data to be drawn in the display area of the device 470 is stored in advance, and various sound data such as music, sound effects, notification sounds, and notification sounds are also stored in advance.

[7-4-2c. Audio data transmission IC]
When the audio data transmission IC 4160c receives serialized audio data from the sound source built-in VDP 4160a, the audio data transmission IC 4160c converts the right audio data as a positive signal and a negative signal as differential serial data, and outputs a peripheral control output circuit and frame peripheral relay (not shown). A peripheral control output circuit (not shown) is transmitted to the frame decoration drive amplifier board 194 via the terminal board 868 and the peripheral door relay terminal board 882 and as differential serial data with the left audio data as a positive signal and a negative signal. Then, the frame is transmitted to the frame decoration drive amplifier board 194 via the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882. Thereby, music, sound effects, etc. adapted to various effects are reproduced in stereo from the speakers housed in the speaker box 820 provided in the main body frame 3 and the speakers 130 provided in the door frame 5.

  Note that the audio data transmission IC 4160c outputs audio data between the boards extending from the peripheral control board 4140 to the frame decoration drive amplifier board 194 as differential serial data on the left and right sides, for example, a positive signal of the left audio data, Even when the negative signal is affected by noise, the frame decoration drive amplifier board 194 combines the noise component riding on the plus signal and the noise component riding on the minus signal into one left audio data. Since noise components are canceled by canceling each other, noise countermeasures can be taken.

[7-4-2d. Plate-side LCD transmitter IC]
As shown in FIG. 17, drawing data output from the channel CH2 of the sound source built-in VDP 4160a is input to the upper plate side liquid crystal transmitter IC 4160d. As described above, the channel CH2 uses a parallel interface. The drawing data is composed of three video signals, a red video signal, a green video signal, and a blue video signal, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. Each of the green video signal and the blue video signal is composed of 8 bits and a total of 24 bits. In the present embodiment, the red video signal, the green video signal, and the blue video signal that can be input to the upper-plate-side liquid crystal transmitter IC 4160d are 6 bits each, for a total of 18 bits. Is input to the side liquid crystal transmitter IC 4160d. Since the lower 2 bits are extremely weak color information that is difficult for human eyes to discriminate, the lower 2 bits including the weak color information are invalidated although they are output from the sound source built-in VDP 4160a.

  Three video signals such as a red video signal, a green video signal, and a blue video signal, and three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, which are drawing data output from the channel CH2 of the sound source built-in VDP 4160a. Are input to the upper plate side liquid crystal transmitter IC 4160d, the upper plate side liquid crystal transmitter IC 4160d receives three video signals, a red video signal, a green video signal, and a blue video signal, a horizontal synchronization signal, and a vertical synchronization signal. The signal and the three synchronization signals, the clock signal, are serialized into a differential serial signal (serial data) called “V-by-One (registered trademark)” of THINE ELECTRONICS CO., LTD. These various signals are transmitted from the peripheral control board 4140 around the frame. Terminal plate 868, near the door relay terminal plate 882, and transmitted to the touch panel drive board 450 which is housed in the dish unit 300 of the door frame 5.

  As described above, the drawing data output from the channel CH1 of the sound source built-in VDP 4160a is output from the peripheral control board 4140 to the game board side liquid crystal display device 1900, and therefore, the path from the channel CH1 to the game board side liquid crystal display device 1900. Although the length of the wiring required for the (first path) is short, the drawing data output from the channel CH2 of the sound source built-in VDP 4160a is from the peripheral control board 4140 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the door. Since it is output (transmitted) to the upper dish side liquid crystal display device 470 via the touch panel drive substrate 450 housed in the dish unit 300 of the frame 5, the path (second) from the channel CH2 to the upper dish side liquid crystal display device 470 The length of the wiring required for the route) is much longer than the length of the wiring required for the first route. Extremely received tends to the influence of the noise.

  Specifically, since the door frame 5 is pivotally supported so as to be openable and closable with respect to the main body frame 3 shown in FIG. 1, it is opposite to the lock device 1000 shown in FIG. 5 along the open side of the main body frame 3. Provided on the side of the main body frame 3 such as the touch panel drive board 450 accommodated in the dish unit 300 provided in the door frame 5 from the peripheral control board 4140 provided in the game board 4 attached to the main body frame 3, for example. It is necessary to pass various wirings that electrically connect the various substrates and the various substrates provided on the door frame 5 side. However, on the closed side of the main body frame 3, as shown in FIG. 3, in addition to the prize ball device 740, the game balls paid out by the prize ball device 740 are displayed on the plate unit 300 shown in FIG. A full tank branching unit 770 is provided which can be guided to the upper plate 301 and can branch the guided game ball to the lower plate 302 side when the upper plate 301 is filled with game balls. A substrate unit 800 shown in FIG. 5 is arranged below the main body frame 3 in which the power supply substrate 851 and the like shown in FIG. 6 to which power is supplied from the pachinko island facility are grouped. In this way, various wirings for electrically connecting various substrates provided on the main body frame 3 side and various substrates provided on the door frame 5 side are in the vicinity of the prize ball device 740, the full tank branching unit 770, the power supply substrate 851, and the like. In addition to noise due to driving of the payout motor 744 provided in the prize ball device 740, noise due to electrostatic discharge by the game ball and the pachinko island equipment where the pachinko gaming machine 1 is installed are supplied. The environment is subject to noise that has entered the power line.

  For this reason, for the channel CH2 in which the length of the wiring for sending drawing data is extremely longer than that of the channel CH1, the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 provides “ By adopting a differential communication called “V-by-One (registered trademark)”, the mechanism is less susceptible to noise. In this embodiment, an upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 and an upper plate side liquid crystal receiver IC SDIC0 described later provided in the touch panel drive board 450 housed in the plate unit 300 of the door frame 5 are provided. As described above, the differential 1-pair cable is used as the wiring for connecting the connections, that is, between the transmitter and the receiver. However, this differential 1-pair cable has two wirings. It is not a parallel line provided simply in parallel, but a twisted pair cable. This twisted pair cable is a cable in which two wires are twisted together, and is also called a twisted pair wire.

  Here, the case where a parallel line is adopted as a differential one-pair cable for electrically connecting a transmitter and a receiver will be briefly described. With respect to the channel CH2 of the sound source built-in VDP 4160a in which the length of the wiring for sending drawing data is extremely longer than the channel CH1 of the sound source built-in VDP 4160a, the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 Even if it is a mechanism that is difficult to be affected by noise by adopting a differential communication called “V-by-One (registered trademark)” of Co., Ltd., it is only due to electrostatic discharge of a game ball with such a hardware configuration. When serial data in parallel lines is affected by noise, noise entering the power supply line supplied from the pachinko island facility where the pachinko machine 1 is installed, etc., the touch panel stored in the dish unit 300 of the door frame 5 The top side of the drive board 450 Since the noise is not canceled (removed) when it is received by the crystal receiver ICSDIC0, the serial data is received by the upper plate side liquid crystal receiver ICSDIC0 in an affected state, and from the channel CH2 of the sound source built-in VDP 4160a. The drawing data to be output is received by the upper plate side liquid crystal receiver ICSDIC0 as being disturbed different from the normal one, and in the display area of the upper plate side liquid crystal display device 470, an image like a so-called sandstorm is displayed. There is a problem that it cannot be recognized at all whether it is an image.

  Therefore, in this embodiment, the upper plate side provided on the peripheral control board 4140 with respect to the channel CH2 of the sound source built-in VDP 4160a in which the length of the wiring for sending drawing data is extremely longer than the channel CH1 of the sound source built-in VDP 4160a. The transmitter IC 4160d for liquid crystal uses a differential communication called “V-by-One (registered trademark)” of Zain Electronics Co., Ltd. to make it less susceptible to noise, and in addition to such a hardware configuration Even if differential serial data is affected by noise that enters the wiring, a twisted pair cable that can cancel (remove) the noise on the receiving side is electrically connected between the transmitter and the receiver. It was adopted as a differential 1 pair cable. As a result, even if serial data is affected by the twisted pair cable due to noise caused by electrostatic discharge of the game ball, noise entering the power supply line supplied from the pachinko island facility where the pachinko gaming machine 1 is installed, etc., the door The channel of the VDP 4160a with built-in sound source is canceled because the noise is canceled (removed) when receiving by the receiver ICSDIC0 for the upper plate side liquid crystal provided in the touch panel drive substrate 450 housed in the dish unit 300 of the frame 5. The drawing data output from CH2 is reliably received by the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive substrate 450 housed in the plate unit 300 of the door frame 5 and output to the upper plate side liquid crystal display device 470. In the upper plate side liquid crystal display device 470, the liquid crystal and sound control Image source built VDP4160a was produced parts 4160 can be reliably displayed. By canceling (removing) the noise, it is possible to prevent the upper dish side liquid crystal display device 470 from displaying an image that makes it impossible to recognize what the image is like a sandstorm. Therefore, it is possible to suppress a decrease in the player's willingness to play. Therefore, it is possible to suppress a decrease in the player's willingness to play due to the influence of noise.

  In this embodiment, an upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140, and an upper plate side liquid crystal receiver IC SDIC0 described later provided in the touch panel drive board 450 housed in the plate unit 300 of the door frame 5; The frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882 are interposed between the connections of, ie, between the transmitter and the receiver. This is because the main body frame 3 and the door frame 5 are not integrally configured, but a structure in which the door frame 5 is attached to the main body frame 3 after being assembled separately is adopted. After the work of attaching the door frame 5 to 3, various wirings such as harnesses and twist cables from various boards provided on the door frame 5 side are electrically connected to the peripheral door relay terminal plate 882 provided on the main body frame 3 side. Thus, various substrates provided on the main body frame 3 side and various substrates provided on the door frame 5 side can be electrically connected. With such a configuration, after the door frame 5 is opened from the main body frame 3 and various wirings are removed, the main body frame 3 and the door frame 5 can be maintained by removing the door frame 5 from the main body frame 3. If the problem that occurred in the door frame 5 cannot be resolved, another door frame 5 ′ is attached to the main body frame 3 instead of the defective door frame 5, and the door frame 5 By electrically connecting various wirings from various substrates provided on the 'side to the peripheral door relay terminal plate 882 provided on the main body frame 3 side, various substrates provided on the main body frame 3 side and various types provided on the door frame 5' side The substrate can be electrically connected.

  In the present embodiment, as described above, differential communication called “V-by-One (registered trademark)” of Zain Electronics Co., Ltd. is adopted in the transmitter IC 4160d for the upper plate side liquid crystal provided in the peripheral control board 4140. In addition to this hardware configuration, even if differential serial data is affected by noise that enters the wiring, the receiver cancels (removes) the noise. The twisted pair cable that can be used as a differential one-pair cable that electrically connects the transmitter and the receiver. Specifically, between the peripheral control board 4140 and the frame peripheral relay terminal board 868, between the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, and between the peripheral door relay terminal board 882 and the touch panel drive board. The board 450 is electrically connected by a twisted pair cable, while the power supply wiring and other lines for transmitting various signals are electrically connected by a harness. Thereby, in addition to the video transmission wiring pattern for transmitting the serial data by the differential method transmitted by the transmitter IC 4160d for the upper plate side liquid crystal on the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882, A power supply wiring pattern and various signal wiring patterns for transmitting various other signals are mixed. For this reason, the above-described video transmission wiring patterns are formed on the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882 by being separated from the power supply wiring pattern and various signal wiring patterns by a predetermined dimension. Since the route from the transmitter to the receiver spans a plurality of relay terminal plates such as the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882, the video transmission formed on the plurality of relay terminal plates is used. Between the input and output of the wiring pattern, there is a problem that a part of the signal for transmitting the serial data by the differential system transmitted by the upper plate side liquid crystal transmitter IC 4160d is reflected and becomes noise, or the output level of the signal is lowered. Will occur. Therefore, in this embodiment, impedance matching is performed on the video transmission wiring patterns formed on the plurality of relay terminal boards.

  In the present embodiment, as described above, between the peripheral control board 4140 and the frame peripheral relay terminal board 868, between the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, and the peripheral door relay. Between the board of the terminal board 882 and the touch panel drive board 450, each is electrically connected by a twisted pair cable, whereas in the wiring for transmitting power supply wiring and other various signals, each is electrically connected by a harness. Although connected, one of the twisted pair cables is red, the other is gray, and the wiring that supplies power is red, and the other plurality of wirings are gray. Note that the power supply wiring may be yellow instead of red.

[7-4-2e. Forced switching circuit, differential circuit]
Signals output from the upper plate side liquid crystal transmitter IC 4160d are sent to the forced switching circuit 4160f, the peripheral control output circuit (not shown), the frame peripheral relay terminal plate 868, the peripheral door relay terminal plate 882, and the tray unit 300 of the door frame 5. It is transmitted to the touch panel drive substrate 450 to be stored. The forced switching circuit 4160f includes a touch panel drive board serial I / O port built in the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 in addition to the signal output from the upper plate side liquid crystal transmitter IC 4160d. LOCKN signal output request data, which is serial data output from, is differentiated into a plus signal and a minus signal and inputted in the differentiation circuit 4160e. The differential circuit 4160e serializes the LOCKN signal output request data into a differential serial signal (serial data). This LOCKN signal output request data is a demonstration by the game board side liquid crystal display device 1900 during the period when the start-up screen at the time of power-on of the pachinko gaming machine 1 is displayed on the game board side liquid crystal display device 1900, In the period of performing, the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140, and the upper plate side liquid crystal receiver IC SDIC0 described later provided in the touch panel drive board 450 housed in the plate unit 300 of the door frame 5; Is transmitted as an operation confirmation request for the upper plate side liquid crystal display device 470 in order to confirm whether or not a problem has occurred in the connection between the transmitters, that is, between the transmitter and the receiver. Forcibly switching circuit 4160f, when two signals that have been differentiated into a plus signal and a minus signal in differential circuit 4160e are input, the two circuits are connected so as to transmit the two signals. When the two signals differentiated into the plus signal and the minus signal are not input in the inverting circuit 4160e, the circuit configuration is such that the circuit is connected so as to transmit the signal output from the upper plate side liquid crystal transmitter IC 4160d. Has been. As a result, when two signals differentiated into a plus signal and a minus signal are input in the differential circuit 4160e, the two signals are connected to each other so as to transmit the two signals. Are transmitted from the peripheral control board 4140 to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the touch panel drive board 450 housed in the dish unit 300 of the door frame 5, while being added to the differential circuit 4160e. When two signals differentiated into a signal and a minus signal are not input, a circuit connection is made so as to transmit a signal output from the upper plate-side liquid crystal transmitter IC 4160d. The signals output from the peripheral control board 4140, the frame peripheral relay terminal board 868, the peripheral door relay terminal board 82, and transmitted to the touch panel drive board 450 which is housed in the dish unit 300 of the door frame 5. The peripheral control MPU 4150a performs a demonstration by the game board side liquid crystal display device 1900 during a period when the start-up screen at the time of power-on of the pachinko gaming machine 1 is displayed on the game board side liquid crystal display device 1900, During this period, the LOCKN signal output request data from the serial I / O port for the touch panel drive board is sent to the touch panel drive board 450 (actually provided in the peripheral control board 4140) stored in the dish unit 300 of the door frame 5. To the control circuit 4160e).

  When the touch panel drive board 450 accommodated in the dish unit 300 of the door frame 5 receives a serial signal (serial data) from the peripheral control board 4140 by an upper dish-side liquid crystal receiver ICSDIC0 described later, various serialized signals are received. Is converted to a parallel signal and output to the upper plate side liquid crystal display device 470, and a capacitive touch panel provided so as to cover the display area of the upper plate side liquid crystal display device 470 shown in FIG. 480 mainly includes a touch panel circuit 450W that performs detection control of the contact state.

  The upper plate side liquid crystal receiver ICSDIC0 receives the drawing data from the built-in sound source VDP 4160a, and if the received drawing data is determined to be abnormal data, a LOCKN signal to be described later is transmitted to the peripheral door relay terminal board 882. And output to the peripheral control board 4140 via the frame peripheral relay terminal board 868. The LOCKN signal is input to the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 via a peripheral control input circuit (not shown) of the peripheral control board 4140. Peripheral control MPU 4150a, based on the input LOCKN signal, when a predetermined condition is satisfied, generates an image to that effect by controlling sound source built-in VDP 4160a and outputs it to game board side liquid crystal display device 1900. Is displayed on the display area of the game board side liquid crystal display device 1900 for notification.

  Also, when the receiver ICSDIC0 for the upper plate side liquid crystal determines that the two received signals are LOCKN signal output request data from the serial I / O port for the touch panel drive substrate, the LOCKN signal described later is connected to the peripheral door relay terminal. The data is output to the peripheral control board 4140 via the board 882 and the frame peripheral relay terminal board 868. The LOCKN signal is input to the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 via a peripheral control input circuit (not shown) of the peripheral control board 4140. Accordingly, the peripheral control MPU 4150a determines that there is no problem in the connection between the transmitter and the receiver when the LOCKN signal is input as a response signal to the transmission of the LOCKN signal output request data. On the other hand, it can be determined that there is no problem with the touch panel drive board 450 accommodated in the door 300. On the other hand, when the LOCKN signal is not input, it is assumed that there is a problem with the connection between the transmitter and the receiver. It is determined that a defect has occurred in the touch panel drive substrate 450 housed in the dish unit 300 in the frame 5, and a notification image (for example, “A defect has occurred in the upper dish side liquid crystal display device) is reported. Please call the store clerk. ”) Control the VDP4160a with built-in sound source In addition to outputting to the liquid crystal display device 1900, a notification sound indicating that effect (for example, “a defect has occurred in the upper plate side liquid crystal display device”) is output to the audio data transmission IC 4160c by controlling the VDP 4160a with built-in sound source. As a result, a notification sound flows from the speakers 130, 222, 262 and the like provided on the door frame 5. Thus, notification can be performed by the notification image displayed in the display area of the game board side liquid crystal display device 1900 and the notification sound that repeatedly flows from the speakers 130, 222, 262, etc. provided on the door frame 5. It has become. At this time, all of the LEDs for light emitting decoration provided in the door frame 5 and the various LEDs mounted on various decoration boards provided in the game board 4 may be turned on.

[7-4-3. RTC control unit]
As shown in FIG. 15, the RTC control unit 4165 that holds calendar information that specifies the date and time and time information that specifies the hour, minute, and second is configured with an RTC 4165a as the center. The RTC 4165a has a built-in RAM 4165aa that holds calendar information and time information (hereinafter referred to as “RTC built-in RAM 4165aa”). The RTC 4165a is supplied with power from a battery 4165b (in this embodiment, a button battery is used) as a driving power source and a backup power source for the RTC built-in RAM 4165aa. That is, the RTC 4165a is not supplied with any power from the peripheral control board 4140 (pachinko gaming machine 1), but is supplied with power from the battery 4165b independently of the peripheral control board 4140 (pachinko gaming machine 1). Thereby, even if the power of the pachinko gaming machine 1 is cut off, the RTC 4165a can update and hold calendar information and time information by supplying power from the battery 4165b.

  The peripheral control MPU 4150a of the peripheral control unit 4150 acquires calendar information and time information from the RTC built-in RAM 4165aa of the RTC 4165a, sets the information in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c, and stores the acquired calendar information and time information. The production based on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 can be unfolded. As such effects, for example, on December 25, a Christmas tree or reindeer screen is unfolded on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. For example, on New Year's Eve, a screen for executing the New Year countdown may be unfolded between the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. Calendar information and time information are set at the time of factory shipment.

  In addition to calendar information and time information, the RTC built-in RAM 4165aa stores and holds LED brightness setting information when an LED type backlight is attached to the game board side liquid crystal display device 1900. Yes. The peripheral control MPU 4150a obtains luminance setting information from the RTC built-in RAM 4165aa and adjusts the luminance of the backlight by PWM control when the backlight of the game board side liquid crystal display device 1900 is mounted with an LED type. . The luminance setting information includes luminance adjustment information for adjusting the range of the luminance of the LED, which is the backlight of the liquid crystal display device 1900 on the game board side, from 100% to 70% in increments of 5%, and the currently set game. The brightness | luminance of LED which is a backlight of the panel side liquid crystal display device 1900, the movable liquid crystal display devices 1925a-1925d, and the top plate side liquid crystal display device 470 is contained.

  In addition to the calendar information, time information, and luminance setting information, the RTC built-in RAM 4165aa stores the calendar information, time information, and luminance setting information as date / time and hour / minute / second information that was first stored in the RTC built-in RAM 4165aa. Input date information is also stored.

  The peripheral control MPU 4150a has a backlight for the cold-cathode tube type backlights of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. ON / OFF control or ON only.

  Various information stored in the RTC built-in RAM 4165aa, such as calendar information, time information, luminance setting information, and input date / time information, is set in the production line of the gaming machine manufacturer. In the production line, for example, in order to perform various tests such as a display test of the game board side liquid crystal display device 1900, the year when the input date information is entered on the production line as the date when the game board side liquid crystal display device 1900 was first turned on. Set to the date and time of manufacture, which is the date and time.

  Thus, in addition to calendar information and time information, the RTC built-in RAM 4165aa has brightness setting information and input date and time information when the backlight of the game board side liquid crystal display device 1900 is of the LED type, etc. In addition, it is possible to store and hold information that needs to be maintained independently of the model information of the pachinko gaming machine 1 (for example, the probability of occurrence of a big hit gaming state with a low probability or a high probability).

  Also, the brightness setting information and the like stored and held in the RTC built-in RAM 4165aa is too bright for the backlight brightness of the game board side liquid crystal display device 1900 set to the date of manufacture depending on the environment of the hall where the pachinko gaming machine 1 is installed. Or it may be too dark. Therefore, by operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400, the mode can be shifted to the setting mode, and the luminance of the backlight can be adjusted to a predetermined luminance. When the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the pachinko gaming machine 1 is turned on, a screen for performing a setting mode is displayed on the game board side liquid crystal display device 1900. In addition, when the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated during the period when the game board side liquid crystal display device 1900 is in the waiting state and the demonstration is performed, the setting mode is performed. The screen is displayed on the game board side liquid crystal display device 1900. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the setting mode screen, the calendar information and time information can be reset, and the backlight brightness of the game board side liquid crystal display device 1900 can be set to a desired value. It can be adjusted to brightness. The adjusted desired brightness of the backlight of the game board side liquid crystal display device 1900 is overwritten (updated) as the brightness of the LED stored in the brightness setting information.

  In the setting mode, the peripheral control MPU 4150a executes the above-described brightness correction program, and when the backlight of the game board side liquid crystal display device 1900 is an LED type, the game board side liquid crystal is installed. The luminance reduction accompanying the secular change of the display device 1900 is corrected. The peripheral control MPU 4150a acquires input date / time information from the RTC built-in RAM 4165aa of the RTC control unit 4165, specifies the date and time when the game board side liquid crystal display device 1900 is first turned on, and specifies calendar information and time for specifying the date. Time information that specifies minutes and seconds is acquired to specify the current date and time, and the brightness range of the LED, which is the backlight of the game board side liquid crystal display device 1900, is adjusted in increments of 5%. Brightness setting information including brightness adjustment information for performing and the brightness of the LED that is the backlight of the game board-side liquid crystal display device 1900 that is currently set. The acquired brightness setting information is corrected based on correction information stored in advance in the peripheral control ROM 4150b.

  For example, from the date and time when the game board side liquid crystal display device 1900 was first turned on and the current date and time, when six months have already passed since the date and time when the game board side liquid crystal display device 1900 was first turned on, When the corresponding correction information (for example, 5%) is obtained from the peripheral control ROM 4150b and the backlight of the game board side liquid crystal display device 1900 is turned on when the brightness of the LED included in the brightness setting information is 75%, the 75% The luminance of the backlight of the game board side liquid crystal display device 1900 is adjusted based on the luminance adjustment information included in the luminance setting information so that the luminance is further increased by 5% which is the correction information acquired with respect to the luminance setting information. And when the game board side liquid crystal display device 1900 has been powered on for the first time, December has already passed. When the corresponding correction information (for example, 10%) is acquired from 0b and the backlight of the game board side liquid crystal display device 1900 is turned on when the luminance of the LED included in the luminance setting information is 75%, The luminance of the backlight of the game board side liquid crystal display device 1900 is adjusted based on the luminance adjustment information included in the luminance setting information so that the luminance is further increased by 10% which is the correction information acquired in this way. Light.

  The current date and time may be specified by acquiring calendar information for specifying the date and time and time information for specifying the hour, minute, and second directly from the RTC built-in RAM 4165aa of the RTC control unit 4165, or a peripheral described later. Current calendar information that is set in the calendar information storage unit and updated by the system of the peripheral control board 4140 in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c in the current time information acquisition process of step S1002 in the control unit power-on process And the current time information set in the time information storage unit and updated by the system of the peripheral control board 4140 may be acquired to identify the current date and time.

[7-4-4. Volume adjustment volume]
As described above, the volume adjustment volume 4140a is used to rotate the knob portion to adjust the volume of music, sound effects and the like flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. It can be adjusted by doing. As described above, the volume adjustment volume 4140a is configured such that the resistance value can be changed by rotating the knob portion, and the electrically connected peripheral control A / D converter 4150ak is connected to the knob portion. The voltage divided by the resistance value at the rotational position is converted from an analog value to a digital value, and converted into a value in 1024 steps from 0 to 1023. In the present embodiment, as described above, the values of the 1024 steps are divided into seven and managed as the substrate volumes 0 to 6. The substrate volume 0 is set to mute, the substrate volume 6 is set to the maximum volume, and the volume is set to increase from the substrate volume 0 toward the substrate volume 6. The liquid crystal and sound control unit 4160 (VDP 4160a with built-in sound source) is controlled so that the volume is set to the substrate volume 0 to 6, and the speaker and door frame 5 provided in the speaker box 820 provided in the main body frame 3 are provided. Music and sound effects flow from the speaker 130.

  In this way, music and sound effects flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 by volume adjustment based on the turning operation of the knob portion. . Further, in the present embodiment, as described above, in addition to music and sound effects, a notification sound for notifying the clerk of the hall of the occurrence of a malfunction of the pachinko gaming machine 1 or an illegal act against the pachinko gaming machine 1, Announce contents related to game effects (for example, an announcement that the screen developed on the game board side liquid crystal display device 1900 is more powerful, or that there is a high possibility of shifting to a game state advantageous to the player) The notification sound for the flow of sound from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is also operated. It is a mechanism that flows without depending on the volume adjustment based on the sound volume, and the volume from the mute to the maximum volume is programmed by the liquid crystal and sound control unit 4160 (VDP4 with built-in sound source) So that the it can be adjusted by controlling the 60a).

  The volume adjusted by this program can be smoothly changed from the mute to the maximum volume, unlike the substrate volume divided into the above seven stages. Thus, for example, even when a hall clerk or the like rotates the knob portion of the volume adjustment volume 4140a to set the volume to a low level, the speakers and doors housed in the speaker box 820 provided in the main body frame 3 Although the production sound such as music and sound effects flowing from the speaker 130 provided in the frame 5 is reduced, the sound volume is increased when a malfunction occurs in the pachinko gaming machine 1 or when the player is cheating. In the embodiment, the notification sound set to the maximum volume) can be played. Therefore, even if the volume of the production sound is reduced, it is possible to prevent the hall clerk or the like from becoming difficult to notice the occurrence of a malfunction or the player's cheating due to the notification sound.

  Also, based on the current board volume set by volume adjustment based on the turning operation of the knob part, the volume of the advertisement sound is reduced so as not to interfere with the music and sound effects. In addition to music and sound effects, the screen unfolded by the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 is made more powerful. It is also possible to produce an announcement or to announce that there is a high possibility of shifting to a gaming state advantageous to the player.

  In the present embodiment, in addition to adjusting the volume of music and sound effects by turning the knob of the volume adjustment volume 4140a, the dial operation unit 401 and the press of the operation unit 400 are adjusted. By operating the operation unit 405, it is possible to shift to the setting mode and adjust the volume of music and sound effects. When the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated within a predetermined time after the pachinko gaming machine 1 is turned on, a screen for performing a setting mode is displayed on the game board side liquid crystal display device 1900. In addition, when the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated during the period when the game board side liquid crystal display device 1900 is in the waiting state and the demonstration is performed, the setting mode is performed. The screen is displayed on the game board side liquid crystal display device 1900. By operating the dial operation unit 401 and the press operation unit 405 of the operation unit 400 in accordance with the setting mode screen, the volume of music and sound effects can be adjusted to a desired volume. Specifically, the peripheral control A / D converter 4150ak converts the voltage divided by the resistance value at the rotational position of the knob portion of the volume adjustment volume 4140a from an analog value to a digital value. Thus, the value of the substrate volume can be increased or decreased by adding or subtracting a predetermined value according to the operation of the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400. . This adjusted volume is set and updated as a sub-volume value for a track in which sound data of effect sound such as music or sound effect is incorporated among a plurality of tracks in the sound source of the sound source with built-in sound source VDP 4160a. However, it is not reflected in the adjustment of the volume of the notification sound or notification sound described above.

  As described above, in the present embodiment, the volume of the music or the sound effect is adjusted by directly rotating the knob of the volume adjustment volume 4140a, and the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is adjusted. There are two methods: adding or subtracting a predetermined value according to the operation to adjust the volume of music or sound effects by increasing or decreasing the value of the substrate volume. Since the volume adjustment volume 4140a is mounted on the peripheral control board 4140, the main body frame 3 must be opened from the outer frame 2 without fail. Then, the hall clerk can turn the knob of the volume adjustment volume 4140a. However, at the volume adjusted by the hall clerk, it may be difficult for the player to hear the music or sound effect, or may be loud for the player to feel the music or sound effect. Therefore, within a predetermined time after the power of the pachinko gaming machine 1 is turned on, the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 are operated, or a demonstration is performed by the game board side liquid crystal display device 1900 in a waiting state. When the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400 is operated during the period being performed, a screen for performing the setting mode is displayed on the game board side liquid crystal display device 1900. By operating the dial operation unit 401 and the pressing operation unit 405 of the operation unit 400 according to the setting mode screen, the volume of music and sound effects can be adjusted to a desired volume. Thus, the player can adjust the volume of the music and sound effects to a desired volume. Therefore, when the volume of the hall clerk feels low and it is difficult to hear the music and sound effects, the operation unit 400 The dial operation unit 401 and the pressing operation unit 405 can be operated to increase the volume to a desired level. If the volume of the hall clerk feels loud and the music and sound effects are noisy, the operation unit 400 The dial operation unit 401 and the pressing operation unit 405 can be operated to reduce the volume to a desired level.

  Further, in the present embodiment, a state in which no game is played in the pachinko gaming machine 1 is continued for a predetermined period of time, and when the game board side liquid crystal display device 1900 is repeatedly demonstrated (for example, 10 times). ) The volume adjusted by the player who was sitting on the front of the pachinko gaming machine 1 and playing the game last time is canceled and the volume is initialized. In the initialization of the volume, the volume adjusted by the hall clerk, that is, the volume adjusted by the hall clerk by directly rotating the knob portion of the volume adjustment volume 4140a is adjusted. As a result, if it is difficult to hear the music or sound effect by feeling the volume adjusted by the player who was sitting on the front of the pachinko gaming machine 1 last time and adjusting the volume, A player who sits down and plays a game can increase the sound volume to a desired level by operating the dial operation unit 401 or the pressing operation unit 405 of the operation unit 400, or sits in front of the pachinko gaming machine 1 and plays a game. When the player who has played the game feels loud and adjusts the volume, the player who sits on the front surface of the pachinko gaming machine 1 and plays the game this time It is possible to reduce the sound volume to a desired level by operating 401 or the pressing operation unit 405.

[8. Power system]
Next, the power supply system of the pachinko gaming machine 1 will be described with reference to FIGS. FIG. 18 is a block diagram showing a power supply system of a pachinko gaming machine, FIG. 19 is a block diagram (a) showing a power generation circuit, and a diagram showing a relationship between power consumption and a power consumption suppression level accompanying power consumption ( FIG. 20 is a block diagram showing the continuation of FIG. First, the power supply board will be described, and then the power supplied to each control board will be described. Note that the grounds (GND) of the various substrates and the grounds (GND) of the various terminal boards are electrically connected to the ground (GND) of the power supply substrate 851 and are the same ground (GND).

[8-1. Power supply board]
The power supply board 851 is electrically connected to the power cord, and the plug of the power cord is inserted into the power outlet of the pachinko island facility. When the power switch 852 shown in FIG. 3 is operated, the power supplied from the pachinko island facility is supplied to the power supply board 851, and the pachinko gaming machine 1 can be turned on.

  As shown in FIG. 18, the power supply board 851 includes a power supply control unit 855, a firing solenoid drive circuit 858, and a ball feed solenoid drive circuit 859. The power supply control unit 855 is a circuit that creates various DC voltages from AC 24 volts (AC24V) supplied from the Pachinko Island facility, and supplies backup power to the main control board 4100 and the payout control board 4110. The drive circuit 858 is a circuit that drives the firing solenoid 654 of the ball striking device 650 shown in FIG. 5, and the ball feed solenoid drive circuit 859 drives the ball feed solenoid 585 of the ball feed unit 580 shown in FIG. Circuit.

  The power supply control unit 855 includes a synchronous rectification circuit 855a, a power factor correction circuit 855b, a smoothing circuit 855c, a power supply generation circuit 855d, and capacitors BC0 and BC1. The AC 24V supplied from the pachinko island facility is supplied to the gaming ball lending device connection terminal plate 869 via the power supply board 851 and to the synchronous rectifier circuit 855a. The synchronous rectification circuit 855a rectifies 24 volt (AC 24V) supplied from the Pachinko Island facility and supplies the rectified current to the power factor correction circuit 855b. This power factor improvement circuit 855b improves the power factor of the rectified power to create a direct current + 37V (DC + 37V, hereinafter referred to as “+ 37V”) and supplies it to the smoothing circuit 855c. The smoothing circuit 855c removes the supplied + 37V ripple, smoothes + 37V, and supplies it to the firing solenoid drive circuit 858, the ball feed solenoid drive circuit 859, and the power generation circuit 855d.

  The capacitor BC0 supplies backup power to a RAM (main control built-in RAM) built in the main control MPU 4100a of the main control board 4100, and the capacitor BC1 is built in the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110. A backup power source is supplied to the RAM (payout control built-in RAM).

  The launch solenoid drive circuit 858 is controlled by the launch ball feed control circuit 4120ag built in the payout control MPU 4120a of the payout control board 4110 shown in FIG. The driving current to the firing solenoid 654 is adjusted so that the game ball can be launched (launched) toward the game area 1100 based on the operation signal from. Thereby, the game ball can be launched (launched) toward the game area 1100 shown in FIG. 1 with a launch strength (launch strength) corresponding to the rotational position of the front 506 of the rotary handle body shown in FIG. On the other hand, the ball feed solenoid drive circuit 859 is controlled by a launch ball feed control circuit 4120ag built in the payout control MPU 4120a of the payout control board 4110 shown in FIG. Thus, the drive current to the ball feeding solenoid 585 is adjusted to be a constant current. As a result, the ball feeding member of the ball feeding unit 580 receives one game ball stored in the upper plate 301 of the dish unit 300 shown in FIG. 7, and the game ball received by the ball feeding member is directed to the ball hitting device 650. Can send.

  The power generation circuit 855d includes a power consumption monitoring circuit 855da, a + 5V power generation circuit 855db, a + 12V power generation circuit 855dc, and a + 24V power generation circuit 855dd. + 37V supplied from the smoothing circuit 855c is supplied to the + 5V power generation circuit 855db, the + 12V power generation circuit 855dc, and the + 24V power generation circuit 855dd via the power consumption monitoring circuit 855da.

  The power consumption monitoring circuit 855da monitors the power consumption of + 37V supplied from the smoothing circuit 855c. The power consumption monitoring circuit 855da monitors the power consumption of +37 V supplied from the smoothing circuit 855c, and determines a power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption. The determination result is output to the frame peripheral relay terminal plate 868 as a power consumption suppression signal. The power consumption suppression signal output from the power consumption monitoring circuit 855da of the power generation circuit 855d is configured as three signal wires (that is, configured as three parallel signals), and has a value 0 to a value 7 Can be transmitted to the peripheral control board 4140 through the frame peripheral relay terminal plate 868, while being input through the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882. The frame decoration drive amplifier board 194 is inputted (see FIG. 20B). Then, the power consumption suppression signal from the power consumption monitoring circuit 855da of the power generation circuit 855d is input to the decorative board or the like of the door frame via the frame decorative drive amplifier board 194 (FIG. 20 ( see b)).

  Specifically, the power consumption monitoring circuit 855da includes a power measurement circuit 855daa and a power consumption suppression stage determination circuit 855dab as shown in FIG. + 37V supplied from the smoothing circuit 855c is supplied to the + 5V power generation circuit 855db, the + 12V power generation circuit 855dc, and the + 24V power supply generation circuit 855dd via the power measurement circuit 855daa. The power measurement circuit 855daa measures the power consumption of + 37V supplied from the smoothing circuit 855c in real time and outputs it to the power consumption suppression stage determination circuit 855dab. The power consumption suppression stage determination circuit 855dab determines a power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption measured by the power measurement circuit 855daa. The value of the power consumption suppression signal configured as a signal wiring is set and output to the frame peripheral relay terminal board 868.

  The relationship between the power consumption suppression stage indicating how much power consumption should be suppressed, the power consumption measured by the power measurement circuit 855daa, and the power consumption suppression stage indicating how much power consumption should be suppressed (ie, power The relationship between the consumption and the power consumption suppression level accompanying the power consumption) will be briefly described. In the present embodiment, it is assumed that the power (AC 24 V) is supplied to one pachinko gaming machine 1 for one transformer (maximum allowable capacity: 250 VA) provided in the pachinko island facility, as shown in FIG. As shown, when the horizontal axis represents the power consumption with respect to the maximum allowable capacity of the transformer and the vertical axis represents steps 0 to 7 as the power consumption suppression step, the power consumption suppression stage determination circuit 855dab is a power measurement circuit. When the power consumption of + 37V measured at 855daa is 0% or more and less than 10%, it is determined that the power consumption suppression stage is stage 0, the value 0 is set as the value of the power consumption suppression signal, and the power measurement circuit 855daa measures When the power consumption of + 37V is 10% or more and less than 20%, it is determined that the power consumption suppression stage is stage 1, and the value 1 is set as the value of the power consumption suppression signal. When the power consumption of + 37V measured by the power measurement circuit 855daa is 20% or more and less than 30%, it is determined as stage 2 as the power consumption suppression stage, and the value 2 is set as the value of the power consumption suppression signal, When the power consumption of + 37V measured by the power measurement circuit 855daa is 30% or more and less than 40%, it is determined as stage 3 as the power consumption suppression stage, and the value 3 is set as the value of the power consumption suppression signal. When the power consumption of + 37V measured at 855 daa is 40% or more and less than 50%, it is determined as stage 4 as the power consumption suppression stage, and the value 4 is set as the value of the power consumption suppression signal, and measurement is performed by the power measurement circuit 855daa. When the power consumption of + 37V is 50% or more and less than 60%, the power consumption is judged to be stage 5 as the power consumption suppression stage. When the power consumption of + 37V measured by the power measurement circuit 855daa is 60% or more and less than 70%, the value 5 is set as the control signal value, and it is determined as step 6 as the power consumption suppression stage, and the power consumption suppression signal The value 6 is set as the value, and when the power consumption of + 37V measured by the power measuring circuit 855daa is 70% or more, it is determined as the stage 7 as the power consumption suppression stage and the value 7 is set as the value of the power consumption suppression signal To do.

  It should be noted that in the pachinko island facility, a system is usually used in which, for example, four pachinko gaming machines 1 are supplied as a group to one transformer, for example, to supply power (AC24V), respectively (for example, in one row). In the pachinko island facility in which 20 pachinko machines 1 are installed, four pachinko machines 1 are managed as five groups, and one transformer is provided for each group (a total of five transformers). ), Because a system in which power (AC24V) is supplied is adopted), a plurality of transformers having a maximum allowable capacity of 1000 VA are provided in the pachinko island facility.

  The + 5V power supply creation circuit 855db creates DC + 5V (DC + 5V, hereinafter referred to as “+ 5V”) from + 37V supplied from the smoothing circuit 855c via the power consumption monitoring circuit 855da. The +12 V power supply generation circuit 855 dc generates DC +12 V (DC +12 V, hereinafter referred to as “+12 V”) from +37 V supplied from the smoothing circuit 855 c via the power consumption monitoring circuit 855 da. The + 24V power supply generation circuit 855dd generates a direct current + 24V (DC + 24V, hereinafter referred to as “+ 24V”) from + 37V supplied from the smoothing circuit 855c via the power consumption monitoring circuit 855da. + 5V, + 12V, and + 24V are supplied to the payout control board 4110 and the frame peripheral relay terminal board 868, respectively. The power supply system supplied with + 5V is the + 5V power supply line, the power supply system supplied with + 12V is supplied with the + 12V power supply line, and the power supply system supplied with + 24V is supplied with the + 24V power supply line.

  As described later, + 5V generated by the + 5V power supply generation circuit 855db of the power supply generation circuit 855d is supplied to the payout control board 4110. + 5V supplied to the payout control board 4110 is applied to the power supply terminal of the payout control MPU 4120a via the payout control filter circuit 4110a, and to the power supply terminal of the payout control built-in RAM via the diode PD0. ing. + 12V generated by the + 12V power supply generation circuit 855dc of the power supply generation circuit 855d is supplied to the + 5V generation circuit 4100g of the main control board 4100 via the payout control board 4110. The + 5V creation circuit 4100g creates + 5V that is the control reference voltage of the main control MPU 4100a from + 12V from the payout control board 4110. The + 5V generated by the + 5V generating circuit 4100g is supplied to the power supply terminal of the main control MPU 4100a via the main control filter circuit 4100h and is also supplied to the power supply terminal of the main control built-in RAM via the diode MD0. ing.

  The negative terminal of the capacitor BC1 of the power supply board 851 is grounded to the ground (GND), while the positive terminal of the capacitor BC1 is electrically connected to the power supply terminal of the payout control built-in RAM of the payout control board 4110, and is paid out. The cathode terminal of the diode PD0 of the control board 4110 is also electrically connected. In other words, + 5V created by the + 5V power supply creation circuit 855db of the power supply creation circuit 855d on the power supply board 851 flows current toward the power supply terminal of the payout control MPU 4120a, and the power supply of the payout control built-in RAM is forward by the diode PD0. A current flows toward the terminal and the positive terminal of the capacitor BC1. As described above, the capacitor BC1 is electrically connected to the supply control board 4110 and again from the supply control board 4110 to the power supply board 851 by + 5V generated by the + 5V power supply generation circuit 855db of the power supply generation circuit 855d in the power supply board 851. With a simple connection method, + 5V is supplied and charging is possible. As a result, when + 5V generated by the + 5V power generation circuit 855db of the power generation circuit 855d is not supplied to the payout control board 4110, the charge charged in the capacitor BC1 is supplied to the payout control board 4110 as the payout VBB. Since the current is blocked by the diode PD0 and does not flow to the power supply terminal of the payout control MPU 4120a and the payout control MPU4120a does not operate, the payout VBB is supplied to the power supply terminal of the payout control built-in RAM. Thus, the stored contents are held.

  The negative terminal of the capacitor BC0 of the power supply board 851 is grounded to the ground (GND), while the positive terminal of the capacitor BC0 is electrically connected to the power supply terminal of the main control built-in RAM of the main control board 4100 via the payout control board 4110. And is also electrically connected to the cathode terminal of the diode MD0 of the main control board 4100. In other words, + 5V created by the + 5V creating circuit 4100g is such that current flows toward the power supply terminal of the main control MPU 4100a, and the power supply terminal of the main control built-in RAM, which is forward by the diode MD0, and the positive terminal of the capacitor BC0, An electric current flows toward. In this way, the capacitor BC0 is charged with + 5V supplied by the electrical connection method in which + 5V generated by the + 5V generating circuit 4100g is supplied from the main control board 4100 and the payout control board 4110 to the power supply board 851. Can be done. As a result, + 12V generated by the + 12V power generation circuit 855dc of the power generation circuit 855d in the power supply board 851 is not supplied to the + 5V generation circuit 4100g of the main control board 4100 via the payout control board 4110, and the + 5V generation circuit 4100g becomes + 5V. Since the charge charged in the capacitor BC0 is supplied as the main VBB to the main control board 4100 via the payout control board 4110, the main control MPU 4100a Although the main control MPU 4100a does not operate because the current is blocked by the diode MD0 and the main control MPU 4100a does not operate, the main VBB is supplied to the power supply terminal of the main control built-in RAM so that the stored contents are held. Yes.

[8-2. Voltage supplied to each control board]
Next, an outline of the voltage supplied to each control board and the like will be described, and subsequently, the voltage supplied mainly to the payout control board and the voltage supplied to the main control board will be described.

  The three types of voltages of + 5V, + 12V, and + 24V created by the + 5V power generation circuit 855db, the + 12V power generation circuit 855dc, and the + 24V power generation circuit 855dd of the power generation circuit 855d on the power supply board 851 are as shown in FIG. In addition, two types of voltages of + 12V and + 24V among these three types of voltages are supplied to the main control board 4100 via the payout control board 4110. The three types of voltages, + 5V, + 12V, and + 24V, created by the + 5V power generation circuit 855db, the + 12V power generation circuit 855dc, and the + 24V power generation circuit 855dd of the power generation circuit 855d on the power supply board 851 are the frame peripheral relay terminals. In addition to being supplied to the board 868, it is supplied to the peripheral control board 4140 and the peripheral door relay terminal board 882 via the frame peripheral relay terminal board 868.

  As shown in FIG. 20A, the three types of voltages supplied to the peripheral control board 4140 are + 5V, + 12V, and + 24V. The lamp driving circuit 4170a of the lamp driving board 4170 and the driving source driving circuit of the motor driving board 4180 are used. 4180a, respectively. The lamp driving circuit 4170a of the lamp driving board 4170 outputs various signals such as a lighting signal, a blinking signal and a gradation lighting signal to various decorative boards of the game board 4, and the driving source driving circuit 4180a of the motor driving board 4180 is a game. A drive signal is output to an electric drive source such as a motor or solenoid of the panel 4.

  Also, one type of voltage of +12 V supplied to the peripheral control board 4140 is supplied to the game board side liquid crystal module power supply circuit 3420a of the liquid crystal output board 3420 as shown in FIG. The game board side liquid crystal module power supply circuit 3420a creates a direct current of 3.3V (+ 3.3V, hereinafter referred to as “+ 3.3V”) from + 12V. The + 3.3V created by the game board side liquid crystal module power supply circuit 3420a is supplied to various electronic components mounted on the liquid crystal output board 3420, as well as the game board side liquid crystal module backlight power supply circuit 3420b and the game board side. These are supplied to various electronic components mounted on a substrate included in the liquid crystal display device 1900. The voltage generated by the game board side liquid crystal module backlight power supply circuit 3420b is supplied to the backlight included in the game board side liquid crystal display device 1900.

  + 12V is supplied to the movable liquid crystal display devices 1925a to 1925d. In the movable liquid crystal display devices 1925a to 1925d, + 12V from the liquid crystal output substrate 3420 is supplied to the movable liquid crystal module power supply circuit, and the movable liquid crystal module power supply circuit generates + 12V to + 3.3V to move the movable liquid crystal display device 1925a. In addition to being supplied to various electronic components mounted on the substrates included in each of the liquid crystal display devices 1925a to 1925d, the liquid crystal module backlight power supply circuit mounted on the substrates included in the movable liquid crystal display devices 1925a to 1925d. The power generated by each movable liquid crystal module backlight power supply circuit is supplied to the movable backlight provided in the movable liquid crystal display devices 1925a to 1925d.

  On the other hand, three types of voltages, + 5V, + 12V, and + 24V, supplied to the peripheral door relay terminal plate 882 are supplied to the frame decoration drive amplifier board 194 as shown in FIG. The frame decoration drive amplifier board 194 includes a + 9V creation circuit 194a that creates DC + 9V (DC + 9V, hereinafter referred to as “+ 9V”) from + 12V supplied from the peripheral door relay terminal board 882. Along with + 9V created by the + 9V creation circuit 194a, four types of voltages, + 5V, + 12V, and + 24V, supplied from the peripheral door relay terminal board 882, are supplied to various decorative boards and the like of the door frame 5.

  Further, the voltage of +5 V supplied to the peripheral door relay terminal plate 882 is supplied to the touch panel power supply circuit 450 a of the touch panel drive substrate 450. The touch panel power supply circuit 450a creates an analog system voltage and a digital system voltage from a voltage of +5 V, and necessary voltages are supplied to various electronic components constituting the touch panel circuit 450W shown in FIG. At the same time, it is supplied to the touch panel 480. Further, + 12V supplied to the peripheral door relay terminal plate 882 is supplied to the upper plate side liquid crystal module power supply circuit 450x. The upper plate side liquid crystal module power supply circuit 450x creates + 12V to + 3.3V. The + 3.3V created by the upper plate side liquid crystal module power supply circuit 450x is supplied to various electronic components constituting the liquid crystal module circuit 450V shown in FIG. 17, and the upper plate side liquid crystal module backlight power supply circuit 450y. And the various electronic components mounted on the substrate provided in the upper dish side liquid crystal display device 470. The voltage created by the upper plate side liquid crystal module backlight power supply circuit 450y is supplied to the backlight included in the upper plate side liquid crystal display device 470.

[8-2-1. Voltage supplied to dispensing control board]
As shown in FIG. 18, the payout control board 4110 includes a payout control filter circuit 4110a in addition to the payout control MPU 4120a. The payout control filter circuit 4110a is supplied with + 5V from the power supply board 851, and removes noise from the + 5V. In addition to being supplied to the capacitor BC1 of the power supply board 851 via the diode PD0, this + 5V is supplied to, for example, the payout control MPU 4120a of the payout control unit 4120. For example, + 12V from the power supply board 851 is supplied to the payout control input circuit 4120b of the payout control unit 4120 and the like, and is also supplied to the external communication circuit 784a of the external terminal board 784 via the payout control board 4110. The external communication circuit 784a of the external terminal board 784 outputs a signal that conveys the number of game balls paid out by the pachinko gaming machine 1 and game information of the pachinko gaming machine 1 to a hall computer installed in the game hall (hall). Circuit. The hall computer monitors the player's game by grasping the number of game balls paid out by the pachinko gaming machine 1 and the game information of the pachinko gaming machine 1 from the signal output from the external communication circuit 784a. . Note that +24 from the power supply board 851 is supplied to the main control board 4100 via the payout control board 4110 without being used in the payout control board 4110 at all.

[8-2-2. Voltage supplied to main control board]
As shown in FIG. 18, the main control board 4100 includes, in addition to the main control MPU 4100a and the like, a + 5V creation circuit 4100g, a main control filter circuit 4100h, a power failure monitoring circuit 4100e, and the like. The + 5V creation circuit 4100g is supplied with + 12V from the power supply board 851 via the payout control board 4110, and creates + 5V which is the control reference voltage of the main control MPU 4100a from this + 12V. In the main control board 4100, a power supply system supplied with + 5V generated by the + 5V generating circuit 4100g is a + 5V power supply line. In the present embodiment, the + 5V power supply line created by the + 5V power creation circuit 855db of the power supply creation circuit 855d in the power supply board 85 and the + 5V power supply line created by the + 5V creation circuit 4100g of the main control board 4100 are electrically connected. Since the circuit is configured so as not to be connected, the + 5V power supply line created by the + 5V power supply creation circuit 855db of the power supply creation circuit 855d in the power supply board 851 is electrically connected to various electronic components of the main control board 4100. In other words, the + 5V power supply line created by the + 5V creation circuit 4100g of the main control board 4100 is not electrically connected to various electronic components such as other boards other than the main control board 4100.

  The main control filter circuit 4100h is supplied with + 5V created by the + 5V creation circuit 4100g, and removes noise from this + 5V. In addition to being supplied to the capacitor BC0 of the power supply substrate 851 through the diode MD0, this + 5V is supplied to, for example, the main control MPU 4100a. For example, + 12V from the payout control board 4110 is supplied to the main control input circuit 4100b and the like, and + 24V from the payout control board 4110 is supplied to the main control solenoid drive circuit 4100d and the like, for example.

  The power failure monitoring circuit 4100e is supplied with + 12V and + 24V from the power supply board 851 via the payout control board 4110, and monitors these + 12V and + 24V signs of power failure or instantaneous power failure. When the power failure monitoring circuit 4100e detects signs of + 12V and + 24V power failure or instantaneous power failure, the power failure monitoring circuit 4100e outputs a power failure warning signal to the main control MPU 4100a as a power failure warning. The power failure notice signal is input to the payout control MPU 4120a via the main control board 4100 and the payout control input circuit 4120b of the payout control board 4110. The power failure notice signal is input to the peripheral control board 4140 via the main control board 4100. Further, the power failure warning signal is input to the frame decoration drive amplifier board 194 through the peripheral control board 4140, the frame peripheral relay terminal board 868, and the peripheral door relay terminal board 882 as shown in FIG. At the same time, the frame decoration drive amplifier board 194 is inputted to the decoration board of the door frame.

  In the present embodiment, the power failure monitoring circuit 4100e is applied to one of the + 12V power line and the + 24V power line by monitoring the voltages applied to the two power lines, the + 12V power line and the + 24V power line, respectively. Compared with the case where the voltage to be monitored is monitored, it is possible to more accurately grasp the sign of power interruption such as a power failure or a momentary power failure.

[9. Main control board circuit]
Next, the circuit of the main control board 4100 shown in FIG. 12 will be described with reference to FIGS. 21 is a circuit diagram showing a circuit of the main control board, FIG. 22 is a circuit diagram showing a power failure monitoring circuit, and FIG. 23 is a circuit showing an interface circuit for communication between the main control board and the peripheral control board. FIG. First, the main control filter circuit 4100h shown in FIG. 18 will be described, followed by the power source, main control system reset, main control crystal oscillator, main control input circuit, power failure monitoring circuit, main control MPU created by the main control board 4100. Various input / output signals to and from the main control board 4100 and the peripheral control board 4140 will be described.

  The main control board 4100 includes a main control MPU 4100a, a main control input circuit 4100b, a main control output circuit 4100c, a main control solenoid drive circuit 4100d, a power failure monitoring circuit 4100e, a + 5V generation circuit 4100g, and In addition to the control filter circuit 4100h, as a peripheral circuit, as shown in FIG. 21, a main control system reset MIC1 that outputs a reset signal, a main control crystal oscillator MX0 that outputs a clock signal (in this embodiment, 24 MHz (MHz )) Mainly.

[9-1. Main control filter circuit]
As shown in FIG. 21, the main control filter circuit 4100h mainly includes a main control three-terminal filter MIC0. This main control three-terminal filter MIC0 is a T-type filter circuit, and has excellent attenuation characteristics magnetically shielded with ferrite. In the main control three-terminal filter MIC0, + 5V generated by the + 5V generating circuit 4100g is applied to the first terminal, the second terminal is grounded to the ground (GND), and the noise component is removed from the third terminal. + 5V is output. + 5V applied to the first terminal is electrically connected to the other end of the capacitor MC0 whose one end is connected to the ground (GND), so that the ripple (AC component superimposed on the voltage) is first removed. Smoothed.

  + 5V output from the third terminal is electrically connected to the other end of the capacitor MC1 and the electrolytic capacitor MC2 (capacitance: 470 microfarad (μF) in this embodiment), one end of which is grounded with the ground (GND). By connecting to, ripples are further removed and smoothed. The smoothed +5 V is applied to the power supply terminal of the main control system reset MIC1, the VDD terminal that is the power supply terminal of the main control crystal oscillator MX0, the VDD terminal that is the power supply terminal of the main control MPU 4100a, and the like. Note that the power supply terminal of the main control MPU 4100a has a power failure or a momentary power failure, and when the power supply from the pachinko island facility is cut off, the electric charge charged in the electrolytic capacitor MC2 is a power failure or a momentary power failure. It is applied as +5 V over a period of about 7 milliseconds (ms) after the occurrence.

  One end of the VDD terminal of the main control MPU 4100a is electrically connected to the other end of the capacitor MC3 which is grounded to the ground (GND), and + 5V applied to the VDD terminal is further smoothed by removing ripples. The VSS terminal, which is the ground terminal of the main control MPU 4100a, is grounded to the ground (GND).

  In addition, the VDD terminal of the main control MPU 4100a is electrically connected to the anode terminal of the diode MD0 in addition to being electrically connected to the capacitor MC3. The cathode terminal of the diode MD0 is electrically connected to the VBB terminal, which is a power supply terminal of a RAM (main control built-in RAM) built in the main control MPU 4100a, and one end of the capacitor MC4 is grounded to the ground (GND). Is electrically connected to the other end. In addition to being electrically connected to the cathode terminal of the diode MD0 and the other end of the capacitor MC4, the VBB terminal of the main control built-in RAM is connected to the plus of the capacitor BC0 of the power supply board 851 shown in FIG. 18 via the resistor MR0. It is electrically connected to the terminal. That is, +5 V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the VDD terminal of the main control MPU 4100a, and via the diode MD0, the VBB terminal of the main control built-in RAM and the capacitor BC0. Are applied to the positive terminal. Accordingly, as described above, + 12V generated by the + 12V power generation circuit 855dc of the power generation circuit 855d in the power supply board 851 shown in FIG. 18 is transferred to the + 5V generation circuit 4100g of the main control board 4100 via the payout control board 4110. When the + 5V generation circuit 4100g cannot generate + 5V because it is not supplied, the electric charge charged in the capacitor BC0 is supplied to the main control board 4100 as the main VBB. Although the main control MPU 4100a does not operate because the current is blocked by the diode MD0 and does not flow to the VDD terminal of the MPU 4100a, the stored contents are held by applying the main VBB to the VBB terminal of the main control built-in RAM. ing.

[9-2. Main control system reset]
As shown in FIG. 21, + 5V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the power supply terminal of the main control system reset MIC1. The main control system reset MIC1 resets the main control MPU 4100a and the main control output circuit 4100ca with a reset function, and has a built-in delay circuit. One end of the delay capacitor terminal of the main control system reset MIC1 is electrically connected to the other end of the capacitor MC5 grounded to the ground (GND), and the delay time by the delay circuit is set by the capacitance of the capacitor MC5. Be able to. Specifically, when + 5V input to the power supply terminal reaches a threshold value (for example, 4.25V), main control system reset MIC1 outputs a system reset signal from the output terminal after the delay time has elapsed.

  The output terminal of the main control system reset MIC1 is electrically connected to the SRST terminal which is a reset terminal of the main control MPU 4100a and the reset terminal of the main control output circuit 4100ca with reset function. The output terminal is an open collector output type, one end of which is electrically connected to the other end of the pull-up resistor MR1 that is electrically connected to the + 5V power line, and one end of which is grounded to the ground (GND). It is electrically connected to the other end of MC6. Ripple is removed and smoothed by the capacitor MC6. When the voltage input to the power supply terminal is larger than the threshold value, the output terminal is pulled up to + 5V side by the pull-up resistor MR1, and the logic becomes HI. This logic is the SRST terminal of the main control MPU 4100a and the main control output with reset function. When the voltage input to the reset terminal of the circuit 4100ca is lower than the threshold value, the logic is LOW. This logic is the SRST terminal of the main control MPU 4100a and the main control output circuit 4100ca with reset function. Each is input to the reset terminal. Since the SRST terminal of the main control MPU 4100a and the reset terminal of the main control output circuit 4100ca with reset function are negative logic inputs, respectively, when the voltage input to the power supply terminal is smaller than the threshold value, the main control MPU 4100a and the reset function The attached main control output circuit 4100ca is reset. The power supply terminal is electrically connected to the other end of the capacitor MC7 whose one end is grounded (GND), and + 5V input to the power supply terminal is smoothed by removing ripples. The ground terminal is grounded with a grant (GND), and the NC terminal is not electrically connected to the outside.

[9-3. Main control crystal oscillator]
As shown in FIG. 21, +5 V smoothed by removing the noise component by the main control filter circuit 4100h is applied to the VDD terminal which is the power supply terminal of the main control crystal oscillator MX0. This VDD terminal is electrically connected to the other end of the capacitor MC8, one end of which is grounded (GND), and + 5V inputted to the VDD terminal is further smoothed by removing ripples. In addition to the VDD terminal, the smoothed + 5V is also applied to the A terminal, B terminal, C terminal, and ST terminal, which are output frequency selection terminals. The main control crystal oscillator MX0 outputs a clock signal of 24 MHz from the F terminal which is an output terminal by applying + 5V to these A terminal, B terminal, C terminal and ST terminal.

  The F terminal of the main control crystal oscillator MX0 is electrically connected to the CLK terminal which is the clock terminal of the main control MPU 4100a, and a clock signal of 24 MHz is input. Note that the GND terminal, which is the ground terminal of the main control crystal oscillator MX0, is grounded to the ground (GND), and the D terminal that outputs the divided frequency of the F terminal of the main control crystal oscillator MX0 is not electrically connected to the outside. It is in a state.

[9-4. Main control input circuit]
The main control input circuit 4100b receives the detection signals from the general prize opening switches 3020 and 3020, the upper start opening switch 3022, the lower start opening switch 2109, the magnetic detection switch 304, the count switch 2110, and the gate switch 2352 shown in FIG. In addition, this is a circuit to which an operation signal (RAM clear signal) or the like is input from the operation switch 860a provided in the payout control board 4110 shown in FIG. Since the circuit configuration to which the detection signal from each switch is input is the same, here, a circuit to which the operation signal (RAM clear signal) from the operation switch 860a is input will be described.

[9-4-1. A circuit to which an operation signal (RAM clear signal) is input from the operation switch]
First, as described above, the operation switch 860a includes the RAM (payout control built-in RAM) built in the payout control MPU 4120a of the payout control board 4110 and the main control of the main control board 4100 within a predetermined period from when the power is turned on. It is operated when clearing the RAM (main control built-in RAM) built in the MPU 4100a, or when an error is notified after the power is turned on, it is operated to cancel the error. Function to clear RAM within a predetermined period from power-on, and error cancellation after power-on (after a period during which the function is performed as RAM clear, that is, after a predetermined period elapses from power-on) And a function of performing Since the main control board 4100 does not have the error canceling function of the payout control board 4110, if an operation signal is input from the operation switch 860a within a predetermined period from when the power is turned on, the main control board 4100 receives the main control board 4100. A process of clearing the main control built-in RAM is performed as a RAM clear signal for clearing the built-in RAM.

  The main control board 4100 receives an operation signal whose logic is LOW from the payout control board 4110 when the operation switch 860a is not operated, while the logic from the payout control board 4110 when the operation switch 860a is operated. The operation signal in which HI becomes HI is input from the payout control board 4110 (detailed explanation of this point will be described later).

  As shown in FIG. 21, the transmission line for transmitting the operation signal from the operation switch 860a provided in the payout control board 4110 within a predetermined period from when the power is turned on is a pull-up whose one end is electrically connected to the + 12V power line. It is electrically connected to the other end of the resistor MR2 and electrically connected to the base terminal of the transistor MTR0 via the resistor MR3. In addition to being electrically connected to the resistor MR3, the base terminal of the transistor MTR0 is also electrically connected to the other end of the resistor MR4 that is grounded to the ground (GND). The emitter terminal of the transistor MTR0 is grounded to the ground (GND), and the collector terminal of the transistor MTR0 is electrically connected to the other end of the resistor MR5, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Main control via ICMIC 10 (non-inverted buffer ICMIC 10 includes eight non-inverted buffer circuits, and the signal waveform input to one of them (MIC 10A) is shaped and output without being inverted). The MPU 4100a is electrically connected to the input terminal PA0 of the input port PA.

  The circuit that outputs the operation signal from the operation switch 860a in the payout control board 4110 is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and transmits the operation signal from the operation switch 860a. The line is pulled up to the + 12V side by the pull-up resistor MR2. In the main control board 4100, when the operation switch 860a is not operated, the operation signal from the payout control board 4110 is pulled down to the ground (GND) side and the logic is input as LOW, while the operation switch 860a is operated. The operation signal from the payout control board 4110 is pulled up to the + 12V side by the pull-up resistor MR2 and the logic becomes HI.

  A circuit including the resistors MR3 and MR4 and the transistor MTR0 is a switch circuit that is turned on / off by an operation signal from the operation switch 860a.

  When the operation switch 860a is not operated, an operation signal whose logic is LOW is input to the base terminal of the transistor MTR0, so that the transistor MTR0 is turned OFF and the switch circuit is also turned OFF. As a result, the voltage applied to the collector terminal of the transistor MTR0 is pulled up to the + 5V side by the resistor MR5 and the operation signal from the operation switch 860a whose logic becomes HI is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. Is done. The main control MPU 4100a does not instruct to perform RAM clear to erase information stored in the main control built-in RAM when the logical value of the operation signal from the operation switch 860a input to the input terminal PA0 is HI. to decide.

  On the other hand, when the operation switch 860a is operated, an operation signal that is pulled up to + 12V by the pull-up resistor MR2 and has a logic level HI is input to the base terminal of the transistor MTR0, so that the transistor MTR0 is turned on. The circuit is also turned on. As a result, the operation signal from the operation switch 860a in which the voltage applied to the collector terminal of the transistor MTR0 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. Is done. The main control MPU 4100a instructs to clear the RAM for erasing the information stored in the main control built-in RAM when the logical value of the operation signal from the operation switch 860a input to the input terminal PA0 is LOW. Judge.

  The operation signal from the operation switch 860a is pulled up to the + 12V side by the pull-up resistor MR2. This is because an operation signal from the operation switch 860 a is input via the payout control board 4110. That is, between the boards of the main control board 4100 and the payout control board 4110, it is higher than the control reference voltage +5 V in order to suppress the influence of noise entering the wiring (harness) that electrically connects the boards. The reliability of the signal is enhanced by using + 12V which is a voltage. Therefore, in the present embodiment, detection signals from the general winning opening switch 3020, the upper start opening switch 3022, and the lower start opening switch 2109 that are directly input to the main control board 4100 are pulled up to the + 5V side by the pull-up resistor. On the other hand, detection signals from the magnetic detection switch 3024, the count switch 2110, the general winning opening switch 3020, and the gate switch 2352, which are input via the panel relay terminal plate 4161 shown in FIG. Since it is not input, it is pulled up to the + 12V side by a pull-up resistor in the same manner as the operation signal from the operation switch 860a.

[9-5. Power failure monitoring circuit]
As shown in FIG. 18, the main control board 4100 is supplied with two types of voltages of + 12V and + 24V from the power supply board 851 via the payout control board 4110, and + 12V and + 24V are input to the power failure monitoring circuit 4100e. ing. The power failure monitoring circuit 4100e monitors the signs of + 12V and + 24V power failure or instantaneous power failure, and detects a power failure warning signal as a power failure warning signal in addition to the main control MPU 4100a when detecting a power failure or instantaneous power failure sign. 4110 is output to the payout control MPU 4120a and the peripheral control board 4140. Here, the configuration of the power failure monitoring circuit will be described first, followed by the monitoring of the + 24V power failure or instantaneous power failure, the + 12V power failure or instantaneous power failure, and the output of the power failure warning signal.

[9-5-1. Configuration of power failure monitoring circuit]
As shown in FIG. 22, the power failure monitoring circuit 4100e mainly includes a shunt-type stabilized power supply circuit MIC20, an open collector output type comparator MIC21, a D-type flip-flop MIC22, and transistors MTR20 to MTR23.

  The reference voltage input terminal REF terminal and the cathode terminal K terminal of the shunt-type stabilized power supply circuit MIC20 are electrically connected to the other end of the resistor MR20, one end of which is electrically connected to the + 5V power supply line. + 5V is applied, and the current input to the REF terminal is limited by the resistor MR20. The K terminal outputs a reference voltage Vref that is a comparison reference voltage of the comparator MIC21 (in this embodiment, 2.495 V is set). The K terminal is electrically connected to the other end of the capacitor MC20 whose one end is grounded to the ground (GND). The reference voltage Vref output from the K terminal is rippled (convolved with the voltage by the capacitor MC20). AC component) is removed and smoothed. The A terminal, which is the anode terminal of the shunt-type stabilized power supply circuit MIC20, is grounded to the ground (GND).

  The comparator MIC21 includes two voltage comparison circuits, one of which (MIC21A) is used for comparing the monitor voltage V1 of + 24V and the reference voltage Vref, and the other one (MIC21B). , + 12V monitor voltage V2 and reference voltage Vref are used for comparison. The monitoring voltage V1 of + 24V is applied to the third terminal, which is the positive terminal of the MIC 21A, and the reference voltage Vref is applied to the second terminal, which is the negative terminal of the MIC 21A. The monitoring voltage V2 of + 12V is applied to the 5th terminal which is the plus terminal of the MIC 21B, and the reference voltage Vref is applied to the 6th terminal which is the minus terminal of the MIC 21B. These comparison results are input to the D-type flip-flop MIC22. The D-type flip-flop MIC22 includes two D-type flip-flop circuits, one of which (MIC22A) is used in the present embodiment. The Vcc terminal that is the power supply terminal of the comparator MIC21 is electrically connected to the other end of the capacitor MC21 whose one end is grounded (GND), and + 5V applied to the Vcc terminal that is the power supply terminal of the comparator MIC21 is The ripple is removed and smoothed by the capacitor MC21, and the GND terminal which is the ground terminal of the comparator MIC21 is grounded to the ground (GND).

[9-5-2. Monitoring of + 24V power outage or instantaneous power failure]
As described above, the monitoring of the + 24V power failure or instantaneous power failure is performed by the MIC 21A of the comparator MIC21 comparing the + 24V monitoring voltage V1 with the reference voltage Vref. The third terminal, which is the positive terminal of the MIC 21A of the comparator MIC 21 to which the + 24V monitoring voltage V1 is applied, has one end connected to the + 24V power line and the other end of the resistor MR21 as shown in FIG. Is connected to the ground (GND), the other end of the resistor MR22 is electrically connected and the other ends of the resistors MR21 and MR22, and the other end of the capacitor MC23 is grounded to the ground (GND). Are electrically connected. The + 24V monitoring voltage V1 applied to the third terminal, which is the positive terminal of the MIC21A of the comparator MIC21, is divided by + 24V by the resistance ratio of the resistors MR21 and MR22, and the ripple is removed by the capacitor MC23 and is smoothed. . The values of the resistors MR21 and MR22 are preset to the power failure detection voltage V1pf (in the present embodiment, set to 21.40V) when + 24V has a power failure or a momentary power failure, and the voltage starts dropping from + 24V. The monitoring voltage V1 of + 24V is set to be the same value as the reference voltage Vref.

  The first terminal that is the output terminal of the MIC 21A of the comparator MIC 21 is an open collector output, and one end is electrically connected to the other end of the pull-up resistor MR23 that is electrically connected to the + 5V power supply line. One end is electrically connected to the other end of the capacitor MC24, which is grounded with the ground (GND), and is electrically connected to a PR terminal which is a preset terminal of the D-type flip-flop MIC22. The capacitor MC24 plays a role as a low-pass filter.

  When the + 24V voltage is higher than the power failure detection voltage V1pf, the + 24V monitoring voltage V1 becomes higher than the reference voltage Vref, and the voltage applied to the first terminal which is the output terminal of the MIC 21A of the comparator MIC21 is + 5V by the pull-up resistor MR23. A signal whose logic is HI is input to the PR terminal which is a preset terminal of the D-type flip-flop MIC22.

  On the other hand, when the + 24V voltage is smaller than the power failure detection voltage V1pf, the + 24V monitoring voltage V1 becomes smaller than the reference voltage Vref, and the voltage applied to the first terminal which is the output terminal of the MIC 21A of the comparator MIC21 is the ground (GND). The signal having the logic level LOW is input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22.

[9-5-3. Monitoring of + 12V power failure or instantaneous power failure]
As described above, the + 12V power failure or instantaneous power failure is monitored by the MIC 21B of the comparator MIC21 comparing the + 12V monitor voltage V2 with the reference voltage Vref. As shown in FIG. 22, the fifth terminal, which is the plus terminal of the MIC 21B of the comparator MIC 21 to which the monitoring voltage V2 of +12 V is applied, has one end connected to the +12 V power line and the other end of the resistor MR24. Are connected to the other end of the resistor MR25, and the other ends of the resistors MR24 and MR25, and the other end of the capacitor MC25 is connected to the ground (GND). Are electrically connected. The + 12V monitoring voltage V2 applied to the fifth terminal, which is the positive terminal of the MIC21B of the comparator MIC21, is divided by + 12V by the resistance ratio of the resistors MR24 and MR25, and the ripple is removed by the capacitor MC25 and is smoothed. . The values of the resistors MR24 and MR25 are preset to the power failure detection voltage V2pf (in this embodiment, set to 10.47V) when + 12V has a power failure or a momentary power failure, and the voltage starts to drop from + 12V. The monitoring voltage V2 of + 12V is set to be the same value as the reference voltage Vref.

  The 7th terminal, which is the output terminal of the MIC21B of the comparator MIC21, is an open collector output and is electrically connected to the 1st terminal, which is the output terminal of the MIC21A, so that one end is electrically connected to the + 5V power line. The D-type flip-flop MIC22 is preset by being electrically connected to the other end of the pull-up resistor MR23 that is electrically connected, and one end being electrically connected to the other end of the capacitor MC24 that is grounded to the ground (GND). The terminal is electrically connected to the PR terminal. As described above, the capacitor MC24 serves as a low-pass filter.

  When the voltage of + 12V is higher than the power failure detection voltage V2pf, the monitoring voltage V2 of + 12V becomes higher than the reference voltage Vref, and the voltage applied to the seventh terminal which is the output terminal of the MIC21B of the comparator MIC21 is + 5V by the pull-up resistor MR23. A signal whose logic is HI is input to the PR terminal which is a preset terminal of the D-type flip-flop MIC22.

  On the other hand, when the voltage of + 12V is smaller than the power failure detection voltage V2pf, the monitoring voltage V2 of + 12V becomes smaller than the reference voltage Vref, and the voltage applied to the seventh terminal which is the output terminal of the MIC21B of the comparator MIC21 is the ground (GND). The signal with the logic level LOW is input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22.

[9-5-4. Output of power failure warning signal]
The D type flip-flop MIC22 stores the value (logic) of the signal input to the 1D terminal, which is the D input terminal, according to the change in the edge of the clock signal input to the 1CK terminal, which is the clock input terminal. (Logic) is output from the 1Q terminal that is the output terminal, and a value obtained by inverting the stored value (logic) is output from the negative logic 1Q terminal that is the output terminal. In addition, when a signal whose logic is LOW is input to the CLR terminal which is the clear terminal, the D-type flip-flop MIC22 releases the latch state and changes the logic of the signal input to the PR terminal which is the preset terminal. The inverted signal is output from the 1Q terminal that is the output terminal (at this time, the same logic as that of the signal that is inverted from the logic of the signal output from 1Q, that is, the signal that is input to the PR terminal that is the preset terminal) On the other hand, when a signal whose logic is HI is input to the CLR terminal which is the clear terminal, the latch state is set. The D-type flip-flop MIC22 has a logic LOW at the preset terminal PR when a signal whose logic is HI is input to the CLR terminal which is a clear terminal and the latch state is set. When the signal is input, the state that the signal whose logic is HI is output from the 1Q terminal which is the output terminal is maintained (the signal obtained by inverting the logic of the signal output from 1Q is negative logic) The state of outputting from the 1Q terminal is maintained.

  In the D-type flip-flop MIC22, in this embodiment, the 1D terminal that is the D input terminal and the 1CK terminal that is the clock input terminal are grounded to the ground (GND). The circuit configuration is such that there is no change in the edge of the input clock signal, and the value (logic) of the signal input to the 1D terminal which is the D input terminal is stored and is not output from the 1Q terminal which is the output terminal. ing. As described above, the D-type flip-flop MIC22 has a signal from the first terminal that is the output terminal of the MIC21A of the comparator MIC21 that monitors the + 24V power failure or the instantaneous power failure, and the + 12V power failure. Alternatively, a signal from the 7th terminal that is the output terminal of the MIC 21B of the comparator MIC 21 that monitors the instantaneous power failure is input, and a signal is output from the 1Q terminal that is the output terminal based on these signals. The Vcc terminal, which is a power supply terminal, is electrically connected to the other end of the capacitor MC22 whose one end is grounded (GND), and is applied to the Vcc terminal, which is the power supply terminal of the D-type flip-flop MIC22. + 5V is smoothed by removing the ripple by the capacitor MC22, the GND terminal as the ground terminal is grounded to the ground (GND), and the negative logic 1Q terminal that inverts the logic of the 1Q terminal as the output terminal is electrically connected to the outside. In an unconnected state.

  In the present embodiment, in the D-type flip-flop MIC22, the power failure clear signal from the main control MPU 4100a is input to the CLR terminal which is a clear terminal via the main control output circuit 4100ca with a reset function. This power failure clear signal is output after a predetermined time has elapsed after the start of output in the main control-side power-on process described later performed by the main control MPU 4100a. Since the CLR terminal is a negative logic input, the power failure clear signal from the main control MPU 4100a is input to the CLR terminal with the logic being LOW via the main control output circuit 4100ca with a reset function. When the power failure clear signal is input to the CLR terminal, the D-type flip-flop MIC22 cancels the latch state. At this time, the logic input to the PR terminal which is a preset terminal is inverted and the output terminal Is output from the 1Q terminal.

  On the other hand, when the output of the power failure clear signal from the main control MPU 4100a is stopped, the logic becomes HI via the main control output circuit 4100ca with reset function and is input to the CLR terminal. When the power failure clear signal is not input to the CLR terminal, the D-type flip-flop MIC22 sets the latch state, and latches the state where the logic is LOW at the PR terminal.

  The 1Q terminal that is the output terminal of the D-type flip-flop MIC22 is electrically connected to the input terminal PA1 of the input port PA of the main control MPU 4100a via the main control input circuit 4100b, and is the output terminal of the D-type flip-flop MIC22. A signal output from the 1Q terminal is input to the input terminal PA1 of the input port PA of the main control MPU 4100a as a power failure warning signal. The 1Q terminal that is the output terminal of the D-type flip-flop MIC22 is electrically connected to the main control output circuit 4100cb having no reset function, and resets the signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22. The functionless main control output circuit 4100cb outputs a payout power failure notice signal to the payout control board 4110 and also outputs it to the peripheral control board 4140 as a peripheral power failure notice signal.

  The main control input circuit 4100b that electrically connects the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, and the input terminal PA1 of the input port PA of the main control MPU 4100a has a D-type flip-flop as shown in FIG. The 1Q terminal, which is the output terminal of the MIC 22, is electrically connected to the other end of the resistor MR26, one end of which is electrically connected to the + 5V power supply line, and electrically connected to the base terminal of the transistor MTR20 via the resistor MR27. It is connected. In addition to being electrically connected to the resistor MR27, one end of the transistor MTR20 is electrically connected to the other end of the resistor MR28 that is grounded to the ground (GND). The emitter terminal of the transistor MTR20 is grounded to the ground (GND), and the collector terminal of the transistor MTR20 is electrically connected to the other end of the resistor MR29, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Main control via ICMIC 23 (non-inverted buffer ICMIC 23 includes eight non-inverted buffer circuits, and the signal waveform input to one (MIC 23A) is shaped and output without being inverted). The MPU 4100a is electrically connected to the input terminal PA1 of the input port PA.

  The circuit composed of the resistors MR27 and MR28 and the transistor MTR20 is a switch circuit that is turned ON / OFF by a signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22.

  When the logic of the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is LOW, the voltage applied to the base terminal of the transistor MTR20 is pulled down to the ground (GND) side, and the transistor MTR20 is turned OFF. The switch circuit is also turned off. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR20 is raised to the + 5V side, turning on the transistor MTR20, The switch circuit is also turned on.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic is HI is preset in the D-type flip-flop MIC22. Since the signal is output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, the logic becomes LOW and is input to the base terminal of the transistor MTR20. Turn off. As a result, the voltage applied to the collector terminal of the transistor MTR20 is pulled up to + 5V by the resistor MR29, and the power failure warning signal whose logic becomes HI via the non-inverting buffer ICMIC23 is input to the input terminal PA of the input port PA of the main control MPU4100a. Input to PA1.

  On the other hand, when either one of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D Since the signal is input to the PR terminal which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 becomes the logic HI and is input to the base terminal of the transistor MTR20. As a result, the transistor MTR20 is turned ON. Thereby, the voltage applied to the collector terminal of the transistor MTR20 is pulled down to the ground (GND) side, and the power failure warning signal whose logic becomes LOW via the non-inverting buffer ICMIC23 becomes the input terminal of the input port PA of the main control MPU 4100a. Input to PA1.

  Also, as shown in FIG. 22, the main control output circuit 4100cb without reset function that outputs a signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, to the payout control board 4110 as a payout blackout signal is opened. The circuit is configured as a collector output type, and the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and the transistor MTR21 of the previous stage is connected via the resistor MR30. It is electrically connected to the base terminal. In addition to being electrically connected to the resistor MR30, one end of the base terminal of the transistor MTR21 at the previous stage is electrically connected to the other end of the resistor MR31 that is grounded to the ground (GND). The emitter terminal of the front-stage transistor MTR21 is grounded to the ground (GND), and the collector terminal of the front-stage transistor MTR21 is electrically connected to the other end of the resistor MR32 whose one end is electrically connected to the + 5V power supply line. At the same time, it is electrically connected to the base terminal of the subsequent transistor MTR22 via a resistor MR33. In addition to being electrically connected to the resistor MR33, one end of the base terminal of the transistor MTR22 at the subsequent stage is electrically connected to the other end of the resistor MR34 that is grounded to the ground (GND). The emitter terminal of the rear-stage transistor MTR22 is grounded to the ground (GND), and the collector terminal of the rear-stage transistor MTR22 is electrically connected to the other end of the capacitor MC26 whose one end is grounded to the ground (GND). It is electrically connected to the payout control board 4110 via (harness). When the collector terminal of the latter-stage transistor MTR22 is electrically connected to the payout control board 4110 via a wiring (harness), the payout control input of the payout control unit 4120 shown in FIG. In the circuit 4120b, one end of the circuit 4120b is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the + 12V power supply line, and is electrically connected to an input terminal of a predetermined input port of the payout control MPU 4120a shown in FIG. Connected.

  A circuit composed of the resistors MR30 and MR31 and the preceding transistor MTR21 is a preceding switch circuit, and a circuit composed of the resistors MR33 and MR34 and the succeeding transistor MTR22 is a succeeding switch circuit, and is a D-type flip-flop. It is turned ON / OFF by a signal output from the 1Q terminal which is an output terminal of the MIC 22.

  When the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is LOW, the voltage applied to the base terminal of the previous transistor MTR21 is pulled down to the ground (GND) side, and the previous transistor The MTR 21 is turned OFF and the preceding switch circuit is also turned OFF, and the voltage applied to the collector terminal of the preceding transistor MTR 21, which is the voltage applied to the base terminal of the succeeding transistor MTR 22, is raised to the + 5V side by the resistor MR 32. As a result, the rear-stage transistor MTR22 is turned on, and the rear-stage switch circuit is also turned on. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR21 is raised to the + 5V side and the transistor MTR21 is turned ON. The front-stage switch circuit is also turned on, and the voltage applied to the collector terminal of the front-stage transistor MTR21, which is the voltage applied to the base terminal of the rear-stage transistor MTR22, is lowered to the ground (GND) side, thereby The transistor MTR22 is turned off, and the subsequent switch circuit is also turned off.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic is HI is preset in the D-type flip-flop MIC22. Because the signal is input to the PR terminal, which is the terminal, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, becomes logic LOW and is input to the base terminal of the transistor MTR21 in the previous stage. The transistor MTR21 is turned off. As a result, the voltage applied to the collector terminal of the former-stage transistor MTR21 is pulled up to the + 5V side by the resistor MR32 and applied to the base terminal of the latter-stage transistor MTR22. As a result, the voltage applied to the collector terminal of the subsequent transistor MTR22 is pulled down to the ground (GND) side in the payout control board 4110 via the wiring (harness), so that the payout power failure warning signal whose logic is LOW is issued. Input to the control board 4110.

  On the other hand, when either one of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D Since the signal is input to the PR terminal, which is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, becomes logic HI and becomes the base terminal of the transistor MTR21 in the previous stage. As a result of the input, the previous-stage transistor MTR21 is turned ON. As a result, the voltage applied to the collector terminal of the preceding transistor MTR21 is pulled down to the ground (GND) and applied to the base terminal of the succeeding transistor MTR22, thereby turning off the succeeding transistor MTR22. As a result, the voltage applied to the collector terminal of the transistor MTR22 in the subsequent stage is pulled up to + 12V side by the pull-up resistor in the payout control input circuit 4120b of the payout control unit 4120 in the payout control board 4110 via the wiring (harness). A payout power failure notice signal whose logic is HI is input to the payout control board 4110.

  Further, as shown in FIG. 22, the main control output circuit 4100cb having no reset function for outputting the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, to the peripheral control board 4140 as a peripheral power failure warning signal is opened. The circuit is configured as a collector output type, and the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is electrically connected to the resistor MR26 of the main control input circuit 4100b described above, and the base terminal of the transistor MTR23 via the resistor MR35. And are electrically connected. In addition to being electrically connected to the resistor MR35, one end of the transistor MTR23 is electrically connected to the other end of the resistor MR36 that is grounded to the ground (GND). The emitter terminal of the transistor MTR23 is grounded to the ground (GND), and the collector terminal of the transistor MTR23 is electrically connected to the peripheral control board 4140 via a wiring (harness). When the collector terminal of the transistor MTR23 is electrically connected to the peripheral control board 4140 via a wiring (harness), a peripheral control input circuit (not shown) of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. In FIG. 15, one end is electrically connected to the other end of a pull-up resistor (not shown) that is electrically connected to the + 12V power supply line, and is electrically connected to an input terminal of a predetermined input port of the peripheral control MPU 4150a shown in FIG. Connected.

  The circuit composed of the resistors MR35 and MR36 and the transistor MTR23 is a switch circuit that is turned ON / OFF by a signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22.

  When the logic of the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is LOW, the voltage applied to the base terminal of the transistor MTR23 is pulled down to the ground (GND) side, and the transistor MTR23 is turned OFF. The switch circuit is also turned off. On the other hand, when the logic of the signal output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, is HI, the voltage applied to the base terminal of the transistor MTR23 is raised to the + 5V side, and the transistor MTR23 is turned on. The switch circuit is also turned on.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, the signal whose logic is HI is preset in the D-type flip-flop MIC22. Since the signal is output from the 1Q terminal, which is the output terminal of the D-type flip-flop MIC22, the logic becomes LOW and is input to the base terminal of the transistor MTR23. Turn off. Thereby, the voltage applied to the collector terminal of the transistor MTR23 is pulled up to + 12V side by the pull-up resistor in the payout control input circuit of the peripheral control unit 4150 in the peripheral control board 4140 via the wiring (harness), so that the logic becomes HI. The peripheral power failure warning signal is input to the peripheral control board 4140.

  On the other hand, when either one of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, the signal whose logic is LOW is D Since the signal is input to the PR terminal that is the preset terminal of the type flip-flop MIC22, the signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22 becomes the logic HI and is input to the base terminal of the transistor MTR23. As a result, the transistor MTR23 is turned ON. As a result, the peripheral power failure notice signal whose logic is LOW is generated when the voltage applied to the collector terminal of the transistor MTR23 is pulled down to the ground (GND) side in the peripheral control board 4140 via the wiring (harness). 4140 is input.

  As described above, the main control input circuit 4100b that transmits the signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22 to the main control MPU 4100a as a power failure warning signal, and the 1Q terminal that is the output terminal of the D-type flip-flop MIC22. The main control output circuit 4100cb without reset function for outputting the signal output from the peripheral control board 4140 to the peripheral control board 4140 has one transistor, and the power failure warning signal input to the main control MPU 4100a and the peripheral While the logic of the peripheral power failure warning signal input to the control board 4140 is the same logic, the signal output from the 1Q terminal which is the output terminal of the D-type flip-flop MIC22 is sent out to the payout control board 4110 No reset function to output as a power failure warning signal The control circuit 4100cb has two transistors, a front stage and a rear stage, and the logic of the payout power failure warning signal is the logic of the power failure warning signal input to the main control MPU 4100a and the peripheral power failure warning signal input to the peripheral control board 4140. The logic of the signal is inverted and is different from the logic of the power failure warning signal and the logic of the peripheral power failure warning signal.

  The collector terminal of the transistor MTR20 of the main control input circuit 4100b is electrically connected to the other end of the resistor MR29, one end of which is electrically connected to the + 5V power supply line, and the main control MPU 4100a via the non-inverting buffer ICMIC23. The collector terminal of the transistor MTR22 at the subsequent stage of the main control output circuit 4100cb without reset function is electrically connected to the input terminal PA1 of the input port PA of the payout control board via the wiring (harness). In the payout control input circuit 4120b of the payout control unit 4120 in 4110, one end is electrically connected to the other end of the pull-up resistor electrically connected to the + 12V power supply line, and the main control output circuit 4100cb without reset function is connected. The collector terminal of the transistor MTR23 is Wiring through a (harness), the payout control input circuit of the peripheral control unit 4150 in the peripheral control board 4140, which is a pull-up resistor electrically connected to one end of which is connected + 12V power supply line and electrically. This is because the transistor MTR20 and the main control MPU 4100a of the main control input circuit 4100b are connected to the main control board between the collector terminal of the transistor MTR20 of the main control input circuit 4100b and the input terminal PA1 of the input port PA of the main control MPU 4100a. 4100, the main control board 4100 and the payout control board are used to perform the power outage notice by the logic (ON / OFF signal) of the power outage notice signal using + 5V which is the control reference voltage of the main control MPU 4100a. In order to suppress the influence of noise entering the wiring (harness) electrically connecting between the boards, the main control MPU 4100a, between the boards with 4110 and between the boards with the main control board 4100 and the peripheral control board 4140, Dispensing control MPU 4120a and peripheral control MPU 4150a Is performed blackout notice by the logic of a control reference voltage + 5V is at a higher voltage than the + with 12V power failure warning signal (ON / OFF signal).

[9-6. Various input / output signals to main control MPU]
Next, various input / output signals to the main control MPU 4100a will be described with reference to FIG. The RXA terminal, which is the serial data input terminal of the serial input port of the main control MPU 4100a, receives serial data from the payout control board 4110 shown in FIG. 12 as a payer serial data reception signal via the main control input circuit 4100b. . On the other hand, the TXA terminal and the TXB terminal, which are serial data output terminals of the serial output port of the main control MPU 4100a, receive the serial data transmitted from the TXA terminal to the payout control board 4110 as a main payout serial data transmission signal and do not have a reset function. A main payment serial data transmission signal is transmitted to the payout control board 4110 from the main control output circuit 4100cb without reset function to the circuit 4100cb, and the serial data to be sent to the peripheral control board 4140 shown in FIG. The peripheral serial data transmission signal is transmitted to the main control output circuit 4100cb without reset function, and the main peripheral serial data transmission signal is transmitted from the main control output circuit 4100cb without reset function to the peripheral control board 4140.

  In addition to the above-described operation signal (RAM clear signal) being input to each input terminal of a predetermined input port of the main control MPU 4100a, for example, a payout for notifying the completion of normal reception of the above-described main payment serial data reception signal A payer ACK signal from the control board 4110 is input via the main control input circuit 4100b, and detection signals from various switches such as the upper start port switch 3022 shown in FIG. 12 are input via the main control input circuit 4100b. It is input.

  On the other hand, from each output terminal of a predetermined output port of the main control MPU 4100a, for example, a main payment ACK signal that indicates the completion of normal reception of the above-described payment serial data reception signal is output to the main control output circuit 4100ca with reset function. Then, a main payout ACK signal is output from the main control output circuit 4100ca with reset function to the payout control board 4110, or a drive signal is sent to the main control output circuit 4100ca with reset function for the start port solenoid 2105 shown in FIG. To output a drive signal from the main control output circuit 4100ca with reset function to the start port solenoid 2105 via the main control solenoid drive circuit 4100d, or various displays such as the upper special symbol display 1185 shown in FIG. Drive signal to the main control output circuit 4100ca with reset function. Is output to the various display devices from the main control output circuit 4100ca with reset function, or various information about the game (game information) is output to the main control output circuit 4100ca with reset function to output the main signal with the reset function. Various information (game information) related to the game is output to the payout control board 4110 from the control output circuit 4100ca.

[9-7. Interface circuit for communication between main control board and peripheral control board]
Next, a communication interface circuit between the main control board 4100 and the peripheral control board 4140 will be described with reference to FIG. The main control board 4100 is supplied with + 12V from the power supply board 851 shown in FIG. 18 via the payout control board 4110, and the + 5V creation circuit 4100g creates + 5V which is the control reference voltage of the main control MPU 4100a from this + 12V. ing. The main peripheral serial data transmission signal transmitted from the main control board 4100 to the peripheral control board 4140 is affected by noise entering the wiring (harness) that electrically connects the main control board 4100 and the peripheral control board 4140. Therefore, the reliability is enhanced by using + 12V, which is a voltage higher than + 5V, which is the control reference voltage of the main control MPU 4100a.

  Specifically, the main control board 4100 causes the main control output circuit 4100cb without a reset function to function as a communication interface circuit, and the communication interface circuit mainly includes a resistor MR50, resistors MR51 and MR52, and a transistor MTR50. Has been. On the other hand, the peripheral control board 4140 includes a diode AD10, an electrolytic capacitor AC10 (capacitance: 47 μF in this embodiment), and a photocoupler AIC10 (infrared LED and photo IC) as a communication interface circuit. It is mainly configured).

  + 12V supplied from the power supply board 851 is applied to the anode terminal of the diode MD50 of the main control board 4100 through the payout control board 4110, and the minus terminal is grounded to the ground (GND) to the cathode terminal of the diode MD50. The electrolytic capacitor MC50 (capacitance: 220 microfarad (μF) in this embodiment) is electrically connected to the plus terminal. The cathode terminal of the diode MD50 is electrically connected to the positive terminal of the electrolytic capacitor MC50, and is electrically connected to the anode terminal (first terminal) of the photocoupler AIC10 of the peripheral control board 4140 via a wiring (harness). It is connected to the. Thereby, for example, when power from the power supply board 851 is not supplied to the main control board 4100 via the payout control board 4110 due to a power failure or a momentary power failure, the charge charged in the electrolytic capacitor MC50 is reduced. + 12V can be continuously applied from the main control board 4100 to the anode terminal of the photocoupler AIC 10 of the peripheral control board 4140.

  In this way, the VDD terminal, which is the power supply terminal of the main control MPU 4100a, is charged to the electrolytic capacitor MC2 (capacitance: 470 μF in this embodiment) shown in FIG. 21 when a power failure or a momentary power failure occurs. Therefore, the main peripheral serial transmission port 4100ae built in the main control MPU 4100a serially manages at least the command set by the main control CPU core 4100aa in the transmission buffer register 4100aeb. The unit 4100aec can transfer the data to the transmission shift register 41aea and complete the transmission from the transmission shift register 4100aea as main peripheral serial data.

  The main peripheral serial data transmission signal transmitted from the main control board 4100 to the peripheral control board 4140 is connected to the wiring (harness) that electrically connects the main control board 4100 and the peripheral control board 4140 as described above. In order to suppress the influence of intruding noise, the reliability is enhanced by transmitting + 12V, which is a voltage higher than + 5V, which is the control reference voltage of the main control MPU 4100a.

  Therefore, in the present embodiment, when a power failure or a momentary power failure occurs, the charge charged in the electrolytic capacitor MC50 is applied as +12 V to the anode terminal of the photocoupler AIC10 of the peripheral control board 4140 from the main control board 4100. Therefore, the main peripheral serial transmission port 4100ae built in the main control MPU 4100a transfers the command set by the main control CPU core 4100aa in the transmission buffer register 4100aeb to the transmission shift register 41aea by the serial management unit 4100aec and transmits it. When transmission is performed from the shift register 4100aea as main circumference serial data, a main circumference serial data transmission signal having a logic level of HI can be transmitted from the collector terminal of the transistor MTR50 by + 12V.

  In this embodiment, the storage capacity of the transmission buffer register 4100aeb of the main serial transmission port 4100ae built in the main control MPU 4100a has 32 bytes, and one packet is composed of 3 bytes of data. Therefore, data for 10 packets at the maximum is stored in the transmission buffer register 4100aeb. In this embodiment, the transfer bit rate of the main peripheral serial data transmitted from the main control MPU 4100a is set to 19200 bps.

  The cathode terminal (third terminal) of the photocoupler AIC10 is electrically connected to the collector terminal of the transistor MTR50 of the main control board 4100 via the resistor AR10 and its wiring (harness). The resistor AR10 of the peripheral control board 4140 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler AIC10.

  The TXB terminal that outputs a main peripheral serial data transmission signal from the main control MPU 4100a shown in FIG. And is electrically connected to the base terminal of the transistor MTR50. In addition to being electrically connected to the resistor MR51, one end of the transistor MTR50 is electrically connected to the other end of the resistor MR52 that is grounded to the ground (GND). The emitter terminal of the transistor MTR50 is grounded to the ground (GND).

  The circuit composed of the resistors MR51 and MR52 and the transistor MTR50 is a switch circuit. When the logic of the main serial data transmission signal is HI, the voltage applied to the base terminal of the transistor MTR50 is on the ground (GND) side. As a result, the transistor MTR50 is turned off, and the switch circuit is also turned off. As a result, the forward current does not flow through the built-in infrared LED of the photocoupler AIC10 on the peripheral control board 4140, so the photocoupler AIC10 is turned off. On the other hand, when the logic of the main serial data transmission signal is LOW, the voltage applied to the base terminal of the transistor MTR50 is pulled up to + 5V by the resistor MR50, turning on the transistor MTR50 and turning on the switch circuit. . As a result, a forward current flows through the built-in infrared LED of the photocoupler AIC10 on the peripheral control board 4140, so that the photocoupler AIC10 is turned on.

  + 5V supplied from the power supply board 851 is applied to the anode terminal of the diode AD10 of the peripheral control board 4140 via the frame peripheral relay terminal board 868, and the cathode terminal of the diode AD10 is connected to the ground (GND). It is electrically connected to the positive terminal of the grounded electrolytic capacitor AC10. In addition to being electrically connected to the positive terminal of the electrolytic capacitor AC10, the cathode terminal of the diode AD10 is also electrically connected to the Vcc terminal (No. 6 terminal) that is the power supply terminal of the photocoupler AIC10. The emitter terminal (No. 4 terminal) of the photocoupler AIC10 is grounded to the ground (GND), and the collector terminal (No.5 terminal) of the photocoupler AIC10 is a pull-up resistor electrically connected to the plus terminal of the electrolytic capacitor AC10. It is pulled up to + 5V by AR11 and is electrically connected to the input terminal of the serial I / O port for main control board of peripheral control MPU 4150a. When the photocoupler AIC10 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler AIC10 changes, and the signal is used as the main peripheral serial data transmission signal as the serial I / O port for the main control board of the peripheral control MPU4150a. Is input to the input terminal.

  Thereby, as described above, for example, when a power failure or a momentary power failure occurs, +5 V supplied from the power supply board 851 is not supplied to the peripheral control board 4140 via the frame peripheral relay terminal board 868. The electric charge charged in the electrolytic capacitor AC10 can be continuously applied to the Vcc terminal of the photocoupler AIC10 as + 5V. When electric power or a momentary power failure occurs, + 5V from the electrolytic capacitor AC10 is applied, so that the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 is sent to the main control MPU 4100a. The data set in the transmission buffer register 4100aeb of the built-in main circumference serial transmission port 4100ae can be completed, and the main circumference serial data transmission signal in the middle of transmission, that is, the main circumference serial data is cut off. The peripheral control board 4140 reliably receives the signal without being lost or missing.

  When the logic of the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 is HI, the voltage applied to the base terminal of the transistor MTR50 is pulled down to the ground (GND) side and the transistor Since the photocoupler AIC10 is turned off when the MTR50 is turned off, the voltage applied to the collector terminal of the photocoupler AIC10 is pulled up to the + 5V side by the pull-up resistor AR11, and the logic becomes HI. While the serial data transmission signal is input to the input terminal of the serial I / O port for the main control board of the peripheral control MPU 4150a, the logic of the main peripheral serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140 When is LOW Is applied to the collector terminal of the photocoupler AIC10 because the voltage applied to the base terminal of the transistor MTR50 is pulled up to + 5V by the resistor MR50 and the transistor MTR50 is turned on so that the photocoupler AIC10 is turned on. The main peripheral serial data transmission signal whose logic is LOW by the pulled voltage being pulled down to the ground (GND) side is input to the input terminal of the main control board serial I / O port of the peripheral control MPU 4150a. Thus, the logic of the main circumference serial data transmission signal output from the collector terminal of the photocoupler AIC10 is the same as the logic of the main circumference serial data transmission signal transmitted from the TXB terminal of the main control MPU 4100a to the peripheral control board 4140. It is the logic of

  As described above, in this embodiment, the + 5V power supply line to which + 5V that is the control reference voltage of the main control MPU 4100a is applied, and the + 12V power supply line to which + 12V that is the communication voltage applied via the diode MD50 is applied. Measures are taken when a power failure or a momentary power failure occurs and the control reference voltage and the communication voltage drop. That is, for the main peripheral serial transmission port 4100ae built in the main control MPU 4100a, a + 5V power supply line, a positive terminal of the electrolytic capacitor MC2 using the electrolytic capacitor MC2 of the main control filter circuit 4100h as a first auxiliary power supply, Are electrically connected in parallel, so that even if a power failure or a momentary power failure occurs and the control reference voltage applied from the + 5V power supply line decreases, the electrolytic capacitor of the main control filter circuit 4100h as the first auxiliary power supply By applying the control reference voltage from the plus terminal of MC2, the state in which the control reference voltage is applied can be maintained, and the resistor MR50, the resistors MR51 and MR52, and the transistor MTR50 are configured. Main function without reset function to function as a communication interface circuit For the output circuit 4100cb, + 12V applied to the + 12V power supply line is applied as a communication voltage to the anode terminal of the diode MD50, and the positive terminal of the cathode terminal of the diode MD50 and the electrolytic capacitor MC50 as the second auxiliary power supply. Even if a power failure or a momentary power failure occurs and the communication voltage applied from the + 12V power supply line via the diode MD50 is reduced by the terminals being electrically connected in parallel, the second auxiliary power supply is provided. By applying the communication voltage from the positive terminal of the electrolytic capacitor MC50, the state where the communication voltage is applied can be maintained. As a result, it is possible to prevent the command being transmitted from the main control board 4100 to the peripheral control board 4140 from being broken, and to prevent omission of the command, so that the peripheral control board 4140 reliably receives the command being transmitted. can do. Therefore, it is possible to eliminate the missed command immediately after the occurrence of a power failure or during a momentary power failure.

  A plurality of commands set in the transmission buffer register 4100aeb of the main peripheral serial transmission port 4100ae built in the main control MPU 4100a are all composed of a resistor MR50, resistors MR51 and MR52, and a transistor MTR50 as main peripheral serial data. 470 μF is set as the capacitance of the electrolytic capacitor MC2 of the main control filter circuit 4100h so that the transmission to the peripheral control board 4140 can be completed via the main control output circuit 4100cb having no reset function that functions as a communication interface circuit. 220 μF is set as the capacitance of the electrolytic capacitor MC50. As a result, even if a power failure or a momentary power failure occurs during transmission from the main control board 4100 to the peripheral control board 4140, a reset that causes all of the commands set in the transmission buffer register 4100aeb to function as an interface circuit as main peripheral serial data Since the transmission to the peripheral control board 4140 can be completed via the non-functional main control output circuit 4100cb, the peripheral control board 4140 can omit a plurality of commands set in the transmission buffer register 4100aeb without missing them. And can be received reliably.

[10. Dispensing control board circuit]
Next, the circuit of the payout control board 4110 shown in FIG. 13 will be described with reference to FIGS. 24 is a circuit diagram showing a circuit and the like of the payout control unit, FIG. 25 is a circuit diagram showing a payout control input circuit, FIG. 26 is a circuit diagram showing a continuation of FIG. 25, and FIG. 28 is a circuit diagram showing a circuit, FIG. 28 is a circuit diagram showing a CR unit input / output circuit, and FIG. 29 is an input / output diagram showing various input / output signals to / from the main control board and various output signals to an external terminal board. It is. First, the payout control filter circuit will be described, and then the payout control circuit, various input / output signals with the main control board, and various output signals to the external terminal board will be described.

[10-1. Dispensing control filter circuit]
As shown in FIG. 24, the payout control filter circuit 4110a mainly includes a payout control three-terminal filter PIC0. This payout control three-terminal filter PIC0 is a T-type filter circuit, and has excellent attenuation characteristics magnetically shielded with ferrite. The first terminal of the payout control three-terminal filter PIC0 is supplied with + 5V from the power supply board 851 shown in FIG. 18, and is electrically connected to the other end of the capacitor PC0 whose one end is grounded (GND). Then, + 5V from the power supply board 851 is first smoothed by removing the ripple (the AC component superimposed on the voltage) by the capacitor PC0. The second terminal of the payout control 3-terminal filter PIC0 is grounded to the ground (GND), and the third terminal of the payout control 3-terminal filter PIC0 outputs +5 V from which noise components have been removed.

  The third terminal of the payout control three-terminal filter PIC0 has one end connected to the ground (GND) and the other end of the capacitor PC1 and the electrolytic capacitor PC2 (capacitance: 180 microfarad (μF) in this embodiment). By being electrically connected to each other, the ripple is further removed from the +5 V output from the third terminal of the payout control three-terminal filter PIC0 and smoothed. The smoothed + 5V is applied to a power supply terminal of the payout control system reset PIC1, a VCC terminal that is a power supply terminal of the payout control crystal oscillator PX0, a VDD terminal that is a power supply terminal of the payout control MPU 4120a, and the like. . Note that the power supply terminal of the payout control MPU 4120a has a power failure or a momentary power failure, and when the power supply from the pachinko island facility is cut off, the charge charged in the electrolytic capacitor PC2 is subject to a power failure or a momentary power failure. It is applied as +5 V over a period of about 7 milliseconds (ms) after the occurrence.

  The VDD terminal of the payout control MPU 4120a is electrically connected to the other end of the capacitor PC3 whose one end is grounded (GND), and + 5V applied to the VDD terminal is smoothed by further removing ripples by the capacitor PC3. ing. The VSS terminal, which is the ground terminal of the payout control MPU 4120a, is grounded to the ground (GND).

  Further, the VDD terminal of the payout control MPU 4120a is electrically connected to the anode terminal of the diode PD0 in addition to being electrically connected to the capacitor PC3. The cathode terminal of the diode PD0 is electrically connected to the VBB terminal that is a power supply terminal of a RAM (payout control built-in RAM) built in the payout control MPU 4120a, and one end of the capacitor PC4 is grounded to the ground (GND). Is electrically connected to the other end. In addition to being electrically connected to the cathode terminal of the diode PD0 and the other end of the capacitor PC4, the VBB terminal of this payout control built-in RAM is connected to the plus of the capacitor BC1 of the power supply board 851 shown in FIG. 18 via the resistor PR0. It is electrically connected to the terminal. That is, +5 V smoothed by removing noise components by the payout control filter circuit 4110a is applied to the VDD terminal of the payout control MPU 4120a, and via the diode PD0, the VBB terminal of the payout control built-in RAM and the capacitor BC1. Are applied to the positive terminal. As a result, as described above, when + 5V generated by the + 5V power generation circuit 855db of the power generation circuit 855d in the power supply board 851 shown in FIG. 18 is not supplied to the payout control board 4110, the capacitor BC1 is charged. Since the discharged charge is supplied as the payout VBB to the payout control board 4110, the current is prevented from flowing to the VDD terminal of the payout control MPU 4120a by the diode PD0 and the payout control MPU4120a does not operate. The stored contents are held by applying the pay VBB to the VBB terminal of the built-in RAM.

[10-2. Circuit of payout control unit]
As shown in FIG. 24, the payout control unit 4120 is reset as a peripheral circuit in addition to the payout control MPU 4120a, the payout control input circuit 4120b, the payout control output circuit 4120c, the payout motor drive circuit 4120d, and the CR unit input / output circuit 4120e. The payout control system reset PIC1 that outputs a signal and the payout control crystal oscillator PX0 that outputs a clock signal (in this embodiment, 8 megahertz (MHz)) are mainly configured. Here, the payout control system reset will be described first, followed by the payout control crystal oscillator, the payout control input circuit, the payout motor drive circuit, the CR unit input / output circuit, and various input / output signals to the payout control MPU.

[10-2-1. Payment control system reset]
As shown in FIG. 24, +5 V smoothed by removing the noise component by the payout control filter circuit 4110a is applied to the power supply terminal of the payout control system reset PIC1. The payout control system reset PIC1 resets the payout control MPU 4120a and the payout control output circuit 4120ca with reset function, and has a built-in delay circuit. One end of the delay control terminal of the payout control system reset PIC1 is electrically connected to the other end of the capacitor PC5 grounded to the ground (GND), and the delay time by the delay circuit is set by the capacitance of the capacitor PC5. Be able to. Specifically, the payout control system reset PIC1 outputs a system reset signal from the output terminal after the delay time elapses when + 5V input to the power supply terminal reaches a threshold value (for example, 4.25V).

  The output terminal of the payout control system reset PIC1 is electrically connected to the SRT0 terminal, which is a reset terminal of the payout control MPU 4120a, and the reset terminal of the payout control output circuit 4120ca with reset function. The output terminal is an open collector output type, one end of which is electrically connected to the other end of the pull-up resistor PR1, which is electrically connected to the + 5V power supply line, and one end of which is grounded to the ground (GND). The other end of the PC 6 is electrically connected. The capacitor PC6 plays a role as a low-pass filter. When the voltage input to the power supply terminal is larger than the threshold value, the output terminal is pulled up to + 5V side by the pull-up resistor PR1, and the logic becomes HI. This logic is the SRT0 terminal of the payout control MPU 4120a and the payout control output with reset function. When the voltage inputted to the reset terminal of the circuit 4120ca is smaller than the threshold value, the logic becomes LOW when the voltage inputted to the power supply terminal is smaller than the threshold value. This logic is the SRT0 terminal of the payout control MPU 4120a and the payout control output circuit 4120ca with reset function Each is input to the reset terminal. Since the SRT0 terminal of the payout control MPU 4120a and the reset terminal of the payout control output circuit 4120ca with reset function are negative logic inputs, respectively, the payout control MPU 4120a and the reset function when the voltage input to the power supply terminal is smaller than the threshold value. The attached payout control output circuit 4120ca is reset. The power supply terminal is electrically connected to the other end of the capacitor PC7 whose one end is grounded (GND), and + 5V input to the power supply terminal is smoothed by removing ripples. The ground terminal is grounded with a grant (GND), and the NC terminal is not electrically connected to the outside.

[10-2-2. Dispensing control crystal oscillator]
As shown in FIG. 24, + 5V smoothed by removing the noise component by the payout control filter circuit 4110a is input to the VCC terminal which is the power supply terminal of the payout control crystal oscillator PX0. The VCC terminal is electrically connected to the other end of the capacitor PC8, one end of which is grounded (GND), and + 5V input to the VCC terminal is further smoothed by removing ripples. In addition to the VCC terminal, the smoothed + 5V is also applied to an OE terminal that is an output enable terminal of the payout control crystal oscillator PX0. The payout control crystal oscillator PX0 outputs an 8 MHz clock signal from the OUT terminal, which is an output terminal, by applying +5 V to its OE terminal.

  The OUT terminal of the payout control crystal oscillator PX0 is electrically connected to the MCLK terminal which is the clock terminal of the payout control MPU 4120a, and an 8 MHz clock signal is input to the payout control MPU 4120a. Note that the GND terminal, which is the ground terminal of the payout control crystal oscillator PX0, is grounded to the grant (GND).

[10-2-3. Dispensing control input circuit]
The payout control input circuit 4120b receives the payout power outage warning signal from the door frame open switch 618, the main body frame open switch 619, and the power outage monitoring circuit 4100e provided in the main control board 4100 shown in FIG. A circuit, a handle relay terminal plate 192 shown in FIG. 13, a circuit to which a detection signal from the full switch 550 is input via the power supply board 851, a circuit to which an operation signal from the operation switch 860a is input, and the like. First, the circuit to which the detection signal from the door frame opening switch is input will be described, then the circuit to which the detection signal from the main body frame opening switch will be input, the circuit to which the payout power failure warning signal from the power failure monitoring circuit will be input, A circuit to which a detection signal from the full switch is input and a circuit to which an operation signal from the operation switch is input will be described. Note that the full switch 550 and various detection switches such as the ball break switch 750, the counting switch 751, and the rotation angle switch 752 shown in FIG. 13 have an output terminal of an open collector output type. Since the circuit configuration to which the detection signal is input is substantially the same, here, a circuit to which the detection signal from the full switch is input will be described.

[10-2-3 (a). Circuit where detection signal from door frame opening switch is input]
The door frame opening switch 618 uses a normally closed type (normally closed (NC)), and the switch is turned on (conducted) with the door frame 5 opened from the main body frame 3 shown in FIG. The switch is turned off (cut) while 5 is closed to the main body frame 3. The second terminal of the door frame opening switch 618 is grounded to the ground (GND), while the first terminal of the door frame opening switch 618 is a pull-up resistor PR20 whose one end is electrically connected to the + 5V power line. It is electrically connected to the end and electrically connected to the base terminal of the transistor PTR20 via the resistor PR21. The base terminal of the transistor PTR20 is electrically connected to the resistor PR21, and one end thereof is electrically connected to the other end of the resistor PR22 that is grounded to the ground (GND). Further, the first terminal of the door frame opening switch 618 is electrically connected to the pull-up resistor PR20, and is also electrically connected to the other end of the capacitor PC20 that is grounded to the ground (GND). . The emitter terminal of the transistor PTR20 is grounded to the ground (GND), and the collector terminal of the transistor PTR20 is electrically connected to the other end of the resistor PR23, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Dispensing control via ICPIC 20 (non-inverted buffer ICPIC 20 includes eight non-inverted buffer circuits, and the signal waveform input to one (PIC20A) is shaped and output without being inverted). The MPU 4120a is electrically connected to the input terminal PA0 of the input port PA. When the transistor PTR20 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR20 changes, and the signal is input to the input terminal PA0 of the input port PA of the payout control MPU 4120a as a door opening signal.

  The first terminal of the door frame opening switch 618 is pulled up to the + 5V side by the pull-up resistor PR20 and is electrically connected to the base terminal of the transistor PTR20 through the resistor PR21, and the + 5V side by the pull-up resistor PR20. And is electrically connected to the base terminal of the transistor PTR21 via the resistor PR24. In addition to being electrically connected to the resistor PR24, one end of the transistor PTR21 is electrically connected to the other end of the resistor PR25 that is grounded to the ground (GND). The emitter terminal of the transistor PTR21 is grounded to the ground (GND), and the collector terminal of the transistor PTR21 is electrically connected to the external terminal plate 784 via a wiring (harness). Note that when the collector terminal of the transistor PTR21 is electrically connected to the external terminal plate 784 via a wiring (harness), one end of the external terminal plate 784 is electrically connected to the + 12V power line. It is electrically connected to the other end of the up resistor. When the transistor PTR21 is turned ON / OFF, the logic of the signal output from the collector terminal of the transistor PTR21 changes, and the signal is input to the external terminal plate 784 as the outer end frame door opening information output signal.

  Further, the first terminal of the door frame opening switch 618 is pulled up to the + 5V side by the pull-up resistor PR20 and is electrically connected to the base terminal of the transistor PTR20 through the resistor PR21, and at the + 5V side by the pull-up resistor PR20. To the base terminal of the transistor PTR21 via the resistor PR24, and to the + 5V side by the pull-up resistor PR20 and electrically connected to the base terminal of the transistor PTR22 via the resistor PR26. ing. The base terminal of the transistor PTR22 is electrically connected to the resistor PR26, and one end is electrically connected to the other end of the resistor PR27 that is grounded to the ground (GND). The emitter terminal of the transistor PTR22 is grounded to the ground (GND), and the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 shown in FIG. 12 via a wiring (harness). When the collector terminal of the transistor PTR22 is electrically connected to the main control board 4100 via wiring (harness), one end of the collector terminal of the main control input circuit 4100b of the main control board 4100 shown in FIG. The other end of a pull-up resistor (not shown) that is electrically connected to the line is electrically connected. When the transistor PTR22 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR22 changes, and the signal is input to the main control board 4100 as the main frame door opening signal.

  The circuit composed of the pull-up resistor PR20 and the capacitor PC20 is a switch signal generation circuit. When the door frame 5 is opened from the main body frame 3, or when the door frame 5 is closed by the main body frame 3, It is configured as a circuit that also has a function of absorbing voltage fluctuations from the door frame opening switch 618 due to a fluttering phenomenon in which the contacts constituting the door frame opening switch 618 are repeatedly turned on and off for a short time.

  A circuit constituted by resistors PR21 and PR22 and a transistor PTR20, a circuit constituted by resistors PR24 and PR25 and a transistor PTR21, and a circuit constituted by resistors PR26 and PR27 and a transistor PTR22 are a door frame opening switch. This is a switch circuit that is turned ON / OFF by a detection signal from 618.

  In the state where the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR20 is pulled down to the ground (GND) side, whereby the transistor PTR20 is The switch circuit is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR20 is pulled up to the + 5V side by the pull-up resistor PR23, and the door frame opening signal whose logic becomes HI is input to the input terminal PA0 of the input port PA of the payout control MPU4120a. The Further, when the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR21 is pulled down to the ground (GND) side, so that the transistor The PTR 21 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR21 is pulled up to + 12V side by the pull-up resistor of the external terminal board 784 via the wiring (harness), and the outer end frame door opening information output signal whose logic becomes HI. Is input to the external terminal board 784. Further, when the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is ON, so that the voltage applied to the base terminal of the transistor PTR22 is lowered to the ground (GND) side, thereby causing the transistor The PTR 22 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR22 is pulled up to the + 12V side by the pull-up resistor of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A door opening signal is input to the main control board 4100.

  On the other hand, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is OFF, so that the voltage applied to the base terminal of the transistor PTR20 is pulled up to the + 5V side by the pull-up resistor PR20. Thus, the transistor PTR20 is turned on and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR20 is pulled down to the ground (GND) side and the door frame opening signal whose logic is LOW is input to the input terminal PA0 of the input port PA of the payout control MPU 4120a. In addition, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is OFF, so that the voltage applied to the base terminal of the transistor PTR21 is pulled up to the + 5V side, thereby turning on the transistor PTR21. The switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR21 is pulled down to the ground (GND) side, and the outer end frame door opening information output signal whose logic is LOW is input to the external terminal plate 784. In addition, when the door frame 5 is closed from the main body frame 3, the door frame opening switch 618 is OFF, so that the voltage applied to the base terminal of the transistor PTR22 is raised to the + 5V side so that the transistor PTR22 is turned ON. The switch circuit is also turned on. As a result, the main frame door opening signal in which the voltage applied to the collector terminal of the transistor PTR22 is pulled down to the ground (GND) side and the logic becomes LOW is input to the main control board 4100.

  As described above, when the door frame 5 is opened from the main body frame 3, the door frame opening switch 618 is turned ON, so that the door frame opening signal whose logic is HI is input to the input terminal PA of the input port PA of the dispensing control MPU 4120a. While the outer frame door opening information output signal that is input to PA0 and whose logic is HI is input to the external terminal board 784, the main frame door opening signal that is logic is HI is input to the main control board 4100, When the door frame 5 is closed by the main body frame 3, the door frame opening switch 618 is turned OFF, so that the door frame opening signal whose logic is LOW is input to the input terminal PA0 of the input port PA of the dispensing control MPU 4120a. The outer frame door opening information output signal whose logic is LOW is input to the external terminal board 784, and the main frame door opening signal whose logic is LOW is input to the main control board 4100.

[10-2-3 (b). A circuit to which the detection signal from the body frame opening switch is input]
The body frame opening switch 619 uses a normally closed type (normally closed (NC)), and the switch is turned on (conducted) with the body frame 3 opened from the outer frame 2 shown in FIG. The switch is turned off (cut) while 3 is closed by the outer frame 2. The second terminal of the body frame opening switch 619 is grounded to the ground (GND), while the first terminal of the body frame opening switch 619 is connected to the other end of the pull-up resistor PR28 whose one end is electrically connected to the + 5V power supply line. It is electrically connected to the end and electrically connected to the base terminal of the transistor PTR23 via the resistor PR29. In addition to being electrically connected to the resistor PR29, one end of the transistor PTR23 is electrically connected to the other end of the resistor PR30 that is grounded to the ground (GND). In addition to being electrically connected to the pull-up resistor PR28, the first terminal of the body frame opening switch 619 is also electrically connected to the other end of the capacitor PC21 that is grounded to the ground (GND). . The emitter terminal of the transistor PTR23 is grounded to the ground (GND), the collector terminal of the transistor PTR23 is electrically connected to the collector terminal of the transistor PTR21 described above, and is connected to the external terminal plate 784 via a wiring (harness). Electrically connected. Note that when the collector terminal of the transistor PTR23 is electrically connected to the external terminal plate 784 via a wiring (harness), one end of the external terminal plate 784 is electrically connected to the + 12V power supply line (not shown). It is electrically connected to the other end of the up resistor. When the transistor PTR23 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR23 changes, and the signal is input to the external terminal plate 784 as the outer end frame door opening information output signal.

  Further, the first terminal of the body frame opening switch 619 is pulled up to the + 5V side by the pull-up resistor PR28 and is electrically connected to the base terminal of the transistor PTR23 through the resistor PR29, and the + 5V side by the pull-up resistor PR28. And is electrically connected to the base terminal of the transistor PTR24 via the resistor PR31. In addition to being electrically connected to the resistor PR31, one end of the transistor PTR24 is electrically connected to the other end of the resistor PR32 that is grounded to the ground (GND). The emitter terminal of the transistor PTR24 is grounded to the ground (GND), and the collector terminal of the transistor PTR24 is electrically connected to the collector terminal of the transistor PTR22 described above and is shown in FIG. 12 via a wiring (harness). The main control board 4100 is electrically connected. When the collector terminal of the transistor PTR24 is electrically connected to the main control board 4100 via a wiring (harness), one end of the collector terminal of the main control input circuit 4100b of the main control board 4100 shown in FIG. The other end of a pull-up resistor (not shown) that is electrically connected to the line is electrically connected. When the transistor PTR24 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR24 changes, and the signal is input to the main control board 4100 as the main frame door opening signal.

  The circuit composed of the pull-up resistor PR28 and the capacitor PC21 is a switch signal generation circuit, and when the main body frame 3 is opened from the outer frame 2 or when the main body frame 3 is closed by the outer frame 2, The contacts constituting the body frame opening switch 619 are configured as a circuit that also has a function of absorbing fluctuations in voltage from the body frame opening switch 619 due to a fluttering phenomenon in which the contacts that repeatedly turn ON / OFF repeatedly.

  A circuit composed of the resistors PR29 and PR30 and the transistor PTR23 and a circuit composed of the resistors PR31 and PR32 and the transistor PTR24 are switch circuits that are turned on / off by a detection signal from the body frame opening switch 619.

  In the state where the main body frame 3 is opened from the outer frame 2, the main body frame opening switch 619 is ON, so that the voltage applied to the base terminal of the transistor PTR23 is pulled down to the ground (GND) side, whereby the transistor PTR23 is turned on. The switch circuit is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR23 is pulled up to the + 12V side by the pull-up resistor of the external terminal board 784 via the wiring (harness), and the outer end frame door opening information output signal whose logic becomes HI. Is input to the external terminal board 784. In the state where the main body frame 3 is opened from the outer frame 2, the main body frame opening switch 619 is ON, so that the voltage applied to the base terminal of the transistor PTR 24 is lowered to the ground (GND) side, so that the transistor The PTR 24 is turned off and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR24 is pulled up to the + 12V side by the pull-up resistor of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A door opening signal is input to the main control board 4100.

  On the other hand, when the main body frame 3 is closed by the outer frame 2, the main body frame opening switch 619 is OFF, so that the voltage applied to the base terminal of the transistor PTR23 is pulled up to the + 5V side by the pull-up resistor PR28. Thus, the transistor PTR23 is turned on, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR23 is pulled down to the ground (GND) side in the external terminal board 784 via the wiring (harness), and the outer frame door opening information output signal whose logic becomes LOW is output. Input to the external terminal board 784. In the state where the main body frame 3 is closed by the outer frame 2, the main body frame opening switch 619 is OFF, so that the voltage applied to the base terminal of the transistor PTR24 is pulled up to the + 5V side by the pull-up resistor PR28. As a result, the transistor PTR24 is turned on, and the switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the transistor PTR 24 is pulled down to the ground (GND) side in the main control board 4100 via the wiring (harness), and the main frame door open signal whose logic is LOW is generated in the main control board. 4100 is input.

  As described above, when the main body frame 3 is released from the outer frame 2, the main body frame opening switch 619 is turned on so that the outer end frame door opening information output signal whose logic is HI is input to the external terminal plate 784. When the main frame door opening signal whose logic is HI is input to the main control board 4100, while the main body frame 3 is closed to the outer frame 2, the main body frame opening switch 619 is turned OFF, Is output to the external terminal board 784, and the main frame door opening signal whose logic is LOW is input to the main control board 4100.

  In the present embodiment, as described above, one or both of the state in which the door frame 5 is closed by the main body frame 3 and the state in which the main body frame 3 is opened from the outer frame 2 are used. Even in this case, since the main frame door opening signal is input to the main control board 4100, the main control MPU 4100a of the main control board 4100 shown in FIG. Although it is not possible to determine whether the door frame 5 is opened from the main body frame 3 or the main body frame 3 is opened from the outer frame 2, the door frame 5 and / or It can be determined that a state in which the player has opened the main body frame 3 does not occur during a normal game, and an outer end frame door opening information output signal is output to the external terminal board 784. This outer edge because it is designed to be entered The door opening information output signal is transmitted to the hall computer via the external terminal board 784, and the hall computer is in a state where the door frame 5 is opened from the main body frame 3 based on the outer frame door opening information output signal. Although it cannot be determined whether or not the main body frame 3 is opened from the outer frame 2, there is a state in which the player does not occur during normal games that the door frame 5 and / or the main body frame 3 are opened. It can be determined that it has occurred.

  In the present embodiment, as described above, the door frame opening switch 618 and the main body frame opening switch 619 are normally closed, so that the door frame opening switch 618 is short-circuited for some reason and the switch is turned on ( Even if the door frame 5 is opened from the main body frame 3 even if it is in a conductive state, the main body frame opening switch 619 is short-circuited for some reason and the switch is turned on (conductive). 3 is released from the outer frame 2. Thus, by adopting a normally closed switch for the door frame opening switch 618 and the main body frame opening switch 619, a main frame door opening signal can be output to the main control board 4100 even in the event of a short circuit, and the outer end The frame door opening information output signal can be transmitted to the hall computer via the external terminal board 784.

  When the door frame opening switch 618 and the body frame opening switch 619 are changed from a normally closed switch to a normally open type (normally open (NO)) switch (door frame opening switch 618 ′ and body frame opening switch 619 ′). The door frame opening switch 618 ′ is turned on (conductive) when the door frame 5 is closed from the main body frame 3, and is turned off (cut) when the door frame 5 is opened to the main body frame 3. . The body frame opening switch 619 ′ is turned on (conductive) when the body frame 3 is closed from the outer frame 2, and turned off (disconnected) when the body frame 3 is opened to the outer frame 2. Then, even if the door frame opening switch 618 ′ is disconnected due to some cause and the switch is turned off (cut), the door frame 5 is opened from the main body frame 3, and the main body is not used for some reason. Even when the frame opening switch 619 ′ is disconnected and the switch is turned off (cut), the main body frame 3 is released from the outer frame 2. As described above, even if the door frame opening switch 618 ′ and the body frame opening switch 619 ′ adopt a normally open switch, even when a disconnection occurs, the main frame door opening signal can be output to the main control board 4100, An outer end frame door opening information output signal can be transmitted to the hall computer via the external terminal board 784.

[10-2-3 (c). A circuit that receives a power outage warning signal from the power outage monitoring circuit]
A transmission line for transmitting a payout power failure notice signal from the power failure monitoring circuit 4100e provided on the main control board 4100 is electrically connected to the other end of the pull-up resistor PR40, one end of which is electrically connected to the + 12V power supply line, and a resistor. It is electrically connected to the base terminal of the transistor PTR40 via PR41. In addition to being electrically connected to the resistor PR41, one end of the transistor PTR40 is electrically connected to the other end of the resistor PR42 that is grounded to the ground (GND). The emitter terminal of the transistor PTR40 is grounded to the ground (GND), and the collector terminal of the transistor PTR40 is electrically connected to the other end of the resistor PR43, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Dispensing control via ICPIC 40 (non-inverted buffer ICPIC 40 includes eight non-inverted buffer circuits, and the signal waveform input to one (PIC 40A) is shaped and output without being inverted). The MPU 4120a is electrically connected to the input terminal PA1 of the input port PA. When the transistor PTR40 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR40 changes, and the signal is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a as a payout power failure notice signal.

  A circuit composed of the resistors PR41 and PR42 and the transistor PTR40 is a switch circuit that is turned ON / OFF by a payout power failure notice signal from a power failure monitoring circuit 4100e provided in the main control board 4100.

  As described above, the power failure monitoring circuit 4100e monitors the signs of power failure or instantaneous power failure of two types of voltages, + 12V and + 24V, from the power supply board 851, and if a power failure or power failure sign is detected, there is no reset function. A payout blackout notice signal is output to the payout control board 4110 as a blackout notice via the main control output circuit 4100cb. The power failure monitoring circuit 4100e monitors the signs of a power failure or instantaneous power failure at + 12V and + 24V voltages. As described above, the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf, and the voltage of + 12V is higher than the power failure detection voltage V2pf. When both conditions are satisfied, the voltage applied to the collector terminal of the subsequent transistor MTR22 is pulled down to the ground (GND) side in the payout control board 4110 via the wiring (harness), and the logic becomes LOW. One of a condition that the + 24V voltage is smaller than the power failure detection voltage V1pf and a condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is input to the dispensing control board 4110. When the condition is satisfied, the subsequent transistor MTR22 Payout power failure warning signal of the voltage applied to the collector terminal wiring logic by via (harness) is pulled up to + 12V side by the pull-up resistor PR40 described above it becomes HI is input to the payout control board 4110.

  When both the condition that the voltage of + 24V is larger than the power failure detection voltage V1pf and the condition that the voltage of + 12V is larger than the power failure detection voltage V2pf are satisfied, that is, there is no sign of power failure or instantaneous interruption of the voltages of + 12V and + 24V. In some cases, a payout power failure warning signal whose logic is LOW is input to the payout control board 4110, so that the voltage applied to the base terminal of the transistor PTR40 is pulled down to the ground (GND) side to turn off the transistor PTR40. The voltage applied to the collector terminal of the transistor PTR40 is pulled up to the + 5V side by the resistor PR43. As a result, a payout power failure warning signal whose logic is HI is input from the collector terminal of the transistor PTR40 to the input terminal PA1 of the input port PA of the payout control MPU 4120a.

  On the other hand, when either one of the condition that the voltage of + 24V is smaller than the power failure detection voltage V1pf and the condition that the voltage of + 12V is smaller than the power failure detection voltage V2pf is satisfied, that is, the voltage of + 12V and / or + 24V When there is an indication of a power outage or a momentary power failure, a payout power outage warning signal whose logic is HI is input to the payout control board 4110 and is applied to the base terminal of the transistor PTR 40 by a payout power outage notice signal from the power outage monitoring circuit 4100e. Is pulled up to + 12V by the pull-up resistor PR40, the transistor PTR40 is turned on, and the voltage applied to the collector terminal of the transistor PTR40 is pulled down to the ground (GND) side. As a result, a payout power failure warning signal whose logic at the collector terminal of the transistor PTR40 is LOW is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a.

  Thus, when there is an indication of a power failure or instantaneous power failure at a voltage of +12 V and / or +24 V, a payout power failure notice signal whose logic is HI is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a, When there is no sign of a power failure or a momentary power failure at voltages of +12 V and +24 V, a payout power failure notice signal whose logic is LOW is input to the input terminal PA1 of the input port PA of the payout control MPU 4120a. This is because, as described above, when there is an indication of a power failure or a momentary power failure at a voltage of + 12V and / or + 24V, a power failure warning signal whose logic is HI is input to the input terminal PA1 of the input port PA of the main control MPU 4100a. On the other hand, when there is no sign of + 12V and + 24V power failure or instantaneous power failure, a power failure warning signal is input to the input terminal PA1 of the input port PA of the main control MPU 4100a. The logic of the payout blackout signal input to the payout control MPU 4120a and the logic of the blackout notice signal input to the main control MPU4100a are the same logic.

[10-2-3 (d). Circuit that receives detection signal from full switch]
A detection signal from the full switch 550 provided in the foul cover unit 540 shown in FIG. 1 is sent to the payout control board 4110 via the handle relay terminal plate 192 shown in FIG. 1 and the power supply board 851 shown in FIG. Have been entered. The output terminal of the full switch 550 is configured as an open collector output type in which the emitter terminal is grounded to the ground (GND), and one end of the payout control board 4110 is electrically connected to the + 12V power supply line. The pull-up resistor PR44a is electrically connected to the other end of the pull-up resistor PR44a and electrically connected to the first terminal of the full-switch three-terminal filter PIC50. This full-tank switch three-terminal filter PIC50 is a T-type filter circuit, and has excellent attenuation characteristics magnetically shielded with ferrite.

  The second terminal of the full tank switch three-terminal filter PIC50 is grounded to the ground (GND), and the third terminal of the full tank switch three-terminal filter PIC50 is connected to the full tank switch three-terminal filter PIC50 via the resistor PR44b. Is electrically connected to the base terminal of the transistor PTR41 via the resistor PR45. Thereby, the detection signal of the full tank switch 550 is input to the base terminal of the transistor PTR 41 after the noise component is removed in the full terminal switch three-terminal filter PIC50. In addition to the resistor PR45 being electrically connected, the base terminal of the transistor PTR41 is electrically connected to the other end of the resistor PR46 that is grounded to the ground (GND), and has one end connected to the ground (GND). The other end of the electrically connected capacitor PC40 is electrically connected. The capacitor PC40 plays a role as a low-pass filter. The emitter terminal of the transistor PTR41 is grounded to the ground (GND), and the collector terminal of the transistor PTR41 is electrically connected to the other end of the resistor PR47, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. Payout control via ICPIC 40 (non-inverted buffer ICPIC 40 includes eight non-inverted buffer circuits, and the signal waveform input to one (PIC 40B) is shaped and output without being inverted). The MPU 4120a is electrically connected to the input terminal PA2 of the input port PA. When the transistor PTR41 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR41 changes, and the signal is input as a full signal to the input terminal PA2 of the input port PA of the payout control MPU 4120a.

  A circuit composed of the resistors PR45 and PR46 and the transistor PTR41 is a switch circuit that is turned on / off in response to a detection signal from the full switch 550.

  As described above, the full tank switch 550 detects whether or not the storage space in the second ball passage of the foul cover unit 540 is full with the stored game balls. In this embodiment, when the storage space is not full with the stored game balls, the voltage applied to the output terminal of the full switch 550 is paid out via the handle relay terminal plate 192 and the power supply board 851. When the control board 4110 is pulled up to the + 12V side by the pull-up resistor 44a and the logic becomes HI, the signal is input to the payout control board 4110, while the game ball in which the accommodation space is stored is full. The voltage applied to the output terminal of the full switch 550 is pulled down to the ground (GND) side in the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851, and a signal whose logic is LOW is sent out. Input to the control board 4110.

  When the storage space is not full of stored game balls, the voltage applied to the output terminal of the full switch 550 is pulled on the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851. When the signal that has been pulled up to + 12V by the up resistor 44a and whose logic has become HI is input to the base terminal of the transistor PTR41 described above, the transistor PTR41 is turned ON and the switch circuit is also turned ON. As a result, a full signal in which the voltage applied to the collector terminal of the transistor PTR41 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal PA2 of the input port PA of the payout control MPU 4120a.

  On the other hand, when the game ball in which the accommodation space is stored is full, the voltage applied to the output terminal of the full tank switch 550 is supplied to the payout control board 4110 via the handle relay terminal board 192 and the power supply board 851. When the signal that is pulled down to the ground (GND) side and becomes logic LOW is input to the base terminal of the transistor PTR41 described above, the transistor PTR41 is turned OFF and the switch circuit is also turned OFF. As a result, a full-tank signal whose voltage applied to the collector terminal of the transistor PTR41 is pulled up to the + 5V side by the resistor PR47 and becomes logic HI is input to the input terminal PA2 of the input port PA of the payout control MPU 4120a.

  In the present embodiment, the detection signal from the full switch 550 is input to a switch circuit constituted by the resistor PR45, the resistor PR46, and the transistor PTR41 via the full switch three-terminal filter PIC50. However, the detection signals from various detection switches such as the ball break switch 750, the counting switch 751, and the rotation angle switch 752 shown in FIG. 13 are T-type filter circuits such as a full-switch three-terminal filter PIC50. It is a circuit configuration that is directly input to each switch circuit without going through. Since the full tank switch 550 is provided in the foul cover unit 540 attached to the door frame 5, the ball break switch 750, the counting switch 751, and the rotation angle switch 752 provided in the prize ball device 740 attached to the main body frame 3. Compared to the above, the path for transmitting the detection signal is extremely long, and it is very susceptible to noise.

  The full tank switch 550 detects whether or not the storage space in the second ball passage of the foul cover unit 540 is full with the stored game balls. The payout control MPU 4120a If it is determined that the game space in which the accommodation space is stored is full, the drive control of the payout motor 744 is forcibly stopped and the payout of the game ball by the payout rotating body is stopped. To do. In other words, when noise enters a transmission path (transmission line) that transmits a detection signal from the full tank switch 550, the payout control MPU 4120a drives the payout motor 744 even though the game ball in which the accommodation space is stored is not full. In some cases, the control is forcibly stopped and the payout of the game ball by the payout rotating body is stopped, or the payout motor 744 is driven and controlled even though the storage space is full with the stored game balls. If the game ball is filled up to the upstream side of the above-mentioned prize ball passage by rotating the payout rotator and continuing to pay out the game ball, the payout rotator itself can no longer rotate and the payout motor 744 The load is abnormal, the payout motor 744 is overloaded, abnormally generates heat and breaks down, or the rotary shaft of the payout motor 744 is transmitted to the rotary motion of the payout rotating body. Sometimes referred to 構等 is or failure. Therefore, in this embodiment, in order to prevent such a problem from occurring, the circuit configuration is adopted so that the noise component is first removed from the detection signal from the full tank switch 550 in the full terminal switch three-terminal filter PIC50. .

[10-2-3 (e). Circuit that receives operation signals from operation switches]
The output terminals 1 and 2 of the operation switch 860a are connected to the ground (GND), and the output terminals 3 and 4 of the operation switch 860a are connected to the + 5V side by the pull-up resistor PR48. It is pulled up and electrically connected to the base terminal of the previous-stage transistor PTR42 via the resistor PR49. In addition to being electrically connected to the resistor PR49, one end of the base terminal of the transistor PTR42 in the previous stage is electrically connected to the other end of the resistor PR50 that is grounded to the ground (GND). The fourth terminal, which is the output terminal of the operation switch 860a, is electrically connected to the pull-up resistor PR48, and is also electrically connected to the other end of the capacitor PC41 whose one end is grounded to the ground (GND). ing. The emitter terminal of the front-stage transistor PTR42 is grounded to the ground (GND), and the collector terminal of the front-stage transistor PTR42 is electrically connected to the other end of the resistor PR51 whose one end is electrically connected to the + 5V power supply line. At the same time, it is electrically connected to the base terminal of the subsequent transistor PTR43 via the resistor PR52. In addition to being electrically connected to the resistor PR52, one end of the base terminal of the transistor PTR43 at the subsequent stage is electrically connected to the other end of the resistor PR53 that is grounded to the ground (GND). The emitter terminal of the rear-stage transistor PTR43 is grounded to the ground (GND), and the collector terminal of the rear-stage transistor PTR43 is electrically connected to the other end of the resistor PR54 whose one end is electrically connected to the + 5V power supply line. A non-inverted buffer ICPIC 40 (the non-inverted buffer ICPIC 40 includes eight non-inverted buffer circuits, and shapes and outputs the signal waveform input to one of them (PIC 40C) without inversion). Via the input terminal PA3 of the input port PA of the payout control MPU 4120a. The logic of the signal output from the collector terminal of the downstream transistor PTR43 is changed by turning ON / OFF the upstream and downstream transistors PTR42 and PTR43, and the signal changes as an RWMCLR signal to the input terminal PA3 of the input port PA of the payout control MPU 4120a. Is input.

  The third and fourth terminals, which are the output terminals of the operation switch 860a, are pulled up to the + 5V side by the pull-up resistor PR48 and are electrically connected to the base terminal of the previous transistor PTR42 via the resistor PR49. The voltage is pulled up to + 5V by the pull-up resistor PR48 and is electrically connected to the base terminal of the transistor PTR44 via the resistor PR55. In addition to being electrically connected to the resistor PR55, one end of the transistor PTR44 is electrically connected to the other end of the resistor PR56 that is grounded to the ground (GND). The emitter terminal of the transistor PTR44 is grounded to the ground (GND), and the collector terminal of the transistor PTR44 is electrically connected to the main control board 4100 via a wiring (harness). When the collector terminal of the transistor PTR 44 is electrically connected to the main control board 4100 via a wiring (harness), one end of the collector terminal of the transistor PTR 44 is + 12V in the main control input circuit 4100b of the main control board 4100 shown in FIG. It is electrically connected to the other end of pull-up resistor MR2 that is electrically connected to the power supply line. When the transistor PTR44 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR44 changes, and the signal is input as the RAM clear signal to the input terminal PA0 of the input port PA of the main control MPU 4100a.

  The circuit composed of the pull-up resistor PR48 and the capacitor PC41 is a switch signal generation circuit, and when the operation switch 860a is pressed, the contact that constitutes the operation switch 860a repeatedly turns on and off for a short time. Is configured as a circuit that also has a function of absorbing fluctuations in voltage from the operation switch 860a.

  A circuit composed of the resistors PR49 and PR50 and the transistor PTR42 is a front-stage switch circuit, and a circuit composed of the resistors PR52 and PR53 and the transistor PTR43 is a rear-stage switch circuit, and the resistors PR55 and PR56 and the transistor PTR44. Is a switch circuit that is turned ON / OFF by an operation signal from the operation switch 860a.

  As described above, the operation switch 860a is connected to the RAM (payout control built-in RAM) built in the payout control MPU 4120a of the payout control board 4110 and the main control MPU 4100a of the main control board 4100 within a predetermined period from when the power is turned on. It is operated when clearing the built-in RAM (main control built-in RAM), or when an error is reported after the power is turned on, it is operated to cancel the error. A function for clearing RAM within a predetermined period from the time and canceling an error after the power is turned on (after a period during which the function is performed as a RAM clear has elapsed, that is, after a predetermined period has elapsed since the power was turned on) And has a function. The operation signal from the operation switch 860a becomes a RAM clear signal in the function of performing a RAM clear within a predetermined period from the time of turning on the power, and after the power is turned on (after a predetermined period has elapsed since the time of turning on the power). In the function for performing error cancellation in (), an error cancellation signal is generated.

  When the operation switch 860a is not operated, the operation signal whose logic becomes HI by pulling up the third terminal and the fourth terminal, which are the output terminals of the operation switch 860a, to the + 5V side by the pull-up resistor PR48 is transmitted to the previous stage transistor. When input to the base terminal of the PTR 42, the previous stage transistor PTR 42 is turned ON, and the previous stage switch circuit is also turned ON, and is applied to the collector terminal of the previous stage transistor PTR 43, which is a voltage applied to the base of the subsequent stage transistor PTR 43. As a result, the rear-stage transistor PTR43 is turned OFF, and the rear-stage switch circuit is also turned OFF. Thereby, the voltage applied to the collector terminal of the transistor PTR43 at the subsequent stage is pulled up to the + 5V side by the resistor PR54, and the RWMCLR signal whose logic becomes HI is input to the input terminal PA3 of the input port PA of the payout control MPU 4120a. The payout control MPU 4120a performs a RAM clear for erasing information stored in the payout control built-in RAM when the logic of the RWMCLR signal input to the input terminal PA3 is HI within a predetermined period from the time when the power is turned on. If the logic of the RWMCLR signal input to the input terminal PA3 is HI after the power is turned on (after a predetermined period has elapsed since the power was turned on), the error is canceled. Judge that it is not an instruction.

  When the operation switch 860a is not operated, the operation signal in which the output terminal of the operation switch 860a is the third terminal and the fourth terminal are pulled up to the + 5V side by the pull-up resistor PR48 and the logic becomes HI is output from the transistor PTR44. The transistor PTR44 is turned on and the switch circuit is also turned on. As a result, the RAM clear signal in which the voltage applied to the collector terminal of the transistor PTR44 is pulled down to the ground (GND) side in the main control board 4100 via the wiring (harness) and the logic becomes LOW is sent to the main control board 4100. Entered. When the RAM clear signal whose logic is LOW is input within a predetermined period from when the power is turned on, the main control MPU 4100a of the main control board 4100 has the logic shown in FIG. Is input to the base terminal of the transistor MTR0, the transistor MTR0 is turned OFF and the switch circuit is also turned OFF. Thereby, the voltage applied to the collector terminal of the transistor MTR0 is pulled up to the + 5V side by the resistor MR5 and the logic clear signal HI is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. The main control MPU 4100a determines that the RAM clear signal for erasing the information stored in the main control built-in RAM is not instructed when the logic of the RAM clear signal input to the input terminal PA0 is HI.

  On the other hand, when the operation switch 860a is operated, the operation signal whose logic is LOW by pulling down the third terminal and the fourth terminal, which are output terminals of the operation switch 860a, to the ground (GND) side is the transistor in the previous stage. When input to the base terminal of the PTR 42, the previous stage transistor PTR 42 is turned OFF, and the previous stage switch circuit is also turned OFF. As a result, the subsequent transistor PTR43 is turned on and the subsequent switch circuit is also turned on. As a result, the voltage applied to the collector terminal of the subsequent transistor PTR43 is pulled down to the ground (GND) side, and the RWMCLR signal whose logic is LOW is input to the input terminal PA3 of the input port PA of the payout control MPU 4120a. The payout control MPU 4120a performs a RAM clear for erasing information stored in the payout control built-in RAM when the logic of the RWMCLR signal input to the input terminal PA3 is LOW within a predetermined period from when the power is turned on. If the logic of the RWMCLR signal input to the input terminal PA3 is LOW after the power is turned on (after a predetermined period has elapsed since the power was turned on), the error is canceled. Judge that it is an instruction.

  In addition, when the operation switch 860a is being operated, an operation in which the logic becomes LOW because the third and fourth terminals, which are output terminals of the operation switch 860a, are pulled down to the ground (GND) side by the pull-up resistor PR48. A signal is input to the base terminal of the transistor PTR44, the transistor PTR44 is turned OFF, and the switch circuit is also turned OFF. As a result, the voltage applied to the collector terminal of the transistor PTR44 is pulled up to the + 12V side by the pull-up resistor MR2 of the main control input circuit 4100b of the main control board 4100 via the wiring (harness), and the logic becomes HI. A clear signal is input to the main control board 4100. When the RAM clear signal whose logic is HI is input within a predetermined period from when the power is turned on, the main control MPU 4100a of the main control board 4100 has the logic shown in FIG. When the RAM clear signal is input to the base terminal of the transistor MTR0, the transistor MTR0 is turned on and the switch circuit is also turned on. As a result, the RAM clear signal in which the voltage applied to the collector terminal of the transistor MTR0 is pulled down to the ground (GND) side and the logic becomes LOW is input to the input terminal PA0 of the input port PA of the main control MPU 4100a. When the logic of the RAM clear signal input to the input terminal PA0 is LOW, the main control MPU 4100a determines that the instruction is to instruct RAM clear to erase information stored in the main control built-in RAM.

[10-2-4. Dispensing motor drive circuit]
Next, a payout motor drive circuit 4120d for outputting a drive signal to the payout motor 744 of the prize ball device 740 shown in FIG. 5 will be described. As shown in FIG. 27, the payout motor drive circuit 4120d mainly includes a voltage switching circuit 4120da and a drive ICPIC 60. The power input terminals 1 and 2 of the voltage switching circuit 4120da are electrically connected to the + 12V power supply line and the + 5V power supply line, respectively, and +12 and + 5V are applied thereto, respectively. The ground terminal of the voltage switching circuit 4120da is the ground (GND). Grounded. A voltage switching signal is input to the power source switching input terminal of the voltage switching circuit 4120da. This voltage switching signal is output from the output terminal of the predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120ca with reset function, and is output from the payout control output circuit 4120ca with reset function to the power supply switching input terminal of the voltage switch circuit 4120da. It has come to be. The power output terminal of the voltage switching circuit 4120da is electrically connected to the third terminal and the tenth terminal, which are the cathode terminals of the drive ICPIC 60, via the Zener diode PZD60, and electrically connected to the power supply terminal of the payout motor 744. Based on the voltage switching signal input to the voltage switching input terminal of the voltage switching circuit 4120da, + 12V or + 5V is used as the motor driving voltage, and the third terminal which is the cathode terminal of the drive ICPIC60 through the Zener diode PZD60 The power is supplied to the terminal and the 10th terminal, and supplied to the dispensing motor 744.

  The drive ICPIC 60 includes four Darlington power transistors. In the present embodiment, the sixth terminal and the seventh terminal, which are the emitter terminals of the drive ICPIC 60, are grounded to the ground (GND), respectively, and are the base terminals of the drive ICPIC 60. The payout motor drive signal is input to the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal through the resistors PR60 to PR63, respectively. The second terminal, the fourth terminal, the ninth terminal, and the eleventh terminal that are the collector terminals of the drive ICPIC 60 are the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal that are the base terminals of the drive ICPIC 60, respectively. If the payout motor drive signal is input to the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal of the drive ICPIC 60 through the resistors PR60 to PR63, respectively, A certain drive pulse is output to each phase (/ B phase, B phase, A phase, / A phase) corresponding to the dispensing motor 744. This payout motor drive signal is output from the output terminal of a predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120ca with reset function, and from the payout control output circuit 4120ca with reset function via the resistors PR60 to PR63, the drive ICPIC60. The signal is output to the first terminal, the fifth terminal, the eighth terminal, and the twelfth terminal, which are base terminals. These drive pulses are generated by switching excitation currents that flow through the phases (/ B phase, B phase, A phase, / A phase) of the dispensing motor 744, and rotate the dispensing motor 744. Note that a back electromotive force is generated when the drive pulse (excitation signal) of each phase (/ B phase, B phase, A phase, / A phase) is cut off by this switching. When this back electromotive force exceeds the withstand voltage of the drive ICPIC 60, the drive ICPIC 60 is damaged. As a protection, the above-described Zener diode PZD0 is electrically connected to the third terminal and the tenth terminal before the drive ICPIC 60. The circuit configuration is adopted.

[10-2-5. CR unit input / output circuit]
Next, a CR unit input / output circuit 4120e for inputting / outputting various signals to / from the CR unit 6 shown in FIG. 14 will be described. As described above, the payout control board 4110 receives the ball rental request signal BRDY and one payout operation start request signal BRQ from the CR unit 6 via the game ball rental device connection terminal plate 869. , And a predetermined voltage VL (+12 V) and a ground LG created from the AC24V supplied from the power supply board 851 shown in FIG. 14 are supplied, while the payout control board 4110 is connected to a lending device such as a game ball. Via the terminal board 869, an EXS signal that indicates that one payout operation has been started or ended, and a PRDY signal that indicates that a payout operation for paying out a rental ball is possible or impossible. And are output. As shown in FIG. 28, the input / output circuit for inputting / outputting these various signals mainly includes photocouplers PIC70 to PIC74 (infrared LEDs and phototransistors are incorporated).

  The predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70 via the resistor PR70. The cathode terminal of the photocoupler PIC 70 is electrically connected to the ground LG from the CR unit 6. The resistor PR60 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC70. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on, while the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70. In some cases, the photocoupler PIC 70 is turned off. The emitter terminal of the photocoupler PIC70 is grounded to the ground (GND), and the collector terminal of the photocoupler PIC70 is electrically connected to the base terminal of the transistor PTR70 via the resistor PR71, and the transistor via the resistor PR72. It is electrically connected to the base terminal of the PTR 71. In addition to being electrically connected to the resistor PR71, the collector terminal of the photocoupler PIC70 is electrically connected to the other end of the pull-up resistor PR73 that is electrically connected to the + 5V power supply line.

  In addition to being electrically connected to the resistor PR71, the base terminal of the transistor PTR70 is electrically connected to the other end of the resistor PR74 that is grounded to the ground (GND). The emitter terminal of the transistor PTR70 is grounded to the ground (GND), and the collector terminal of the transistor PTR70 is electrically connected to the other end of the resistor PR75, one end of which is electrically connected to the + 5V power supply line, and a non-inverting buffer. 24, the ICPIC 80 (the non-inverted buffer ICPIC 80 includes eight non-inverted buffer circuits and shapes and outputs the signal waveform input to one of the non-inverted buffers (PIC 80A) without inversion). Are electrically connected to an input terminal of a predetermined input port of the payout control MPU 4120a shown in FIG. When the transistor PTR 70 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR 70 changes, and the signal is input as the CR connection signal 1 to the input terminal of the predetermined input port of the payout control MPU 4120a.

  On the other hand, the base terminal of the transistor PTR71 is electrically connected to the resistor PR72 and one end is electrically connected to the other end of the resistor PR76 that is grounded to the ground (GND). The emitter terminal of the transistor PTR71 is grounded to the ground (GND), and the collector terminal of the transistor PTR71 is electrically connected to the power supply substrate 851 via a wiring (harness). Note that when the collector terminal of the transistor PTR71 is electrically connected to the power supply substrate 851 via a wiring (harness), one end of the collector terminal of the power supply substrate 851 is electrically connected to the + 12V power supply line (not shown). Is electrically connected to the other end. When the transistor PTR71 is turned on / off, the logic of the signal output from the collector terminal of the transistor PTR71 changes, and the signal is input to the power supply board 851 as a CR connection signal.

  A circuit composed of the resistors PR71 and PR74 and the transistor PTR70 is a switch circuit that is turned on / off by turning on / off the photocoupler PIC70.

  When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off, and the transistor PTR70 is turned on by being pulled up to the + 5V side by the pull-up resistor PR73, and the switch circuit is also turned on. It will be turned on. As a result, the voltage applied to the collector terminal of the transistor PTR 70 is pulled down to the ground (GND) side, and the CR connection signal 1 whose logic becomes LOW is input to the input terminal of the predetermined input port of the payout control MPU 4120a.

  On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on, and the voltage applied to the base terminal of the transistor PTR70 is pulled down to the ground (GND) side. As a result, the transistor PTR 70 is turned OFF, and the switch circuit is also turned OFF. As a result, the voltage applied to the collector terminal of the transistor PTR70 is pulled up to the + 5V side by the pull-up resistor PTR75, and the CR connection signal 1 whose logic becomes HI is input to the input terminal of the predetermined input port of the payout control MPU4120a. The

  The circuit composed of the resistors PR72 and PR76 and the transistor PTR71 is also a switch circuit that is turned on / off by turning on / off the photocoupler PIC70.

  When the predetermined voltage VL from the CR unit 6 is not applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned off and pulled up to the + 5V side by the pull-up resistor PR73, thereby turning on the transistor PTR71 and the switch circuit also It will be turned on. As a result, the CR connection signal in which the voltage applied to the collector terminal of the transistor PTR71 is pulled down to the ground (GND) side in the power supply board 851 via the wiring (harness) and the logic becomes LOW is input to the power supply board 851. The

  On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC70, the photocoupler PIC70 is turned on, and the voltage applied to the base terminal of the transistor PTR71 is pulled down to the ground (GND) side. As a result, the transistor PTR 71 is turned off, and the switch circuit is also turned off. As a result, the voltage applied to the collector terminal of the transistor PTR71 is pulled up to + 12V side by the pull-up resistor of the power supply board 851 via the wiring (harness), and the CR connection signal whose logic becomes HI is input to the power supply board 851. Is done.

  The predetermined voltage VL from the CR unit 6 is applied not only to the anode terminal of the photocoupler PIC70 but also to the anode terminal of the photocoupler PIC71 via the resistor PR77. The BRDY from the CR unit 6 is input to the cathode terminal of the photocoupler PIC71. The resistor PR77 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC71. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the BRDY logic from the CR unit 6 is LOW, the photocoupler PIC71 is turned on, while the photocoupler PIC71 is turned on. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC71 and the BRDY logic from the CR unit 6 is HI, the photocoupler PIC71 is turned off. Yes. The emitter terminal of the photocoupler PIC71 is grounded to the ground (GND), and the collector terminal of the photocoupler PIC71 is electrically connected to the other end of the pull-up resistor PR78 whose one end is electrically connected to the + 5V power supply line. A non-inverted buffer ICPIC 80 (the non-inverted buffer ICPIC 80 includes eight non-inverted buffer circuits, and shapes and outputs the signal waveform input to one of them (PIC 80B) without inverting it). To the input terminal of a predetermined input port of the payout control MPU 4120a. When the photocoupler PIC71 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC71 changes, and the signal is input as a BRDY signal to the input terminal of a predetermined input port of the payout control MPU 4120a.

  When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the BRDY logic from the CR unit 6 is LOW, the photocoupler PIC71 is turned on. The BRDY signal whose logic is set to LOW when the voltage applied to the collector terminal of the coupler PIC71 is pulled down to the ground (GND) side is input to the input terminal of a predetermined input port of the payout control MPU 4120a. On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC71 and the BRDY logic from the CR unit 6 is HI, the photocoupler PIC71 is turned off. Then, the BRDY signal whose logic applied to HI is pulled up to the + 5V side by the pull-up resistor PR78 and the voltage applied to the collector terminal of the photocoupler PIC71 is input to the input terminal of the predetermined input port of the payout control MPU 4120a. Thus, the logic of the BRDY signal output from the collector terminal of the photocoupler PIC 71 is the same as the logic of BRDY from the CR unit 6.

  The predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 via the resistor PR79 in addition to the anode terminal of the photocoupler PIC70 and the anode terminal of the photocoupler PIC71. The BRQ from the CR unit 6 is input to the cathode terminal of the photocoupler PIC72. The resistor PR79 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC72. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the BRQ logic from the CR unit 6 is LOW, the photocoupler PIC72 is turned on, while the photocoupler PIC72 is turned on. When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the coupler PIC 72 and the BRQ logic from the CR unit 6 is HI, the photo coupler PIC 72 is turned off. Yes. The emitter terminal of the photocoupler PIC72 is grounded to the ground (GND), and the collector terminal of the photocoupler PIC72 is electrically connected to the other end of the pull-up resistor PR80 whose one end is electrically connected to the + 5V power supply line. A non-inverted buffer ICPIC 80 (the non-inverted buffer ICPIC 80 includes eight non-inverted buffer circuits, and shapes and outputs the signal waveform input to one of them (PIC 80C) without inverting it). To the input terminal of a predetermined input port of the payout control MPU 4120a. When the photocoupler PIC72 is turned on / off, the logic of the signal output from the collector terminal of the photocoupler PIC72 changes, and the signal is input as a BRQ signal to the input terminal of a predetermined input port of the payout control MPU 4120a.

  When the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and when the BRQ logic from the CR unit 6 is LOW, the photocoupler PIC72 is turned on. A BRQ signal whose logic is LOW when the voltage applied to the collector terminal of the coupler PIC 72 is pulled down to the ground (GND) side is input to the input terminal of a predetermined input port of the payout control MPU 4120a. On the other hand, when the predetermined voltage VL from the CR unit 6 is applied to the anode terminal of the photocoupler PIC72 and the BRQ logic from the CR unit 6 is HI, the photocoupler PIC72 is turned off. The voltage applied to the collector terminal of the photocoupler PIC72 is pulled up to the + 5V side by the pull-up resistor PR80, and the BRQ signal whose logic becomes HI is input to the input terminal of the predetermined input port of the payout control MPU4120a. Thus, the logic of the BRQ signal output from the collector terminal of the photocoupler PIC 72 is the same as the logic of the BRQ from the CR unit 6.

  An EXS signal notifying that the one-time payout operation is started or ended from the output terminal of the predetermined output port of the payout control MPU 4120a is output to the payout control output circuit 4120cb without reset function, and the payout control output circuit without reset function 4120cb is input to the cathode terminal of the photocoupler PIC73 via the resistor PR81. One end of the anode terminal of the photocoupler PIC73 is electrically connected to the other end of the resistor PR82 that is electrically connected to the + 12V power supply line. The resistor PR82 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC73. EXS output when + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82 and output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. When the logic of the signal is LOW, the photocoupler PIC73 is turned on, while + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, and a predetermined output port of the payout control MPU 4120a. The photocoupler PIC 73 is turned OFF when the logic of the EXS signal output from the output terminal via the non-reset payout control output circuit 4120cb is HI. The emitter terminal of the photocoupler PIC73 is grounded to the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC73 is connected to the inside of the CR unit 6 via the pull-up resistor PR83 via the game ball lending device connection terminal plate 869. The voltage is raised to a predetermined voltage VL and electrically connected to the built-in control device. When the photocoupler PIC73 is turned ON / OFF, the logic of the signal output from the collector terminal of the photocoupler PIC73 changes, and the signal is input as EXS to the built-in control device of the CR unit 6.

  EXS output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function when + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82. When the logic of the signal is LOW, the photocoupler PIC73 is turned ON, so that the voltage applied to the collector terminal of the photocoupler PIC73 is pulled down to the ground (GND) side, and EXS in which the logic becomes LOW is the CR unit. 6 built-in control device. On the other hand, when + 12V is applied to the anode terminal of the photocoupler PIC73 via the resistor PR82, the output is output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. When the logic of the EXS signal is HI, the photocoupler PIC73 is turned OFF, so that the voltage applied to the collector terminal of the photocoupler PIC73 is pulled up to the predetermined voltage VL by the pull-up resistor PR83, and the logic becomes HI. EXS is input to the built-in control device of the CR unit 6. Thus, the logic of the EXS output from the collector terminal of the photocoupler PIC73 is the logic of the EXS signal output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without a reset function. It has the same logic.

  The PRDY signal that indicates that the payout operation for paying out the rented ball from the output terminal of the predetermined output port of the payout control MPU 4120a is possible or impossible is a cathode terminal of the photocoupler PIC74 via the resistor PR84. Has been entered. One end of the anode terminal of the photocoupler PIC74 is electrically connected to the other end of the resistor PR85 that is electrically connected to the + 12V power supply line. The resistor PR85 is a limiting resistor for limiting the current flowing through the built-in infrared LED of the photocoupler PIC74. PRDY output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85. When the logic of the signal is LOW, the photocoupler PIC74 is turned on, and when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, the predetermined output port of the payout control MPU4120a When the logic of the PRDY signal output from the output terminal via the payout control output circuit 4120cb without reset function is HI, the photocoupler PIC74 is turned OFF. The emitter terminal of the photocoupler PIC74 is grounded to the ground LG from the CR unit 6, and the collector terminal of the photocoupler PIC74 is connected to the inside of the CR unit 6 by a pull-up resistor PR86 via a game ball lending device connection terminal plate 869. The voltage is raised to a predetermined voltage VL and electrically connected to the built-in control device. When the photocoupler PIC74 is turned on / off, the logic of the signal output from the collector terminal of the photocoupler PIC74 changes, and the signal is input as PRDY to the built-in control device of the CR unit 6.

  PRDY output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85. When the signal logic is LOW, the photocoupler PIC74 is turned on. Therefore, the voltage applied to the collector terminal of the photocoupler PIC74 is pulled down to the ground (GND) side, and the PRDY whose logic is LOW is the CR unit. 6 built-in control device. On the other hand, when + 12V is applied to the anode terminal of the photocoupler PIC74 via the resistor PR85, it is output from the output terminal of a predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. When the logic of the PRDY signal is HI, the photocoupler PIC74 is turned OFF, so that the voltage applied to the collector terminal of the photocoupler PIC74 is pulled up to the predetermined voltage VL by the pull-up resistor PR86, and the logic becomes HI. The PRDY is input to the built-in control device of the CR unit 6. Thus, the logic of PRDY output from the collector terminal of the photocoupler PIC74 is the logic of the PRDY signal output from the output terminal of the predetermined output port of the payout control MPU 4120a via the payout control output circuit 4120cb without reset function. It has the same logic.

[10-2-6. Various input / output signals to payout control MPU]
Next, various input / output signals input / output from the input / output terminals of the various input / output ports of the payout control MPU 4120a will be described.

  The RXD terminal, which is the serial data input terminal of the serial input port of the payout control MPU 4120a, receives serial data from the main control board 4100 as a main pay serial data reception signal via the payout control input circuit 4120b as shown in FIG. Is done. On the other hand, from the TXD terminal which is the serial data output terminal of the serial output port of the payout control MPU 4120a, serial data to be sent to the main control board 4100 is sent as a payer serial data transmission signal to the payout control output circuit 4120cb without reset function. A payer serial data transmission signal is transmitted from the payout control output circuit 4120cb having no reset function to the main control board 4100.

  Each input terminal of the predetermined input port of the payout control MPU 4120a has the above-described RWMCLR signal, payout blackout signal, door open signal, full signal, various signals from the CR unit 6 (BRQ signal, BRDY signal, CR connection) For example, a main pay ACK signal from the main control board 4100 that informs the completion of normal reception of the payer serial data reception signal is sent via the payout control input circuit 4120b. The detection signals from the ball break switch 750, the count switch 751, the rotation angle switch 752, and the like shown in FIG. 13 are input via the payout control input circuit 4120b, and the potentiometer shown in FIG. An operation signal from the meter 512, the touch switch 516, the firing stop switch 518 shown in FIG. Detection signal is power supply board 851 from Tan switch 550 etc., and the like or are input via the payout control input circuit 4120b payout control board 4100.

  On the other hand, the EXS signal and the PRDY signal described above are output from the output terminals of the predetermined output port of the payout control MPU 4120a to the payout control output circuit 4120cb without reset function, respectively, and the EXS signal from the payout control output circuit 4120cb without reset function and The PRDY signal is output to the CR unit input / output circuit 4120e, or the voltage switching signal described above is output to the payout control output circuit 4120ca with reset function, and the voltage switching signal is output from the payout control output circuit 4120ca with reset function to the voltage switching circuit 4120da. Or outputs a payout motor drive signal to the payout control output circuit 4120ca with reset function, and outputs a payout motor drive signal from the payout control output circuit 4120ca with reset function to the payout motor 744 via the payout motor drive circuit 4120d. In addition, for example, a payer ACK signal for notifying completion of normal reception of the main payment serial data reception signal described above is output to the payout control output circuit 4120ca with reset function, and the payout control output circuit 4120ca with reset function pays off. The main ACK signal is output to the main control board 4100, or the drive signal of the error LED display 860b shown in FIG. 13 is output to the payout control output circuit 4120ca with reset function to drive the drive signal from the payout control output circuit 4120ca with reset function. Is output to the error LED display 860b, or a control signal for adjusting the drive current to the firing solenoid drive circuit 858 shown in FIG. 13 is output to the payout control output circuit 4120ca with a reset function to output a payout control output circuit with a reset function. Outputs drive current from 4120ca to firing solenoid 654 Or a control signal for adjusting the drive current to the ball feed solenoid drive circuit 859 shown in FIG. 13 is output to the payout control output circuit 4120ca with reset function, and the drive current is sent from the payout control output circuit 4120ca with reset function to the ball feed solenoid. Output to 585 or the like.

[10-3. Various input / output signals with the main control board and various output signals to the external terminal board]
Next, various input / output signals between the payout control board 4110 and the main control board 4100 and various output signals from the payout control board 4110 to the external terminal board 784 will be described with reference to FIG.

[10-3-1. Various input / output signals with the main control board]
The payout control board 4110 exchanges various input / output signals with the main control board 4100. Specifically, as shown in FIG. 29A, the payout control board 4110 has the above-described payer serial data transmission signal, payer ACK signal, operation signal (RAM clear signal), main frame door open signal, and the like. Is output to the main control board 4100. These output signals are pulled up to + 12V by the pull-up resistor of the main control input circuit 4100b of the main control board 4100.

  On the other hand, in addition to the main payment serial data reception signal, the main payment ACK signal, and the operation signal (RAM clear signal), the payout control board 4110 has a 15 round big hit information output signal, a two round big hit information output signal, etc. Jackpot information output signal, probabilistic fluctuation information output signal, special symbol display information output signal, normal symbol display information output signal, short and middle information output signal, start opening prize information output signal, etc. A signal or the like is input from the main control board 4100. These input signals are pulled up to the + 12V side by the pull-up resistor of the payout control input circuit 4120b of the payout control unit 4120 of the payout control board 4110.

[10-3-2. Various output signals to external terminal board]
The payout control board 4110 outputs various signals to the external terminal board 784. Specifically, as shown in FIG. 29 (b), in addition to the outer frame door opening information output signal described above, the number of game balls actually paid out by the payout motor 744 as prize balls reaches 10 balls. Winning ball number information output signal output every time, 15 round jackpot information output signal and 2 round jackpot information output signal via main control board 4100 through payout control board 4110, information output during probability variation A game information signal such as a signal, a special symbol display information output signal, a normal symbol display information output signal, a short time information output signal, and a start opening prize information output signal is output to the external terminal board 784. These output signals are pulled up to the + 12V side by the pull-up resistor of the external terminal board 784.

  In addition to the various signals described above being input to the external terminal board 784, as shown in FIG. 29B, the main prize-ball number information output signal and the power-saving mode information output signal from the peripheral control board 4140 Is entered. The main prize-ball number information output signal will be briefly described. The main control board 4100 includes an upper start opening 2101, a lower start opening 2102, general winning openings 2104, 2201, and the like shown in FIG. The number of game balls to be paid out as a prize ball based on the game balls entered in various winning openings such as the big prize opening 2103 is set to a predetermined number (10 in this embodiment). ), A main prize ball number information output command, which will be described later, is transmitted to the peripheral control board 4140. The peripheral control board 4140, based on the received main prize ball number information output command, Based on the game balls that have entered the various winning ports such as the upper starting port 2101, the lower starting port 2102, the general winning port 2104, 2201, and the big winning port 2103, etc. Each time the number of game balls reaches a predetermined number of balls (in this embodiment, 10 is set), the main prize ball number information output signal is sent to the external terminal as the main prize ball number information. The data is output to the board 784 and transmitted to the hall computer. The main prize ball number information output signal is pulled up to the + 12V side by the pull-up resistor of the external terminal board 784.

  Next, the power saving mode information output signal will be briefly described. The peripheral control board 4140 is based on the power consumption status history information stored and held in the power consumption status history RAM 4150f shown in FIG. The status of the transition to power saving mode at the time of power recovery that suppresses the power consumed by the pachinko gaming machine 1 by grasping the power status consumed by the pachinko gaming machine 1 at the time of power recovery when the power is turned off (immediately before the power is turned off) This is transmitted to the hall computer via the terminal board 784. Specifically, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. 15 performs power saving power recovery mode transition determination processing in the power-on processing of the peripheral control unit described later that is executed at the time of power recovery. Based on the power consumption status history information stored and held in the consumption status history RAM 4150f, the power status consumed by the pachinko gaming machine 1 when the power is turned off (immediately before the power is turned off) (the power consumption suppression stage described later) is specified. It is determined whether or not to enter the power saving mode during power recovery. The peripheral control MPU 4150a outputs a power saving mode information output signal to the external terminal board 784 as power saving mode information and notifies the hall computer when the determination result does not shift to the power saving mode at the time of power recovery. When shifting to the power saving mode at the time of power recovery, a power saving mode information output signal is output to the external terminal board 784 as power saving mode information to inform the hall computer. This power saving mode information output signal is pulled up to + 12V by the pull-up resistor of the external terminal board 784.

  That is, the external terminal board 784 outputs two signals, that is, an outer end frame door opening information output signal from the payout control board 4110 side and a prize ball number information output signal, and a 15 round big hit from the main control board 4100 side. There are seven signals: an information output signal, a 2-round jackpot information output signal, a probability changing information output signal, a special symbol display information output signal, a normal symbol display information output signal, a short time medium information output signal, and a start opening prize information output signal. Two signals, that is, a main prize ball number information output signal and a power saving mode information output signal from the peripheral control board 4140 side are output through (passing through) the payout control board 4110.

  A signal output from the external terminal board 784 is transmitted to a hall computer installed in a game hall (hall) (not shown), and the hall computer monitors a player's game and the like. When the 15 round jackpot information output signal or the 2 round jackpot information output signal is output to the hall computer as one jackpot information output signal, the hall computer counts the number of jackpots (two round jackpots). And the number of jackpots with 15 rounds (number of jackpots for 15 rounds) is the sum of the number of jackpots of the pachinko gaming machine 1. For this reason, since the hall computer cannot grasp the number of occurrences of 2 rounds of big hits and the number of occurrences of 15 land big hits from the total number of big hits, the number of big hits actually generated in the pachinko gaming machine 1 is large. However, it is not possible to grasp whether it is a big hit of 2 rounds or a big hit of 15 rounds. In addition, a data counter (not shown) is arranged above the pachinko gaming machine 1, and a player determines whether or not to play a game with reference to the number of occurrences of the big hit gaming state displayed on the data counter. Some people choose.

  However, the number of occurrences of the jackpot gaming state displayed in the data counter may actually be biased to the number of occurrences of two rounds of big hits, so even if the player starts the game, only two rounds of big hits will occur. 15 round hits may not occur easily. As described above, the number of occurrences of the jackpot gaming state displayed on the data counter can give the player a sense of expectation, but may cause the player to be more eager than necessary.

  Therefore, in the present embodiment, as the jackpot information output signal, the 15 round jackpot information output signal and the two round jackpot information output signal are separately output to the hall computer, so that the hall computer can generate the number of occurrences of the two round jackpot, The number of occurrences of 15 round big hits can be accurately grasped. Therefore, the hall computer can grasp whether the number of big hits actually generated in the pachinko gaming machine 1 is a big hit of two rounds or a big hit of 15 rounds. Since the number of occurrences of big hits for rounds and the number of occurrences of big hits for two rounds can be displayed separately or only the number of occurrences of big hits for 15 rounds can be displayed as the number of occurrences of big hit gaming status, Nor.

  In the present embodiment, the 2-round jackpot information output signal is output to the hall computer in the period from when the 2-round jackpot is generated until it is finished, and the 15-round jackpot information output signal is also a 15-round jackpot. It is in a state of being output to the hall computer during the period from occurrence to termination. In addition to the method of outputting the 2-round jackpot information output signal and the 15-round jackpot information output signal to the hall computer as in the present embodiment, for example, when a 2-round jackpot occurs, the 2-round jackpot information output signal is output only for a predetermined period. When the 15 round jackpot is generated and the 15 round jackpot information output signal is output to the hall computer for a predetermined period when the 15 round jackpot occurs, such a 2 round jackpot information output signal and 15 round jackpot information are output. A method of outputting the output signal to the hall computer for the same predetermined period can also be mentioned.

[11. Output terminal arrangement of external terminal board]
Next, the arrangement of the output terminals of the external terminal board 784 that outputs various signals to the hall computer installed in the game hall (hall) will be described with reference to FIG. The external terminal plate 784 is attached to the rear surface of the prize ball base 710 attached to the rear surface of the main body frame base 600 shown in FIG. 3, and the rear side is covered with the external terminal plate cover 786. FIG. 30 is a diagram showing an arrangement of output terminals of the external terminal board.

  As described above, the external terminal board 784 includes an outer frame door opening information output signal, a prize ball number information output signal, a 15-round jackpot information output signal and a 2-round jackpot information output signal, and a probability varying signal. An information output signal, a special symbol display information output signal, a normal symbol display information output signal, a short time medium information output signal, and a start opening prize information output signal are input from the payout control board 4110, and a main prize ball number information output signal, The power saving mode information output signal is input from the peripheral control board 4140, and these various signals are output to the outside of the pachinko gaming machine 1. The hall computer is electrically connected to the external terminal board 784 so that a signal larger than the minimum detection signal width (for example, a signal width of 60 ms) can be detected as various signals from the external terminal board 784. It has become.

  Briefly explaining these various signals, the outer end frame door opening information output signal is not generated during a normal game by a player that the door frame 5 and / or the main body frame 3 shown in FIG. 1 is opened. The signal indicating that a state has occurred. The prize ball number information output signal is displayed every time the number of game balls actually paid out by the payout motor 744 shown in FIG. 5 reaches 10 balls. The main winning ball number information output signal is input to various winning ports such as the upper starting port 2101, the lower starting port 2102, the general winning port 2104, 2201, and the large winning port 2103 shown in FIG. This is a signal to notify that every time the number of game balls scheduled to be paid out as award balls reaches 10 based on the game balls that have been struck, the power saving mode information output signal is when power is turned off (immediately before power is turned off) Consumed in pachinko machine 1 It is a signal that tells the state of power that has been lost at the time of power recovery and reports the state of transition to the power saving mode during power recovery that suppresses the power consumed by the pachinko machine 1. A signal indicating that a two-round jackpot has been generated, a signal indicating that a two-round jackpot has been generated, and an information output signal during probability variation being a probability variation The special symbol display information output signal is transmitted through the upper special symbol display 1185 and the lower special symbol display 1186 of the function display board 1191 shown in FIG. The signal indicating that the variable display is finished (stopped), and the normal symbol display information output signal is the normal symbol display 11 of the function display board 1191 shown in FIG. 9 is a signal indicating that the normal symbol variation display has been completed (stopped), and the time-short-time information output signal is a signal indicating that a time-short state has occurred, and the start opening prize information output signal Is a signal that informs each time a game ball enters the upper start opening 2101 or the lower start opening 2102 shown in FIG.

  On the external terminal plate 784, as shown in FIG. 30, output terminals PT1 to PT11 are arranged horizontally in a row. The output terminal PT1 is provided in white and outputs an award ball number information output signal. As described above, the award ball number information output signal is a signal to notify that every time the number of game balls actually paid out as award ball by the payout motor 744 shown in FIG. In the embodiment, the output terminal PT1 is set to 0.106 seconds (in this embodiment, 2 ms is set as an interrupt cycle when a payout control unit timer interrupt process described later is performed, so an output period of 0.106 seconds (that is, The signal width of the award ball number information output signal output from the output terminal PT1) is output during a period in which the payout control unit timer interrupt process is repeated 53 times) based on an interrupt period of 2 ms). ing. When the prize ball number information output signal from the external terminal board 784 is input to the hall computer, the hall computer outputs the prize motor 744 of the pachinko gaming machine 1 as a prize ball every time the prize ball number information output signal is input. It is possible to grasp that 10 game balls have been paid out as prize balls, and to count the number of game balls that have been paid out and to grasp the total number of game balls paid out by the pachinko gaming machine 1 it can.

  The output terminal PT2 is provided in green and outputs an outer end frame door opening information output signal. As described above, the outer end frame door opening information output signal has a state in which the player does not generate a normal game when the door frame 5 and / or the main body frame 3 shown in FIG. 1 is opened. In this embodiment, the signal is output while the door frame 5 and / or the main body frame 3 are opened from the output terminal PT2. When the outer end frame door opening information output signal from the external terminal board 784 is input to the hall computer, the hall computer outputs the door frame 5 of the pachinko gaming machine 1 while the outer end frame door opening information output signal is input. And / or it can grasp | ascertain that the main body frame 3 is open | released.

  The output terminal PT3 is provided in gray and outputs a special symbol display information output signal. As described above, the special symbol display information output signal is displayed in a state where the special symbol variation display is ended (stopped) by the upper special symbol display 1185 or the lower special symbol display 1186 shown in FIG. In this embodiment, the signal is 0.128 at the time of termination (stop) of the special symbol variation display on the function display board 1191 from the output terminal PT3 on the upper special symbol display 1185 or the lower special symbol display 1186. It is output for 2 seconds. When the special symbol display information output signal from the external terminal board 784 is input to the hall computer, the hall computer receives the special symbol display information output signal, and then the upper special symbol on the function display board 1191 of the pachinko gaming machine 1. The display 1185 and the lower special symbol display 1186 can grasp that the variation display of the special symbol has ended (stopped), and the upper special symbol of the function display board 1191 of the pachinko gaming machine 1 is counted by counting the number of times. The total number of times the special symbol is variably displayed on the display 1185 or the lower special symbol display 1186 can be grasped.

  The output terminal PT4 is yellow and outputs a start opening winning information output signal. As described above, the start opening winning information output signal is a signal to notify that every time a game ball enters the upper start opening 2101 or the lower start opening 2102 shown in FIG. Every time a game ball enters the upper start port 2101 or the lower start port 2102 from the terminal PT4, it is output for 0.128 seconds. When the start opening prize information output signal from the external terminal board 784 is input to the hall computer, the hall computer starts the upper start opening 2101 or the lower start of the pachinko gaming machine 1 every time the start opening prize information output signal is input. It is possible to grasp that a game ball has entered the mouth 2102 and count the number of times the start opening prize information output signal is input to enter the upper start opening 2101 or the lower start opening 2102 of the pachinko gaming machine 1. The total number of game balls played can be grasped.

  The output terminal PT5 is black and outputs a 15 round big hit information output signal. As described above, the 15-round jackpot information output signal is a signal that indicates that the 15-round jackpot has been generated. In the present embodiment, while the 15-round jackpot is generated from the output terminal PT5, It is output. When the 15 round jackpot information output signal from the external terminal board 784 is input to the hall computer, the hall computer generates 15 round jackpots in the pachinko machine 1 while the 15 round jackpot information output signal is input. The number of times that the 15 round jackpot information output signal has been input can be counted, and the total number of times that 15 round jackpots have occurred in the pachinko gaming machine 1 can be determined.

  The output terminal PT6 is colored pink and outputs a 2-round jackpot information output signal. As described above, the 2-round jackpot information output signal is a signal that indicates that the 2-round jackpot has occurred. In the present embodiment, while the 2-round jackpot is being generated from the output terminal PT6, It is output. When a 2-round jackpot information output signal from the external terminal board 784 is input to the hall computer, the hall computer generates a 2-round jackpot on the pachinko machine 1 while the 2-round jackpot information output signal is being input. It is possible to grasp the total number of occurrences of two round big hits in the pachinko gaming machine 1 by counting the number of times the two round big hit information output signal is input.

  The output terminal PT7 is provided in blue and outputs a normal symbol display information output signal. As described above, the normal symbol display information output signal is a signal that indicates that the normal symbol change display of the normal symbol display 1189 of the function display board 1191 shown in FIG. In this embodiment, the output is performed for 0.128 seconds from the output terminal PT7 when the normal symbol variation display 1189 of the function display board 1191 is ended (stopped). When the normal symbol display information output signal from the external terminal board 784 is input to the hall computer, the hall computer displays the normal symbol display on the function display board 1191 of the pachinko gaming machine 1 when the normal symbol display information output signal is input. It is possible to grasp that the fluctuation display of the normal symbol is finished (stopped) in the device 1189, and the number of times is counted to display the fluctuation of the normal symbol on the normal symbol display 1189 of the function display board 1191 of the pachinko gaming machine 1. Can grasp the total number of times.

  The output terminal PT8 is provided in red and outputs an information output signal for a short time. As described above, the time reduction / medium information output signal is a signal indicating that a time reduction state has occurred, and in the present embodiment, the signal is output from the output terminal PT8 while the time reduction state is occurring. ing. When the time and medium information output signal from the external terminal board 784 is input to the hall computer, the hall computer grasps that the time and time state has occurred in the pachinko gaming machine 1 when the time and medium information output signal is input. In addition, the total number of times that the time-saving state has occurred in the pachinko gaming machine 1 can be grasped by counting the number of times the time-short-time information output signal is input.

  The output terminal PT9 is provided with an orange color to output a probability changing information output signal. As described above, the probability variation in-progress information output signal is a signal that informs that the probability variation is occurring. In this embodiment, the signal is output while the probability variation is occurring from the output terminal PT9. It has become so. When the information output signal during probability variation from the external terminal board 784 is input to the hall computer, the hall computer is in a state where probability variation occurs in the pachinko gaming machine 1 when the information output signal during probability variation is input. And the total number of times the probability variation has occurred in the pachinko gaming machine 1 can be grasped by counting the number of times the information output signal during probability variation is input.

  The output terminal PT10 is light blue and outputs a main prize ball number information output signal. As described above, the main prize ball number information output signal is based on a command from the main control board 4100 (main prize ball number information output command described later), and the upper start opening 2101 and the lower start opening 2102 shown in FIG. , Every time the number of game balls to be paid out as prize balls reaches 10 on the basis of the game balls entered in various prize openings such as the general prize opening 2104, 2201 and the big prize opening 2103, the fact is output. In this embodiment, the output terminal PT10 performs 0.128 seconds (peripheral control unit 1 ms timer interrupt processing, which will be described later, as the interrupt cycle when the later-described payout control unit timer interrupt processing is performed in this embodiment. Is set to 1 ms, unlike the interrupt cycle (2 ms), the output period of 0.128 seconds (that is, output from the output terminal PT10) Signal width of the main prize cell count information output signal), based on the interrupt period of 1ms, the period being repeated peripheral controller 1ms timer interrupt processing 128 times), it is outputted. When the main prize ball number information output signal from the external terminal board 784 is input to the hall computer, the hall computer receives 10 pachinko gaming machines 1 as prize balls each time the main prize ball number information output signal is input. The number of game balls to be paid out by the pachinko gaming machine 1 can be determined by counting the number of game balls to be paid out. Can be grasped. It should be noted that, based on commands from the main control board 4100 (main prize ball number information output command to be described later), various types such as an upper start opening 2101, a lower start opening 2102, a general winning opening 2104, 2201, a large winning opening 2103, and the like When the number of game balls scheduled to be paid out as prize balls reaches 20 or more based on the game balls entered in the winning opening and the main prize ball number information output signal is output a plurality of times, the number of main prize balls The information output signal is output from the peripheral control board 4140 to the external terminal board 784 with an interval of 0.128 seconds so that the information output signal is one continuous signal for 0.256 (= 0.128 seconds × 2 times). It has come to be.

  The output terminal PT11 is provided in yellow green to output a power saving mode information output signal. As described above, the power saving mode information output signal is generated when power is turned off (immediately before power is turned off) based on the power consumption status history information stored in the power consumption status history RAM 4150f shown in FIG. The peripheral control MPU 4150a shown in FIG. 15 grasps the power state consumed in the pachinko gaming machine 1 at the time of power recovery, and notifies the transition state to the power saving mode during power recovery that suppresses the power consumed by the pachinko gaming machine 1. In this embodiment, in the state of shifting to the power saving power saving mode, in this embodiment, the power saving power saving mode state maintaining period, which is the upper limit time described later, from the output terminal PT11 is 5 minutes (peripheral control unit 1 ms timer interrupt described later) In this embodiment, an interrupt cycle when a payout control unit timer interrupt processing (to be described later) is performed (as an interrupt cycle when processing is performed) The output period of 5 minutes (300 seconds) (that is, the signal width of the power saving mode information output signal output from the output terminal PT11) is set based on the interrupt cycle of 1 ms. The control unit 1 ms timer interruption process is repeated for 300,000 times).

  Among the output terminals PT1 to PT11 of the external terminal plate 784, the output terminals PT1 and PT2 output various signals output on the payout control board 4110 side, and the output terminals PT3 to PT9 output on the main control board 4100 side. The various signals are output (passed) through the payout control board 4110, and the output terminals PT10 and PT11 are arranged so that signals output on the peripheral control board 4140 side are output. Each of the output terminals PT1 to PT11 is colored, and by electrically connecting wirings having connectors colored in the same colors as these colors to the output terminals PT1 to PT11, the other wirings are mistakenly electrically connected. Connection can be prevented. The payout control board 4110 does not mix various signals output on the payout control board 4110 side, various signals output on the main control board 4100 side, and signals output on the peripheral control board 4140 side. Output terminals PT1 and PT2 for transmitting various signals output on the side to the hall computer are arranged in a line on the left side of the external terminal board 784, and for transmitting various signals output on the main control board 4100 side to the hall computer. The output terminals PT3 to PT9 are arranged in a row from the center left side to the right side of the external terminal board 784, and the output terminals PT10 and PT11 for transmitting signals output on the peripheral control board 4140 side to the hall computer are external terminal boards. The output terminals PT1 to PT11 are arranged on the right side of 784. By arranging them in a line, the wiring for transmitting various signals output on the payout control board 4110 side to the hall computer and the various signals output on the main control board 4100 side are also transferred to the hall computer. It is possible to prevent an erroneous electrical connection between the wiring for transmitting to the wiring and the wiring for transmitting a signal output on the peripheral control board 4140 side to the hall computer.

  In the present embodiment, the prize ball number information output signal output on the payout control board 4110 side and the main prize ball number information output signal output on the peripheral control board 4140 side are respectively transmitted from the external terminal board 784 to the hall. It is configured to communicate to a computer. This is because, for example, the game balls stored in the prize ball tank 720 are not supplied to the prize ball tank 720 shown in FIG. 1 due to some trouble in the pachinko island equipment. If the 15-round big hit happens to happen in the pachinko gaming machine 1 at the time when there is a short remaining, the number of game balls stored in the prize ball tank 720 for paying out game balls as prize balls will be insufficient. (For example, if a clogged ball or a ball is generated in the prize ball device 740, the game ball cannot be paid out unless it can be eliminated). Then, the prize ball number information output signal output on the payout control board 4110 side is, as described above, the number of game balls actually paid out as prize balls by the payout motor 744 shown in FIG. 5 reaches 10 balls. Since it is a signal to notify that every time, it becomes impossible to pay out the game ball, so that the payout control board 4110 outputs a prize ball number information output signal to the hall computer via the external terminal board 784. become unable. When the game ball is not paid out, the player calls a hall clerk or the like. The hall clerk, for example, checks the position of the ball clogging by checking a hose-like supply nozzle for supplying game balls from the Pachinko Island facilities to the prize ball tank 720 (for example, in the prize ball device 740) When the generated ball clogging position and the position of the ball stagnation are specified and resolved, the game ball is returned to a state where it is paid out.

  However, even if the hall clerk etc. is working, the game by the main control board 4100 is in progress, and after the big round of 15 rounds is finished, the game ball is paid out by the work of the hall clerk etc. When the state returns to the state, the payout control board 4110 pays out unpaid game balls one after another, and the payout control board 4110 is in a period when the 15th round big hit ends and the 15th round big hit has not occurred. Outputs an award ball number information output signal indicating that every time the number of game balls actually paid out by the payout motor 744 reaches 10 balls, and transmits it to the hall computer via the external terminal board 784. It will be. Then, in spite of the fact that 15 rounds of big hits have not occurred, an extremely large number of game balls will be paid out. Therefore, the gaming state of the pachinko gaming machine 1 and the game balls paid out by the pachinko gaming machine 1 There arises a problem that the hall computer cannot accurately grasp the relationship between the number of balls.

  Therefore, in this embodiment, regardless of whether or not the payout motor 744 is driven and controlled by the payout control board 4110 and is actually paid out as a prize ball, that is, different from the prize ball number information output signal output by the payout control board 4110. As shown in FIG. 8, the main control board 4100 is based on the game balls that have entered the various winning ports such as the upper starting port 2101, the lower starting port 2102, the general winning ports 2104, 2201, and the big winning port 2103 shown in FIG. Each time the number of game balls scheduled to be paid out as award balls reaches ten, a command (a main prize ball number information output command to be described later) is transmitted to the peripheral control board 4140, and the peripheral control board 4140 Based on the received command (main prize ball number information output command described later), the upper start opening 2101, the lower start opening 2102, the general winning opening 2104, 2 When the number of game balls to be paid out as prize balls reaches 10 on the basis of the game balls entered in various winning holes such as 01 and the grand prize opening 2103, the main prize ball number information is used as the main prize ball number information. A mechanism was adopted in which a prize ball number information output signal is output to the external terminal board 784 and transmitted to the hall computer. As a result, even if the above-described troubles (troubles such as clogging of the refilling nozzle or the like, clogging of the ball in the prize ball device 740, or ball clogging) occur, the gaming state of the pachinko gaming machine 1 and this gaming state It is possible to accurately convey the relationship between the number of game balls to be paid out and the hall computer. Therefore, the hall computer can accurately grasp the relationship between the gaming state of the pachinko gaming machine 1 and the number of game balls to be paid out in the gaming state.

[12. Circuit of LCD output board]
Next, four 4.3 inch movable liquid crystal display devices 1925a to 1925d arranged on the upper left, lower left, lower right, and upper right of the front side of the 12 inch game board side liquid crystal display device 1900 shown in FIG. A circuit of the liquid crystal output substrate 3420 for drawing the display area will be described with reference to FIGS. First, a circuit configuration of the liquid crystal output substrate will be described, and subsequently, a drawing data creation method, and examples of effects of the game board side liquid crystal display device and the movable liquid crystal display device will be described. FIG. 31 is a block diagram showing a circuit configuration of the liquid crystal output substrate, FIG. 32 is a diagram showing an example of a drawing data creation method, FIG. 33 is a conceptual diagram showing a configuration example of each mask pattern, and FIG. FIG. 35 is a diagram showing an example of an effect example of the game board side liquid crystal display device and the movable liquid crystal display device, and FIG. 35 is a diagram showing a continuation of the example of the effect example of FIG.

[12-1. Circuit configuration of LCD output board]
When the screen data is input from the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 as described above, the liquid crystal and sound source built-in VDP 4160a in the peripheral control board 4140 receives the input screen data. The game board side liquid crystal display device 1900 and the movable liquid crystal display device are created by extracting the game board side character data and the upper plate side character data from the liquid crystal and sound control ROM 4160b of the liquid crystal and sound control unit 4160 based on A VRAM is also built in (built-in VRAM) for generating drawing data for one screen (one frame) to be displayed on 1925a to 1925d and the upper plate side liquid crystal display device 470. The built-in sound source VDP 4160a draws drawing data for the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d among the drawing data generated on the built-in VRAM from the channel CH1 via the liquid crystal output board 3420. In addition to outputting to the display device 1900 and the movable liquid crystal display devices 1925a to 1925d, drawing data for the upper plate side liquid crystal display device 470 is output from the channel CH2 to a peripheral control output circuit, frame peripheral relay terminal plate 868, peripheral door relay terminal (not shown). The game board side liquid crystal display device 1900 and the movable liquid crystal are output (transmitted) to the upper plate side liquid crystal display device 470 via the plate 882 and the touch panel drive substrate 450 housed in the plate unit 300 of the door frame 5. Display devices 1925a to 1925d and an upper plate side liquid crystal display device 470; Thereby achieving synchronization.

  As described above, the channel CH1 employs the dual link method as the LVDS. The first signal transmission path is an even channel, the second signal transmission path is an odd channel, and drawing data for the game board side liquid crystal display device 1900 is transmitted from the even channel to the liquid crystal output board 3420, while the odd channel has four channels. Drawing data for the movable liquid crystal display devices 1925a to 1925d is transmitted to the liquid crystal output substrate 3420. Drawing data is transmitted simultaneously for even and odd addresses by the dual link method.

  As shown in FIG. 31, the liquid crystal output substrate 3420 mainly includes an RGB conversion circuit 3420x and signal division circuits 3420y and 3420z. The RGB conversion circuit 3420x converts the input serial signal into three video signals such as a red video signal, a green video signal, and a blue video signal, and three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. Is converted into a parallel signal. In the signal dividing circuits 3420y and 3420z, a control signal indicating whether or not to accept the parallel signal from the RGB conversion circuit 3420x is input from the VDP 4160a with built-in sound source, and the parallel signal from the RGB conversion circuit 3420x is received based on this control signal. The size is adjusted so as to be received and drawn in the display areas of the movable liquid crystal display devices 1925a to 1925d and output to the movable liquid crystal display devices 1925a to 1925d.

  Specifically, when drawing data (serial signal) for the movable liquid crystal display devices 1925a to 1925d from the odd-numbered channels is received (input) by the RGB conversion circuit 3420x, the RGB conversion circuit 3420x receives the received drawing. Data (input serial signal) is composed of three video signals, a red video signal, a green video signal, and a blue video signal, and three sync signals, a horizontal sync signal, a vertical sync signal, and a clock signal. To parallel signal. The parallel signals converted by the RGB conversion circuit 3420x are input to the signal division circuits 3420y and 3420z.

  When the control signal from the sound source built-in VDP 4160a indicates that the drawing data for the movable liquid crystal display devices 1925a and 1925b should be received and taken in, the signal dividing circuit 3420y takes in the drawing data and moves the movable liquid crystal display device 1925a. , 1925b is adjusted in size to be drawn and output to the movable liquid crystal display devices 1925a and 1925b, while a control signal from the sound source built-in VDP 4160a should accept and draw drawing data for the movable liquid crystal display devices 1925a and 1925b. If it is a message indicating that it is not, the drawing data is not captured.

  When the control signal from the sound source built-in VDP 4160a indicates that the drawing data for the movable liquid crystal display devices 1925c and 1925d should be received and taken in, the signal dividing circuit 3420z takes in the drawing data and moves the movable liquid crystal display device 1925c. , 1925d is adjusted in size to be drawn and output to the movable liquid crystal display devices 1925c and 1925d, while a control signal from the sound source built-in VDP 4160a should accept and draw drawing data for the movable liquid crystal display devices 1925c and 1925d. If it is a message indicating that it is not, the drawing data is not captured.

  On the other hand, drawing data (serial signal) from the even address to the game board side liquid crystal display device 1900 passes through the liquid crystal output board 3420 and is output to the game board side liquid crystal display device 1900 as it is.

  By the way, as described above, the movable devices 1925aa to 1925da capable of independently moving the movable liquid crystal display devices 1925a to 1925d in the vertical and horizontal directions respectively include two stepping motors and output shafts of the two stepping motors. Conversion mechanisms for converting rotational motion into linear motion, and two stepping motors (total of eight stepping motors) respectively provided in the movable devices 1925aa to 1925da are provided around the peripheral control unit 4150 in the peripheral control board 4140. The drive is controlled by the control MPU 4150a. The movable devices 1925aa to 1925da are each provided with a photosensor (not shown) for detecting the state in which the movable liquid crystal display devices 1925a to 1925d are in their original positions, and the detection signals from these photosensors are used for peripheral control. Each input to the MPU 4150a, the peripheral control MPU 4150a determines whether or not the movable liquid crystal display devices 1925a to 1925d are in the standby state based on the detection signal from the photosensor. Peripheral control MPU4150a outputs a drive signal (drive pulse) from the state where movable liquid crystal display devices 1925a to 1925d are in their original positions to the stepping motors provided in movable devices 1925aa to 1925da based on the detection signal from the photosensor Thus, the rotation angle per step of the rotation axis of the stepping motor is determined, so that the movable positions of the movable liquid crystal display devices 1925a to 1925d are estimated based on the output drive signal (drive pulse). .

[12-2. How to create drawing data]
Next, drawing data for the game board side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output substrate 3420, and drawing data for the four movable liquid crystal display devices 1925a to 1925d transmitted from the odd channel to the liquid crystal output substrate 3420 A method of creating the above will be described.

  As described above, the built-in sound source VDP 4160a is a frame buffer for holding drawing data for one screen (one frame) to be drawn on the screen of the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d. Two frame buffers (double buffers) having the same storage capacity are provided in the built-in VRAM. The drawing data for the game board side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output substrate 3420 and the drawing data for the four movable liquid crystal display devices 1925a to 1925d transmitted from the odd channel to the liquid crystal output substrate 3420 are: The liquid crystal on the peripheral control board 4140 and the frame buffers MVD and MVD ′ on the built-in VRAM of the sound source built-in VDP 4160a of the sound control unit 4160 are respectively created and held. Since the procedure for creating and holding the drawing data is the same in both the frame buffers MVD and MVD ′, the frame buffer MVD will be described here.

[12-2-1. Drawing data transmitted from even channels]
The frame buffer MVD for creating drawing data for the game board side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output board 3420 has a frame buffer size corresponding to an image size of 1600 × 600 dots (storage capacity) in advance. Allocated. The frame buffer MVD is twice as large as the image size (12 inches) 800 × 600 dots of the game board side liquid crystal display device 1900 in the horizontal direction. As shown in FIG. 32A, the built-in sound source VDP 4160a displays a large original image MVD0 for drawing in the display area of the game board-side liquid crystal display device 1900 in the frame buffer MVD, in the upper right part of FIG. The origin is created with 600 dots downward from the origin in FIG. 32B and 800 dots left from the origin in FIG. Accordingly, the large original image MVD0 has a size of horizontal width: 800 dots and vertical width: 600 dots. Subsequently, the original image MVD0 is subjected to a process of extending the original image MVD0 from the first row constituting the 800 dots to the last row one by one in sequence (that is, doubled), thereby executing the original image MVD0. A stretched image MVD1 is created by stretching MVD0 twice in the horizontal direction (leftward in FIG. 32B).

  Specifically, in the present embodiment, the origin of the large original image MVD0 is set to the upper left of the large original image MVD0 (that is, the origin of the frame buffer MVD (set to the upper right portion in FIG. 32A). In FIG. 32 (a), the leftmost column of the large original image MVD0 is set as the first column passing through the origin of the large original image MVD0. In contrast, the rightmost column of the original image MVD0 is set as the last column. The width of the original image MVD0: In the case of performing the process of extending one column at a time from the first column forming 800 dots to the last column in order (that is, doubled), first, FIG. ), The first column of the large original image MVD0 is moved to two columns (that is, 1600 dots away from the origin of the frame buffer MVD (the position set in the upper right portion) to the left) of the frame buffer MVD. (Ie, 1600 dots and 1599 dots away from the origin of the frame buffer MVD), and then adjacent to this arranged row, the first of the original image MVD0 The next row after the row is extended to two rows and arranged adjacent to the arrangement by two rows (that is, twice) (that is, from the origin of the frame buffer MVD). To the left 1598 dot, and spaced apart from 1597 dots). At this time, the first column of the original image MVD0 and the column following this first column are not overwritten even if they are extended and arranged in two columns, and are deleted from the frame buffer MVD. Not.

  Such a stretching process is sequentially repeated one by one toward the last column, and 400 columns are set to the leftmost of the frame buffer MVD (the origin of the frame buffer MVD (the upper right of the frame buffer MVD (upper right)). 2) (ie, doubled) from the position set in the section) to the left side (position that is 800 dots away) (ie, 800 dots to the left side from the origin of the frame buffer MVD, and 799 dots) Place them apart). At this point, the first column of the original image MVD0 and the column following this first column are 400 columns as the columns following the first column of the original image MVD0 (that is, Is doubled) and placed in the frame buffer MVD to be overwritten and deleted from the frame buffer MVD.

  Then, such a stretching process is sequentially repeated one by one toward the last column, and 800 columns as the last column of the large original image MVD0 are placed on the leftmost side of the frame buffer MVD (the origin of the frame buffer MVD (in the upper right part). 2) (ie, doubled) from the set position) to 1599 dots away) (ie, 2 dots from the origin of the frame buffer MVD to the left and 1 dot apart) ). At this time, the last column of the original image MVD0 is preceded by one column (that is, 799 columns as the previous row of the last column of the original image MVD0), and the last column is 800 columns. Are overwritten by extending 800 columns as the last column of the large original image MVD0 to 2 columns (that is, 2 times) and arranging them in the frame buffer MVD, and are deleted from the frame buffer MVD.

  In this way, the large original image MVD0 is subjected to the process of extending the original image MVD0 from the first row constituting the 800 dots to the last row one by one in sequence (that is, doubled). MVD0 width: If one column is extended to two columns from the first column to the last column constituting 800 dots, one column is not overwritten by the two expanded columns, and other columns following the one column If one of the columns is extended by two columns, one column is overwritten by the two extended columns, and if the last column of the original image MVD0 is extended to two columns, the original is generated by the two extended columns. By overwriting the last column of the image MVD0, the large original image MVD0 stored in the frame buffer MVD is extended to delete the large original image MVD0 from the frame buffer MVD (that is, the frame Mubaffa the Omoto image MVD0 by stretching the Omoto image MVD0 stored while removed from the frame buffer MVD in MVD) is generating stretched images MVD1.

  Note that this enlargement is performed when the sound source built-in VDP 4160a creates the large original image MVD0, based on the screen data from the peripheral control MPU 4150a, character data is extracted from the liquid crystal and sound control ROM 4160b and enlarged and reduced to create sprite data. It is executed by the same command. In other words, the command used for creating various sprite data arranged in the large original image MVD0 is used as a command for extending the large original image MVD0.

  The sound source built-in VDP 4160a creates a stretched image MVD1 (corresponding to the first stretched effect image) and then removes the image at the portion corresponding to the odd address of the frame buffer MVD (for example, it is painted in black. FIG. 32 (c)). Then, in order to make the drawing easy to see, it is painted white.) The following mask processing is performed. That is, the sound source built-in VDP 4160a uses a predetermined slit-like odd-numbered mask pattern generated so that odd-numbered mask dots are alternately arranged with blank dots as shown in FIG. 33 (d). As shown in the figure, by removing the image of the portion corresponding to each odd dot row that can be specified by an odd address in a lattice shape (slit shape) along the vertical direction, the portion corresponding to the even dot row that can be specified by an even address A grid-like processed image MVD2 that is processed into a grid shape so that only the plurality of strip-like images remain is created.

  Here, the default slit-like odd-numbered mask pattern is a default odd-numbered dot mask pattern in which odd-numbered mask dots shown in FIG. 33B are alternately arranged in a row with blank dots as shown in FIG. As shown in the drawing, by stretching in the vertical direction, the odd-numbered mask dots are generated so as to be alternately arranged with the blank dots, and the whole is formed in a lattice shape (slit shape).

  Next, since the odd address and the even address are alternately arranged as the address for specifying the drawing data created in the frame buffer MVD, the frame buffer MVD has the vertical direction shown in FIG. A grid-like processed image MVD2 is obtained in which the image for one line (that is, the image in the vertical direction for one dot) is removed. A large original image MVD0 shown in FIG. 32 (a) is created at the origin (upper right part of FIG. 32 (b)), and this large original image MVD0 is moved in the horizontal direction (leftward in FIG. 32 (b)). Even if the lattice-like processed image MVD2 is created by stretching it twice, if the image for one line in the vertical direction shown in FIG. 32C is omitted and the space between them is shortened, the origin shown in FIG. This is the same image as the image MVD0. FIG. 32C shows an image for a plurality of lines (that is, an image for one line in the vertical direction (that is, a vertical image for one dot) from the viewpoint of easy viewing of the drawing. , A vertical image of a plurality of dots) is removed.

  When the drawing data for the game board side liquid crystal display device 1900 created in the frame buffer MVD is transmitted to the liquid crystal output board 3420 from the even channel of the channel CH1 in the built-in sound source VDP 4160a, the liquid crystal display on the game board side is displayed via the liquid crystal output board 3420. Output to the device 1900. Since the image size of the large original image MVD0 of the drawing data is the same as the image size (12 inches) 800 × 600 dots of the game board side liquid crystal display device 1900, an image of the same size as the large original image MVD0 is displayed on the game board side liquid crystal. Drawing is performed in the display area of the display device 1900.

[12-2-2. Drawing data sent from odd channels]
The drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted from the odd channel to the liquid crystal output board 3420 is generated in the frame buffer MVD by the drawing data for the game board side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output board 3420. Then, the frame buffer MVD is created, and a large original image is created in the four frame buffers SVDA to SVDD having a size smaller than the frame buffer size of the frame buffer MVD. It has become. The four frame buffers SVDA to SVDD are different from frame buffers MVD and MVD ′ that are provided independently in the built-in VRAM and configured as double buffers.

  The frame buffer SVDA is an area for creating a large original image SVDA0 to be drawn in the display area of the movable liquid crystal display device 1925a shown in FIG. As a frame buffer size, a size (storage capacity) corresponding to an image size of 720 × 204 dots is allocated in advance. The frame buffer SVDB is an area for creating a large original image SVDB0 to be drawn in the display area of the movable liquid crystal display device 1925b shown in FIG. 32 (d). (Memory capacity) is allocated in advance. The frame buffer SVDC is an area for creating a large original image SVDC0 to be drawn in the display area of the movable liquid crystal display device 1925c shown in FIG. 32 (d). (Memory capacity) is allocated in advance. The frame buffer SVDD is an area for creating a large original image SVDD0 to be drawn in the display area of the movable liquid crystal display device 1925d shown in FIG. (Memory capacity) is allocated in advance.

  The large original images SVDA0 to SVDD0 are smaller than the image size (4.3 inches) 480 × 272 dots of the movable liquid crystal display devices 1925a to 1925d, and are therefore smaller. The frame buffer SVDA is twice as large in the horizontal direction as compared with the other frame buffers SVDB to SVDD.

  As shown in FIG. 32 (e), the built-in sound source VDP 4160a uses the frame buffer SVDA to display a large original image SVDA0 for drawing in the display area of the movable liquid crystal display device 1925a from the origin to the lower side. It is created with 204 dots and 360 dots to the left from the origin. Thus, the large original image SVDA0 has a size of horizontal width: 360 dots and vertical width: 204 dots. Subsequently, the large original image SVDA0 is subjected to a process of extending the original image SVDA0 by extending the first row constituting the 360 dots from the first row to the last row in order of two rows (that is, twice). A stretched image SVDA1 is created by stretching SVDA0 twice in the horizontal direction (leftward in FIG. 32D).

  Specifically, in the present embodiment, the origin of the large original image SVDA0 is set at the upper left corner of the large original image SVDA0 (that is, the origin of the frame buffer SVDA (set at the upper right portion in FIG. 32D). In FIG. 32D, the leftmost column of the large original image SVDA0 is set as the first column passing through the origin of the large original image SVDA0. In contrast, the rightmost column of the large original image SVDA0 is set as the last column. The width of the large original image SVDA0: When performing a process of extending one column at a time from the first column constituting 360 dots toward the last column in order (that is, twice), first, FIG. ), The first column of the large original image SVDA0 is moved to two columns (that is, 720 dots away from the origin of the frame buffer SVDA (the position set in the upper right portion) to the left) of the frame buffer SVDA. (That is, 720 dots and 719 dots away from the origin of the frame buffer SVDA to the left), and then adjacent to the arranged row, the first original image SVDA0 The column following the column is extended to two columns and arranged adjacent to the arrangement in two columns (that is, doubled) (that is, the frame buffer SVDA). 718 dots from the origin to the left side, and spaced apart from 717 dots). At this time, the first column of the large original image SVDA0 and the column following this first column are not overwritten even if they are extended and arranged in two columns, and are deleted from the frame buffer SVDA. Not.

  This stretching process is repeated in order toward the last column, one column at a time, and the 180th column is the leftmost column of the frame buffer SVDA (the origin of the frame buffer SVDA (upper right) 2) (ie, doubled) from the position set in the section) to the left side (position that is 360 dots away) (ie, 360 dots from the origin of the frame buffer SVDA to the left side, and 359 dots) Place them apart). At this point, the first column of the original image SVDA0 and the column following this first column are 180 columns as the columns following the first column of the original image SVDA0 (that is, 2) and overwritten by being placed in the frame buffer SVDA and deleted from the frame buffer MVD.

  Then, such a stretching process is repeated in sequence one by one toward the last column, and 360 columns as the last column of the large original image SVDA0 are placed on the leftmost side of the frame buffer SVDA (the origin of the frame buffer SVDA (in the upper right part). 2) (ie, doubled) from the set position) to 359 dots away) (ie, 2 dots to the left from the origin of the frame buffer SVDA and 1 dot apart) ). At this time, the last column of the large source image SVDA0 is preceded by one column (that is, 359 columns as the previous row of the last row of the large source image SVDA0), and the last column is 360 columns. Are overwritten by extending 360 columns as the last column of the large original image SVDA to 2 columns (that is, 2 times) and arranging them in the frame buffer SVDA, and are deleted from the frame buffer MVD.

  In this way, by performing the process of extending the original image SVDA0 in the order of two rows (that is, twice) from the first row constituting the horizontal width: 360 dots toward the last row in order, the large original image The width of SVDA0: If one column is extended from the first column to the last column constituting 360 dots to two columns, one column is not overwritten by the two expanded columns, and the other columns following the one column If one of the columns is extended by two columns, one column is overwritten by the two extended columns, and when the last column of the large original image SVDA0 is extended to two columns, By overwriting the last column of the image SVDA0, the original image SVDA0 stored in the frame buffer SVDA is extended and the original image SVDA0 is deleted from the frame buffer SVDA. (I.e., while deleting the Omoto image SVDA0 by stretching the Omoto image SVDA0 stored in the frame buffer SVDA from the frame buffer SVDA) it is generating the stretched image SVDA1.

  As described above, this extension is performed by extracting character data from the liquid crystal and sound control ROM 4160b based on the screen data from the peripheral control MPU 4150a when the sound source built-in VDP 4160a creates the large original image MVD0 or the large original image SVDA0. Then, it is executed by the same command as the command that created the sprite data by scaling. In other words, a command used to create various sprite data arranged in the large original image SVDA0 is used as a command for extending the large original image SVDA0.

  The sound source built-in VDP 4160a removes the image in the portion corresponding to the even address of the frame buffer SVDA from the extended image SVDA1 created by the frame buffer SVDA (for example, it is painted in black. FIG. 32 (f) makes it easy to see the drawing). In view of the above, it is painted white.) The following mask processing is performed. That is, the sound source built-in VDP 4160a uses a predetermined slit-shaped even-numbered mask pattern generated so that the even-numbered mask dots MD are alternately arranged with the blank dots BD as shown in FIG. ) By removing the image of the portion corresponding to each even dot row that can be specified by even addresses in a grid (slit shape) along the vertical direction, it corresponds to odd dot rows that can be specified by odd addresses A grid-like processed image SVDA2 that is processed into a grid shape so that only a plurality of strip-like images of the portion to be left remains is created.

  Here, the default slit-shaped even-numbered mask pattern is a predetermined even-numbered dot mask pattern in which the even-numbered mask dots MD shown in FIG. 33B are alternately arranged in a line with the blank dots BD. ), The even-numbered mask dots MD are generated so as to be alternately arranged with the blank dots BD, and are formed in a lattice shape (slit shape) as a whole.

  In the frame buffer MVD, areas RGNA to RGND for arranging drawing data for the movable liquid crystal display devices 1925a to 1925d are partitioned in advance. As shown in FIG. 32 (g), the region RGND for arranging drawing data for the movable liquid crystal display device 1925d is an area of 204 dots downward from the origin and 720 dots left from the origin, with the upper right part as the origin. The area RGNC for arranging drawing data for the movable liquid crystal display device 1925c is arranged adjacently (continuously) below the area RGND and 204 dots downward from the lower right point of the area RGND. The region RGNB is arranged in a region of 720 dots in the left direction from the lower right point of the region RGND, and the region RGNB for arranging drawing data for the movable liquid crystal display device 1925b is adjacent to the left side of the region RGNC (continuously). Arranged, 204 dots downward from the upper left point of region RGNC (lower left point of region RGGND), upper left point of region RGNC The area RGNA for arranging drawing data for the movable liquid crystal display device 1925a is arranged adjacent to the left side of the area RGND (continuously). ) And adjacent to (continuously) above the region RGNB, 204 dots downward from the upper left point of the region RGND, and 720 dots leftward from the upper left point of the region RGND Placed in the area. As described above, the four regions RGNA to RGND are arranged adjacent to each other (sequentially), and as a whole, as shown in FIG. 32G, the upper right part is the origin and 408 dots downward from the origin. An area of (204 dots + 204 dots) and 1440 (720 dots + 720 dots) from the origin is partitioned in the frame buffer MVD.

  The built-in tone generator VDP 4160a creates a stretched image SVDA1 in the frame buffer SVDA, and a grid-like processed image processed into a grid so that only a plurality of strip-like images corresponding to odd-numbered dot rows that can be specified by odd-numbered addresses remain. When the SVDA 2 is created, it is transferred to the region RGNA of the frame buffer MVD as shown in FIG. 32 (g) (in FIG. 32 (g), the grid pattern processing shown in FIG. The image MVD2 is omitted).

  The sound source built-in VDP 4160a is a large original image SVDB0 for drawing in the display area of the movable liquid crystal display device 1925b created in the frame buffer SVDB (the large original image SVDB0 has a size of horizontal width: 360 dots and vertical width: 204 dots). Is transferred to the frame buffer SVDA and arranged at the same position as the large original image SVDA0, and the horizontal width of the large original image SVDB0: from the first column constituting 360 dots toward the last column By performing the process of sequentially extending each column by two columns (that is, by double), the large image SVDB0 is expanded by a factor of two in the horizontal direction (leftward in FIG. 32 (d)). Create Specifically, by performing again the extension process performed when creating the enlarged image SVDA1 from the large original image SVDA0 described above, the enlarged image SVDB1 is created from the large original image SVDB0 in the frame buffer SVDA. As a result, the original image SVDB0 has a horizontal width of 360 dots, and the process of extending the original image SVDB0 from the first column to the last column one by one in order to two columns (that is, twice) is performed again. The width of the image SVDB0: If one column of the first column to the last column constituting 360 dots is extended to two columns, one column is not overwritten by the two extended columns, and the other columns following the one column are not overwritten. If any one of the columns is extended by two columns, one column is overwritten by the two extended columns, and if the last column of the large original image SVDB0 is extended to two columns, the expanded two columns are larger. By overwriting the last column of the original image SVDB0, the large original image SVDB0 stored in the frame buffer SVDA is extended and the large original image SVDB0 is deleted from the frame buffer SVDA. Together are generating stretched images SVDB1 (i.e., while deleting the Omoto image SVDB0 by stretching the Omoto image SVDB0 stored in the frame buffer SVDA from the frame buffer SVDA). As described above, this extension is performed by extracting character data from the liquid crystal and sound control ROM 4160b based on the screen data from the peripheral control MPU 4150a when the sound source built-in VDP 4160a creates the large original image MVD0 or the large original image SVDB0. Then, it is executed by the same command as the command that created the sprite data by scaling. In other words, a command used to create various sprite data arranged in the large original image SVDB0 is used as a command for extending the large original image SVDB0. The sound source built-in VDP 4160a removes the image in the portion corresponding to the even address of the frame buffer SVDA from the extended image SVDB1 created by the frame buffer SVDA, and therefore the mask processing performed when creating the grid-processed image SVDA2 When the lattice-like processed image SVDB2 processed in a lattice shape so that only a plurality of strip-like images corresponding to odd-numbered dot rows that can be specified by odd addresses remains is created by performing The image SVDB2 is transferred to the region RGNB of the frame buffer MVD as shown in FIG. 32 (g) (in FIG. 32 (g), the lattice-like processed image shown in FIG. MVD2 is omitted).

  The sound source built-in VDP 4160a is a large original image SVDC0 for drawing in the display area of the movable liquid crystal display device 1925c created in the frame buffer SVDC (the large original image SVDC0 has a size of horizontal width: 360 dots and vertical width: 204 dots). Is transferred to the frame buffer SVDA and arranged at the same position as the large original images SVDA0 and SVDB0, and the horizontal width of the large original image SVDC0: from the first column constituting 360 dots to the last column By performing a process of sequentially stretching the original image SVDC0 by two columns (that is, doubled), the large image SVDC0 is stretched by a factor of two in the horizontal direction (leftward in FIG. 32D). An image SVDC1 is created. Specifically, by executing again the enlargement process performed when creating the enlarged images SVDA1 and SVDB1 from the large original images SVDA0 and SVDB0, the enlarged image SVDC1 is created from the large original image SVDC0 in the frame buffer SVDA. To do. As a result, the original image SVDC0 has a horizontal width of 360 dots, and the process of extending the original image sequentially from the first column to the last column in two columns (that is, twice) is performed again. Width of image SVDC0: If one column is extended from the first column to the last column constituting 360 dots to two columns, one column is not overwritten by the two expanded columns, and the other columns following the one column If one of the columns is extended by two, one column is overwritten by the two extended columns, and when the last column of the large original image SVDC0 is extended to two columns, the two expanded columns are larger. By overwriting the last column of the original image SVDC0, the large original image SVDC0 stored in the frame buffer SVDA is extended and the large original image SVDC0 is deleted from the frame buffer SVDA. Together are generating stretched images SVDC1 (i.e., while deleting the Omoto image SVDC0 by stretching the Omoto image SVDC0 stored in the frame buffer SVDA from the frame buffer SVDA). As described above, this extension is performed by extracting character data from the liquid crystal and sound control ROM 4160b based on the screen data from the peripheral control MPU 4150a when the sound source built-in VDP 4160a creates the large original image MVD0 or the large original image SVDC0. Then, it is executed by the same command as the command that created the sprite data by scaling. In other words, a command used to create various sprite data arranged in the large original image SVDC0 is used as a command for extending the large original image SVDC0. The sound source built-in VDP 4160a is performed when creating the grid-processed images SVDA2 and SVDB2 in order to remove the image in the portion corresponding to the even address of the frame buffer SVDA from the extended image SVDC1 created by the frame buffer SVDA. When the lattice processing image SVDC2 processed so as to leave only a plurality of strip-shaped images corresponding to the odd-numbered dot rows that can be specified by the odd-numbered addresses by performing the mask processing again, the lattice-shaped processed image SVDC2 is created. The processed image SVDC2 is transferred to the region RGNC of the frame buffer MVD as shown in FIG. 32 (g) (in FIG. 32 (g), the lattice shape shown in FIG. The processed image MVD2 is omitted).

  The sound source built-in VDP 4160a is a large original image SVDD0 for drawing in the display area of the movable liquid crystal display device 1925c created in the frame buffer SVDD (the large original image SVDD0 has a size of horizontal width: 360 dots, vertical width: 204 dots). Is transferred to the frame buffer SVDA and arranged at the same position as the large original images SVDA0, SVDB0, SVDC0, and the horizontal width of the large original image SVDD0: from the first column constituting 360 dots to the last By performing a process of extending the original image SVDD0 in the horizontal direction (leftward in FIG. 32 (d)) by executing the process of sequentially extending the data to each column in two columns (that is, twice). A stretched image SVDD1 is created. Specifically, the frame buffer SVDA extends from the large original image SVDD0 by performing again the expansion processing performed when creating the extended images SVDA1, SVDB1, and SVDC1 from the large original images SVDA0, SVDB0, and SVDC0. An image SVDD1 is created. As a result, the original image SVDD0 has a horizontal width of 360 dots, and the process of extending the original image sequentially from the first column to the last column in two columns (that is, twice) is performed again. Width of the image SVDD0: When one column of the first column to the last column constituting 360 dots is extended to two columns, one column is not overwritten by the two extended columns, and the other columns following the one column are not overwritten. If any one of the columns is extended by two columns, one column is overwritten by the two extended columns, and if the last column of the large original image SVDD0 is extended to two columns, the two expanded columns are larger. By overwriting the last column of the original image SVDD0, the large original image SVDD0 stored in the frame buffer SVDA is extended and the large original image SVDD0 is deleted from the frame buffer SVDA. Together are generating stretched images SVDD1 (i.e., while deleting the Omoto image SVDD0 by stretching the Omoto image SVDD0 stored in the frame buffer SVDA from the frame buffer SVDA). As described above, this extension is performed by extracting character data from the liquid crystal and sound control ROM 4160b based on the screen data from the peripheral control MPU 4150a when the sound source built-in VDP 4160a creates the large original image MVD0 or the large original image SVDD0. Then, it is executed by the same command as the command that created the sprite data by scaling. In other words, the command used for creating various sprite data arranged in the large original image SVDD0 is used as a command for extending the large original image SVDD0. The sound source built-in VDP 4160a removes the image in the portion corresponding to the even address of the frame buffer SVDA from the expanded image SVDD1 created by the frame buffer SVDA, and therefore when creating the grid-like processed images SVDA2, SVDB2, SVDC2. By executing the mask processing again, creating a grid-like processed image SVDD2 processed into a grid so that only a plurality of strip-like images corresponding to odd-numbered dot rows that can be specified by odd addresses remain, This grid-like processed image SVDD2 is transferred to the region RGND of the frame buffer MVD as shown in FIG. 32 (g) (FIG. 32 (c) shows from the viewpoint of easy viewing of the drawing. (The grid-like processed image MVD2 is omitted).

  As described above, among the procedures for creating drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted from the odd-numbered channels to the liquid crystal output substrate 3420, first, the large original images SVDA0 to SVDD0 are respectively created in the four frame buffers SVDA to SVDD. After that, when a stretched image SVDA1 is created in the frame buffer SVDA to create a grid-like processed image SVDA2 and transferred to the region RGNA of the frame buffer MVD, subsequently, the large original images SVDB0 to SVDD0 created in the frame buffers SVDB to SVDD Are expanded in the frame buffer SVDA to create the grid-processed images SVDB1 to SVDD1 to create the grid-processed images SVDB2 to SVDD2, and to the regions RGNB to RGND of the frame buffer MVD, respectively. By transferring the turn, lattice-like processed image SVD2 composed of four grid-like processed image SVDA2~SVDD2 is created in the frame buffer MVD.

  In the procedure for creating drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted from the odd-numbered channels to the liquid crystal output board 3420, first, after generating the large original images SVDA0 to SVDD0 in the four frame buffers SVDA to SVDD, respectively. Then, a stretched image SVDA1 is created in the frame buffer SVDA to create a grid-like processed image SVDA2 and transferred to the region RGNA of the frame buffer MVD. Subsequently, the large original images SVDB0 to SVDD0 created in the frame buffers SVDB to SVDD are framed. In the buffer SVDA, stretched images SVDB1 to SVDD1 are created to create grid-like processed images SVDB2 to SVDD2, and sequentially into the regions RGNB to RGND of the frame buffer MVD. For the procedure of sending, the game board side liquid crystal transmitted to the liquid crystal output board 3420 from the even-numbered channel “create the enlarged image MVD1 in the same frame buffer MVD after creating the large original image MVD0 in the frame buffer MVD”. This is different from the procedure for creating drawing data for the display device 1900.

  The drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted from the odd channel to the liquid crystal output substrate 3420 is the drawing data for the game board side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output substrate 3420. Then, since it is created in this frame buffer MVD, the drawing data for the game board side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output board 3420 and the odd channel are used. When drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted to the liquid crystal output board 3420 is created in the same frame buffer called the frame buffer MVD, as shown in FIG. 32 (h), FIG. Lattice processing shown in An image in which the image MVD2 and the grid-like processed image SVD2 shown in FIG. 32 (g) are alternately arranged without interfering with each other (in other words, comb teeth of the grid-like processed image MVD2 shown in FIG. 32 (c)) And an image arranged in a state where the comb teeth of the grid-like processed image SVD2 shown in FIG.

  When the drawing data for the movable liquid crystal display devices 1925a to 1925d created in the frame buffer MVD is transmitted from the odd channel of the channel CH1 in the sound source built-in VDP 4160a to the liquid crystal output board 3420, the liquid crystal output board 3420 receives the RGB data as described above. The conversion circuit 3420x comprises the received drawing data from three video signals, a red video signal, a green video signal, and a blue video signal, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. Converted into parallel signals. The parallel signals converted by the RGB conversion circuit 3420x are input to the signal division circuits 3420y and 3420z.

  The signal dividing circuit 3420y takes in the drawing data when the control signal from the built-in sound source VDP 4160a informs that the drawing data for the movable liquid crystal display devices 1925a and 1925b should be accepted and taken in. Since the image size of the drawn drawing data is the image size 360 × 204 dot of the large original images SVDA0 and SVDB0, it is compared with the image size (4.3 inches) 480 × 272 dots of the movable liquid crystal display devices 1925a and 1925b. Small in both vertical and horizontal directions. Therefore, the signal dividing circuit 3420y performs size adjustment for drawing in the display area of the movable liquid crystal display devices 1925a and 1925b and outputs the result to the movable liquid crystal display devices 1925a and 1925b. That is, images obtained by enlarging the large original images SVDA0 and SVDB0 are drawn in the display areas of the movable liquid crystal display devices 1925a and 1925b, respectively.

  The signal dividing circuit 3420z takes in the drawing data when the control signal from the built-in sound source VDP 4160a informs that the drawing data for the movable liquid crystal display devices 1925c and 1925d should be received and taken in. Since the image size of the drawn drawing data is the image size 360 × 204 dot of the large original images SVDC0 and SVDD0, it is compared with the image size (4.3 inches) 480 × 272 dots of the movable liquid crystal display devices 1925c and 1925d. Small in both vertical and horizontal directions. Therefore, the signal dividing circuit 3420z adjusts the size for drawing in the display area of the movable liquid crystal display devices 1925c and 1925d and outputs the result to the movable liquid crystal display devices 1925c and 1925d. That is, images obtained by enlarging the large original images SVDC0 and SVDD0 are drawn in the display areas of the movable liquid crystal display devices 1925c and 1925d, respectively.

[12-2-3. Mask pattern]
Next, drawing data for the game board side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output substrate 3420, and drawing data for the four movable liquid crystal display devices 1925a to 1925d transmitted from the odd channel to the liquid crystal output substrate 3420 The mask pattern used in the mask processing performed when creating the above will be described.

  The sound source built-in VDP 4160a generates drawing data from necessary sprite data among a plurality of sprite data, stores the drawing data in a built-in VRAM (storage means) as a frame buffer, and outputs the stored drawing data by a dual link method. be able to.

  In the liquid crystal and sound control ROM 4160b, at least one type of mask pattern data (hereinafter simply referred to as “mask pattern”) used for masking the effect image corresponding to the drawing data stored in the frame buffer in a lattice shape (slit shape). Instead of being stored in advance, as shown in FIG. 33 (a), a basic mask pattern constituted by a combination of dots (mask dots and blank dots) constituting a part of this mask pattern is used. Data (also simply referred to as “basic mask pattern”) is stored in advance. In this embodiment, such a basic mask pattern is a minimum combination of dots constituting a part of a predetermined even-numbered dot row mask pattern as shown in FIG. A predetermined even basic dot row mask pattern as shown in FIG.

  The predetermined even basic dot row mask pattern can be designated by an even address in the built-in VRAM, and corresponds to one dot in each even strip area arranged in a lattice shape (slit shape) shown in FIG. It is composed of a combination of a mask dot (also referred to as “even mask dot”) for masking an even unit region (for example, the head even dot) and a blank dot.

  On the other hand, in this embodiment, the built-in tone generator VDP 4160a inverts the mask dot and the blank dot in the combination of the mask dot and the blank dot constituting the predetermined even basic dot row mask pattern to thereby generate the odd basic dot row mask pattern ( "Default odd basic dot row mask pattern") is generated. The predetermined odd basic dot row mask pattern can be designated by an odd address in the built-in VRAM, and corresponds to one dot in each odd strip area arranged in a lattice shape (slit shape) shown in FIG. It is configured by a combination of a mask dot (also referred to as “odd mask dot”) for masking an odd unit region (for example, the first odd dot) and a blank dot. The predetermined odd basic dot row mask pattern may be stored in advance in the liquid crystal and sound control ROM 4160b together with the predetermined even basic dot row mask pattern instead of being generated as described above.

  On the other hand, the predetermined even-numbered dot row mask pattern is obtained by arranging the predetermined even-numbered basic dot row mask pattern shown in FIG. As an example, a combination of blank dots (white dots shown in the figure) is generated to be a mask pattern that is repeated four times.

  In the present embodiment, the built-in tone generator VDP 4160a shifts the predetermined even-numbered dot row mask pattern bit by bit using, for example, a shift register and the most significant bit (MSB) or least significant bit that is not the overflowed bit By adding to (LSB), an odd dot row mask pattern (hereinafter referred to as “default odd dot row mask pattern”) is generated. The predetermined odd dot row mask pattern can be designated by an odd address in the built-in VRAM, and is an odd number corresponding to one dot in each odd strip area arranged in a lattice shape (slit shape) shown in FIG. Mask dots (also referred to as “odd mask dots”) for masking a unit area (for example, the first odd dot) are alternately arranged in a row with blank dots BD as shown in FIG. . On the other hand, in the present embodiment, instead of each bit of the predetermined even-numbered dot row mask pattern, a predetermined even-numbered dot row mask pattern may be generated.

  The sound source built-in VDP 4160a displays drawing data of the first effect image displayed on the game board side liquid crystal display device 1900 (that is, image data for the game board side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output board 3420). The drawing data of the second effect image displayed on the movable liquid crystal display devices 1925a to 1925d (that is, from the odd channel to the liquid crystal output substrate 3420) is stored in the frame buffer MVD as each even strip area that can be designated by the even address of the built-in VRAM. (Drawing data for the four movable liquid crystal display devices 1925a to 1925d) transmitted to the frame buffer MVD is stored in the frame buffer MVD as each even strip area that can be specified by an odd address of the built-in VRAM.

[12-3. Example of game board side liquid crystal display device and movable liquid crystal display device]
As described above, the channel CH1 in the sound source built-in VDP 4160a employs the dual link method as the LVDS. The first signal transmission path is an even channel, the second signal transmission path is an odd channel, and drawing data for the game board side liquid crystal display device 1900 is transmitted from the even channel to the liquid crystal output board 3420, while the odd channel has four channels. Drawing data for the movable liquid crystal display devices 1925a to 1925d is transmitted to the liquid crystal output substrate 3420. At this time, the built-in sound source VDP 4160a simultaneously transmits the drawing data in the storage area specified by the even address and the drawing data in the storage area specified by the odd address by the dual link method. When drawing data for the game board side liquid crystal display device 1900 created in the frame buffer MVD (or frame buffer MVD ′) is transmitted from the even channel of the channel CH1 in the sound source built-in VDP 4160a to the liquid crystal output substrate 3420, the liquid crystal output substrate 3420 is displayed. The large original image MVD0 is output to the game board side liquid crystal display device 1900 through the display area of the game board side liquid crystal display device 1900, and the liquid crystal output board created in the frame buffer MVD (or frame buffer MVD ′). When the drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted to 3420 is transmitted to the liquid crystal output board 3420 from the odd channel of the channel CH1 in the built-in sound source VDP 4160a, the drawing data is separated in the liquid crystal output board 3420. (Division) and expanded by moving the liquid crystal display device 1925A～1925d to be outputted by Omoto image SVDA0~SVDD0 is drawn respectively in the display area of the movable liquid crystal display device 1925A～1925d.

  Here, among a plurality of modes in which the movable liquid crystal display devices 1925a to 1925d are movable, as one example thereof, the movable liquid crystal display devices 1925a to 1925d are moved from their original positions toward the center of the display area of the game board side liquid crystal display device 1900. A mode of appearing on the front surface of the game board side liquid crystal display device 1900 and combining as one display device to cover the entire display area of the game board side liquid crystal display device 1900 will be briefly described.

  As described above, the movable liquid crystal display devices 1925a to 1925d are in positions that are difficult to see when the pachinko gaming machine 1 is viewed from the front side in the standby state at the original position (movable liquid crystal display devices 1925a, 1925a, 1925a, 1925b stands by with the rear left upper side and rear lower left side of the gear decoration body unit 3500 shown in FIG. 9 as the original positions, and the movable liquid crystal display devices 1925c and 1925d are behind the character unit 3400 shown in FIG. It is in a state of waiting with the lower right side and the upper right side as the original position.

  As described above, the movable liquid crystal display devices 1925a to 1925d include the movable devices 1925aa, 1925ba, 1925ca, which are provided on the rear upper left, the rear lower left, the rear lower right, and the rear upper right of the back box 3001 shown in FIG. By 1925da, it is configured to be independently movable in the vertical and horizontal directions.

  The movable liquid crystal display devices 1925a to 1925d draw the images obtained by enlarging the large original images SVDA0 to SVDD0 shown in FIG. 32 (d) in the respective display areas, while the movable devices 1925aa, 1925ba, 1925ca, and 1925da perform FIG. As shown to (a), it starts moving toward the center of the display area of the game board side liquid crystal display device 1900 from each original position. At this time, the original image MVD0 shown in FIG. 32A is drawn in the display area of the game board side liquid crystal display device 1900. Then, as shown in FIG. 35 (b), the game board side liquid crystal display device 1900 appears from the four corners on the front surface of the game board side liquid crystal display device 1900, and as shown in FIG. In the center of the display area of the display device 1900, the liquid crystal display devices are combined as one liquid crystal display device so as to cover the entire display area of the game board side liquid crystal display device 1900.

  Thereafter, the movable liquid crystal display devices 1925a to 1925d are moved from the combined state as one liquid crystal display device at the center of the display area of the game board side liquid crystal display device 1900 to the original positions by the movable devices 1925aa, 1925ba, 1925ca, and 1925da. It starts to move, passes through the four corners of the game board side liquid crystal display device 1900, returns to its original position, and enters a standby state.

  In the present embodiment, as described above, the channel CH1 in the sound source built-in VDP 4160a employs the dual link method as the LVDS, so that even-numbered addresses and odd-numbered addresses are simultaneously transmitted with drawing data. Drawing data for the substrate 3420 is transmitted, and drawing data for the four movable liquid crystal display devices 1925a to 1925d is transmitted from the odd-numbered channels. Therefore, regardless of the movable positions of the movable liquid crystal display devices 1925a to 1925d, that is, the images drawn in the display areas of the movable liquid crystal display devices 1925a to 1925d in a state where the movable liquid crystal display devices 1925a to 1925d stand by in their original positions. Even when it is difficult for the player to visually recognize, the drawing data for drawing in the display area of the movable liquid crystal display devices 1925a to 1925d is transmitted from the odd channel of the channel CH1 in the sound source built-in VDP 4160a.

[13. Touch panel drive circuit]
Next, the detection of the contact state of the capacitive touch panel 480 provided so as to cover the display area of the upper dish side liquid crystal display device 470 attached to the right side of the dish unit 300 of the door frame 5 shown in FIG. A circuit of the touch panel drive substrate 450 that performs the control and draws the display area of the upper plate side liquid crystal display device 470 will be described with reference to FIGS. 36 to 39. As described above, the touch panel drive substrate 450 is disposed in the vicinity of the lower side of the upper dish side liquid crystal display device 470 attached to the right side of the dish unit 300 of the door frame 5 and is stored in the dish unit 300. It is mainly composed of a liquid crystal module circuit 450V that draws a display area of the dish side liquid crystal display device 470 and a touch panel circuit 450W that performs detection control of the touch state of the touch panel 480. FIG. 36 is a circuit diagram showing a liquid crystal module circuit that draws a display area of the upper plate side liquid crystal display device, FIG. 37 is a block diagram of a touch panel circuit that performs detection control of the touch state of the touch panel, and FIG. 38 is a touch panel. FIG. 39 is a schematic diagram showing a continuation of FIG. 38. First, the liquid crystal module circuit will be described, and then the touch panel circuit will be described.

[13-1. LCD module circuit]
As shown in FIG. 36, the liquid crystal module circuit 450V of the touch panel drive substrate 450 is mainly composed of an upper plate side liquid crystal receiver IC SDIC0.

  The liquid crystal module circuit 450V receives a serial signal (serial data) by the differential method “V-by-One (registered trademark)” of THINE ELECTRONICS CO., LTD. Is transmitted to the common mode choke coil SDL0 via the frame peripheral relay terminal plate 868 and the peripheral door relay terminal plate 882, respectively, and the common mode choke coil SDL0 Noise can be separated from the negative signal. The plus signal and minus signal from which the noise has been separated are input to the RXIN + terminal and the RXIN- terminal of the upper plate side liquid crystal receiver ICSDIC0, respectively. A resistor SDR0 is electrically connected between the RXIN + terminal and the RXIN− terminal. The resistor SDR0 is a termination resistor (terminator), which prevents the plus signal and the minus signal from being reflected at the RXIN + terminal and the RXIN− terminal, respectively, and prevents the serial signal from being disturbed.

  Based on the serial signals (serial data) input to the RXIN + terminal and the RXIN- terminal, the upper plate side liquid crystal receiver IC ICDIC0 includes three video signals, a red video signal, a green video signal, and a blue video signal, It is restored to three synchronizing signals, that is, a horizontal synchronizing signal, a vertical synchronizing signal, and a clock signal (that is, restored to a parallel signal before being serialized). As described above, the red video signal, the green video signal, and the blue video signal are 8 bits each of the red video signal, the green video signal, and the blue video signal output from the channel CH2 of the sound source built-in VDP 4160a. Since the red video signal, the green video signal, and the blue video signal that can be input to the upper-plate-side liquid crystal transmitter IC 4160d are 6 bits each for a total of 18 bits, they are the upper 6 bits of each video signal.

  As described above, the liquid crystal module circuit 450V includes the touch panel drive board built in the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140, in addition to the signal from the upper plate side liquid crystal transmitter IC 4160d of the peripheral control board 4140. The LOCKN signal output request data, which is serial data output from the serial I / O port, is also input to the differential circuit 4160e of the peripheral control board 4140, which is differentiated into a plus signal and a minus signal. It is like that. As described above, the forcible switching circuit 4160f of the peripheral control board 4140 transmits these two signals when the differential circuit 4160e receives two signals differentiated into a plus signal and a minus signal. On the other hand, when the two signals differentiated into the plus signal and the minus signal are not input in the differential circuit 4160e, the signal output from the upper plate side liquid crystal transmitter IC 4160d is transmitted. The circuit configuration is such that the circuit is connected. As a result, when two signals differentiated into a plus signal and a minus signal are input in the differential circuit 4160e, the two signals are connected to each other so as to transmit the two signals. The peripheral control board 4140 is transmitted to the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, and the liquid crystal module circuit 450V of the touch panel drive board 450 housed in the dish unit 300 of the door frame 5, while the differential When the two signals differentiated into the plus signal and the minus signal are not input in the inverting circuit 4160e, the circuit is connected so as to transmit the signal output from the transmitter LCD transmitter IC 4160d. The signal output from the side liquid crystal transmitter IC 4160d is transmitted from the peripheral control board 4140 to the frame peripheral relay terminal. Plate 868, near the door relay terminal plate 882, and transmitted to the liquid crystal module circuit 450V of the touch panel driving substrate 450 housed in the dish unit 300 of the door frame 5.

  The forced switching circuit 4160f is a signal output from the upper plate side liquid crystal transmitter IC 4160d, that is, the upper plate, when the two signals differentiated into the plus signal and the minus signal are not input in the differential circuit 4160e. A serial signal (serial data) by the differential method “V-by-One (registered trademark)” of THINE ELECTRONICS CO., LTD. From the side liquid crystal transmitter IC 4160d is converted into a plus signal and a minus signal from the peripheral control board 4140 to the frame peripheral relay terminal board. 868 and the peripheral door relay terminal plate 882, and is input to the common mode choke coil SDL0 and input to the RXIN + terminal and the RXIN− terminal of the upper plate side liquid crystal receiver ICSDIC0, respectively, while the differential circuit 4160e In When the two signals differentiated into the negative signal and the negative signal are input from the peripheral control board 4140 via the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, the two signals are common. The signal is input to the mode choke coil SDL0 and input to the RXIN + terminal and the RXIN− terminal of the upper plate side liquid crystal receiver ICSDIC0. When the two signals differentiated into the plus signal and the minus signal are input in the differential circuit 4160e, the upper plate side liquid crystal receiver IC SDIC0 determines that it is an output request of the LOCKN signal, A LOCKN signal is output from a LOCKN terminal described later to the peripheral control board 4140 via the peripheral door relay terminal plate 882 and the frame peripheral relay terminal plate 868. The LOCKN signal is input to the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 via a peripheral control input circuit (not shown) of the peripheral control board 4140.

  Note that, as described above, the LOCKN signal output request data, which is serial data output from the serial I / O port for the touch panel drive board incorporated in the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140, is a pachinko game. The peripheral control board during the period when the start-up screen at the time of power-on of the machine 1 is displayed on the game board side liquid crystal display device 1900 or during the period when the game board side liquid crystal display device 1900 is in the waiting state Whether there is a problem in the connection between the upper plate side liquid crystal transmitter IC 4160d provided in 4140 and the upper plate side liquid crystal receiver IC SDIC0 provided in the touch panel drive board 450, that is, in the connection between the transmitter and the receiver. To confirm, the upper side liquid crystal display device 47 Which is transmitted as the operation confirmation request. Although the LOCKN signal output request data in the present embodiment is differentiated into a plus signal and a minus signal in the differential circuit 4160e, the signal output from the upper plate side liquid crystal transmitter IC 4160d, that is, the above-mentioned zain electronics stock The data format is completely different from that of the company's “V-by-One (registered trademark)” differential serial signal (serial data). For this reason, when the LOCKN signal output request data is received by the upper plate side liquid crystal receiver ICSDIC0, it is determined that the upper plate side liquid crystal receiver ICSDIC0 is not a signal that is output from the upper plate side liquid crystal transmitter IC 4160d. As data, a LOCKN signal is output from a LOCKN terminal described later. In other words, in the present embodiment, the LOCKN signal is output from the LOCKN terminal, which will be described later, by using the function of the upper plate-side liquid crystal receiver ICSDIC0 that outputs the LOCKN signal when it is determined that the received data is abnormal data. In order to forcibly output the signal, the LOCKN signal output request data having a structure different from that of the signal output from the plate-side liquid crystal transmitter IC 4160d is intentionally sent to the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140. By outputting from the built-in serial I / O port for the touch panel drive substrate, it is possible to confirm whether or not the device called the receiver ICSDIC0 for the upper plate side liquid crystal is operating normally. Thereby, it is possible to confirm whether or not a failure has occurred in the connection between the transmitter and the receiver.

  The VDD terminal, VDDO terminal, LVDSVDD terminal, PLLVDD terminal, and PDWN terminal of the receiver ICSDIC0 for the upper plate side liquid crystal are supplied with + 3.3V created by the upper plate side liquid crystal module power supply circuit 450x shown in FIG. The GND terminal, the GNDO terminal, the LVDSGND application paper, the PLLGND terminal, the EDGE terminal, the OE terminal, the MODE0, and the MODE1 terminal of the dish-side liquid crystal receiver ICSDIC0 are grounded.

  The VDD terminal is a power supply terminal for a digital circuit, and a capacitor SDC0 is electrically connected between the terminal and the GND terminal which is a ground for the digital circuit, and a + 3.3V power supply supplied to the VDD terminal. High frequency noise is removed from the line.

  The VDDO terminal is a power supply terminal for TTL (Transistor-Transistor Logic) output, and a capacitor SDC1 is electrically connected between the terminal and the GNDO terminal serving as the ground for this TTL output, and is supplied to the VDDO terminal. High frequency noise is removed from the + 3.3V power line.

  The LVDSVDD terminal is a power supply terminal for LVDS (Low Voltage Differential Signaling) input, and a capacitor SDC2 is electrically connected between the terminal and the LVDSGND terminal which is the ground for this LVDS input, and is supplied to the LVDSVDD terminal. High frequency noise is removed from the + 3.3V power line.

  The PLLVDD terminal is a power supply terminal for a PLL (Phase Locked Loop) circuit, and a capacitor SDC3 is electrically connected between the terminal and the PLLGND terminal that is the ground for the PLL circuit, and is supplied to the PLLVDD terminal. High frequency noise is removed from the + 3.3V power line.

  The PDWN terminal tells that the logic is HI when + 3.3V is supplied (applied), and that the normal operation is performed, while the supply of +3.3 is stopped and the logic becomes LOW and the power down. It is a terminal to convey. The PDWN terminal is supplied with + 3.3V via the resistor SDR1, and is electrically connected to the other end of the varistor SDZ0 whose one end is grounded. The varistor SDZ0 suppresses noise and overvoltage of the + 3.3V electric line supplied via the resistor SDR1.

  The EDGE terminal transmits various signals output from various output terminals (DE terminal, SYNC0 terminal to SYNC2 terminal, and D0 terminal to D17 terminal) based on a clock signal DCLK output from the CLKOUT terminal, which will be described later. (The logic transitions from LOW to HI) or a falling edge (the logic transitions from HI to LOW). As described above, the falling edge is designated by grounding the EDGE terminal to the ground. Incidentally, when the EDGE terminal is connected to + 3.3V, the rising edge can be designated.

  The OE terminal instructs whether to allow the output of various output terminals (DE terminal, SYNC0 terminal to SYNC2 terminal, D0 terminal to D17 terminal, and CLKOUT terminal) to be described later. As described above, the output is always possible by grounding the OE terminal to the ground. By the way, if the OE terminal is connected to + 3.3V, it cannot be output.

  The MODE0 terminal and the MODE1 terminal are terminals for selecting an operation mode, and the operation mode can be selected by grounding both to the ground. The operation modes include a normal mode and a shake hand mode. In the normal mode, three video signals (18-bit video signal) of a red video signal, a green video signal, and a blue video signal based on serial signals (serial data) respectively input at the RXIN + terminal and the RXIN- terminal. And a normal operation mode in which the upper LCD receiver ICSDIC0 restores a parallel signal composed of three synchronization signals (3-bit synchronization signal) of a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. is there. In shake hand mode, check the connection between the upper plate side liquid crystal transmitter IC 4160d provided on the peripheral control board 4140 and the upper plate side liquid crystal receiver IC SDIC0 provided on the touch panel drive board 450, that is, the connection between the transmitter and the receiver. In this mode, a LOCKN signal is output from the LOCKN terminal to request transmission of a predetermined data pattern (SYNC pattern) for recovery. This shake hand mode is automatically switched.

  For example, three video signals (18-bit video signal) of a red video signal, a green video signal, and a blue video signal based on serial signals (serial data) respectively input at the RXIN + terminal and the RXIN- terminal, For some reason, the receiver ICSDIC0 for the upper plate side liquid crystal is restored to a parallel signal composed of three synchronization signals (three-bit synchronization signal): a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. When it is difficult to draw on the upper plate side liquid crystal display device 470 with the correct data, the normal mode is automatically switched to the shake hand mode and the LOCKN signal is output from the LOCKN terminal. This LOCKN signal is input to the peripheral control board 4140 via the resistor SDR2, which is a damping resistor, the peripheral door relay terminal board 882, and the frame peripheral relay terminal board 868, and enters a peripheral control input circuit (not shown) of the peripheral control board 4140. Via the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140. The peripheral control MPU 4150a, when a predetermined condition is established based on the input LOCKN signal, transmits a connection confirmation signal to the INIT terminal of the upper plate side liquid crystal transmitter IC 4160d to notify the upper plate side liquid crystal transmitter IC 4160d to that effect. Is output. When this connection confirmation signal is input to the INIT terminal, the upper plate-side liquid crystal transmitter IC 4160d establishes a connection between the upper plate-side liquid crystal receiver ICSDIC0 provided on the touch panel drive substrate 450, that is, between the transmitter and the receiver. A predetermined data pattern (SYNC pattern) for recovery is received from the peripheral control board 4140 through the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882, and the receiver ICSDIC0 for the upper plate side liquid crystal provided on the touch panel drive board 450 Send to. When such a predetermined data pattern (SYNC pattern) is received by the upper plate side liquid crystal receiver ICICSIC0, the connection between the transmitter and the receiver can be easily recovered. The predetermined data pattern (SYNC pattern) is stored in advance in the upper plate side liquid crystal transmitter IC 4160d. Note that the INIT terminal of the upper plate side liquid crystal transmitter IC 4160d provided on the peripheral control board 4140 and the LOCKN terminal of the upper plate side liquid crystal receiver ICSDIC0 provided on the touch panel drive board 450 are connected to the frame peripheral relay terminal plate 868 and the peripheral door relay. You may electrically connect directly via the terminal board 882.

  As described above, the LOCKN terminal is connected between the upper plate side liquid crystal transmitter IC 4160d provided on the peripheral control board 4140 and the upper plate side liquid crystal receiver IC SDIC0 provided on the touch panel drive board 450, that is, between the transmitter and the receiver. Is a terminal that outputs a request to transmit a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection. The LOCKN signal output from the LOCKN terminal is input to the peripheral control board 4140 via the resistor SDR2, which is a damping resistance of the touch panel drive board 450, the peripheral door relay terminal board 882, and the frame peripheral relay terminal board 868, and the peripheral control is performed. The signal is input to the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 via a peripheral control input circuit (not shown) of the board 4140.

  The SYNC0 to SYNC2 terminals output three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, which are restored based on serial signals (serial data) input at the RXIN + terminal and the RXIN- terminal, respectively. Terminal. In the present embodiment, since the restored three synchronization signals of the horizontal synchronization signal, the vertical synchronization signal, and the clock signal are not used, the SYNC0 terminal to the SYNC2 terminal are unconnected terminals.

  The DE terminal is a terminal that outputs a DE signal that reports that a clock signal output from the CLKOUT terminal and data output from the D0 to D17 terminals, which are data output terminals, are valid or invalid, which will be described later. The DE signal output from the DE terminal is input to the upper dish side liquid crystal display device 470 via the resistor SDR3 which is a damping resistor.

  The CLKOUT terminal is a terminal for outputting a clock signal DCLK generated by a PLL circuit built in the upper plate side liquid crystal receiver ICSDIC0. The clock signal DCLK output from the CLKOUT terminal is input to the upper dish side liquid crystal display device 470 via the resistor SDR4 which is a damping resistor.

  The D0 to D17 terminals are provided with three video signals (18, red video signal, green video signal, and blue video signal restored on the basis of serial signals (serial data) input at the RXIN + terminal and RXIN- terminal, respectively. This is a data output terminal for outputting a bit video signal. Blue video signals B0 to B5 (6 bits) are output from the 6-bit data output terminals D0 to D5 in synchronization with the clock signal DCLK, and each signal line of the blue video signals B0 to B5 is a damping resistor. The data is input to the upper plate side liquid crystal display device 470 via the ladder resistor SDRA0. Green video signals G0 to G5 (6 bits) are output from the 6-bit data output terminals D6 to D11 in synchronization with the clock signal DCLK, and each signal line of the green video signals G0 to G5 is a damping resistor. These are input to the upper dish side liquid crystal display device 470 via the ladder resistor SDRA1. The red video signals R0 to R5 (6 bits) are output in synchronization with the clock signal DCLK from the 6-bit data output terminals D12 to D17, and each signal line of the red video signals R0 to R5 is a damping resistor. These are input to the upper dish side liquid crystal display device 470 via the ladder resistor SDRA2.

  The grounds of the peripheral control board 4140, the frame peripheral relay terminal board 868, the peripheral door relay terminal board 882, the touch panel drive board 450, and the upper dish side liquid crystal display device 470 are electrically connected and become the same ground. ing.

[13-2. Touch panel circuit]
As shown in FIG. 37, the touch panel circuit 450W of the touch panel drive board 450 includes a touch panel power supply circuit 450a that generates and supplies an analog voltage and a digital voltage from a predetermined voltage from the peripheral control board 4140, as well as a touch panel controller. An oscillator 450c, a sensing IC 450d, and an amplifier circuit 450e are mainly configured around the IC 450b. The touch panel controller IC 450b is configured to send a control command transmitted from the peripheral control board 4140 via the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882 based on the control command from the peripheral control board 4140. And based on the received control command, the sensing IC 450d is driven and controlled to detect the touch state of the touch panel 480, and the position (contact position data) where the finger touches the touch panel 480 is determined as the peripheral door relay terminal board. 882 is transmitted to the peripheral control board 4140 via the frame peripheral relay terminal board 868, or a transition to the power saving mode is performed. The oscillator 450c outputs a reference clock signal to the touch panel controller IC 450b. The sensing IC 450d is driven and controlled by the touch panel controller IC 450b, senses the contact state of the touch panel 480, and outputs the capacitance value of the touch panel 480 as an analog signal. The amplifier circuit 450e amplifies the analog signal from the sensing IC 450d and outputs it to the touch panel controller IC 450b.

  The touch panel controller IC 450b is configured around the controller 450ba, and is an analog-to-digital conversion circuit (hereinafter referred to as “ADC”) that converts the contact state of the touch panel 480 sensed by the sensing IC 450d input via the amplifier circuit 450e from an analog signal to a digital signal. 450bb and various programs (for example, when the power is turned on (including when the power is turned on, and when the power is restored due to a power failure or a momentary power failure, the same applies hereinafter)). Power-on program for performing power-on processing, detection control program for detecting the touch state of the touch panel 480, power-saving mode transition program for shifting to the power-saving mode, canceling the power-saving mode, and starting Is stored in advance) OM450bc, two-point contact position storage register 450bd that can store contact positions (X coordinate, Y coordinate) at the maximum of two points of the touch state of the touch panel 480 based on the digital signal converted by ADC450bd, and an oscillator The phase synchronization circuit (so-called “PLL circuit”) 450be that creates a control clock signal from the reference clock signal from 450c and the touch panel controller IC 450b and the sensing IC 450d are synchronized based on the control clock signal from the PLL circuit 450be. A synchronization signal output circuit 450bf for outputting a synchronization signal for sensing, a serial interface 450bg for sensing IC for outputting serial data for instructing a sensing position of the touch panel 480, and each of the peripheral control boards 4140 The realized seed command is received through the frame peripheral relay terminal board 868 and the peripheral door relay terminal board 882 and transmitted to the controller 450ba, while the contact position stored in the two-point contact position storage register 450bd (maximum The peripheral control board serial interface 450bh that serializes the contact position data of the two contact positions) and transmits the serial data to the peripheral door relay terminal board 882 and the peripheral control board 4140 via the frame peripheral relay terminal board 868, mainly. It is configured.

  The sensing IC 450d has a serial interface 450da that receives serial data for indicating the sensing position of the touch panel 480 transmitted from the sensing IC serial interface 450bg of the touch panel controller IC 450b, and the serial data received by the serial interface 450da. The decoder 450db that restores the sensing position data that indicates the sensing position of the touch panel and the sensing position data restored by the decoder 450db are input to open and close the electrical connection to the sensing position in the entire area of the touch panel 480. An analog multiplexer 450 dc that outputs the capacitance value of the touch panel 480 at the position as an analog signal; The synchronization signal input circuit 450de to which the synchronization signal from the synchronization signal output circuit 450bf of the controller IC 450b is input and the sensing position data restored by the decoder 450db are input, and the synchronization signal is input to the synchronization signal input circuit 450de, A sensing unit 450df that senses an analog signal from the analog multiplexer 450dc and outputs the analog signal to the amplifier circuit 450e is mainly configured.

  Here, the operations of the touch panel controller IC 450b and the sensing IC 450d will be briefly described. For example, the controller 450ba of the touch panel controller IC 450b starts detection control for starting detection control of the touch state of the touch panel 480 from the peripheral control board 4140. When the command is transmitted via the peripheral control board serial interface 450bh, a detection control program for detecting the touch state of the touch panel 480 is read from the ROM 450bc (or the RAM (not shown) provided in the touch panel controller IC 450b is turned on. In this case, when various programs stored in advance in the ROM 450bc are copied, they are read from the RAM), and the read detection control program is started. That. When this detection control program is started, the controller 450ba transmits serial data for indicating the sensing position of the touch panel 480 from the sensing IC serial interface 450bg to the sensing IC 450d.

  The sensing IC 450d receives serial data at the serial interface 450da and outputs the serial data to the decoder 450db, and restores the sensing position data at the decoder 450db. The analog multiplexer 450dc opens and closes the electrical connection to the sensing position in the entire area of the touch panel 480 according to the sensing position data from the decoder 450db, and uses the capacitance value of the touch panel 480 at the sensing position as an analog signal as a sensing unit 450df. Output to. The controller 450ba of the touch panel controller IC 450b outputs a synchronization signal from the synchronization signal output circuit 450bf to the sensing IC 450d. When this synchronization signal is input to the synchronization signal input circuit 450de of the sensing IC 450d and transmitted to the sensing unit 450df, this is triggered. The sensing unit 450df opens and closes the electrical connection to the sensing position in the entire area of the touch panel 480 according to the sensing position data from the decoder 450db when the analog signal from the analog multiplexer 450dc opens and closes the capacitance of the touch panel 480 at the sensing position. Is output to the amplifier circuit 450e. The analog signal amplified through the amplifier circuit 450e is converted into a digital signal by the ADC 450bb of the touch panel controller IC 450b and input to the controller 450ba.

  The controller 450ba transmits serial data indicating the sensing position of the touch panel 480 from the sensing IC serial interface 450bg to the sensing IC 450d, and repeatedly performs control to output a synchronization signal from the synchronization signal output circuit 450bf to the sensing IC 450d. The entire area of the touch panel 480 is sensed to determine the area of the contact surface among the entire area of the touch panel 480, and the position where the finger touches the touch panel is specified.

  At this time, when the controller 450ba determines that the finger is not touching the touch panel 480, the controller 450ba stores no-contact information as contact position data in the two-point contact position storage register 450bd. On the other hand, as shown in FIG. When it is determined that only the index finger of the left hand is touching the touch panel 480 (that is, one point is touched), the contact position data is stored in the two-point contact position storage register 450bd as shown in FIG. P0 (x0, y0) is stored. On the other hand, as shown in FIG. 38C, for example, it is determined that the left index finger and the middle finger are touching the touch panel 480 (ie, touching two points). As the contact position data in the point contact position storage register 450bd, there are two contact positions as shown in FIG. 38 (d). 0 (x0, y0) and P1 (x1, y1) and stores, respectively. The two-point contact position storage register 450bd is updated every time the detection control program is started.

  This detection control program sends a detection control start command from the peripheral control board 4140 to the frame peripheral relay in the touch panel process of the peripheral control part steady process repeatedly performed every 16 ms in the peripheral control part power-on process of the peripheral control board 4140 described later. When received via the terminal board 868 and the peripheral door relay terminal board 882, the power of the pachinko gaming machine 1 is shut off or the power saving mode transition command for shifting to the power mode is not received from the peripheral control board 4140. In such a case, the sensing of the entire area of the touch panel 480 is finished before 16 ms elapses. In the touch panel processing of the peripheral control unit steady process, a contact position data request command for requesting the position (contact position data) where the finger touches the touch panel 480 is sent from the peripheral control board 4140 to the frame peripheral relay terminal board 868, and the peripheral door When received via the relay terminal board 882, that is, the controller 450ba transmits a contact position data request command for requesting a position (contact position data) where the finger touches the touch panel 480 from the peripheral control board 4140. When transmitted via the interface 450bh, the contact position data stored in the two-point contact position storage register 450bd is serialized and transmitted from the peripheral control board serial interface 450bh to the peripheral control board 4140.

  When the controller 450ba determines that three or more points are touched on the touch panel 480, the contact surface determined as the first point and the contact surface determined as the second point in the sensing order by a predetermined algorithm. And the contact surface determined as the third point, the contact surface determined as the fourth point,... The first and second contact positions (P0 (x0, y0) and P1 (x1, y1)) are stored as contact position data in the storage register 450bd, respectively.

  Specifically, as shown in FIG. 39E, for example, when the touch panel 480 is touched in the order of the left index finger, the middle finger, and the ring finger, the controller 450ba touches the touch panel 480 with the left index finger, the middle finger, and the ring finger. Is touched (that is, touching three points), the position of the contact surface determined as the first point in the sensing order as shown in FIG. That is, the contact position P0 (x0, y0) of the left index finger and the position of the contact surface determined as the second point (that is, the contact position P1 (x1, y2) of the middle finger of the left hand) are validated (that is, The contact position P0 (x0, y0) of the left index finger and the contact position P1 (x1, y2) of the middle finger of the left hand are validated. ), The position of the contact surface determined as the third point (ie, the left ring finger contact position P2 (x2, y2)) is invalidated (ie, the left ring finger contact position P2 (x2, y2) is invalid) 2) The contact positions of the first and second points (P0 (x0, y0) and P1 (x1, x1)) are stored as contact position data in the two-point contact position storage register 450bd. Each of y1))) is stored.

  Thus, even if it is determined that the controller 450ba is touching the touch panel 480 with three or more points, the two-point contact position storage register 450bd of the touch panel controller IC 450b detects the first detected contact position and the second detected position. Since only two contact positions, that is, the contact position, can be stored, three or more contact positions can be invalidated. Thereby, since the number of fingers required for the player to operate the touch panel 480 can be limited to a maximum of two, it is possible to prevent the player from placing a burden on the operation of the touch panel 480.

  Here, the effect using two fingers will be briefly described. When a big hit gaming state has occurred, the big hit effect (for example, round-of-rounds) is displayed in the display area of the game board side liquid crystal display device 1900 of the game board 4. In the display area of the upper plate side liquid crystal display device 470 attached to the right side of the plate unit 300, a treasure search effect for searching for treasure during a big hit is made. It has come to be. In this treasure hunting effect, the treasure is sealed with a bivalve shell, and the player touches the touch panel 480 so that the player can pry open the upper shell and the lower shell using two fingers (for example, the index finger and the middle finger of the left hand). If you can move it while touching and open the bivalves to gain treasure, you can promote the probability fluctuation, but if you can not open the bivalves and you can not acquire the treasure, you will stay at the normal probability . In this way, a change due to the touch on the touch panel 480 can be given to the image displayed in the display area of the upper dish side liquid crystal display device 470 based on the contact state of the finger.

  Note that a touch panel provided so as to cover a display area of a display device in a mobile terminal such as a mobile phone can change the posture of the mobile terminal in accordance with a finger operating the touch panel (that is, easy to operate). Therefore, for example, when the touch panel is operated using two fingers, other fingers can be prevented from touching the touch panel. On the other hand, since the touch panel 480 in the present embodiment is provided so as to cover the display area of the upper dish side liquid crystal display device 470 as described above, the touch panel 480 is fixed. For this reason, the posture of the touch panel 480 cannot be changed in accordance with the finger operated by the player (that is, easy to operate). Thereby, for example, even if the player operates the touch panel 480 using two fingers, the player may be touching the touch panel 480 without notice of other fingers. There is also a method of creating a program that exclusively detects that such other fingers are touching the touch panel 480, but the algorithm for distinguishing between fingers necessary for operation and fingers not necessary for operation becomes complicated, There is a problem that the program becomes huge.

[14. Various commands related to transmission / reception of main control board]
Next, various commands transmitted from the main control board 4100 to the payout control board 4110 and various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described with reference to FIGS. FIG. 40 is a table showing an example of various commands transmitted from the main control board to the payout control board, and FIG. 41 is a table showing an example of various commands sent from the main control board to the peripheral control board. 41 is a table showing the continuation of various commands transmitted from the main control board to the peripheral control board in FIG. 41, and FIG. 43 is a table showing an example of various commands from the payout control board received by the main control board. First, a prize ball command that is a command related to payout transmitted from the main control board to the payout control board will be described, and then various commands transmitted from the main control board to the peripheral control board will be described and received by the main control board. Various commands from the payout control board will be described.

[14-1. Various commands sent from the main control board to the payout control board]
The main control MPU 4100a of the main control board 4100 receives detection signals from various winning switches such as the general winning opening switches 3020 and 3020, the upper starting opening switch 3022, the lower starting opening switch 2109, and the count switch 2110 shown in FIG. When inputted, based on these detection signals, a prize ball command for paying out a predetermined number of game balls as prize balls is transmitted to the payout control board. This prize ball command is a command having a storage capacity of 1 byte (8 bits). In this embodiment, the pachinko gaming machine 1 and the CR unit 6 (communicating with the pachinko gaming machine 1 and driving the payout motor 744 of the pachinko gaming machine 1 (prize ball device 740) to store the upper plate 301 or When the lower plate 302 is electrically connected to a device for paying out a game ball as a rental ball (such a pachinko game machine is referred to as a “CR machine”), as shown in FIG. In addition, commands 10H to 1EH (“H” represents a hexadecimal number) are prepared as prize ball commands transmitted from the main control board 4100 to the payout control board 4110. In the command 10H, one prize ball is designated. In the command 11H, two prize balls are designated, and in the command 1EH, 15 prize balls are designated. The payout control board 4110 controls to pay out the game balls by driving the payout motor 744 for the designated number of prize balls.

  Also, a pachinko gaming machine 1 and a ball lending machine (a device that pays out game balls directly to the upper plate 301 and the lower plate 302 as balls for lending) are installed adjacent to the game hall (hall). When the gaming machine 1 and the ball lending machine are electrically connected (such a pachinko gaming machine is referred to as a “general machine”), as shown in FIG. Command 20H to command 2EH are prepared as prize ball commands to be transmitted to the control board 4110, one prize ball is designated by the command 20H, two prize balls are designated by the command 21H,... In 2EH, 15 prize balls are designated. The payout control board 4110 controls to pay out the game balls by driving the payout motor 744 for the designated number of prize balls.

  As a command common to the CR machine and the general machine, a command 30H is prepared as shown in FIG. 40C, and the self-check is designated in the command 30H. By transmitting a command 30H and checking whether or not an ACK signal is input when the transmitting side does not input an ACK signal output as a command reception confirmation from the receiving side for a predetermined period after the command is transmitted. Check the connection status. In the case of the CR machine in the present embodiment, the payout control board 4110 confirms the connection state with the CR unit 6.

[14-2. Various commands sent from the main control board to the peripheral control board]
Next, various commands transmitted from the main control board 4100 to the peripheral control board 4140 will be described. The main control MPU 4100a of the main control board 4100 transmits various commands to the peripheral control board 4140 based on the progress of the game. These various commands are commands having a storage capacity of 2 bytes (16 bits). As shown in FIGS. 41 and 42, a status indicating the type of command having a storage capacity of 1 byte (8 bits), and And a mode showing variations of performance having a storage capacity of 1 byte (8 bits).

  As shown in FIG. 41 and FIG. 42, the various commands are related to special figure 1 synchronization effect, special figure 2 synchronization effect, jackpot related, power-on, general drawing synchronization effect, ordinary electric role effect related, notification display, state Classified into display and other.

[14-2-1. Special Figure 1 Entrainment Production Related]
The special figure 1 tuning effect is based on the detection signal from the upper start-up switch 3022 shown in FIG. 12, and as shown in FIG. 41, the function display board 1191 shown in FIG. Concerning the upper special symbol display 1185, it is composed of commands with names of special figure 1 synchronization effect start, special symbol 1 designation, special figure 1 synchronization production end, and change state designation. These various commands are assigned “A * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The special figure 1 synchronized production start command instructs the start of the special figure synchronized production with the production pattern designated in the mode, and the special symbol 1 designated command designates the off, specific big hit, and non-specific big hit. The special figure 1 tuning effect end command is for instructing the end of the special figure 1 tuning effect, and the variable state designation command is for instructing the probability and the short time state. Note that the probability and short-time state include a low-probability short-time state that indicates a low-probability state and a short-time state, a high-probability time-short state that indicates a high-probability state and a short-time state, and low It consists of a low-probability non-time-short state that indicates that it is a probabilistic state and not a short-time state, and a high-probability non-time-short state that indicates that it is a high-probability state and not a short-time state (as a normal gaming state, , Low probability non-short state is set). Here, the high probability state is a state in which the probability of a big hit is set higher than the low probability state (normal game state), and the short time state is, for example, a normal symbol display 1189 shown in FIG. Compared with the non-short-time state (normal game state), the time for displaying the symbols in a variable manner is shortened and stopped with a light emission pattern corresponding to the normal lottery result. In addition to increasing the number of stop displays compared to the non-time-short state, the period for opening and closing the pair of movable pieces 2106 shown in FIG. A state where a lottery opportunity for special symbols can be obtained without reducing the number of possessed balls by increasing the acceptance rate (entrance rate) of game balls to the lower start opening 2102 shown in FIG. In comparison with the state, the determination of whether or not to open / close the pair of movable pieces 2106 is increased, and in the case of opening / closing the pair of movable pieces 2106, the period of the opening / closing operation of the pair of movable pieces 2106 is lengthened. Thus, the acceptance rate (entrance rate) of game balls to the lower start port 2102 is increased).

  As the transmission timing of these various commands, the special symbol 1 tuning effect start command is transmitted at the start of the special symbol 1 variation, and the special symbol 1 designation command is transmitted immediately after the start of the special symbol 1 tuning effect. The effect end command is transmitted when the special symbol 1 variation time has elapsed (when the special symbol 1 is determined), and the variation state designation command is transmitted immediately after the special symbol winning information designation. These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process described later.

[14-2-2. Special figure 2 synchronized production]
The special figure 2 tune production effect is based on the detection signal from the lower start port switch 2109 shown in FIG. 12, and, as shown in FIG. Concerning the lower special symbol display 1186, it is composed of commands named special figure 2 synchronization effect start, special symbol 2 designation, and special figure 2 synchronization effect end. These various commands are assigned “B * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The special figure 2 synchronized production start command instructs the start of the special figure synchronized production with the production pattern designated in the mode, and the special symbol 2 designated command designates the off, specific big hit, and non-specific big hit. The end of the special figure 2 synchronization effect instructs the end of the special figure 2 synchronization effect.

  As the transmission timing of these various commands, the special symbol 2 tuning effect start command is transmitted at the start of the special symbol 2 fluctuation start, and the special symbol 2 designation command is transmitted immediately after the start of the special symbol 2 tuning effect. The effect end command is transmitted when the special symbol 2 variation time has elapsed (when the special symbol 2 is confirmed). These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

[14-2-3. Jackpot related]
As shown in FIG. 41, the jackpot-related category includes a jackpot opening, a grand prize opening 1 open Nth display, a big prize opening 1 closing display, a big prize opening 1 count display, a big hit ending, a big hit symbol display, and a small hit opening. , A small hit opening display, a small hit count display, and a command with the names of small hit ending. These various commands are assigned “C * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The jackpot opening command is for instructing the start of the jackpot opening, and the Nth display command for the winning prize opening 1 is started during the opening of the winning prize opening 1 for the 1st to 16th rounds (the attack unit 2100 shown in FIG. 8). The command indicating that the Nth round of the grand prize opening 2103 is being opened or the opening is started, and the grand prize opening 1 closing display command starts the closing of the grand prize opening 1 between rounds (the grand prize opening of the attacker unit 2100) 2103 during the closing of the round or start of closing), and the winning prize 1 count display command indicates that the number of 0 to 10 game balls has been counted (the count switch shown in FIG. 12). The number of game balls that have entered the big prize opening 2103 detected by the H.210, and the jackpot ending command is large. Ri is intended to instruct the ending start, big hit symbol display command is for instructing the big hit symbol information display.

  The small hit opening command is for instructing the start of the small hit opening, and the small hit opening display command is for starting the small hit opening (during opening or releasing the big winning opening 2103 of the attacker unit 2100 at the time of the small hit). The small hit count display command is used when the count switch 2110 detects a game ball that has entered the big winning opening 2103 during the small hit. The small hit ending command is an instruction to start the small hit ending.

  As the transmission timing of these various commands, the big hit opening command is sent at the start of the big hit opening, and the big winning opening 1 opening N-th display command is when the big winning opening 1 is opened in the 1st to 16th rounds (the large amount of the attacker unit 2100). The winning prize opening 1 closing display command is transmitted when the winning prize opening 1 is closed (the closing of the winning prize opening 2103 of the attacker unit 2100) and is sent to the winning prize. The mouth 1 count display command is used when the winning prize opening 1 is opened and when the count changes to the winning prize opening 1 (when the winning prize opening 2103 of the attacker unit 2100 is opened and when the game ball that has entered the winning prize opening 2103 is counted. The jackpot ending command is sent at the start of the jackpot ending. Transmitted, big hit symbol display command is sent during the special winning opening open (when opening the special winning opening 2103 attacker unit 2100).

  The small hit opening command is transmitted at the start of the small hit opening, and the small hit release display command is transmitted when the small hit is released (when the big winning opening 2103 of the attacker unit 2100 is opened at the small hit). The hit count display command is transmitted at the time of winning a small hit medium / large winning opening (when a game ball that has entered the large winning opening 2103 is detected by the count switch 2110 during the small hit), and the small hit ending command is Sent when a small hit ending starts. These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

[14-2-4. Power on]
As shown in FIG. 41, the power-on classification is composed of commands named “power-on state”, “power-on main control return destination”, and “power-on main prize ball number information output determination counter notification”. . These various commands are assigned “D * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The power-on state command is for instructing the start of the RAM clear effect and the gaming state. The power-on status command is used when the power-on (including when the power is turned on, and also when the power is restored due to a power failure or a momentary power failure) of the payout control board 4110 shown in FIG. When the operation switch 860a is operated to clear the RAM, information indicating that, and when the power is turned on (in addition to when the power is turned on, including when the power is restored due to a power failure or a momentary power failure) )), The information indicating which state (probability and short-time state) to recover from among the low-probability short-time state, high-probability short-time state, low-probability non-short-time state, and high-probability non-short-time state, And information indicating the model code of the pachinko gaming machine. The model code of this pachinko machine, for example, when creating a so-called max type, middle type, and sweet digital type, for which work is the copyright, what game specifications (for example, the probability variation is When the game happens, the game will continue until the next jackpot game state is generated, and the game where the probability variation occurs when the number of changes in the special symbol is limited (for example, 30 times or 70 times). It is to specify whether it is a specification (so-called ST machine). In other words, the information on the model code of the pachinko machine specifies the series code for specifying which type is the max type, middle type, or sweet digital type indicating the model type, and the copyright of the work. Copyright code and game specifications (for example, if a probability change occurs, the game will continue until the next jackpot game state occurs, and the probability of a special symbol with a limited number of changes) It is mainly composed of a game specification code for specifying a game specification (ST machine, etc.) that causes fluctuation.

  The main control return destination command at power-on indicates the return destination of the main control board 4100 itself. The power-on main control return destination command mainly includes information for instructing the driving state of the start port solenoid 2105 shown in FIG. 12 and information for instructing the driving state of the attacker solenoid 2108 shown in FIG. ing.

  The main notification ball number information output determination counter notification command when the power is turned on includes an upper start opening 2101, a lower start opening 2102, a general winning opening 2104, 2201, a large winning opening 2103, etc., on which the main control board 4100 is provided in the game board 4. Main control built-in RAM that indicates the value of the main prize ball number information output determination counter that counts the number of game balls scheduled to be paid out as prize balls based on the game balls entered in the various prize opening Is stored and backed up as one piece of game backup information. The main prize ball number information output determination counter notification command at power-on is main when power is turned on (including when power is restored and when power is restored due to a power outage or momentary power failure). The value of the main prize ball number information output determination counter is read out and created from the game backup information stored and backed up (backed up) in the control built-in RAM. Note that when the operation switch 860a of the payout control board 4110 shown in FIG. 13 is operated to clear the RAM, the game backup information stored and backed up in the main control built-in RAM is initialized to initialize the main game backup information. The value of the winning ball number information output determination counter is set to the initial value 0 (zero) (that is, when the operation switch 860a of the payout control board 4110 shown in FIG. 13 is operated to clear the RAM. Is forcibly set to zero game balls to be paid out as prize balls).

  As the transmission timing of the power-on status command, power-on main control return destination command, and power-on main prize ball number information output judgment counter notification command, the main control board power-on (in addition to power-on, (Including when power is restored due to a power outage or instantaneous power failure). Specifically, when the pachinko gaming machine 1 is turned on, when recovering from a power failure or a momentary power failure, the main control side power-on process described later is executed, and the peripheral control board in step S120 in the main control side timer interruption process In the command transmission process, a power-on state command, a power-on main control return destination command, and a power-on main prize ball number information output determination counter notification command are transmitted.

[14-2-5. General drawing related production]
The general-synchronization effect is based on the detection signal from the gate switch 2352 shown in FIG. 12, and as shown in FIG. 41, the normal symbol display of the function display board 1191 shown in FIG. The command 1189 is composed of commands with the names of start of ordinary drawing synchronization effect, designation of ordinary symbol, end of ordinary figure synchronization effect, and designation of state at the time of change. These various commands are assigned “E * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The general pattern synchronization production start command is for instructing the general pattern synchronization production start with the production pattern specified in the mode. The figure synchronization effect end command is for instructing the end of the common figure synchronization effect, and the variable state designation command is for instructing the probability and the short time state. As described above, the probability and the short time state include a low probability short time state that indicates a low probability state and a short time state, and a high probability state that indicates a high probability state and a short time state. It consists of a short-time state, a low-probability non-time-short state that indicates a low-probability state and not a time-short state, and a high-probability non-time-short state that indicates a high-probability state and not a time-short state ( As the normal gaming state, a low probability non-short-time state is set).

  As the transmission timings of these various commands, the ordinary symbol synchronization effect start command is transmitted at the time of the normal symbol 1 variation start, the ordinary symbol designation command is transmitted immediately after the ordinary symbol synchronization effect start, and the ordinary symbol synchronization effect end command is When the normal symbol variation time has elapsed (when the normal symbol is determined), the variation state designation command is transmitted immediately after the ordinary symbol winning information designation. These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

[14-2-6. Ordinary electric role production related]
The ordinary electric role effect is related to the pair of movable pieces 2106 shown in FIG. 8 that are opened and closed by driving the start opening solenoid 2105 shown in FIG. It consists of commands named “Opening per figure”, “Opening of public power”, and “Ending per common figure”. These various commands are assigned “F * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The opening command per base map is an instruction to start the opening per base map, and the open command display command for general power is started during normal power release. The ending command per universal map indicates the start of ending per universal map.

  As the transmission timing of these various commands, the opening command per base map is transmitted at the start of the opening per base map, and the general power open display command is displayed when the general power is open (the pair of movable pieces 2106 are driven by the start opening solenoid 2105). The ending command per universal map is transmitted at the start of ending per universal map. These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

[14-2-7. Notification display]
As shown in FIG. 42, the notification display section includes commands having the names of winning abnormality display, connection abnormality display, disconnection / short circuit abnormality display, magnetic detection switch abnormality display, door opening, and door closing. These various commands are assigned “6 * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The winning anomaly display command is used when a winning ball is won other than during a big hit (while the condition device is operating) (a game ball enters the big winning port 2103 of the attacker unit 2100 even though it is not a big hit) (When the count switch 2110 detects), an instruction to start winning abnormality notification is instructed, and the connection abnormality display command is, for example, an electrical connection in a path between the main control board 4100 and the payout control board 4110. When there is an abnormality, an instruction to start connection abnormality notification is given, and the disconnection / short circuit abnormality display command includes, for example, the main control board 4100, the upper start port switch 3022, the lower start port switch 2109, the count switch 2110, Instructs the start of the disconnection / short circuit abnormality display when a disconnection / short circuit of the electrical connection occurs. Display command is for instructing the start of magnetic detection switch abnormality notification when an abnormality occurs in the magnetic detection switch 3024 shown in FIG. 12.

  Further, the door opening command is sent from the door frame 5 to the main body frame 3 based on a detection signal (opening signal) from the door frame opening switch 618 input via the payout control board 4110 shown in FIG. In the opened state, the door opening notification is instructed, and the door frame closing command is based on the detection signal from the door frame opening switch 618 and the door frame 5 is closed with respect to the main body frame 3. When it is in the state, it is instructed to end the door opening notification. On the other hand, the main body frame opening command is sent from the main body frame 3 to the outer frame 2 based on the detection signal (open signal) from the main body frame opening switch 619 input via the payout control board 4110 shown in FIG. In the open state, the main body frame close command is sent to the outer frame 2 based on the detection signal from the main body frame open switch 619. In the closed state, the main body frame opening notification is instructed to end.

  As the transmission timing of these various commands, the winning abnormality display command is transmitted when winning a big winning opening other than during the big hit (the condition device is operating), and the connection abnormality displaying command is sent from the main control board 4100 to the payout control board 4110. The command is sent when there is no ACK reply (ACK signal) from the payout control board 4110 at the time of command transmission to the command, and the disconnection / short circuit abnormality display command is one of the upper start port switch 3022, the lower start port switch 2109, the count switch 2110, etc. , Which is transmitted when a break or short circuit occurs, and the magnetic detection switch abnormality display command is transmitted when an abnormality of the magnetic detection switch 3024 is detected. The door opening command is transmitted when door opening is detected (when the door frame 5 is in an open state with respect to the main body frame 3 based on a detection signal from the door frame opening switch 618). The frame closing command is transmitted when door closing is detected (when the door frame 5 is closed with respect to the main body frame 3 based on a detection signal from the door frame opening switch 618). The body frame release command is transmitted when the body frame release is detected (when the body frame 3 is opened to the outer frame 2 based on the detection signal from the body frame release switch 619). The frame closing command is transmitted when the body frame closing is detected (when the body frame 3 is closed with respect to the outer frame 2 based on the detection signal from the body frame opening switch 619). These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

[14-2-8. Status display]
As shown in FIG. 42, the status display section is composed of commands named frame status 1 command (corresponding to an error occurrence command), error canceling navigation command (corresponding to error canceling command), and frame status 2 command. Yes. These various commands are assigned a status of “7 * H” and a mode of “** H” (“H” represents a hexadecimal number) (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The frame status 1 command, the error canceling navigation command, and the frame status 2 command are commands having a storage capacity of 1 byte (8 bits) transmitted from the payout control board 4110, and detailed descriptions thereof will be described later. . When the main control MPU 4100a of the main control board 4100 receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, as shown in FIG. 42, “7 * H” is displayed. While setting as a status, the received command is set as a mode as it is. That is, when the main control MPU 4100a receives the frame state 1 command, the error release navigation command, and the frame state 2 command from the payout control board 4110, it adds “7 * H” as additional information to these received commands. Thus, the command is shaped into a command having a storage capacity of 2 bytes (16 bits).

  The shaped frame status 1 command is transmitted when the power is restored, when the status of the frame is changed, and when the error cancellation navigation is performed. The error cancellation navigation command is transmitted during the error cancellation navigation. The frame status 2 command is transmitted when the power is restored. And when the frame state changes. Note that the shaped frame state 1 command, error release navigation command, and frame state 2 command are actually transmitted in the peripheral control board command transmission process of step S120 in the main control timer interrupt process.

[14-2-9. Test related]
As shown in FIG. 42, the test-related category is composed of various commands named test. This test command is assigned “8 * H” as a status and “** H” (“H” represents a hexadecimal number) as a mode (“*” is a specific hexadecimal number). And is predetermined according to the specification content of the pachinko gaming machine 1).

  The test command instructs various inspections of the peripheral control board 4140 (for example, the peripheral control unit 4150, the liquid crystal and sound control unit 4160, the lamp driving board 4170, the motor driving board 4180, and the frame shown in FIG. 15). Inspects various substrates such as the decorative drive amplifier substrate 194).

  As a test command transmission timing, it is transmitted when the main control board power is turned on when the RAM is not cleared and when the RAM is not cleared. Specifically, when the power of the pachinko gaming machine 1 is turned on, when the operation switch 860a of the payout control board 4110 is operated when the power is restored from a power failure or a momentary power interruption, the main control side power-on process described later And the test command is transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

[14-2-10. Others]
As shown in FIG. 42, the other categories include start opening prize, change shortening operation end designation, high probability end designation, special symbol 1 memory, special symbol 2 memory, normal symbol memory, special symbol 1 memory pre-reading effect, special It consists of a command with a name of design 2 memory pre-reading effect and main prize ball number information output. These various commands are assigned a status of “9 * H” and a mode of “** H” (“H” represents a hexadecimal number) (“*” is a specific hexadecimal number). This is predetermined according to the specification contents of the pachinko gaming machine 1).

  The start opening prize command is an instruction to start the start opening winning effect. When the game ball enters the upper start opening 2101 based on the detection signal from the upper start opening switch 3022, Based on the detection signal from the start port switch 2109, it instructs to start the production when a game ball enters the lower start port 2102. The command for instructing state transition to the fluctuation shortening non-operation state is instructed. The high probability end designation command is for instructing state transition from the high probability state to the low probability state, and the special symbol 1 storage command is a special symbol. 1 hold 0-4 pieces (a game ball enters the upper start port 2101 shown in FIG. 8 and the special symbol display 1185 on the function display board 1191 still displays the variation of the special symbol. The special symbol 2 memory command is used to transmit 0 to 4 special symbol 2 hold commands (the game ball enters the lower start port 2102 shown in FIG. 8). The special symbol display 1186 under the function display board 1191 conveys the number of balls that have not been used yet for the special symbol variation display (the number of holdings), and the normal symbol storage command is 0 to 4 normal symbol 1 holds. (A game ball passes through the gate part 2350 shown in FIG. 8, and the normal symbol display 1189 of the function display board 1191 conveys the number of balls (the number of holdings that are not yet used for the normal symbol variation display). The special symbol 1 storage pre-reading effect command is pre-read based on the special symbol 1 hold before the special symbol 1 hold is used for the variable symbol display on the special display 1118 on the function display board 1191. special The special symbol 2 storage prefetching effect command is used to instruct the start of the pre-reading effect to notify the advance notice of the display result by the design indicator 1185. Is used for pre-reading and informing the start of a pre-reading effect informing the advance notice of the display result by the lower special symbol indicator 1186 based on the special symbol 2 hold before the display of the fluctuation of the main symbol, and the main winning ball number information output The command is to be paid out as a winning ball based on game balls that the main control board 4100 has entered in various winning ports such as the upper starting port 2101, the lower starting port 2102, the general winning port 2104, 2201, and the big winning port 2103. Each time the number of game balls reaches 10 balls, the main prize ball number information output signal is sent to the hall via the external terminal board 784 as the main prize ball number information. It tells the computer to tell.

  As the transmission timing of these various commands, the start opening prize command is the start opening prize (when a game ball enters the upper start opening 2101 based on the detection signal from the upper start opening switch 3022 or the lower start opening switch 2109 (when a game ball enters the lower start port 2102 based on the detection signal from 2109), the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the door frame shown in FIG. 5 is transmitted mainly from the speaker 130 provided in order to notify the fact by voice, and the change shortening operation end designation command is sent at the end of the stop period after the end of the change after confirming the change of the specified number of changes (the elapse of the stoppage period) The high-probability end designation command is sent at the end of the stop period after the change is confirmed (after the lapse of the stoppage period). The special symbol 1 storage command is used when the special symbol 1 operation holding ball number changes (the game ball enters the upper start port 2101 and is still used for the special symbol change display on the special display 1118 on the function display board 1191. In the state where there is an unreserved number, when a game ball enters the upper start port 2101 and the retained number increases, the upper special symbol display 1185 is used to display the variation of the special symbol from the retained number. The special symbol 2 memory command is sent when the number of special symbol 2 actuated balls is changed (a game ball enters the lower start port 2102 and the lower special symbol of the function display board 1191). In the state where there is a number of holdings that are not yet used for the change display of the special symbol on the display unit 1186, when the number of holdings increases when the game ball enters the lower start port 2102 or when the number of holdings increases, the lower special symbol table The normal symbol storage command is sent when the number of reserved symbols of the normal symbol 1 is changed (when the game ball passes through the gate portion 2350). In the state where there is a reserve number that is not yet used for the normal symbol variation display on the normal symbol display 1189 of the function display board 1191, when the game ball passes through the gate part 2350 and the reserve number increases, or the reserve Is sent to the normal symbol display 1189 when the number of reserved symbols decreases and the number of reserved symbols decreases. Is sent when the game ball enters the mouth 2101 and the number of held balls increases, and the special symbol 2 memory pre-reading effect command is sent when the number of the special symbol 2 action held balls increases (the game ball enters the lower start port 2102) The main prize ball number information output command is sent at the time of various prize opening prizes (based on the detection signal from the upper start opening switch 3022) and the game ball enters the upper start opening 2101. When a ball is played, a game ball enters the lower start port 2102 based on the detection signal from the lower start port switch 2109. When the game ball enters the lower start port 2102, the general winning port 2104, 2201 is input based on the detection signal from the general winning port switches 3020, 3020. When a game ball enters the game ball, and when a game ball enters a winning port such as when a game ball enters the big winning port 2103 based on a detection signal from the count switch 2110). These various commands are actually transmitted in the peripheral control board command transmission process in step S120 in the main control timer interrupt process.

  By the way, as described above, the start opening prize command is received at the start opening winning (when a game ball enters the upper start opening 2101 based on the detection signal from the upper start opening switch 3022 or from the lower start opening switch 2109. (When a game ball enters the lower start port 2102 based on the detection signal), the speaker is housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 mainly by voice. Although it is transmitted to notify the effect, how the peripheral control board 4140 shown in FIG. 15 uses the start opening winning command may differ depending on the specifications of the pachinko gaming machine. For example, in the pachinko gaming machine 1 in the present embodiment, in addition to notifying by voice from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the presence or absence of fraudulent activity is monitored. It is the specification of using for the purpose. On the other hand, in other pachinko machines, the peripheral control board 4140 simply receives the start opening prize command, and the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker provided in the door frame 5 Some specifications do not notify by voice from 130.

[14-3. Various commands from the payout control board received by the main control board]
Next, various commands from the payout control board 4110 received by the main control board 4100 will be described.

  As shown in FIG. 43, the various commands from the payout control board 4110 are composed of commands named frame state 1, error release navigation, and frame state 2, and include frame state 1, error release navigation, and Priorities are set in the order of frame state 2.

  For the frame status 1 command (corresponding to an error occurrence command), a ball breakage, a full tank, a connection abnormality and a CR non-connection in 50 or more stocks are prepared, and bit 0 (B0, “B”) in the ball breakage. Represents a bit.) Is set to 1; when full, bit 1 (B1) is set to 1; in more than 50 stocks, bit 2 (B2) is set to 1; A value 1 is set in bit 3 (B3), and a value 1 is set in bit 4 (B4) when the CR is not connected. In bit 5 (B5) to bit 7 (B7) of the frame state 1 command, a value 1 is set in B5, a value 0 is set in B6, and a value 0 is set in B7.

  The error clearing navigation command (corresponding to the error clearing command) includes a ball round, a count switch error, and a retry error. In the ball round, a value 1 is set in bit 2 (B2). Value 1 is set in bit 3 (B3), and value 1 is set in bit 4 (B4) in the case of a retry error. Here, “counting switch error” indicates whether or not the counting switch 751 shown in FIG. 13 has a problem. The “retry error” indicates that a game ball that is not consistent with the retry operation has been repeatedly paid out. Bit (B0), bit (B1), and bit 5 (B5) to bit 7 (B7) of the error cancellation navigation command have a value 0 for B0, a value 0 for B1, a value 0 for B5, a value 1 for B6, The value 0 is set in B7.

  In the frame state 2 command, a shot ball feed control circuit error is prepared, and in the shot ball feed control circuit error, a value 1 is set to bit 0 (B0). Bit 1 (B1) to Bit 7 (B7) of the frame status 2 command include a value 0 for B1, a value 0 for B2, a value 0 for B3, a value 0 for B4, a value 1 for B5, a value 1 for B6, and The value 0 is set in B7.

  As the transmission timing of these various commands, the frame state 1 command is transmitted when the power is restored, the frame state is changed, and the error cancellation navigation is performed. The error cancellation navigation command is transmitted during the error cancellation navigation, and the frame state 2 command is transmitted. Is transmitted when the power is restored and when the frame state changes. These various commands are actually transmitted in the command transmission process in step S558 in the payout control unit main process of the payout control part power-on process described later.

[15. Various control processes of main control board]
Next, various control processes performed by the main control board 4100 shown in FIG. 12 according to the progress of the game of the pachinko gaming machine 1 will be described with reference to FIGS. 44 to 46. 44 is a flowchart showing an example of main control-side power-on processing, FIG. 45 is a flowchart showing continuation of main control-side power-on processing of FIG. 44, and FIG. 46 is an example of main control-side timer interrupt processing. It is a flowchart which shows. First, various random numbers used for game control will be described, and then the operation of the initial value update type counter, main control side power-on processing, and main control side timer interrupt processing will be described.

[15-1. Various random numbers]
As the various random numbers used for game control, a big hit determination random number used for determining whether or not to generate a big hit gaming state, and whether or not to generate a reach (reach out) when no big hit gaming state is generated Reach determination random number for use in determination, and a variable display pattern for use in determining the variable display pattern of the special symbol displayed by the upper special symbol display 1185 and the lower special symbol display 1186 shown in FIG. A random number for use in determining the jackpot symbol derived and displayed by the upper special symbol display unit 1185 and the lower special symbol display unit 1186 when the jackpot gaming state is generated, and the random number for the jackpot symbol Random number for determining the initial value for the big hit symbol for use in determining the initial value, the upper special symbol indicator 1185 for generating the small hit gaming state, and Random numbers for small hit symbols for use in determining the small hit symbols derived and displayed by the special symbol display 1186, random numbers for determining initial values for small hit symbols for use in determining the initial values of the random numbers for small hit symbols, etc. Is prepared. Further, in addition to these random numbers, a determination random number for normal symbols for use in determining whether or not to move the movable piece 2106 shown in FIG. 8 and an initial value of the random numbers for determination per normal symbol are determined. Random numbers for determining initial values for normal symbols to be used, random numbers for normal symbol variation display patterns for use in determining the variation display pattern of ordinary symbols variably displayed on the ordinary symbol display unit 1189 shown in FIG. Is prepared.

  Of the various random numbers used for such game control, the jackpot determination random number is updated by hardware, while the other various random numbers are updated by software.

  For example, the big hit determination random number is directly updated by hardware by the main control built-in hardware random number circuit 4100an built in the main control MPU 4100a shown in FIG. As described above, when the main control MPU 4100a is reset, the main random number built-in circuit 4100an first sets a clock signal input to the main control MPU 4100a as an initial value within a predetermined numerical range. Based on (the clock signal output from the main control crystal oscillator MX0 shown in FIG. 21), other values within a predetermined numerical range are extracted one after another at a high speed, and all values within the predetermined numerical range are extracted. When the extraction is completed, one value within the predetermined numerical range is extracted again, and other values within the predetermined numerical range are extracted one after another based on the clock signal input to the main control MPU 4100a. To do. The main control built-in hard random number circuit 4100an repeats such a high-speed lottery, and the main control MPU 4100a wins the value extracted by the main control built-in hard random number circuit 4100an at the time of acquiring a value from the main control built-in hard random number circuit 4100an. It is set as a random number for judgment.

  On the other hand, the counter for updating the random number for determination per normal symbol is updated within a predetermined fixed numerical value range from the minimum value to the maximum value, and a range from the minimum value to the maximum value will be described later. Each time the main control side timer interrupt process is performed, the value is incremented by one. This counter counts up from the normal value for determining the initial value for determination per normal symbol toward the maximum value, and then counts up from the minimum value to the random number for determining the initial value for determination per normal symbol. When the counter finishes counting up the range from the minimum value to the maximum value of the random number for normal symbol determination, the random number for initial value determination for normal symbol is updated. Such a counter updating method is referred to as an “initial value updating type counter”. The random value for determining the initial value for normal symbol determination can be obtained by executing an initial value lottery process for drawing one value from the fixed numerical range of the counter for updating the random number for determination per normal symbol. .

  In this embodiment, when the operation switch 860a of the payout control board 4110 shown in FIG. 13 is operated when the power is turned on, or in the main control side power-on process described later, the main control MPU 4100a shown in FIG. The check sum value (sum value) obtained by calculating the sum of various information stored in the main control built-in RAM as numerical values is stored in the main control side power-off process (when the power is turned off). When the entire area of the main control built-in RAM is cleared, such as when the checksum value (sum value) does not match, the random number for determining the initial value for determining the normal per symbol is the main control MPU 4100a shown in FIG. Takes out the ID code from the built-in non-volatile RAM, and based on this extracted ID code, it is a fixed numerical range of the counter that updates the random number for normal symbol determination Always run the initial value derivation process of deriving the same fixed value, a fixed value this derivation has a mechanism to be set. That is, the random value for determining the initial value for determining the normal symbol is always overwritten and updated with the same fixed value derived based on the ID code by executing the initial value deriving process. As described above, the value set as the random number for determining the initial value for determining the normal per symbol is derived using the ID code, and the nonvolatile RAM built into the main control MPU 4100a by the manufacturer that manufactured the main control MPU 4100a. If the ID code is stored in the ID code, the ID code is not rewritten even if an external device is used, and the ID code is executed by executing the initial value derivation process when clearing the entire area of the main control built-in RAM. The second security measure of deriving the same fixed value based on the above and the two steps of security measures are taken to prevent analysis.

  Here, an advantage will be described in which an ID code is extracted from a nonvolatile RAM incorporated in the main control MPU 4100a, and the extracted ID code is used as a random number for determining an initial value for normal symbol determination. For example, a person who illegally acquires a game ball to be paid out as a prize ball obtains the game board 4 by some method and disassembles it, and uses an ID code stored in advance in a nonvolatile RAM built in the main control MPU 4100a. Even if the counter value that is obtained illegally and the counter value for updating the determination random number per normal symbol and the determination value per normal symbol match can be grasped, the ID code is unique for identifying the individual. Since the reference numerals are attached, the ID codes are completely different from the ID codes stored in advance in the nonvolatile RAM built in the main control MPU 4100a ′ provided in the other game board 4 ′. In other words, in the other game boards 4 ′, the timing at which the counter value for updating the random number for normal symbol determination matches the normal symbol determination value is also completely different from that of the acquired game board 4. In other words, the ID code obtained by disassembling and analyzing the obtained game board 4 is not useful at all on the other game board 4 ', that is, the other pachinko gaming machine 1', so it is disassembled and analyzed. Even if a momentary power failure is generated at every predetermined interval and the game ball is passed through the gate portion 2350 shown in FIG. 8, the movable piece 2106 shown in FIG. A gaming state in which a game ball can be received at the lower start port 2102 cannot be generated.

[15-2. Main control side power-on processing]
First, when the power is turned on to the pachinko gaming machine 1, the main control MPU 4100a is configured so that the stack pointer is set to a predetermined address as a default. This stack pointer indicates, for example, the address accumulated on the stack to temporarily store the contents of the memory element (register) being used, or the return address of this routine when the subroutine is terminated and the routine returns. This indicates the address accumulated on the stack for temporary storage, and the stack pointer advances each time the stack is stacked.

  Then, under the control of the main control MPU 4100a of the main control board 4100, the main control program described above performs main control side power-on processing as shown in FIGS. When the main control side power-on process is started, the main control program sets the RAM access permission under the control of the main control MPU 4100a (step S10). Update to the main control built-in RAM (game storage unit) can be performed by setting the RAM access permission.

  Subsequent to step S10, the main control program performs initial value setting and activation setting of the main control built-in WDT 4100af shown in FIG. 12 (step S12). Here, in order to set an initial value in the main control built-in WDT 4100af for monitoring whether or not the operation (system) of the main control MPU 4100a is operating normally, a watchdog timer control register (hereinafter referred to as “the main control MPU 4100a”). The timer setting value is set in the “WDT control register”), the main control built-in WDT 4100af is started, and the time measurement from when the main control MPU 4100a is reset is started. When the main control built-in WDT 4100af is activated, the time measurement by the main control built-in WDT 4100af is started, and the watchdog timer clear register (incorporated in the main control MPU 4100a) is reached by the time set by the timer set value. Hereinafter, if the timer clear setting value is not set in “WDT clear register”), the main control MPU 4100a is forcibly reset by the main control built-in WDT 4100af. On the other hand, when the main control built-in WDT 4100af is activated and time measurement is started, the timer clear setting value is set in the WDT clear register until the time measured reaches the time set by the timer setting value. Timekeeping by the main control built-in WDT 4100af is cleared, and timekeeping is started again. As described above, the operation (system) of the main control MPU 4100a operates normally by repeatedly performing the process of clearing the time measurement by the main control built-in WDT 4100af until the time set by the timer set value is reached and starting the time measurement again. It can be monitored whether or not.

  Subsequent to step S12, the main control program performs a power failure clear process (step S14). In this electric power clearing process, first, output of a power outage clear signal is started to the power outage monitoring circuit 4100e shown in FIG. The power failure monitoring circuit 4100e includes a comparator MIC21 that is a voltage comparison circuit and a D-type flip-flop MIC22. The comparator MIC21, which is a voltage comparison circuit, compares the voltage between + 24V and the reference voltage, or compares the voltage between + 12V and the reference voltage, and outputs the comparison result. This comparison result shows that when no power failure or instantaneous power failure occurs, the logic becomes HI and is input to the PR terminal which is the preset terminal of the D-type flip-flop MIC22, while when a power failure or instantaneous power failure occurs. The logic becomes LOW and is input to the PR terminal which is a preset terminal of the D-type flip-flop MIC22.

  In the electric power clear process, first, output of a power outage clear signal is started to the power outage monitoring circuit 4100e, thereby starting output of the power outage clear signal to the CLR terminal which is a clear terminal of the D-type flip-flop MIC22. This power failure clear signal is input from the output terminal of the predetermined output port of the main control MPU 4100a to the CLR terminal which is the clear terminal of the D-type flip-flop IC via the main control output circuit 4100ca with a reset function by setting the logic to LOW. Is done. As a result, the main control MPU 4100a can release the latch state of the D-type flip-flop MIC22. It can be inverted and output from the 1Q terminal, which is the output terminal, and the signal from the 1Q terminal can be monitored.

  Subsequently, in the electric power clear process, a wait timer process is performed to determine whether or not a power failure notice signal is input. The voltage does not increase immediately from when the power is turned on until the voltage reaches the predetermined voltage. On the other hand, when there is a power failure or a momentary power failure (a phenomenon in which the supply of power is temporarily stopped), when the voltage drops and becomes lower than the power failure warning voltage, a power failure warning signal is input as a power failure warning from the power failure monitoring circuit 4100e. Similarly, if the voltage becomes lower than the power failure warning voltage from when the power is turned on until it reaches the predetermined voltage, a power failure warning signal is input from the power failure monitoring circuit 4100e. Therefore, in the wait timer process, after the power is turned on, the process waits until the voltage becomes larger than the power failure warning voltage and stabilizes. In this embodiment, 200 milliseconds (ms) is set as the wait time (wait timer). Has been. Whether or not the power failure warning signal is input is determined based on the signal output from the 1Q terminal that is the output terminal of the D-type flip-flop MIC22 as the power failure warning signal.

  If the power failure warning signal is not input even after waiting for the voltage to become larger than the power failure warning voltage and stabilize after the power is turned on, the main control program sends a power failure clear signal to the CLR terminal which is the clear terminal of the D-type flip-flop MIC22. Stop output. Here, the power failure clear signal is output from the output terminal of a predetermined output port of the main control MPU 4100a, the logic is HI, and the CLR terminal which is the clear terminal of the D-type flip-flop IC via the main control output circuit 4100ca with reset function. Is input. As a result, the main control MPU 4100a can set the D-type flip-flop MIC22 to the latched state. When the D-type flip-flop MIC22 latches the state in which the logic is LOW and is input to the PR terminal which is the preset terminal, the D-type flip-flop MIC22 outputs a power failure warning signal from the 1Q terminal which is the output terminal.

  Subsequent to step S14, the main control program makes a state in which RAM clear processing for initializing the main control built-in RAM (game storage unit) can be executed for a predetermined time from when the power is turned on (when the game side power is turned on). Operation control means). Specifically, the main control program first determines whether or not the operation switch 860a of the payout control board 4110 shown in FIG. 13 is operated (step S16). In this determination, the main control program inputs an error release navigation command (first error release command) based on an operation signal (detection signal) associated with the operation switch 860a of the payout control board 4110 being operated to the main control MPU 4100a. Depending on whether or not it is done. Based on the logic value of the operation signal, the main control program determines that the RAM is not instructed to be cleared when the logic value of the operation signal from the operation switch 860a is HI. On the other hand, when the logical value of the operation signal from the operation switch 860a is LOW, it is determined that the instruction to perform the RAM clear is made and it is determined that the operation switch 860a is operated.

  In step S16, when the operation switch 860a is operated, the main control program sets a value 1 to the RAM clear notification flag RCL-FLG (step S18). On the other hand, when the operation switch 860a is not operated in step S16, the main control program sets the RAM clear notification flag RCL-FLG to 0 (step S20). That is, the main control program can execute a RAM clear process that initializes the RAM (that is, the main control built-in RAM (game storage unit)) built in the main control MPU 4100a for a predetermined time from the time when the power is turned on. State (game control side power-on operation control means). The RAM clear notification flag RCL-FLG described above is stored in the main control built-in RAM (game storage unit) of the main control MPU 4100a, and game information related to games such as probability variation, unpaid out prize balls, and other information (for example, , A flag indicating whether or not to delete various information including information indicating the value of the main prize ball number information output determination counter). Value 1 when deleting various information, value 0 when not deleting various information Respectively. Note that the value of the RAM clear notification flag RCL-FLG set in step S18 and step S20 is stored in the general-purpose storage element (general-purpose register) of the main control MPU 4100a.

  Subsequent to step S18 or step S20, the main control program performs a wait time standby process (step S22). In this wait time waiting process, the liquid crystal and sound control unit 4160 of the peripheral control board 4140 shown in FIG. Wait until the system that controls drawing starts (boots). In this embodiment, 2.5 seconds (s) is set as a standby time (boot timer) until booting.

  Subsequent to step S22, the main control program determines whether or not a power failure notice signal is input (step S24). As described above, when the power of the pachinko gaming machine 1 is shut off, or when a power failure or a momentary power failure occurs, a power failure notice signal is input from the power failure monitoring circuit 4100e as a power failure notice if the voltage falls below the power failure notice voltage. The determination in step S24 is made based on this power failure notice signal. When there is a power failure warning signal input in the determination in step S24, the main control program returns to the determination in step S24 again, and repeats the determination in step S24 as long as the power failure warning signal continues to be input. As a result, the timer clear setting value is set in the WDT clear register built in the main control MPU 4100a for the main control built-in WDT 4100af activated in step S12, the time measurement by the main control built-in WDT 4100af is cleared, and the time measurement is started again. The main control MPU 4100a is forcibly reset by the built-in main control WDT 4100af. Thereafter, the main control program performs this main control side power-on process again under the control of the main control MPU 4100a of the main control board 4100. A detailed description will be given later on that the determination in step S24 is performed following the wait time waiting process in step S22.

  When the power failure warning signal is not input in the determination in step S24, the main control program determines whether or not the RAM clear notification flag RCL-FLG is 0 (step S26). As described above, the RAM clear notification flag RCL-FLG is set to a value 1 when various information is erased and a value 0 when various information is not erased. When the RAM clear notification flag RCL-FLG is 0 in step S26, that is, when various information is not deleted, a checksum is calculated (step S28). This checksum is calculated by considering various information stored in the main control built-in RAM as numerical values.

  Subsequent to step S28, the main control program calculates the checksum value (sum value) stored in the main-control-side power-off process (power-off) described later and the calculated checksum value (sum value). It is determined whether or not they match (step S30). If they match, the main control program determines whether or not the backup flag BK-FLG is 1 (step S32). The backup flag BK-FLG stores game information such as various information, checksum value (sum value) and backup flag BK-FLG in the main control built-in RAM in the main control side power-off process described later. This flag is set to a value of 1 when the main control-side power-off process is normally terminated, and a value of 0 when the main-control-side power-off process is not terminated normally. In the inspection process of the production line of the main control board 4100, when the main control board 4100 is first turned on after being manufactured for inspection, the checksum is calculated in step S28, and the determination is made in step S30. A detailed description will be given later.

  When the backup flag BK-FLG has a value of 1 in step S32, that is, when the main control side power-off process has been normally terminated, the main control program sets the work area of the main control built-in RAM as the power is restored ( Step S34). In this setting, power recovery time information is read from a ROM (that is, main control internal ROM) built in the main control MPU 4100a, and the power recovery time information is set in the work area of the main control built-in RAM. Thereby, various information is read from the game backup information, and various commands corresponding to the various information are stored in a predetermined storage area of the main control built-in RAM. Note that “power recovery” refers to a state in which the power is turned on after being turned off, a state in which power is restored after a power outage or a momentary power failure, and unauthorized means (for example, an unauthorized person is placed on the skirt of his arm). A state in which the main control board 4100 is irradiated with a high frequency from the hidden high-frequency output device) and the main control MPU 4100a itself is reset and then restored is also included.

  Subsequent to step S34, the main control program sets a value 0 to the backup flag BK-FLG (step S36). As a result, various information, checksum value (sum value), and the like are changed by performing various processes thereafter. Therefore, the main control-side power-off process described later is terminated normally and the backup flag BK- If the value 1 is not set in FLG, as will be described later, the entire area of the main control built-in RAM is cleared.

  On the other hand, when the RAM clear notification flag RCL-FLG is not 0 (value 1) in step S26, that is, when various information is deleted, or when the checksum value (sum value) does not match in step S30. Alternatively, when the backup flag BK-FLG is not a value 1 (value 0) in step S32, that is, when the main control side power-off process has not been terminated normally, the main control program stores all the main control built-in RAM. The area is cleared (step S38). That is, the main control program executes the game control side RAM clearing process triggered by the input of the detection signal accompanying the operation of the operation switch 860a described above (payout control side power-on operation control means). Specifically, the main control program is executed by writing the value 0 in the main control built-in RAM. Alternatively, the main control program may read and set a predetermined value from the main control built-in ROM as an initial value. Further, the main control MPU 4100a instructs the RAM clear of the operation signal from the operation switch 860a, erases various information, does not match the sum value, or performs a process when the main control side power is cut off. When not finished normally, a unique ID code stored in the nonvolatile RAM of the main control MPU 4100a is taken out, and a fixed numerical value range of a counter that updates a random number for normal symbol determination based on the taken out ID code The initial value derivation process for always deriving the same fixed value from is performed, and this fixed value is set as the normal value determining random number for determining the initial value for the normal symbol determining random value described above. To do.

  Subsequent to step S38, the main control program sets a work area of the main control built-in RAM as an initial setting (step S40). This setting is performed by reading the initial information from the main control built-in ROM and setting the initial information in the work area of the main control built-in RAM. Thereby, the game backup information is initialized, and for example, the value of the main prize ball number information output determination counter is set (set) to the initial value 0 (zero).

  Subsequent to step S36 or step S40, the main control program performs interrupt initialization (step S42). This setting is to set an interrupt cycle when a main control timer interrupt process described later is performed. In this embodiment, it is set to 4 milliseconds (ms).

  Subsequent to step S42, the main control program performs serial communication initial setting (step S44). Here, various serial input / output ports (for example, serial input / output ports (reception channels and transmission channels) for the payout control board 4110) and serial input / output ports (reception channels and transmission channels) for the peripheral control board 4140 are incorporated in the main control MPU 4100a. ) Corresponding to the transmission serial port prescaler, the transmission speed is set and the parity is set, and the transmission serial port control register is set to initialize the transmission circuit and set transmission permission.

  Subsequent to step S44, the main control program performs test signal output port initialization settings (step S46). Here, a test signal output port (not shown) for outputting various types of inspection information is initialized (set to OFF data output) when the power is turned on in the testing institution of the gaming machine.

  Subsequent to step S46, the main control program performs activation setting of the main random number circuit 4100an with built-in main control shown in FIG. 12 (step S48). Here, among the various random numbers related to the game, a hard random number control register built in the main control MPU 4100a for updating by hardware the random number for determining the big hit for use in determining whether or not to generate the big hit gaming state In addition, a setting such as latching and acquiring a random number is set, and activation of the hard random number circuit 4100an with built-in main control is set in the hard random number setting register. When the main control built-in hard random number circuit 4100an is activated by these settings, it is predetermined in advance at high speed based on the clock signal (clock signal output from the main control crystal oscillator MX0 shown in FIG. 21) input to the main control MPU 4100a. Extract other values in the numerical range one after another without duplication, and once all the values in the predetermined numerical range have been extracted, again extract one value in the predetermined numerical range, Based on the clock signal input to the main control MPU 4100a, other values within a predetermined numerical range are extracted one after another without overlapping. When the main control MPU 4100a acquires a random number (random number value) from the main random number 4100an with built-in main control, it outputs a latch signal to the main random number circuit 4100an with main control, and the main control when this latch signal is input. The random number (random number value) extracted by the built-in hard random number circuit 4100an is obtained from a hard random number latch register built in the main control built-in main control MPU 4100a. The main control MPU 4100a sets the acquired random number value as a jackpot determination random number.

  Subsequent to step S48, the main control program performs reservation setting for a command to be transmitted when the power is turned on (step S50). Here, in order to notify that the power is turned on (power recovery) based on the power recovery time information set in the work area of the main control built-in RAM in the setting of the work area of the main control built-in RAM in step S34, FIG. Main control built-in RAM as transmission information by creating the power-on status command, the power-on main control return destination command, and the power-on main prize ball number information output determination counter notification command shown in Stored in the transmission information storage area. In the transmission information storage area of the main control built-in RAM, in the setting of the work area of the main control built-in RAM in step S34, various commands are read from the game backup information and various commands corresponding to the various information are stored. is there. In such a case, first after completion of transmission of various commands according to game information among various information, then power-on status command, power-on main control return destination command, and power-on main prize ball number information An output determination counter notification command is transmitted. These commands are transmitted in the main control side timer interrupt processing described later. A detailed description will be given later of reservation setting of a command to be transmitted at power-on in step S50.

  Subsequent to step S50, the main control program performs interrupt permission setting (step S52). With this setting, the main control side timer interrupt processing described later is repeated every interrupt cycle set in step S42, that is, every 4 ms.

  Subsequent to step S52, the main control program executes an error canceling navigation command associated with the operation of the operation switch 860a (operation switch) when a predetermined time elapses from when the power is turned on, that is, when the main process on the main control side is started. Execution of the game control side RAM clear process triggered by the reception will be restricted (normal operation control means). As described above, the main control program uses the error sharing navigation command for a predetermined time from the time of power-on as described above, based on the concept of time sharing, based on the concept of time sharing. When the input is triggered, the RAM clear process is executed (game control side power-on operation control means), and after the predetermined time has elapsed, the execution of the RAM clear process is restricted even if the error canceling navigation command is input ( The game control side normal operation control means) is handled as a release switch for releasing the error notification associated with the error that has occurred. In other words, the operation switch 860a (error release unit) that should have been used to release an error that has occurred in relation to the payout operation is used as a game storage unit instead of a predetermined time after the power is turned on. The main control built-in RAM (and a payout control built-in RAM as a payout storage unit to be described later) functions as an operation unit for executing a RAM clear process for starting initialization, and after the predetermined time has elapsed, It can function as an operation unit for canceling an error that has occurred with respect to the ball dispensing operation.

  Next, the main control program determines whether or not a power failure notice signal is input (step S54). As described above, when the power of the pachinko gaming machine 1 is shut off, or when a power failure or a momentary power failure occurs, a power failure notice signal is input from the power failure monitoring circuit 4100e as a power failure notice if the voltage falls below the power failure notice voltage. The determination in step S54 is made based on this power failure notice signal.

  When no power failure warning signal is input in step S54, the main control program performs a non-winning random number update process (step S56). In the non-winning random number update process, the above-described reach determination random number, variable display pattern random number, big hit symbol initial value determining random number, small hit symbol initial value determining random number, and the like are updated. In this way, in the non-winning random number update process, random numbers that are not involved in the winning determination (big hit determination) are updated by software. It should be noted that the above-described random numbers for normal symbol determination, random numbers for initial value determination for normal symbol determination, random numbers for normal symbol variation display pattern, and the like described above are also updated by this non-winning random number update process.

  Subsequent to step S56, the process returns to step S54 again, and the main control program determines whether or not a power failure warning signal is input. Step S54 to Step S56 are repeated. The processes in steps S54 to S56 are referred to as “main control side main process”.

  On the other hand, when a power failure warning signal is input in step S54, the main control program performs interrupt prohibition setting (step S58). With this setting, the main control side timer interrupt processing described later is not performed, writing to the main control built-in RAM is prevented, and rewriting of various information including game information and other information described above is protected.

  Subsequent to step S58, the main control program starts outputting a power failure clear signal (step S60). Here, the same process as the process that started outputting the power failure clear signal in the power failure clear process in step S14 is performed. Thus, the main control program can release the latched state of the D-type flip-flop MIC22 under the control of the main control MPU 4100a.

  Subsequent to step S60, the main control program is shown in FIG. The drive signals output to the symbol memory display 1187, the normal symbol display 1189, the normal symbol memory display 1188, the game state display 1183, the round display 1190, etc. are stopped (step S62).

  Subsequent to step S62, the main control program calculates a checksum and stores the calculated value (step S64). This checksum is calculated by regarding the game information in the work area of the main control built-in RAM as a numerical value excluding the storage area for the checksum value (sum value) and backup flag BK-FLG described above.

  Subsequent to step S64, the main control program sets a value 1 to the backup flag BK-FLG (step S66). Thereby, storage of game backup information is completed.

  Subsequent to step S66, the main control program sets the RAM access prohibition (step S68). This RAM access prohibition setting prevents access to the main control built-in RAM (game storage unit), thereby preventing the contents of the main control built-in RAM (game storage unit) from being updated.

  Following step S68, an infinite loop is entered. In this infinite loop, the timer clear setting value is set in the WDT clear register built in the main control MPU 4100a for the main control built-in WDT 4100af activated in step S12, the time measurement by the main control built-in WDT 4100af is cleared, and the time measurement is started again. As a result, the main control MPU 4100a is forcibly reset by the main control built-in WDT 4100af. Thereafter, the main control program performs this main control side power-on process again under the control of the main control MPU 4100a of the main control board 4100. The processing from step S58 to step S68 and the infinite loop are referred to as “main control side power-off processing”.

  The pachinko gaming machine 1 (main control MPU 4100a) is reset when a power failure occurs or when an instantaneous power failure occurs, and performs power-on processing on the main control side by subsequent power recovery.

  In step S30, it is checked whether or not the game backup information stored in the main control built-in RAM is normal. Subsequently, in step S32, whether or not the main control side power-off process has been normally completed. Are inspected. In this way, by checking the game backup information stored in the main control built-in RAM twice, it is checked whether or not the game backup information is stored by an illegal act.

  Here, the point where the presence / absence of the power failure notice signal in step S24 is determined following the wait time waiting process in step S22 will be described. First, when there is no determination of the presence or absence of a power failure warning signal in step S24, that is, when the value of the RAM clear flag in step S26 is determined following the wait time waiting process in step S22, and the subsequent processing is performed. The problems in will be described.

  As described above, the power supply terminal of the main control MPU 4100a is charged to the electrolytic capacitor MC2 shown in FIG. 21 when a power failure or a momentary power failure occurs and the power supply from the pachinko island facility is cut off. The electric charge is applied as +5 V for a period of about 7 milliseconds (ms) after the occurrence of a power failure or a momentary power failure. In other words, even when the power supply from the Pachinko island facility is shut off due to a momentary power failure or a power failure, the electric charge charged to the hardware called the electrolytic capacitor MC2 is applied as +5 V, so that the power supply from the pachinko island facility is The main control side power-off process can be completed within a period from when the power is shut off until about 7 ms elapses. This is because when a player is playing a game, that is, when the main control side main process or the main control side timer interrupt process described later is performed, a power failure or a momentary power failure occurs and the pachinko island facility When the power is cut off, the main control side power-off process can be completed with certainty.

  However, as an extremely rare phenomenon, in the wait time waiting process of step S22 at the time of power recovery, the game board side liquid crystal display device 1900 and the movable liquid crystal display device by the liquid crystal and sound control unit 4160 of the peripheral control board 4140 shown in FIG. A waiting time (boot timer: 2.5 seconds is set in this embodiment) until the system that performs drawing control of 1925a to 1925d and the upper plate side liquid crystal display device 470 starts (boots). If a momentary power failure or a power failure occurs just before the timing starts and the standby time is reached, the electric charge charged to the hardware called the electrolytic capacitor MC2 is applied to the VDD terminal, which is the power supply terminal of the main control MPU 4100a, as + 5V. , Interrupt initialization is performed in step S42 within a period of about 7 ms, and then step S5 The main control side power interruption process in the main control side power-on process is performed even if the main control side timer interrupt process described later is performed and the contents of the main control built-in RAM are updated. May not be able to complete. For this reason, the main control side power-on process is started again at the time of power recovery without storing the calculated value of the checksum based on the contents of the main control built-in RAM.

  Then, the main control side power-on process is started at the time of the current power recovery, and the wait time waiting process in step S22 is completed without causing an instantaneous power failure or a power failure. Thereafter, in step S28, the main control built-in RAM If the value calculated in the checksum based on the contents of the checksum is compared with the value stored in the main control built-in RAM immediately before the instantaneous power failure or power failure occurs in step S30, the checksum value should match. In step S38, the entire area of the main control built-in RAM is cleared. In other words, even if the operation switch 860a is operated by the hall clerk at the time of power recovery and the intention of the hall clerk such as RAM clear is not indicated, the game backup information described above is forcibly stored in the main control built-in RAM. There is a problem that will be erased.

  Therefore, in this embodiment, immediately after the wait time waiting process in step S22, a process for determining whether or not a power failure warning signal is input is provided as step 24, and when a power failure warning signal is input, Returning to the determination in step S24, the determination in step S24 is repeatedly performed as long as the power failure warning signal continues to be input. As a result, the timer clear setting value is set in the WDT clear register built in the main control MPU 4100a for the main control built-in WDT 4100af activated in step S12, the time measurement by the main control built-in WDT 4100af is cleared, and the time measurement is started again. Therefore, the main control MPU 4100a can be forcibly reset by the main control built-in WDT 4100af. Although the RAM clear notification flag RCL-FLG is set to a value in the RAM clear notification flag RCL-FLG in step S18 or step S20 before the wait time waiting process in step S22, the value of the RAM clear notification flag RCL-FLG is as described above. Since it is stored in the general-purpose storage element (general-purpose register) of the control MPU 4100a, even if the RAM access permission is set in step S10, the contents (game information) of the main control built-in RAM are not changed at all.

  In this way, immediately after the wait time waiting process in step S22, a process for determining whether or not a power failure warning signal is input is provided as step 24, and when a power failure warning signal is input (ie, step If the power to the pachinko gaming machine 1 is cut off after waiting in the wait time waiting process of S22 (when determined by the determination of step S24), the process returns to the determination of step S24 again as long as the power failure warning signal continues to be input. By repeating the determination of step S24, the main control MPU 4100a of the main control board 4100 can be forcibly reset and the main control board 4100 can be restarted. Game information and other information (for example, the value of the main prize ball number information output determination counter) It is possible to prevent the various kinds of information including to information, etc.) is updated, so that never change occurs in the checksum calculation result. Thereby, when restarting, the main control MPU 4100a of the main control board 4100 determines that the checksum calculation result in step S28 matches the checksum calculation value stored in step S64. Therefore, the game information that is stored and held in the main control built-in RAM is not initialized immediately before a momentary power failure or power failure occurs. Therefore, at the time of power recovery, it is possible to prevent the game information immediately before the occurrence of a momentary power failure or a power failure from being initialized.

  Further, immediately after the wait time waiting process in step S22, a process for determining whether or not a power failure warning signal is input is provided as step 24, and when a power failure warning signal is not input (that is, in step S22). When the main control MPU 4100a of the main control board 4100 is proceeding with the game (when it is determined by the determination in step S24 that the power to the pachinko gaming machine 1 is not cut off after waiting in the wait time waiting process) Even if the power supply to the gaming machine 1 is cut off, game information and other information by the progress of this game are supplied to the VDD terminal, which is the power supply terminal of the main control MPU 4100a, by the power supply by the electrolytic capacitor MC2 shown in FIG. (For example, information indicating the value of the main prize ball number information output determination counter, etc.) is stored. Because the main control MPU 4100a of the main control board 4100 can complete the main control side power-off process constituted by the process of step S58 to step S68 and the infinite loop that is the backup process for When the main control MPU 4100a of the main control MPU 4100a is restarted, the checksum calculation result in step S28 and the checksum calculation result in the backup process (that is, the checksum calculation value stored in step S64) are displayed. Since it is determined that they match, the game information that is stored and held in the main control built-in RAM is not initialized immediately before a momentary power failure or power failure occurs. That is, the main control board 4100 can be activated by being restored to the game information immediately before the momentary power failure or power failure occurs.

  Further, immediately after the wait time waiting process in step S22, when it is determined in step S24 that a power failure warning signal has been input, the main control MPU 4100a is forcibly reset by the main control built-in WDT 4100af so that the contents of the main control built-in RAM The main control side power-off process can be started again without updating the process at all. On the other hand, immediately after the wait time standby process in step S22, if it is determined in step S24 that the power failure warning signal has not been input, As a result, it is possible to reliably complete the main control side power-off process within the “instantaneous power failure or power failure securing period” of about 7 ms. That is, in the present embodiment, when the main control side power-on process is performed at the time of power recovery, a power failure from the pachinko island facility is interrupted due to an instantaneous power failure or a power failure, and the main control MPU 4100a The electric charge charged in the electrolytic capacitor MC2 shown in FIG. 21 is applied to the VDD terminal, which is a power supply terminal, as +5 V over a period of about 7 milliseconds (ms) after the occurrence of a power failure or a momentary power failure. Therefore, if the main control-side power-off process cannot be completed within the “instantaneous power failure or power supply securing period” of about 7 ms by the hardware of the electrolytic capacitor MC2, the wait time waiting process of step S22 is performed. In step 24 immediately after that, it is determined whether or not a power failure warning signal is input. If a power failure warning signal is input, step S24 is performed. Returning to the determination again, as long as the power failure warning signal continues to be input, the determination in step S24 is repeated to clear the timer in the WDT clear register built in the main control MPU 4100a with respect to the main control built-in WDT 4100af activated in step S12. The main control MPU 4100a can be forcibly reset by the main control built-in WDT 4100af by setting the set value and clearing the time measured by the main control built-in WDT 4100af and making it impossible to start the time measurement again. . The main control MPU 4100a is forcibly reset by such software built-in main control WDT 4100af, so that the step after step S24 (specifically, interrupt initialization is performed in step S42, and then in step S52). The contents of the main control built-in RAM (game information, and other information (for example, the number of main winning balls) are set by interrupt permission to prevent progress to the main control side timer interrupt processing described later. A mechanism is adopted in which it is possible to avoid updating various information) including information indicating information output determination counter values). Thus, when a power failure or a momentary power failure occurs and the power supply from the pachinko island facility is shut off, the contents of the main control built-in RAM (game information and other information (for example, main prize ball number information output determination counter) The various information including the information indicating the value of the data) is covered by software so that it will not be changed at all, and the contents of the main control built-in RAM (game information, and other The information (for example, various information including information indicating the value of the main prize ball number information output determination counter) is divided into two parts that are covered by hardware so that the information is not changed at all. It is possible to reliably prevent the contents of the control built-in RAM (game information and other information (for example, various information including the value of the main prize ball number information output determination counter)) from being changed. It has been cut way.

  Next, a description will be given of the reservation setting of the command to be transmitted when the power is turned on in step S50. In step S50, as described above, the fact that the power has been turned on (recovered) based on the power recovery time information set in the work area of the main control built-in RAM in the setting of the work area of the main control built-in RAM in step S34. In order to communicate, a power-on state command, a power-on main control return destination command, and a power-on main prize ball number information output determination counter notification command shown in FIG. Information is stored in the transmission information storage area of the main control built-in RAM. As described above, the power-on main control return destination command mainly includes information for instructing the driving state of the start-up solenoid 2105 and information for instructing the driving state of the attacker solenoid 2108 shown in FIG. Yes. In this case, first, when the power-on main control return destination command does not include the information for instructing the driving state of the start solenoid 2105 and the information for instructing the driving state of the attacker solenoid 2108 shown in FIG. The problem in the case where the reservation setting of the command to be transmitted when the power-on main control return destination command is turned on in step S50 is not performed in step S50 will be described.

  For example, when the peripheral control board 4140 controls the display of the big hit game state screen (for example, the big hit game effect screen) in the display area of the game board side liquid crystal display device 1900 shown in FIG. When the attacker solenoid 2108 is driven and the large winning opening 2103 shown in FIG. 8 is opened by the opening / closing member 2107, an instantaneous power failure or power failure occurs, and then the power is restored, the main control board 4100 Based on the power recovery time information set in the work area of the main control built-in RAM in the setting of the work area of the main control built-in RAM in S34, the game state immediately before the occurrence of a momentary power failure or power failure is restored. The drive of the solenoid 2108 is started, and the state where the special winning opening 2103 is closed by the opening / closing member 2107 is changed to the opened state; That.

  However, when a momentary power failure or a power failure occurs, the peripheral control board 4140 receives various commands from the main control board 4100 and returns when power is restored. Then, when the power is restored thereafter, the peripheral control board 4140 can return based on the probability indicated by the power-on state command received from the main control board 4100 at the time of power restoration and the short-time state. However, when the main control board 4100 is generating a big hit gaming state as a gaming state, if an instantaneous power failure or a power failure occurs, and then power is restored, the peripheral control board 4140 is in the main control board 4100 when power is restored. Even if the screen can be displayed in the display area of the game board side liquid crystal display device 1900 and returned based on the probability and the short time state based on the probability and the short time state indicated by the power-on state command received from It is not possible to indicate at all which round of the jackpot gaming state. In other words, for example, a prize winning port 1 count display command for transmitting the number of gaming balls detected by the count switch 2110 shown in FIG. Even if the main control board 4100 transmits to the peripheral control board 4140 and the peripheral control board 4140 receives the peripheral control board 4140, the peripheral control board 4140 has a game ball ball that has entered the big winning opening 2103 on the screen according to the probability and the short time state. Even if the number can be displayed in the display area of the game board side liquid crystal display device 1900, it is not possible to display which round of the big hit gaming state (that is, how many rounds).

  In such a situation, for example, when the main control board 4100 finishes the fourth round (fourth round) in the big hit gaming state, the driving of the attacker solenoid 2108 is stopped and the big winning opening 2103 is opened by the opening / closing member 2107. From the main control board 4100 to the peripheral control board for instructing to shift from the closed state to the closed state (that is, closing start between rounds of the big prize opening 2103 of the attacker unit 2100). 4140, when the main control board 4100 starts the fifth round of the big hit gaming state (the fifth round), the attack solenoid 2108 starts to be driven and the big prize opening 2103 is closed by the opening / closing member 2107 To the state of being released from the state (that is, the big prize opening 2103 To send a special winning opening open the fifth display command instructing the open start) times th round from the main control board 4100 to the peripheral control board 4140. As a result, the peripheral control board 4140 finally switches the screen of starting five rounds of the big hit gaming state from the screen corresponding to the above-described probability and short time state, and displays it on the display area of the game board side liquid crystal display device 1900. Become.

  In addition, for example, a screen (for example, a game indicating that the movable piece has been expanded) indicating that the gaming state is such that the gaming ball can be received at the lower start port 2102 and the gaming state is advantageous to the player. When the peripheral control board 4140 controls the display on the display area of the game board side liquid crystal display device 1900, the main control board 4100 drives the start port solenoid 2105 to display the pair of screens shown in FIG. When a momentary power failure or a power failure occurs when the movable piece 2106 is expanded in the left-right direction and then power is restored, the main control board 4100 displays the work area of the main control built-in RAM in step S34. Based on the power recovery information set in the work area of the main control built-in RAM in the setting, the driving state of the start port solenoid 2105 is opened by being restored to the gaming state immediately before the momentary power failure or power failure occurs. And thus the transition to a state of being expanded from a pair of the movable piece 2106 is up standing substantially perpendicularly to the lateral direction by.

  However, when a momentary power failure or a power failure occurs, the peripheral control board 4140 receives various commands from the main control board 4100 and returns when power is restored. When power is restored thereafter, the peripheral control board 4140 can be restored based on the power-on state command received from the main control board 4100 at the time of power restoration. However, when the main control board 4100 is in a gaming state and a gaming state in which a gaming ball can be received in the lower start port 2102 is generated and a gaming state advantageous to the player is generated, a momentary power failure or power failure occurs. Then, when the power is restored, the peripheral control board 4140 plays the screen according to the probability and the time-short state based on the probability and the time-short state indicated by the power-on state command received from the main control board 4100 when the power is restored. Even if it can be displayed in the display area of the board side liquid crystal display device 1900 and returned, it becomes a gaming state in which a gaming ball can be received in the lower start port 2102 and is in a gaming state advantageous to the player. The peripheral control board 4140 cannot display the display screen on the display area of the game board side liquid crystal display device 1900 at all. For this reason, a player sitting in front of a pachinko machine is surprised that a momentary power failure or a power failure has occurred, and when the power is restored, the game ball is received at the lower start port 2102 immediately before the momentary power failure or power failure occurs. In some cases, it is forgotten that the game state is enabled. In such a case, the game state at the time of power recovery is returned to the game state where the game ball can be received at the lower start port 2102. Nevertheless, when the power is restored, a screen for instructing a game in the display area of the game board side liquid crystal display device 1900 (that is, a screen for instructing a game to enter a game ball into the lower start port 2102) is not displayed. There is also a problem that the player does not know what kind of game he plays.

  As described above, in the two examples described above, there is a problem that it is not possible to quickly return to the gaming state immediately before the instantaneous power failure or the power failure after the power is restored. In other words, a player who sits in front of a pachinko gaming machine appears to be in a state where the system of the pachinko gaming machine is clumped, a so-called frozen state, when a power failure occurs after a momentary power failure or power failure, There was a problem of misunderstanding.

  Therefore, in the present embodiment, when the main control board 4100 is turned on (including when the power is turned on, and also when the power is restored due to a power failure or a momentary power failure), the power-on state command In order to transmit the power-on main control return destination command to the peripheral control board 4140, in step S50, the power-on state command and power-on main control return destination command shown in FIG. Then, a counter notification command for determining the main prize ball number information output at power-on is created and stored as transmission information in the transmission information storage area of the main control built-in RAM. These commands are transmitted in a main control timer interrupt process described later.

  Thereby, the peripheral control board 4140, for example, in the above-described example, in the four rounds of the big hit gaming state, based on the power-on state command and the power-on main control return destination command received from the main control board 4100. When a momentary power failure or power failure occurs, and then the power is restored, as the return destination of the main control board 4100, the attacker solenoid 2108 starts to be driven and the special winning opening 2103 is released from the state closed by the opening / closing member 2107. The peripheral control board 4140 can tell the peripheral control board 4140 that it is to shift to the current state, so that the peripheral control board 4140 has specified that it is the fourth round of the big hit gaming state (that is, a screen showing how many rounds it is) ) Cannot be displayed in the display area of the liquid crystal display device 1900 on the game board side, A screen (for example, “It is a big hit. The big prize opening is open. A game is played in the big prize opening is displayed.) The driving of the casoleole 2108 is started and the big prize opening 2103 is opened by the opening / closing member 2107. Play the game to make the ball enter the player. ”Is displayed on the display area of the liquid crystal display device 1900 on the game board side, and the player who sits in front of the pachinko machine is restored. It is possible to instruct the game to enter the game ball into the grand prize opening 2103 after the electric train. For example, in the above-described example, the game state is such that the game ball can be received at the lower start port 2102. When a momentary power failure or power failure occurs in a game state advantageous to the user and then power is restored, the start port solenoid 210 is used as a return destination of the main control board 4100. A screen (for example, “The movable piece is widened. A game ball is inserted into the lower start opening.” The peripheral control board 4140 displays on the display area of the liquid crystal display device 1900 on the game board side and displays the message “Please play the game to the player” to the player sitting on the front of the pachinko gaming machine. It is possible to instruct the game to enter the game ball into the lower start port 2102 after power is restored. Thereby, when a power failure occurs or a power failure occurs and then power is restored, the return destination of the peripheral control board 4140 can be finely instructed on the main control board 4100 side. Therefore, it is possible to quickly return to the gaming state immediately before the momentary power failure or power failure after the power recovery. In other words, a player who sits in front of a pachinko gaming machine appears to be in a state where the system of the pachinko gaming machine is clumped, a so-called frozen state, when a power failure occurs after a momentary power failure or power failure, Misunderstanding can be prevented.

  Next, in the main control board inspection process, which is an inspection process for the production line of the main control board 4100, when the main control board 4100 is first turned on after being manufactured for inspection, Calculation and determination in step S30 will be described. In the main control board inspection process, when the main control board 4100 is turned on for the first time after being manufactured for inspection, the main control board is configured by the above-described processes of steps S58 to S68 which are backup processes and an infinite loop. Since the main control MPU 4100a of the main control board 4100 has never executed the control-side power-off process, even if the checksum based on the contents of the main control built-in RAM is calculated in step S28, in step S30. In the comparison determination, the checksum values cannot be matched, and the entire area of the main control built-in RAM is always cleared in step S38. As a result, when the reservation setting of the command to be transmitted at power-on is performed in step S50, the power-on state command, power-on main control return destination command, and power-on time shown in FIG. By creating a counter notification command for main prize ball number information output determination and storing it as transmission information in the transmission information storage area of the main control built-in RAM, a power-on status command, a power-on main control return destination command, and a power Only three commands, the counter notification command for main prize ball number information output determination at the time of insertion, are stored in the transmission information storage area of the main control built-in RAM as transmission information. In these main control side timer interrupt processing, which will be described later, first, a power-on state command is transmitted, followed by a power-on main control return destination command, followed by a power-on main prize ball number. An information output determination counter notification command is transmitted. Using this, in the main control board inspection process, when the main control board 4100 is first turned on after manufacturing for inspection, the power-on state command is sent from the main control board 4100 as the first command. It is transmitted to the inspection device in the main control board inspection process.

  By the way, as described above, the power-on state command is shown in FIG. 13 when the power is turned on (including when the power is turned on and when the power is restored by a power failure or a momentary power failure). When the operation switch 860a of the payout control board 4110 shown in the figure is operated to clear the RAM, information indicating that and when the power is turned on (in addition to when the power is turned on, a power failure or a momentary power failure occurs, (Including the time of recovery to recover)) In any of the above states (probability and short-time state) among the low-probability short-time state, high-probability short-time state, low-probability non-short-time state, and high-probability non-short-time state Information indicating whether or not to perform, and information indicating a model code of the pachinko gaming machine. Here, a problem in the case where the power-on state command does not include information indicating the model code of the pachinko gaming machine will be described.

  As described above, the model code of the pachinko gaming machine is the type of pachinko gaming machine 1 (to be precise, the main control board 4100) which is created when each of the so-called max type, middle type and sweet digital type is created. What kind of gaming specifications (for example, if the probability change occurs, the game will continue until the next big hit gaming state occurs, and the number of special symbol changes is limited ( For example, it is possible to specify whether the game specification (so-called ST machine) in which the probability variation occurs in the state of 30 times or 70 times))).

  In the production line of the manufacturer that manufactures the pachinko gaming machine 1, when the main control board 4100 is manufactured, the main control board 4100 for the copyrights of a plurality of types of works may be mixed. Then, the worker on the production line is responsible for the copyright of which work among the copyrights of a plurality of kinds of works (for example, the copyrights of the works of movie A, movie B, drama C, movie D, comic E, and comic F). It is difficult to know whether the main control board 4100 is flowing to the production line in order to manufacture the control board 4100, or the main control board for one copyright (for example, the copyright of the movie D) among a plurality of types of works. Although the main control board 4100 flows to the production line to manufacture the 4100, the main control board 4100 is used to manufacture the main control board 4100 for another copyright (for example, the copyright of the work of the comic F). There is also a misunderstanding and misunderstanding that it is flowing in the production line. For this reason, when manufacturing the main control board 4100 in the manufacturing line of the manufacturer that manufactures the pachinko gaming machine 1, if the main control boards 4100 for the copyrights of a plurality of types of works are mixed, the operator of the manufacturing line It is not possible to confirm which copyright of the work is the main control board 4100 manufactured in, and for any copyright of the same work, which model type (max type, middle type, sweet digital type, It is also not possible to confirm what type of game it is and what game specifications (game specifications or ST machines that will continue until the next jackpot gaming state occurs when probability changes occur) . Thus, when the main control board 4100 is manufactured in the production line of the manufacturer that manufactures the pachinko gaming machine 1 and the main control board 4100 for the copyrights of a plurality of types of works is mixed, the main control over the copyrights of the types of works is mixed. The board 4100 is mixed and sent to the game board assembly line for attaching the main control board 4100 to the game board 4. For this reason, the operator of the game board assembly line may attach the main control board 4100 that does not correspond to the game board 4 for the copyright of the work to the game board 4. As a result, there is a problem that the production efficiency of the game board 4 decreases.

  Therefore, in the present embodiment, when the main control board 4100 is turned on (including when the power is turned on, and also when the power is restored due to a power failure or a momentary power failure), the model of the pachinko gaming machine In order to transmit a power-on state command including information indicating a code to the peripheral control board 4140, in step S50, a power-on state command classified into power-on shown in FIG. A command and a main notice ball number information output determination counter notification command upon power-on are created and stored as transmission information in a transmission information storage area of the main control built-in RAM. These commands are transmitted in a main control timer interrupt process described later.

  Thereby, an operator of the manufacturing line of the manufacturer that manufactures the pachinko gaming machine 1 turns on the main control board 4100 in the main control board inspection process, which is the inspection process of the production line, so that the inspection apparatus can control the main control board. Based on the information indicating the model code of the pachinko gaming machine included in the power-on state command received from 4100, that is, constituting the information indicating the model code of the pachinko gaming machine, the above-described max type indicating the model type, A series code for specifying which type is a middle type or a sweet digital type, a copyright code for specifying the copyright of a work, and a game specification (for example, if a probability change occurs, the next jackpot In addition to the game specification that the state will continue until the game state occurs, the number of fluctuations of the special symbol is limited Based on a game specification code for specifying a game specification (ST machine, etc.) in which a probability variation occurs, the main control board 4100 determines which work piece the main control board 4100 displays by checking the detailed model information displayed on the inspection monitor. It is possible to determine whether it is for the copyright, and for the copyright of the same work, which model type (max type, middle type, and sweet digital type) and how It is also possible to determine whether the game specification is a game specification (a game specification or ST machine in which, if a probability change occurs, that state will continue until the next big hit gaming state occurs). Thereby, when manufacturing the main control board 4100 in the manufacturing line of the manufacturer that manufactures the pachinko gaming machine 1, even if the main control board 4100 for the copyrights of a plurality of types of works is mixed, the main control board inspection of the manufacturing line The operator of the process can determine the model type of the main control board 4100, the copyright of the work, and the game specifications accurately by visually checking the inspection monitor, so that the main control board 4100 with respect to the copyright of the work is sorted and followed. To the game board assembly line Then, the operator of the game board assembly line can securely attach the main control board 4100 corresponding to the game board 4 for the copyright of the work to the game board 4, and the main control board not corresponding to the game board 4 for the copyright of the work. It is possible to prevent the production efficiency of the game board 4 from being lowered due to the work of attaching 4100 to the game board 4. Therefore, it can contribute to the improvement of the production efficiency of the game board 4.

[15-3. Main control timer interrupt processing]
Next, the main control timer interrupt process will be described. This main control side timer interrupt process is repeated at every interrupt period (4 ms in this embodiment) set in the main control side power-on process shown in FIGS.

  When the main control side timer interrupt process is started, in the main control board 4100, the main control program switches the register banks as shown in FIG. 46 under the control of the main control MPU 4100a (step S100). The general-purpose storage element (general-purpose register) of the main control MPU 4100a has two register banks each composed of a first register bank and a second register bank. The first register bank is used in the main control main process in the main control side power-on process described above, while the second register bank is used in the main control side timer interrupt process which is this routine. In step S100, since the second register bank is used in the main control side timer interrupt processing which is this routine, the second register bank is used from the first register bank used in the main control main processing in the main control side power-on processing. The register bank is switched to the register tank. In the present embodiment, when the main control timer interrupt process, which is this routine, is started, the process of saving each register to the stack is not necessary.

  Subsequent to step S100, the main control program performs timer subtraction processing (step S102). In this timer subtraction process, for example, the time during which the upper special symbol display 1185 and the lower special symbol display 1186 are turned on in accordance with the variable display pattern determined in the special symbol and special electric accessory control processing described later, In addition to the time that the normal symbol display 1189 is turned on in accordance with the normal symbol variation display pattern determined in the normal electric accessory control process, the payout control substrate 4110 is normal for various commands transmitted by the main control board 4100 (main control MPU 4100a). When it is determined whether or not a payer ACK signal indicating that it has been received is input, time management such as an ACK signal input determination time set as a determination condition is performed. Specifically, when the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is 5 seconds, the timer interruption period is set to 4 ms. Therefore, every time this timer subtraction process is performed, the fluctuation time is subtracted by 4 ms. When the subtraction result is 0, the fluctuation time of the fluctuation display pattern or the normal symbol fluctuation display pattern is accurately measured.

  In this embodiment, the ACK signal input determination time is set to 100 ms. Each time this timer subtraction process is performed, the ACK signal input determination time is subtracted by 4 ms, and the result of the subtraction becomes 0, thereby accurately measuring the ACK signal input determination time. The various times and the ACK signal input determination time are stored as time management information in the time management information storage area of the main control built-in RAM.

  Subsequent to step S102, the main control program performs switch input processing (step S104). In this switch input process, various signals input to input terminals of various input ports of the main control MPU 4100a are read and stored as input information in an input information storage area of the main control built-in RAM. Specifically, this main control program is, for example, a detection signal from the general winning opening switch 3020, 3020 shown in FIG. 12 that detects a game ball that has entered the general winning opening 2104, 2201 shown in FIG. FIG. 12 is a diagram showing a detection signal from the count switch 2110 shown in FIG. 12 for detecting a game ball that has entered the big winning opening 2103 shown in FIG. FIG. 8 shows a detection signal from the upper start opening switch 3022, a detection signal from the lower start opening switch 2109 shown in FIG. 12 that detects a game ball entering the lower start opening 2102 shown in FIG. A detection signal from the gate switch 2352 shown in FIG. 12 for detecting a game ball that has passed through the gate portion 2350 shown in FIG. 12, and a magnetic detection switch for detecting fraud using the magnet shown in FIG. A payer ACK signal from the payout control board 4110 for indicating that the payout control board 4110 shown in FIG. 12 has normally received a detection signal from the H3030 and a prize ball command transmitted in a prize ball control process to be described later. Read and store as input information in the input information storage area. Further, a detection signal from an upper start port switch 3022 that detects a game ball that has entered the upper start port 2101 and a detection signal from a lower start port switch 2109 that detects a game ball that has entered the lower start port 2102 are read. 42, and corresponding to the other start port winning commands shown in FIG. 42 are stored as transmission information in the transmission information storage area described above. In other words, if there is a detection signal from the upper start port switch 3022, the corresponding start port winning command is stored as transmission information in the transmission information storage area, and if there is a detection signal from the lower start port switch 2109, A start opening winning command corresponding to this is stored as transmission information in the transmission information storage area.

  In the present embodiment, the detection signal from the general winning opening switches 3020 and 3020 for detecting the game balls that have entered the general winning opening 2104 and 2201, and the count switch 2110 for detecting the gaming balls that have entered the large winning opening 2103 are shown. , A detection signal from an upper start switch 3022 that detects a game ball that has entered the upper start port 2101, a detection signal from a lower start port switch 2109 that detects a game ball that has entered the lower start port 2102 , And a detection signal from the gate switch 2352 that detects a game ball that has passed through the gate portion 2350 is read as the first time when the switch input process is started, and after a predetermined time (for example, 10 μs) has elapsed. It is read again as the second time. Then, the result read at the second time is compared with the result read at the first time. It is determined whether there is a comparison result among the comparison results. Those that are not the same result are read again as the third time, and the result read at the third time is compared with the result read at the second time. It is determined again whether there is a comparison result among the comparison results. Those that are not the same result are read again as the fourth time, and the result read at the fourth time is compared with the result read at the third time. It is determined again whether there is a comparison result among the comparison results. Those with the same result are treated as having no game balls.

  As described above, in the switch input process, the main control program receives the detection signals from the general winning award port switches 3020 and 3020, the count switch 2110, the upper start port switch 3022, the lower start port switch 2109, and the gate switch 2352 for the first time. -False detection due to the influence of chattering, noise, etc. by reading twice in total, that is, twice reading compared for the third time and twice reading compared for the second time to the fourth time Therefore, the reliability of detection signals from the general winning award opening switches 3020 and 3020, the count switch 2110, the upper starting opening switch 3022, the lower starting opening switch 2109, and the gate switch 2352 is improved. be able to.

  Subsequent to step S104, the main control program performs a winning random number update process (step S106). In this winning random number update process, the big hit symbol random number and the small hit symbol random number described above are updated. Further, in addition to these random numbers, the big hit symbol initial value determination random number updated in the non-winning random number update process of step S56 in the main control side power-on process (main control side main process) shown in FIG. And the random number for determining the initial value for the small hit symbol is also updated. These random numbers for determining the initial value for the big hit symbol and the random numbers for determining the initial value for the small hit symbol are updated in the main control side main process and the main control side timer interrupt process, respectively, thereby increasing the randomness. . On the other hand, since the big hit symbol random number and the small hit symbol random number are random numbers related to the winning determination (big hit determination), each counter is incremented only when the winning random number update process is performed. Note that the above-described random numbers for normal symbol determination and random numbers for determining the initial value for normal symbol determination are also updated by this winning random number update process.

  For example, as described above, the counter that updates the random number for normal symbol determination is an initial value update type counter, and is updated within a predetermined fixed numerical value range from the minimum value to the maximum value. To the maximum value, the value is incremented by adding 1 each time the main control timer interrupt process is performed. The random number for determining the initial value for determination per normal symbol is counted up toward the maximum value, and then the random number for determining the initial value for determination per normal symbol is counted up from the minimum value. When the counter finishes counting up the range from the minimum value to the maximum value of the random number for normal symbol determination, the random number for initial value determination for big hit determination is updated by this winning random number update processing. The random value for determining the initial value for normal symbol determination can be obtained by executing an initial value lottery process for drawing one value from the fixed numerical range of the counter for updating the random number for determination per normal symbol. .

  In the present embodiment, the big hit symbol initial value determining random number and the small hit symbol initial value determining random number are stored in the main control side power-on processing (main control side main processing) shown in FIG. The winning random number update process and the winning random number update process in step S106 in the main control timer interrupt process, which is this routine, are updated respectively. However, each time an interrupt timer is generated, the processing time of this routine becomes uneven. If the number of executions of the non-winning random number update process in step S56 is random by repeatedly executing the main process on the main control side within the remaining time until the interrupt timer is generated, a random number for determining the initial value for the big hit symbol , And the random number for determining the initial value for the small hit symbol may be updated only in the non-winning random number update process in step S56.

  Subsequent to step S106, the main control program performs prize ball control processing (step S108). In this prize ball control process, the prize information shown in FIG. 40 for reading out the input information from the above-mentioned input information storage area and paying out the game ball based on this input information is created, or the main control board 4100 and The self-check command shown in FIG. 40 for confirming the connection state between the payout control board 4110 and the board is created. Then, the created prize ball command and self-check command are transmitted to the payout control board 4110 as main payout serial data. For example, when one game ball enters the big prize opening 2103 shown in FIG. 8, a prize ball command for paying out 15 balls as a prize ball is created, and the number of game balls to be paid out as a prize ball Is set to 10 balls, the main prize ball number information output signal output is set in order to notify that, and is stored in the output information storage area as output information, and a prize ball command is transmitted to the payout control board 4110. If the payer ACK signal notifying that the payout control board 4110 has successfully received the prize ball command is not input within a predetermined time, the connection state between the main control board 4100 and the payout control board 4110 is confirmed. A self-check command to be generated is transmitted to the payout control board 4110.

  In the prize ball control process in step S108, when the input information is read from the above-described input information storage area and the number of game balls scheduled to be paid out as a prize ball reaches 10 based on this input information. In order to notify that, a main prize ball number information output command classified into others shown in FIG. 42 is created and stored in the transmission information storage area as transmission information. The main prize ball number information output command is created based on the value of the main prize ball number information output determination counter. The value of the main prize ball number information output determination counter is obtained by reading the input information from the input information storage area described above and based on this input information, that is, the upper start opening 2101, the lower start opening 2102 provided in the game board 4, The number of game balls to be paid out as prize balls is counted based on the game balls that have entered the various prize openings, such as the general prize opening 2104, 2201, and the big prize opening 2103, and the award in step S108. In the ball control processing, the award ball schedule information storage area of the main control built-in RAM is stored and updated. In the prize ball control process of step S108, the value of the main prize ball number information output determination counter stored in the prize ball schedule information storage area of the main control built-in RAM is read, and the read main prize ball number information output determination counter is read. The input information is read from the input information storage area described above, and the number of game balls to be paid out as a prize ball is added based on this input information, and the value indicating the added number is 10 When the number of game balls is over (that is, when the number of game balls scheduled to be paid out as prize balls has reached 10), a main prize ball number information output command is created to inform the fact, and as transmission information The award ball schedule information storage area of the main control built-in RAM described above is stored in the output information storage area, and the value indicating the number of balls exceeding the value is used as the main prize ball number information output determination counter value. It is adapted to store update.

  Subsequent to step S108, the main control program performs a frame command reception process (step S110). In the payout control board 4110, the payout control program executes various commands of 1 byte (8 bits) classified into the status display shown in FIG. 43 (for example, frame status 1 command, error release navigation command, and frame status 2 command). Send. On the other hand, as described later, the payout control program outputs an error occurrence command when an error occurs in the payout operation, or outputs an error cancellation navigation command based on a detection signal of the operation switch 860a. In the frame command reception process described above, when the main control program normally receives the various commands as payer serial data, information that informs the payout control board 4110 to that effect is stored as output information in the main control built-in RAM. Store in the area. Also, the main control program reformats the command received normally as the payer serial data into a 2-byte (16-bit) command (various commands (frame status 1 command, error cancelation) classified in the status display of FIG. The navigation command and the frame state 2 command))) are stored in the transmission information storage area described above as transmission information. The frame state 1 command here corresponds to the first error occurrence command, and the error cancellation navigation command corresponds to the first error cancellation command.

  Subsequent to step S110, the main control program performs a fraud detection process (step S112). In this fraud detection process, the abnormal state related to the prize ball is confirmed. For example, when the input information is read from the above-described input information storage area and the detection signal from the count switch 2110 is input when the game state is not a big hit game state (when a game ball enters the big prize opening 2103), etc. Then, a winning abnormality display command classified into the notification display shown in FIG. 42 as an abnormal state is created, and stored as transmission information in the transmission information storage area described above.

  Subsequent to step S112, the main control program performs a special symbol and special electric accessory control process (step S114). In the special symbol and special electric accessory control processing, a latch signal is output to the main random number circuit 4100an with built-in main control shown in FIG. 12, and the random number extracted by the main random number circuit 4100an with main control when the latch signal is input. (Random number value) is acquired from a hard random number latch register incorporated in main control built-in main control MPU 4100a, and the obtained random number value is set as a big hit determination random number. Whether or not the jackpot determination random number (that is, the random number value acquired from the hard random number latch register built in the main control built-in main control MPU 4100a) matches the jackpot determination value stored in advance in the main control built-in ROM. (Determining whether or not to generate a big hit gaming state (referred to as “special lottery”)) or taking out the value of the counter for updating the big hit symbol random number and pre-stored in the main control built-in ROM It is determined whether or not it matches with the probability variation determination value (determination of whether or not to generate a probability fluctuation). Here, “probability fluctuation” means that the probability of a big hit changes to a high probability (at the time of probability change) that is set higher than that at normal time (low probability). In the present embodiment, the value 32668 to the value 32767 are set in the low probability as the range of the big hit determination value (big hit determination range) described above, and read from the normal determination table, whereas the value 31768 in the high probability. ˜value 32767 is set and read from the probability variation determination table. As described above, in the special symbol and special electric accessory control process in step S114, the big hit determination random number (that is, the random number value acquired from the hard random number latch register incorporated in the main control built-in main control MPU 4100a) and the built-in main control. When determining whether or not the jackpot determination value stored in advance in the ROM matches, the jackpot determination random number (that is, the random value acquired from the hard random number latch register built in the main control built-in main control MPU 4100a) Is determined by whether or not is included in the jackpot determination range.

  When these determination results are based on the upper start port switch 3022, various commands related to the special figure 1 synchronization effect shown in FIG. 41 are created, while the lottery results are based on the lower start port switch 2109. 41, various commands related to the special figure 2 tuning effect shown in FIG. 41 are created and stored in the transmission information storage area as transmission information, and the upper special symbol display 1185 or the lower symbol is displayed according to the determined special symbol variation display pattern. The output of the lighting signal to the upper special symbol display 1185 or the lower special symbol display 1186 is set so that the special symbol display 1186 is lit, and is stored as output information in the output information storage area described above. Depending on the game state to be generated, for example, when the game state is a big hit game state, various commands classified into the big hit relation shown in FIG. 41 (a big hit opening command, a big winning opening 1 opening Nth display command, a big winning opening 1 Closing display command, winning prize 1 count display command, jackpot ending command, and jackpot symbol display command) are created and stored in the transmission information storage area as transmission information, or the opening / closing member 2107 shown in FIG. 8 is opened / closed. When the output of the drive signal to the attacker solenoid 2108 is set and stored in the output information storage area as output information, or when the number of times (round) when the special winning opening 2103 is opened from the closed state is two times, 2 to turn on the two-round indicator lamp 1190a of the round indicator 1190 shown in FIG. When the output of the lighting signal to the wind display lamp 1190a is set and stored in the output information storage area as output information, or when the round is 15 times, the 15 round display lamp 1190b of the round indicator 1190 shown in FIG. The lighting signal output to the 15-round display lamp 1190b is set so as to be lit, and stored as output information in the output information storage area, or to the gaming state display 1183 so that the presence / absence of probability variation is lit in a predetermined color The output of the lighting signal is set and stored as output information in the output information storage area.

  Subsequent to step S114, the main control program performs a normal symbol and normal electric accessory control process (step S116). In the normal symbol and normal electric accessory control process, the input information is read from the above-described input information storage area, and the gate winning process is performed based on the input information. In this gate winning process, it is determined from the input information whether the detection signal from the gate switch 2352 has been input to the input terminal. Based on this determination result, when a detection signal is input to the input terminal, the gate information storage area of the main control built-in RAM is extracted as gate information by extracting the counter value etc. for updating the random number for determination per normal symbol described above To remember.

  This gate information storage area is provided with 0th partition to 3rd partition (four partitions), and gate information is stored in the order of 0th partition, 1st partition, 2nd partition, and 3rd partition. It is like that. For example, when gate information is stored in the 0th to 2nd sections of the gate information storage, when the detection signal from the gate switch 2352 is input to the input terminal, the gate information is stored in the third section of the gate information storage. To do.

  The gate information stored in the 0th section of the gate information storage is set in the work area of the main control built-in RAM. When this gate information is set, the gate information of the first section of the gate information storage is in the 0th section of the gate information storage, the gate information of the second section of the gate information storage is in the first section of the gate information storage, The gate information of the third section of the information storage is shifted to the second section of the gate information storage, respectively, and the third section of the gate information storage becomes an empty area. For example, when gate information is stored in the first partition to the second partition of the gate information storage, the gate information of the first partition of the gate information storage is stored in the 0th partition of the gate information storage. The gate information of the two sections is shifted to the first section of the gate information storage, and the second section of the gate information storage and the third section of the gate information storage become empty areas. Here, when the gate information is stored in the first to third sections of the gate information storage, the above-described gate information is turned on so that the normal symbol storage display 1188 is turned on using the total number of stored gate information as a holding ball. Based on the above, the output of the lighting signal of the normal symbol storage display 1188 is set and stored as output information in the output information storage area described above.

  Following the gate winning process, the gate information set in the work area of the main control built-in RAM is read out, and the normal design random number is extracted from the read gate information and stored in the main control built-in ROM in advance. It is determined whether or not it matches the determination value per normal symbol (referred to as “normal lottery”). Whether or not the movable piece 2106 is opened / closed is determined based on the determination result (the lottery result of the normal lottery). In the case of performing the opening / closing operation by this determination, the pair of movable pieces 2106 is in a state of being expanded in the left-right direction, so that a gaming state in which a game ball can be received at the lower start port 2102 is achieved, which is advantageous to the player. It becomes a gaming state. The variable display pattern of the normal symbol corresponding to this determination is determined based on the above-mentioned random number for the normal symbol variable display pattern, and various commands classified as related to the general pattern synchronization effect shown in FIG. The output of the lighting signal to the normal symbol display 1189 is set so that the normal symbol display 1189 is turned on in accordance with the determined normal symbol variation display pattern, and is stored in the transmission information storage area described above. Store in the output information storage area. For example, when the extracted random number for normal symbol determination matches the normal symbol determination value stored in advance in the main control built-in ROM, various commands related to the ordinary electric role effect shown in FIG. Is generated and stored as transmission information in the transmission information storage area, and the output of the drive signal to the start port solenoid 2105 is set so as to open and close the movable piece 2106, and is stored as output information in the output information storage area described above. On the other hand, when the extracted random number for normal symbol determination does not match the normal symbol determination value stored in advance in the main control built-in ROM, the normal symbol based on the normal symbol variation display pattern random number described above is used. The variable display pattern is determined, and various commands classified as related to the general drawing synchronization effect shown in FIG. 41 are created and described above as the transmission information. The lighting information is stored in the signal information storage area, and the output of the lighting signal to the normal symbol display 1189 is set so that the normal symbol display 1189 is turned on according to the determined normal symbol variation display pattern. Store in the area.

  Subsequent to step S116, the main control program performs port output processing (step S118). In this port output process, output information is read from the output information storage area described above from the output terminals of the various output ports of the main control MPU 4100a, and various signals are output based on the output information. This main control program, for example, outputs a main payout ACK signal when the various commands from the payout control board 4110 are normally received from the output terminal of a predetermined output port of the main control MPU 4100a based on the output information. Or a drive signal to the starter solenoid 2105 for opening / closing the movable piece 2106, or a drive signal for the opening / closing member 2107 of the winning prize opening 2103. 15 round jackpot information output signal, 2 round jackpot information output signal, probability changing information output signal, special symbol display information output signal, normal symbol display information output signal, short and medium time information output signal, start Pay various information (game information) signals related to the game, such as the winning prize information output signal And outputs to the control board 4110.

  Subsequent to step S118, the main control program performs peripheral control board command transmission processing (step S120). In the peripheral control board command transmission process, the main control program reads the transmission information from the transmission information storage area described above and transmits the transmission information to the peripheral control board 4140 as main peripheral serial data. The transmission information includes various commands created in the main control side timer interruption process which is this routine and shown in FIG. Various winning commands are classified based on commands and jackpots (for example, when a game ball that has entered a big winning opening 2103 (see FIG. 8) is detected, a big winning opening based on a detection signal from the count switch 2110 (see FIG. 12). 42), various commands classified as power-on, various commands classified as related to ordinary tuning effects, various commands classified as related to ordinary electronic effects, FIG. Various commands (door opening command, door frame closing command, main body frame opening command, main body frame closing command, etc.) that are categorized as notification display, and status display Various commands (frame state 1 command, error release navigation command and frame state 2 command), various commands classified as related to the test, and various commands classified into others (for example, the main control board 4100 is the upper start port 2101, Each time the number of game balls scheduled to be paid out as award balls reaches 10 balls based on the game balls entered in various winning ports such as the lower start port 2102, the general winning ports 2104, 2201, and the large winning port 2103 A main prize ball number information output command for instructing the main computer to send a main prize ball number information output signal to the hall computer via the external terminal board 784 is stored. The main serial data consists of 3 bytes per packet. Specifically, the main peripheral serial data includes a status indicating a type of command having a storage capacity of 1 byte (8 bits), a mode indicating a production variation having a storage capacity of 1 byte (8 bits), and a status. And a sum value obtained by calculating the sum with the mode regarded as a numerical value, and this sum value is created at the time of transmission.

  In this peripheral control board command transmission processing, the main control program transmits various commands as main peripheral serial data to the peripheral control board 4140 in the order of status, mode, and sum value. As described above, the charge charged in the electrolytic capacitor MC2 shown in FIG. 21 is applied to the VDD terminal, which is the power supply terminal of the main control MPU 4100a, as +5 V when a power failure or a momentary power failure occurs. Therefore, the main peripheral serial transmission port 4100ae built in the main control MPU 4100a shown in FIG. 23 shifts at least the command set by the main control CPU core 4100aa in the transmission buffer register 4100aeb by the serial management unit 4100aec. The data can be transferred to the register 41aea and transmitted from the transmission shift register 4100aea as the main serial data. When the power to the pachinko gaming machine 1 is turned on, or when power is restored after a power failure or a momentary power failure occurs after the power is turned on, when the power is turned on in step S50 in the main control side power-on process shown in FIG. In the reservation setting of the command to be transmitted, the power-on state command, the power-on main control return destination command, and the power-on main prize ball shown in FIG. Since the counter notification command for the number information output determination is created and stored as transmission information in the transmission information storage area of the main control built-in RAM, the status, mode, Then, it is sent to the peripheral control board 4140 in the order of the sum value, and then the status, mode, Are sent to the peripheral control board 4140 in the order of the sum value, and then the main prize ball number information output determination counter notification command at the time of power-on is configured. Send. In the transmission information storage area of the main control built-in RAM, various information is read from the game backup information in accordance with the various information in the setting of the work area of the main control built-in RAM in step S34 in the main control side power-on process. Various commands may be stored. In such a case, first after completion of transmission of various commands according to game information among various information, then power-on status command, power-on main control return destination command, and power-on main prize ball number information An output determination counter notification command is transmitted.

  In this peripheral control board command transmission process, when the main control program receives a frame state 1 command (first error occurrence command) from the payout control board 4110 via the RXA terminal reception port, the peripheral control board 4140 (effect control unit) ) Frame status 1 command (second error occurrence command) is transmitted (error command sending means). In this case, the main control program transfers the frame state 1 command in the form shown in FIG. 43 received from the payout control board 4110 to the peripheral control board 4140 as the frame state 1 command in the form shown in FIG.

  On the other hand, in this peripheral control board command transmission process, if the main control program receives an error release navigation command (first error release command) from the payout control board 4110 via the RXA terminal reception port, the peripheral control board 4140 An error cancellation navigation command (second error cancellation command) is transmitted to (error command sending means). In this case, the main control program transfers the error release navigation command in the form shown in FIG. 43 received from the payout control board 4110 to the peripheral control board 4140 as the error release navigation command in the form shown in FIG.

  Furthermore, in this peripheral control board command transmission process, when the main control program receives a main body frame release command (first main body frame release command) from the payout control board 4110 via the RXA terminal reception port, the peripheral control board 4140 A main body frame release command (second main body frame release command) is transmitted to the (production control unit) (main body frame command sending means, second main body frame sending means). In this case, the main control program transfers the body frame release command in the form shown in FIG. 43 received from the payout control board 4110 to the peripheral control board 4140 as the body frame release command in the form shown in FIG. On the other hand, in this peripheral control board command transmission process, when the main control program receives a main body frame close command (first main body frame close command) from the payout control board 4110 through the reception port of the RXA terminal, the peripheral control board 4140 ( A main body frame closing command (second main body frame closing command) is transmitted to the effect control unit) (main body frame command sending means, second main body frame command sending means). In this case, the main control program transfers the main body frame closing command in the form shown in FIG. 43 received from the payout control board 4110 to the peripheral control board 4140 as the main body frame closing command in the form shown in FIG.

  In this peripheral control board command transmission process, when the main control program receives a door opening command (first door opening command) from the payout control board 4110 through the RXA terminal reception port, the peripheral control board 4140 (effect control) A door opening command (second door frame opening command) (door frame command sending means, second door frame command sending means). In this case, the main control program transfers the door frame closing command in the form shown in FIG. 43 received from the payout control board 4110 to the peripheral control board 4140 as the door closing command in the form shown in FIG. On the other hand, in this peripheral control board command transmission processing, when the main control program receives a door closing command (first door closing command) from the payout control board 4110 via the RXA terminal reception port, the peripheral control board 4140 (effect control) A door closing command (second door closing command) (door frame command sending means, second door frame command sending means). In this case, the main control program transfers the door closing command in the form shown in FIG. 43 received from the payout control board 4110 to the peripheral control board 4140 as the door closing command in the form shown in FIG.

  Subsequent to step S120, the main control program clears the main control built-in WDT 4100af shown in FIG. 12 (step S122), and ends this routine. The main control built-in WDT 4100af in step S22 is cleared by setting a timer clear setting value in a WDT clear register built in the main control MPU 4100a. Thereby, the time count by the main control built-in WDT 4100af is cleared. Then, the time measurement by the main control built-in WDT 4100af is started again, so that the main control MPU 4100a is not forcedly reset by the main control built-in WDT 4100af.

  As described above, the main control board 4100 stores the game information according to the progress of the game before the power to the pachinko gaming machine 1 is cut off during the progress of the game. The power supply to the pachinko gaming machine 1 can be completed based on the game information on which the backup process was executed as a return destination of the game progress by the main control board 4100 at the time of power recovery. The peripheral control of the power-on main control return destination command in FIG. 41 for instructing the driving state of the start port solenoid 2105 and the attacker solenoid 2108, which are electrical drive sources by the port output processing of step S118 in this routine when shut off. It is possible to output to the substrate 4140. That is, the main control board 4100 performs main setting in the work area setting of the main control built-in RAM in step S34 in the reservation setting of the command to be transmitted at power-on in step S50 in the main-control-side power-on process in FIG. Based on the power recovery time information set in the work area of the control built-in RAM, in order to notify that the power is turned on (power recovery), the power-on status command classified into power-on in FIG. A control return destination command and a power-on main prize ball number information output determination counter notification command are created and stored as transmission information in the transmission information storage area of the main control built-in RAM, and the peripheral control board command in step S120 in this routine In the transmission process, as the main peripheral serial data, the status, mode , And are transmitted to the peripheral control board 4140 in the order of the sum value, and then transmitted to the peripheral control board 4140 in the order of the status, mode, and sum value constituting the main control return destination command when the power is turned on. It transmits to the peripheral control board 4140 in the order of status, mode, and thumb value, which constitutes the counter notification command for determining the main prize ball number information output at the time of insertion. Therefore, the peripheral control board 4140 determines the return destination of the progress of the game by the main control board 4100 at the time of power recovery based on the power-on main control return destination command from the main control board 4100. It is possible to display effects in the display area. As a result, when a player is playing a game, when a momentary power failure or power failure occurs, and when power is restored thereafter, the game state immediately before the power failure or power failure is restored immediately after power recovery. In addition, the return destination of the progress of the game by the main control board 4100 can be displayed and notified in the display area of the game board side liquid crystal display device 1900, so that the system of the pachinko gaming machine 1 is gathered, so-called It is possible to prevent a player from being mistaken for a broken state that appears frozen. Therefore, it is possible to prevent the player from misunderstanding that the player has failed by quickly returning to the gaming state immediately before the momentary power failure or power failure after power recovery.

  In the main control board inspection process, which is an inspection process for the production line of the main control board 4100, when the main control board 4100 is first turned on after being manufactured for inspection, as described above, as shown in FIG. In step S38 in the main control side power-on process, the entire area of the main control built-in RAM is necessarily cleared. Thus, in the reservation setting of the command to be transmitted at the time of power-on in step S50 in the same processing, when the reservation setting of the command to be transmitted at the time of power-on is performed, the power-on state command classified into the power-on shown in FIG. When the power is turned on, a main control return destination command at power-on and a main notification ball count information output judgment counter notification command at power-on are created and stored as transmission information in the transmission information storage area of the main control built-in RAM. A state in which only three commands are stored as transmission information in the transmission information storage area of the main control built-in RAM: a status command, a main control return destination command when the power is turned on, and a counter notification command for determining the output of the main prize ball number information when the power is turned on In the peripheral control board command transmission process in step S120 in this routine, Status that constitutes a power-on state command as serial data, which is sent to the inspection device in the main control board inspection process in the order of status, mode, and sum value, and then constitutes a main control return destination command at power-on , Mode, and sum value are sent to the main control board inspection process inspecting device, and then the main prize ball number information output judgment counter notification command at power-on is configured, status, mode, and sum value order Is transmitted to the inspection device of the main control board inspection process. Based on the information indicating the model code of the pachinko gaming machine included in the power-on state command received from the main control board 4100, that is, the information indicating the model code of the pachinko gaming machine, The series code for specifying which type of the above-described Max type, middle type, and sweet digital type, and the copyright code for specifying the copyright of the work, Game specifications (for example, a game specification in which if a probability change occurs, the state continues until the next jackpot game state occurs, and a game specification in which a probability change occurs with a limited number of special symbol changes. (ST machine) etc.), and detailed model information is displayed on the inspection monitor of the main control board inspection process based on the game specification code It has become way.

[16. Various control processing of payout control board]
Next, various control processes performed by the payout control board 4110 shown in FIG. 13 will be described with reference to FIGS. 47 to 63. FIG. 47 is a flowchart showing an example of processing when the payout control unit is turned on, FIG. 48 is a flowchart showing continuation of the processing when the payout control unit is turned on in FIG. 47, and FIG. 49 is a payout control unit following FIG. FIG. 50 is a flowchart showing an example of a payout control unit timer interrupt process, FIG. 51 is a flowchart showing an example of a rotation angle switch history creation process, and FIG. 52 is a sprocket. 53 is a flowchart showing an example of the fixed position determination skip process, FIG. 53 is a flowchart showing an example of the ball spot determination process, and FIG. 54 is a flowchart showing an example of the prize ball stock number addition process. 55 is a flowchart showing an example of the winning ball stock number addition process for lending, and FIG. 56 shows an example of the stock monitoring process. FIG. 57 is a flowchart showing an example of the payout ball movement determination setting process, FIG. 58 is a flowchart showing an example of the payout setting process, and FIG. 59 shows an example of the ball movement setting process. 60 is a flowchart illustrating an example of the retry operation monitoring process, FIG. 61 is a flowchart illustrating an example of the inconsistency counter reset determination process, and FIG. 62 is a flowchart illustrating an example of the error release operation determination process. FIG. 63 is a timing chart showing the signal processing (A) and the input signal confirmation processing (A) from the CR unit during the payout operation by ball lending.

  First, payout control unit power-on processing will be described, then payout control unit timer interruption processing, rotation angle switch history creation processing, sprocket fixed position determination skip processing, ball corner determination processing, prize ball stock number addition for prize ball Processing, winning ball stock count addition processing, stock monitoring processing, payout ball binding operation determination setting processing, payout setting processing, ball binding operation setting processing, retry operation monitoring processing, inconsistency counter reset determination processing, error cancellation The operation determination process will be described. In addition, rotation angle switch history creation processing, sprocket fixed position determination skip processing, ball curl determination processing, prize ball award ball stock number addition processing, rental ball award ball stock number addition processing, stock monitoring processing, payout ball fringe The operation determination setting process, the retry operation monitoring process, the inconsistency counter reset determination process, and the error release operation determination process are performed as one process of the main operation setting process in step S562 in the payout control unit power-on process described later. Switch history creation processing, sprocket fixed position determination skip processing, ball edge determination processing, retry operation monitoring processing, inconsistency counter reset determination processing, error release operation determination processing, prize ball prize ball number addition processing, ball rental award Priorities are set in the order of the ball stock count addition processing, stock monitoring processing, and payout ball engagement motion determination setting processing. .

[16-1. Discharge control unit power-on processing]
When the pachinko gaming machine 1 is turned on, the payout control unit 4120 on the payout control board 4110 has a payout control program controlled by the payout control MPU 4120a as shown in FIGS. Process at the time of input. When the payout control unit power-on process is started, the payout control program sets the interrupt mode in the payout control MPU 4120a (step S500). This interrupt mode is for setting the priority order of interrupts of the payout control MPU 4120a. In this embodiment, a payout control unit timer interrupt process, which will be described later, is set as the highest priority, and when an interrupt of this payout control unit timer interrupt process occurs, the process is preferentially performed.

  Subsequent to step S500, the payout control program performs input / output setting (I / O input / output setting) (step S502). In this I / O input / output setting, various input ports and various output ports of the payout control MPU 4120a are set.

  Subsequent to step S502, the payout control program performs wait timer process 1 (step S506), and determines whether or not a power failure warning signal is input (step S508). The voltage does not increase immediately from when the power is turned on until the voltage reaches the predetermined voltage. On the other hand, when a power failure or a momentary power failure (a phenomenon in which the supply of power is temporarily stopped) occurs, the voltage drops and becomes smaller than the power failure warning voltage. A warning signal (paid outage warning signal) is input. Similarly, when the voltage becomes lower than the power failure warning voltage from when the power is turned on until it reaches the predetermined voltage, a power failure warning signal (paid power failure warning signal) is input from the power failure monitoring circuit 4100e of the main control board 4100. Therefore, the wait timer process 1 in step S506 is a process for waiting until the voltage becomes larger than the power failure warning voltage and stabilizes after the power is turned on. In this embodiment, the wait timer process 200 waits for 200 milliseconds (wait timer) (wait timer). ms) is set. The determination in step S508 is performed based on a power failure warning signal (paid power failure warning signal) from the power failure monitoring circuit 4100e of the main control board 4100.

  Subsequent to step S508, the payout control program determines whether or not the operation switch 860a is operated (step S512). This determination is based on the logical value of the operation signal from the operation switch 860a, and when the logical value of the operation signal from the operation switch 860a is HI, it is determined that the RAM clear is not instructed. When it is determined that the operation switch 860a is not operated, the operation switch 860a is operated by determining that the RAM clear is instructed when the logical value of the operation signal from the operation switch 860a is LOW. judge.

  When the operation switch 860a is operated in step S512, the payout control program sets a value 1 to the payout RAM clear notification flag HRCL-FLG (step S514). That is, the payout control program can execute a RAM clear process for initializing a RAM (hereinafter referred to as “payout control built-in RAM”) built in the payout control MPU 4120a for a predetermined time from when the power is turned on. (Pinning control side power-on operation control means). On the other hand, when the operation switch 860a is not operated in step S512, the payout control program sets a value 0 to the payout RAM clear notification flag HRCL-FLG (step S516). This payout RAM clear notification flag HRCL-FLG is stored in the payout control built-in RAM (payout storage unit) of the payout control MPU 4120a, for example, various flags, various information stored in various information storage areas, etc. (for example, The prize ball stock number PBS, real ball count PB, drive command number DRV, inconsistency counter INCC, etc. stored in the prize ball information storage area, and the logic of the PRDY signal stored in the CR communication information storage area Flag indicating whether or not the payout information related to payout of the set status (PRDY signal output setting information, etc.) is to be erased, and is set to a value of 1 when the payout information is erased and a value of 0 when the payout information is not erased. Is done. The payout RAM clear notification flag HRCL-FLG set in steps S514 and S516 is stored in a general-purpose storage element (general-purpose register) of the payout control MPU 4120a.

  Subsequent to step S514 or step S516, the payout control program performs setting for permitting access to the payout control built-in RAM (step S518). With this setting, the payout control built-in RAM can be accessed, and for example, payout information can be written (stored) or read out.

  Subsequent to step S518, the payout control program sets the stack pointer (step S520). The stack pointer indicates, for example, the address accumulated on the stack to temporarily store the contents of the memory element (register) being used, or temporarily returns the return address of this routine when returning to this routine after completing the subroutine. It indicates the address that is stacked on the stack for storage, and the stack pointer advances each time the stack is stacked. In step S520, an initial address is set in the stack pointer, and the contents of the register, the return address, etc. are stacked on the stack from this initial address. Then, the stack pointer returns to the initial address by sequentially reading from the last stacked stack to the first stacked stack.

  Subsequent to step S520, the payout control program determines whether or not the payout RAM clear notification flag HRCL-FLG is 0 (step S522). As described above, the payout RAM clear notification flag HRCL-FLG is set to a value of 1 when the payout information is erased and to a value of 0 when the payout information is not erased.

  When the payout RAM clear notification flag HRCL-FLG is 0 in step S522, that is, when the payout information is not deleted, the payout control program calculates a checksum (step S524). This checksum calculates the sum by regarding the payout information stored in the payout control built-in RAM as a numerical value.

  Subsequent to step S524, the payout control program determines whether or not the calculated checksum value matches the checksum value stored in the payout control unit power-off process (at power-off) described later. (Step S526). If they match, the payout control program determines whether or not the payout backup flag HBK-FLG is 1 (step S528). This payout backup flag HBK-FLG is a flag indicating whether or not payout backup information such as payout information and checksum value is stored in the payout control built-in RAM in the payout control unit power-off process described later. A value of 1 is set when the control unit power-off process is normally terminated, and a value of 0 is set when the payout control unit power-off process is not normally terminated.

  When the payout backup flag HBK-FLG has a value of 1 in step S528, that is, when the payout control unit power-off process has been completed normally, the payout control program sets the work area of the payout control built-in RAM as power recovery. (Step S530). In this setting, in addition to the value 0 being set in the payout backup flag HBK-FLG, information at the time of power recovery is read from the ROM built in the payout control MPU 4120a (hereinafter referred to as “the payout control built-in ROM”). This power recovery information is set in the work area of the payout control built-in RAM. Accordingly, the above-mentioned payout backup information stored in the payout control built-in RAM, various flags, various information stored in various information storage areas, etc. (for example, prizes stored in the prize ball information storage area, PRDY signal output setting information in which the logic state of the PRDY signal stored in the CR communication information storage area, such as the ball stock number PBS, the real ball count PB, the drive command number DRV, the inconsistency counter INCC, and the like, Information used for various processes is set based on payout information relating to payout of inconsistency counter reset determination time (stored in the time management information storage area). Note that “recovery” includes not only a state in which the power is turned off from a state in which the power is turned off but also a state in which the power is restored after a power failure or a momentary power failure.

  On the other hand, when the payout RAM clear notification flag HRCL-FLG is not 0 (value 1) in step S522, that is, when the payout information is erased, or when the checksum values do not match in step S526, or step When the payout backup flag HBK-FLG is not a value 1 (value 0) in S528, that is, when the payout control unit power-off process is not normally terminated, the payout control program reads the entire area of the payout control built-in RAM. Clear (step S532). That is, the payout control program executes the payout control side RAM clear process triggered by detection of the operation signal of the operation switch 860a (payout control side power-on operation control means). As a result, the payout backup information stored in the payout control built-in RAM is cleared.

  Subsequent to step S532, the payout control program sets the work area of the payout control built-in RAM as an initial setting (step S534). In this setting, the initial information is read from the payout control built-in ROM, and the initial information is set in the work area of the payout control built-in RAM.

  Subsequent to step S530 or step S534, the payout control program performs interrupt initialization (step S536). This setting is to set an interrupt cycle when a payout control unit timer interrupt process to be described later is performed. In this embodiment, it is set to 2 ms.

  Subsequent to step S536, the payout control program performs interrupt permission setting (step S538). With this setting, the payout control unit timer interrupt process is repeated every interrupt cycle set in step S536, that is, every 2 ms.

  Subsequent to step S538, the payout control program sets a value A in the watchdog timer clear register HWCL (step S539). The watchdog timer is cleared by setting the value A, the value B, and the value C in this watchdog timer clear register HWCL in order.

  Subsequent to step S539, the payout control program determines whether a power failure notice signal (payout power failure notice signal) has been input (step S540). As described above, when the power of the pachinko gaming machine 1 is cut off, or when a power failure or a momentary power failure occurs, if the voltage falls below the power failure warning voltage, a power failure warning signal (paid power failure warning signal) is used as the main power control board. 4100 is input from the power failure monitoring circuit 4100e. The determination in step S540 is made based on this power failure notice signal.

  When no power failure warning signal is input in step S540, the payout control program determines whether or not the 2 ms elapsed flag HT-FLG is a value 1 (step S542). This 2 ms elapsed flag HT-FLG is a flag for measuring 2 ms in a payout control unit timer interrupt process processed every 2 ms, which will be described later. Is set.

  When the 2 ms elapsed flag HT-FLG is 0 in step S542, that is, when 2 ms has not elapsed, the process returns to step S540, and the payout control program determines whether or not a power failure warning signal (paid power failure warning signal) has been input. Determine.

  On the other hand, when the 2 ms elapsed flag HT-FLG is 1 in step S542, that is, when 2 ms have elapsed, the payout control program sets the value 0 to the 2 ms elapsed flag HT-FLG (step S544).

  Subsequent to step S544, the payout control program sets a value B in the watchdog timer clear register HWCL (step S546). At this time, the value B is set in the watchdog timer clear register HWCL following the value A set in step S539.

  Subsequent to step S546, the payout control program performs port output processing (step S548). In this port output process, various information is read from the output information storage area of the payout control built-in RAM, and various signals are output from the output terminals of the various output ports of the payout control MPU 4120a based on the various information. In the output information storage area, for example, payer ACK information indicating that various commands relating to payout from the main control board 4100 (award ball command and self-check command shown in FIG. Various information such as drive information for performing drive control, prize ball information on the number of balls actually paid out by the payout motor 744, LED display information displayed on the error LED display 860b, and the like are stored. When various commands relating to payout from the main control board 4100 are normally received from the output terminal of a predetermined output port of the payout control MPU 4120a based on the output information, a payer ACK signal is output to the main control board 4100, or a payout motor 744 outputs a drive signal, and the number of balls that the payout motor 744 actually pays out the game balls As a force signal, it is output to the external terminal board 784 (in this embodiment, every time the payout motor 744 actually pays out 10 game balls, a prize ball number information output signal is output to the external terminal board 784. Specifically, a prize ball number information output determination counter for determining whether or not to output prize ball number information is provided. The prize ball number information output determination counter is actually set by the payout motor 744. The number of game balls that have been paid out is counted based on the detection signal from the counting switch 751 shown in FIG. 13 in the port input process in step S550 described later, and the game actually paid out by the payout motor 744. The award ball information storage area of the payout control built-in RAM is updated by a process (program) (not shown) for monitoring the number of balls. In a process (program) (not shown) for monitoring the number of game balls that have been paid out, the value of the prize ball number information output determination counter stored in the prize ball information storage area of the payout control built-in RAM is set to a step described later. Based on the detection signal from the counting switch 751 shown in Fig. 13 in the port input process in S550, the number of game balls actually paid out by the payout motor 744 is added and the memory is updated, in the port output process in step S548. When the value of the prize ball number information output determination counter is read from the prize ball information storage area and the value of the read prize ball number information output determination counter exceeds the value 10 (that is, the payout motor 744 is actually When the number of game balls paid out to 10 has reached 10), an award ball number information output signal is output to the external terminal board 784, and the number of balls exceeding the number Is stored and updated in the prize ball information storage area of the payout control built-in RAM described above as the value of the prize ball number information output determination counter. Or a display signal is output to the error LED display 860b.

  Subsequent to step S548, the payout control program performs port input processing (step S550). In this port input process, various signals input to input terminals of various input ports of the payout control MPU 4120a are read and stored as input information in an input information storage area of the payout control built-in RAM. For example, an operation signal of the operation switch 860a, a detection signal from the rotation angle switch 752, a detection signal from the counting switch 751, a detection signal from the full switch 550, a BRQ signal from the CR unit 6, a BRDY signal, and a CR connection signal, The main payment board ACK signal from the main control board 4100 that informs that the main control board 4100 has normally received various commands transmitted in the command transmission process described later is read and stored as input information in the input information storage area.

  Subsequent to step S550, the payout control program performs timer update processing (step S552). In this timer update process, when the determination is made as to whether or not a ball stagnation state has occurred due to the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, the ball swatch determination set as the determination condition is performed. Time, skip determination time set when the fixed position determination of the payout rotating body is not performed, determination of whether or not the storage space of the foul cover unit 540 shown in FIG. Whether the number of game balls taken into the supply passage of the prize ball device 740 by the detection signal from the full ball determination switch 750, which is set as the determination condition when performing the game, is greater than or equal to a predetermined number In addition to performing time management such as the ball breakage judgment time set as the judgment condition when judging whether or not, the number of game balls delivered and received by the recess of the payout rotating body, and the actual When determining whether or not to reset the inconsistency counter INCC for monitoring whether or not the game balls that are not consistent with the number of balls detected by the count switch 751 are repeatedly paid out The management of the inconsistency counter reset determination time set with the determination condition is performed. For example, when the sphere collision determination time is set to 5005 ms, the timer interruption period is set to 2 ms. Therefore, every time this timer update process is performed, the sphere collision determination time is subtracted by 2 ms, and the subtraction result When the value becomes 0, the ball collision determination time is accurately measured.

  In this embodiment, the skip determination time is set to 22.75 ms, the full tank determination time is set to 504 ms, the ball breakage determination time is set to 119 ms, and the mismatch counter reset determination time is set to 7000 s (about 2 hours). Every time processing is performed, the full tank determination time, the ball breakage determination time, and the inconsistency counter reset determination time are subtracted by 2 ms, and the subtraction result becomes 0. Judgment time is accurately measured. These various determination times are stored as time management information in the time management information storage area of the payout control built-in RAM.

  Subsequent to step S552, the payout control program performs CR communication processing (step S554). In this CR communication processing, whether or not various signals (BRQ signal, BRDY signal, and CR connection signal) from the CR unit 6 are input based on the input information read from the input information storage area described above. Determine. Based on various signals from the CR unit 6, the payout control MPU 4120 a exchanges various signals with the CR unit 6. In the processing for setting the work area of the payout control built-in RAM in step S530, as described above, the payout backup information stored in the payout control internal RAM, various flags, and various information stored in the various information storage areas. (For example, the prize ball stock number PBS, the real ball count PB, the drive command number DRV, the inconsistency counter INCC, etc. stored in the prize ball information storage area, the PRDY stored in the CR communication information storage area, etc. Information to be used for various processes is set based on payout information relating to payout of PRDY signal output setting information or the like in which the logic state of the signal is set.

  By this process, for example, even if there is a momentary power failure or a power failure, values such as the prize ball stock number PBS, the real ball count PB, the drive command number DRV, and the inconsistency counter INCC at the time of power recovery are stored as payout backup information. The value of the award ball stock number PBS, the real ball count PB, the drive command number DRV, the inconsistency counter INCC, etc. immediately before the momentary power failure or power failure can be restored. As a result, when the game ball payout operation by the prize ball device 740 is being executed, even if the payout operation cannot be continued due to a momentary power failure or power failure, the payout operation should be continued at the time of power recovery. Therefore, the game balls can be paid out to the upper plate 301 and the lower plate 302 without excess or deficiency. In other words, in the CR communication process, the payout control MPU 4120a exchanges various signals with the CR unit 6 and, when paying out the game ball to the upper plate 301 or the lower plate 302, the payout control MPU4120a Even if the exchange of various signals with the unit 6 is interrupted and the payout of the game ball cannot be continued, the prize ball stock number PBS, the real ball count PB, the drive command number DRV, and the inconsistency counter INCC at the time of power recovery Etc. are restored to values such as the prize ball stock number PBS, the real ball count PB, the drive command number DRV, the inconsistency counter INCC, etc., which are stored as the payout backup information and immediately before the momentary power failure or power failure. Exchange of various signals between the pachinko gaming machine 1 (payout control MPU 4120a) and the CR unit 6 immediately before a momentary power failure or power failure And it is possible to continue from the time of power restoration, so that it is possible to continue to payout of game balls.

  As described above, the exchange of various signals between the pachinko gaming machine 1 (the payout control MPU 4120a) and the CR unit 6 is restored to the state immediately before the instantaneous power outage or stop at the time of power recovery even if the power outage stops or stops. Thus, various signals from the pachinko gaming machine 1 (payout control MPU 4120a) and the CR unit 6 do not change due to the influence of the instantaneous stop or stop. Therefore, the reliability of the exchange of various signals between the pachinko gaming machine 1 (payout control MPU 4120a) and the CR unit 6 can be enhanced.

  Various information stored in the CR communication information storage area is included in the payout backup information as described above. In the CR communication process, when power is restored, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM set in the process of setting the work area of the payout control built-in RAM in step S530. When the read PRDY signal output setting information is set to the logic state of the PRDY signal that indicates that the payout operation for paying out the rented ball is not possible, for example, the PRDY signal is paid out. The data is output to the CR unit 6 from the output terminal of the predetermined output port of the MPU 4120a. The value of the inconsistency counter INCC in the prize ball information storage area stored in the payout control built-in RAM, which is included in the payout backup information, for example, in the retry operation monitoring process performed as one process of the main action setting process Is determined whether the value of the mismatch counter INCC is smaller than the mismatch threshold INCTH. If the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH, the retry operation is abnormal. That is, it is determined that the game ball payout operation by the prize ball device 740 is in an abnormal state, the value 1 is set to the retry error flag RTERR-FLG, and the payout ball engagement operation determination setting process As an example of setting the error status output to the CR unit 6, for example, when not communicating with the CR unit 6 The logic state of the PRDY signal informing of dispensing operation is not possible (LOW) is set to PRDY signal output setting information stored in the CR communication information storage area for dispensing.

  Thereby, in the CR communication process, the logic state of this PRDY signal is read from the CR communication information storage area and the PRDY signal is output from the output terminal of the predetermined output port of the payout control MPU 4120a at the next timer interrupt from the power recovery. To the CR unit 6. Thus, for example, if the game ball payout operation by the prize ball device 740 is in an abnormal state immediately before the momentary stop, the state is restored at the time of power recovery. At an early stage, a PRDY signal notifying that a payout operation for paying out a ball cannot be performed can be output from the output terminal of a predetermined output port of the payout control MPU 4120a to the CR unit 6. It can be notified that the game ball payout operation by the prize ball device 740 is in an abnormal state. As a result, it is possible to prevent the BRDY, which is a useless lending request signal from the CR unit 6, from being output at an extremely early stage from the time of power recovery.

  In the CR communication process, when the CR connection signal is read from the input information storage area of the payout control built-in RAM and the logic is HI based on the CR connection signal in the port input process of step S550, that is, a pachinko game. When the machine 1 is powered on and when the payout control board 4110 and the CR unit 6 are electrically connected via the game ball lending device connection terminal plate 869, the payout of the ball is made. When the logic state of the PRDY signal is output to the CR unit 6 from the output terminal of the predetermined output port of the payout control MPU 4120a while the logic state of the PRDY signal is HI, In other words, when the pachinko gaming machine 1 is powered on, the payout control board 4110 and the CR unit 6 are used for lending devices such as game balls. When it is not electrically connected via the connecting terminal board 869, the logic state of the PRDY signal is set to LOW to notify that the payout operation for paying out the rented ball is impossible. Is output to the CR unit 6 from the output terminal of the output port. The logical state of the EXS signal that indicates that one payout operation has been started or ended is stored as EXS signal output setting information in the CR communication information storage area of the payout control built-in RAM, and the payout control board 4110 A CR connection signal that tells whether or not the CR unit 6 is electrically connected is stored in the state information storage area as CR connection information.

  Subsequent to step S554, the payout control program performs a full tank and ball break check process (step S556). In this full tank and out-of-ball check process, the input information is read from the above-mentioned input information storage area, and based on this input information, the accommodation space of the above-mentioned foul cover unit 540 is stored by the detection signal from the full tank switch 550. It is determined whether the game balls are full or the number of game balls taken into the supply path of the award ball device 740 is equal to or greater than a predetermined number based on a detection signal from the ball break switch 750. It is determined whether or not. For example, whether or not the storage space of the foul cover unit 540 is full with the game balls stored is determined by using the timer interruption period 2 ms and the full tank and full ball check processing at this time. The detection signal from 550 is ON, and when the detection signal from the full tank switch 550 is turned OFF in the last full (2 ms before) full ball and ball check check process, that is, the detection signal from the full tank switch 550 is ON from OFF. When the transition is made, the time for the full tank determination time (504 ms) described above is started in the timer update process in step S552. When the full tank determination time becomes 0 in the timer update process, that is, when the full tank determination time is reached, whether or not the detection signal from the full tank switch 550 is ON in this full tank and out-of-ball check process. Determine whether. In this determination, when the detection signal from the full tank switch 550 is ON, the above-mentioned state information memory stores the full tank information indicating that the storage space of the foul cover unit 540 is full with the stored game balls. Store in the area. On the other hand, when the detection signal from the full tank switch 550 is OFF, the full tank information indicating that the storage space of the foul cover unit 540 is not full with the stored game ball is stored in the state information storage area. .

  Whether or not the number of game balls taken into the supply path of the award ball apparatus 740 is equal to or greater than a predetermined number is also determined by using the timer interruption period 2 ms, When the detection signal from the ball break switch is ON, and when the detection signal from the ball break switch is turned OFF in the previous full (2 ms before) full ball and ball break check processing, that is, the detection signal from the ball break switch 750 is turned ON from OFF. When the transition is made, the timer update process in step S552 starts counting the ball breakage determination time (119 ms) described above. When the ball break determination time becomes 0 in the timer update process, that is, when the ball break determination time is reached, whether or not the detection signal from the ball break switch 750 is ON in the full tank and ball break check processing. Determine whether. In this determination, when the detection signal from the ball break switch 750 is ON, the ball break information indicating that the number of game balls taken into the supply passage of the prize ball device 740 is greater than or equal to a predetermined number is displayed. While the information is stored in the information storage area, when the detection signal from the ball break switch 750 is OFF, the ball break is transmitted to the effect that the number of game balls taken into the supply passage of the prize ball device 740 is not more than a predetermined number. Information is stored in the state information storage area.

  Subsequent to step S556, the payout control program performs a shot ball feed control circuit error check process (step S557). In this shot ball feed control circuit error check process, status information is acquired from the shot ball feed fault monitoring circuit 4120ah shown in FIG. 13 to determine whether or not a fault has occurred in the shot ball feed control circuit 4120ag. As described above, the firing ball feed failure monitoring circuit 4120ah determines whether or not a failure has occurred in the firing ball feed control circuit 4120ag that performs the launch control by the launch solenoid 654 and the ball feed control by the ball solenoid 585. Monitoring is performed, and the monitoring result (whether or not a defect occurs) can be stored and held as status information. The payout control program obtains status information from the launching ball sending defect monitoring circuit 4120ah to determine whether or not the launching ball sending control circuit 4120ag has a problem. When the payout control program obtains the status information from the launching ball feed failure monitoring circuit 4120ah and determines that there is no malfunction in the launching ball feed control circuit 4120ag, the launching ball feed control circuit 4120ag performs the launch control of the game ball. In order to start, the launching operation permission is set for the launching ball feed control circuit 4120ag, and the launching operation permission information for notifying that the launching operation is permitted is stored in the state information storage area, while the launching ball feed control circuit 4120ag. When it is determined that a failure has occurred, the launching ball sending control circuit 4120ag is set to prohibit the launching operation in order to forcibly stop the launching control of the game ball by the launching ball feed control circuit 4120ag, and The launching operation prohibition information that indicates that the operation is prohibited is stored in the state information storage area.

  Subsequent to step S557, the payout control program performs command reception processing (step S558). In this command reception process, various commands related to payout from the main control board 4100 (award ball command and self-check command shown in FIG. 40) are received. When the various commands are normally received, the payer ACK information indicating that is stored in the output information storage area. On the other hand, when various commands cannot be received normally, a connection abnormality that indicates that an abnormality has occurred in the connection between the main control board 4100 and the payout control board 4110 (an abnormality has occurred in various command signals). Information is stored in the state information storage area described above.

  Subsequent to step S558, the payout control program performs command analysis processing (step S560). In this command analysis processing, the command received in step S558 is analyzed, and the analyzed command is stored as received command information in the received command information storage area of the payout control built-in RAM.

  Subsequent to step S560, the payout control program performs main operation setting processing (step S562). In this main operation setting process, operation settings such as winning balls, rental balls, ball removal and ball scoring are performed, retry operations are judged, and the number of unpaid balls (the number of winning ball stock) is monitored. To do.

  Subsequent to step S562, the payout control program performs LED display data creation processing (step S564). In this LED display data creation processing, various types of information are read from the state information storage area described above, display data to be displayed on the error LED indicator 860b of the payout control board 4110 is created, and LED display information is stored in the output information storage area described above. Remember. For example, when the above-mentioned ball piece information is read from the state information storage area and the number of game balls taken into the supply passage of the prize ball device 740 is not more than a predetermined number based on this piece of ball information, the corresponding display data (In this embodiment, a display value 1 (number “1”)) is created and LED display information is stored in the output information storage area.

  Subsequent to step S564, the payout control program performs command transmission processing (step S566). In this command transmission process, various types of information are read from the above-described state information storage area, and various commands (door opening command, door frame closing command, body frame opening) classified into the status display shown in FIG. 43 based on the various information. Main control board 4100 by creating a command, a body frame closing command, a frame state 1 command (corresponding to the first error occurrence command), an error canceling navigation command (corresponding to the first error canceling command) and a frame state 2 command) Send to. For example, when the out-of-ball information is read from the state information storage area, if the number of game balls taken into the supply passage of the prize ball device 740 is not equal to or greater than a predetermined number based on this out-of-ball information, a frame state 1 command is issued. When it is created and transmitted to the main control board 4100, or when the firing operation permission information is read from the state information storage area, a frame state 2 command (to notify that it is not a firing ball feed control circuit error) based on this firing operation permission information When the value 0 is set to B0 and transmitted to the main control board 4100 or when the firing operation prohibition information is read from the state information storage area, the frame state 2 command ( A value 1 is set in B0 in order to notify that it is a shot ball feed control circuit error.) Is generated and transmitted to the main control board 4100. Further, in this command transmission process, this payout control program, when there is a change in the frame state such as an error relating to a game ball payout operation, for example, information relating to the location of the error that has occurred with respect to this payout operation (hereinafter referred to as “the game ball payout operation”). A frame status 1 command (first error cancellation command) including “error occurrence position information”) is generated (error occurrence command generation means). On the other hand, in this command transmission process, if the payout control program indicates that the payout RAM clear notification flag HRCL-FLG has a value of 1, that is, if an operation signal corresponding to the operation of the operation switch 860a is detected, the error described above. A cancellation navigation command (first error cancellation command) is output (command sending means). The payout control program transmits a body frame release command (first body frame release command) when a body frame release detection signal is input from the body frame release switch 619 (body frame command sending means, 1 body frame command sending means). A walker, this payout control program, when a body frame closing detection signal from the body frame opening switch 619 is inputted, transmits a body frame closing command (first body frame closing command) (body frame command sending means) , First body frame command sending means). Further, the payout control program transmits a door frame opening command (first door frame opening command) when a door frame opening detection signal is input from the door frame opening switch 618 (door frame command sending means; 1 door frame command sending means). On the other hand, when a door frame closing detection signal is input from the door frame opening switch 618, the payout control program transmits a door frame closing command (first door frame closing command) (door frame command sending means, 1 door frame command sending means). In addition, the payout control program reads out error information including error contents from the state information storage area described above in the command transmission process (step S566) described above, and the machine number information for identifying itself from other pachinko machines, and An error information signal based on the error information is output to the hall computer via the external terminal board 784. Upon receiving this error information signal, the hall computer provides the above-mentioned machine number information and error information to the radio device possessed by the hall clerk, and this hall clerk provides the pachinko machine with the machine number based on this machine number information. It is possible to recognize that the error content included in the error information has occurred.

  Subsequent to step S566, the payout control program sets a value C in the watchdog timer clear register HWCL (step S568). By setting the value C in the watchdog timer clear register HWCL in step S568, the value C is set in the watchdog timer clear register HWCL following the value B set in step S546. As a result, the value A, the value B, and the value C are sequentially set in the watchdog timer clear register HWCL, and the watchdog timer is cleared.

  Following step S568, the process returns to step S539 again, and the payout control program sets a value A to the watchdog timer clear register HWCL, and whether or not a power failure warning signal (paid power failure warning signal) is input in step S540. If this power failure warning signal (paid power failure warning signal) is not input, it is determined in step S542 whether or not the 2 ms elapsed flag HT-FLG has a value of 1, and the 2 ms elapsed flag HT-FLG has a value of 1. When 2 ms has elapsed, that is, when 2 ms has elapsed, the value 0 is set in the 2 ms elapsed flag HT-FLG in step S544, the value B is set in the watchdog timer clear register HWCL in step S546, and port output processing is performed in step S548 In step S550, port input processing is performed. In step S552, Immediate update processing is performed, CR communication processing is performed in step S554, full tank and out of ball check processing is performed in step S556, command reception processing is performed in step S558, command analysis processing is performed in step S560, and main processing is performed in step S562. Operation setting processing is performed, LED display data creation processing is performed in step S564, command transmission processing is performed in step S566, value C is set in watchdog timer clear register HWCL in step S568, and steps S539 to S568 are repeated. . The processing from step S539 to step S568 is referred to as “payout control unit main processing”.

  Depending on the progress of the game by the main control board 4100, the processing content of the payout control unit main process varies. For this reason, the time required for the processing of the payout control MPU 4120a varies. Accordingly, the payout control MPU 4120a preferentially outputs to the main control board 4100 a payer ACK signal notifying that various commands related to payout from the main control board 4100 have been normally received in the port output processing of step S548. Yes. As a result, the payout control MPU 4120a ensures the processing time so that other fluctuating processes can be sufficiently performed.

  On the other hand, when a power failure warning signal (paid power failure warning signal) is input in step S540, interrupt prohibition setting is performed (step S570). With this setting, the payout control unit timer interrupt processing described later is not performed, writing to the payout control built-in RAM is prevented, and rewriting of the payout information described above is protected.

  Subsequent to step S570, the payout control program stops outputting the drive signal to the payout motor 744 (step S574). Thereby, payout of the game ball is stopped.

  Subsequent to step S574, the payout control program performs clear setting of the watchdog timer (step S576). As described above, the clear setting is performed by sequentially setting the value A, the value B, and the value C in the watchdog timer clear register HWCL.

  Subsequent to step S576, the payout control program calculates a checksum and stores the calculated value (step S578). The checksum is calculated by regarding the payout information in the work area of the payout control built-in RAM as a numerical value excluding the storage area for the checksum value calculated in step S524 and the payout backup flag HBK-FLG.

  Subsequent to step S578, the payout control program sets a value 1 to the payout backup flag HBK-FLG (step S580). Thereby, storage of the payout backup information is completed.

  Subsequent to step S580, the payout control program performs prohibition of access to the payout control built-in RAM (step S582). With this setting, access to the payout control built-in RAM is prohibited and writing and reading cannot be performed, and payout backup information stored in the payout control internal RAM is protected.

  Following step S582, the payout control program enters an infinite loop. In this infinite loop, the value A, the value B, and the value C are not set in this order in the watchdog timer clear register HWCL, so that the watchdog timer is not cleared. Therefore, the payout control MPU 4120a is reset, and thereafter, the payout control program performs the payout control unit power-on process again under the control of the payout control MPU4120a. Note that the processing in step S570 to step S582 and the infinite loop are referred to as “payout control unit power-off processing”.

  The pachinko gaming machine 1 (payout control MPU 4120a) is reset when a power failure occurs or when an instantaneous power failure occurs, and performs a payout control unit power-on process upon power recovery thereafter.

  In step S526, it is checked whether or not the payout backup information stored in the payout control built-in RAM is normal, and then in step S528, whether or not the payout control unit power-off process is normally completed. Are inspected. In this way, by checking the payout backup information stored in the payout control built-in RAM twice, it is checked whether or not the payout backup information is stored by fraud.

[16-2. Payment control unit timer interrupt processing]
Next, the payout control unit timer interrupt process will be described. This payout control unit timer interrupt process is repeated at every interrupt cycle (2 ms in this embodiment) set in the payout control unit power-on process shown in FIGS.

  When the payout control unit timer interrupt process is started, in the payout control unit 4120 of the payout control board 4110, the payout control program sets the timer interrupt to be prohibited as shown in FIG. 50 under the control of the payout control MPU 4120a. Then, the register is switched (saved) (step S590). Here, the general purpose storage element (general purpose register) used in the above-described payout control unit main process is switched to the auxiliary register. By using this auxiliary register in the payout control unit timer interrupt process, the value of the general-purpose register is not overwritten. This prevents the contents of the general-purpose register used in the payout control unit main process from being destroyed.

  Subsequent to step S590, the payout control program sets a value 1 to the 2 ms elapsed flag HT-FLG (step S592). This 2 ms elapsed flag HT-FLG is a flag that counts 2 ms every time this payout control unit timer interrupt processing is performed, that is, every 2 ms, a value of 1 when 2 ms elapses, and a value of 0 when 2 ms elapses. Each is set.

  Subsequent to step S592, the payout control program switches (returns) the register (step S594). This restoration is switched from the auxiliary register used in the payout control unit timer interrupt processing to the general-purpose storage element (general-purpose register). By using this general-purpose register in the payout control unit main process, the value of the auxiliary register is not overwritten. This prevents destruction of the contents of the auxiliary register used in the payout control unit timer interrupt process.

  Subsequent to step S594, the payout control program sets interrupt permission (step S596), and ends this routine.

[16-3. Rotation angle switch history creation process]
Next, rotation angle switch history creation processing will be described. In this rotation angle switch history creation processing, a history of detection signals from the rotation angle switch 752 shown in FIG. 13 is created.

  When the rotation angle switch history creation process is started, the payout control unit 4120 in the payout control board 4110 executes a payout control program from the payout control built-in RAM as shown in FIG. 51 under the control of the payout control MPU 4120a. The switch detection history information RSW-HIST is read (step S610). This rotation angle switch detection history information RSW-HIST is 1 byte (8 bits: most significant bits B7, B6, B5, B4, B3, B2, B1, least significant bit B0, "B" represents a bit). A history of detection signals from the rotation angle switch 752 is stored as rotation angle switch detection history information RSW-HIST in the rotation angle switch history information storage area of the payout control built-in RAM. In step S610, rotation angle switch detection history information RSW-HIST is read from the rotation angle switch history information storage area.

  Subsequent to step S610, the payout control program determines whether there is a detection signal from the rotation angle switch 752 (step S612). This determination is made based on the detection signal from the rotation angle switch 752 in the port input process of step S550 in the payout control part power-on process (payout control part main process) shown in FIG. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S612, input information is read from this input information storage area, and it is determined whether or not there is a detection signal from the rotation angle switch 752. When there is a detection signal from the rotation angle switch 752 in the input information, the payout control program detects the rotation position of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. It is determined that the shaft is in a state where the shaft has transitioned from the cut-off state to the non-cut-off state. On the other hand, when there is no detection signal from the rotation angle switch 752 in the input information, the payout control program determines that the detection slit has changed the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state.

  When the detection slit is in a state where the optical axis of the rotation angle switch 752 is changed from the blocked state to the non-blocked state in step S612, the payout control program performs a rotation process of the rotation angle switch detection history information (step S614). In this rotation angle switch detection history information shift process, the rotation angle switch detection history information RSW-HIST read in step S610 is converted into the most significant bits B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2. , B2 ← B1, B1 ← the least significant bit B0, and so on, and is shifted bit by bit from the least significant bit B0 toward the most significant bit B7.

  Subsequent to step S614, the payout control program sets the value 1 to the least significant bit B0 of the rotation angle switch detection history information RSW-HIST (step S616), and ends this routine.

  On the other hand, when the detection slit is in a state where the optical axis of the rotation angle switch 752 is changed from the non-blocking state to the blocking state in step S612, the payout control program performs the rotation angle switch detection history information shift process (step S618). . In the rotation angle switch detection history information shift process, the payout control program performs the same process as the rotation angle switch detection history information shift process in step S614, and the rotation angle switch detection history information RSW-HIST read in step S610. From the least significant bit B0 to the most significant bit B7, such as B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2, B2 ← B1, B1 ← the least significant bit B0. Shift one bit at a time.

  Subsequent to step S618, the payout control program sets the value 0 to the least significant bit B0 of the rotation angle switch detection history information RSW-HIST (step S620), and ends this routine.

  Thus, each time this rotation angle switch history creation process is performed, the detection slit rotates after the rotation angle switch detection history information RSW-HIST is shifted bit by bit from the least significant bit B0 toward the most significant bit B7. Depending on the state in which the optical axis of the angle switch 752 has been changed from the non-blocking state to the non-blocking state or the state in which the detection slit has shifted the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state, Since the value 0 is set, a history of detection signals from the rotation angle switch 752 can be created.

[16-4. Sprocket fixed position determination skip processing]
Next, the sprocket fixed position determination skip process will be described. This sprocket fixed position determination skip process skips the determination of whether or not the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted is in a fixed position when a predetermined condition is satisfied. The fixed position determination of the payout rotator is also performed when the payout of the game ball by the prize ball device 740 is completed. Thereby, rotation of the rotating shaft of the payout motor 744 can be reliably started in a state in which no ball is generated.

  When the sprocket fixed position determination skip process is started, the payout control unit 4120 in the payout control board 4110 causes the payout control program to execute a fixed position determination skip flag SKP− as shown in FIG. 52 under the control of the payout control MPU 4120a. It is determined whether FLG is 0 (step S630). The fixed position determination skip flag SKP-FLG is a flag indicating whether or not the fixed position determination of the payout rotating body is to be performed, and is 1 when the fixed position determination of the payout rotating body is not performed (when skipping). The value is set to 0 when the body position determination is performed (when skipping is not performed).

  When the fixed position determination skip flag SKP-FLG is 0 (not skipped) in step S630, that is, when the fixed position determination of the payout rotating body is performed, the payout control program stores the rotation angle switch history information of the payout control built-in RAM. The rotation angle switch detection history information RSW-HIST is read from the storage area (step S632), and it is determined whether or not it matches the fixed position determination value (step S634). This fixed position determination value is stored in the payout built-in ROM, and is “00001111B (“ B ”represents a bit)” in this embodiment, and the upper 4 bits B7 to B4 are the value 0 and the lower 4 Bits B3 to B0 have a value of 1. In the determination in step S634, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  Here, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST have the value 1, the above described detection slit is the optical axis of the rotation angle switch 752 continuously in four timer interruption cycles. Is a state in which the state is changed from the cut-off state to the non-cut-off state. In the occurrence of the four timer interruption cycles, the payout motor 744 shown in FIG. 13 rotates four steps. The rotation of the payout motor 744 is the rotation of the payout rotating body of the rotation detection board via the first gear, the second gear, and the third gear. Since these first gear, second gear, and third gear have play (backlash), the payout rotating body rotates clockwise or counterclockwise. Since the rotation is designed to be equivalent to about two steps of rotation of the payout motor 744, in this embodiment, when the fixed position determination of the payout rotating body is performed, the rotation angle switch 752 The rotation angle switch detection history information RSW-HIST is generated by the detection signal history, rotation angle switch history generation processing shown in FIG. 51, and the lower 4 bits B3 to B0 of the generated rotation angle switch detection history information RSW-HIST, that is, This is performed based on a detection signal from the rotation angle switch 752 when the latest four timer interruption periods occur. As a result, in the four timer interruption cycles, the payout motor 744 rotates four steps, so that it rotates more than the rotation of the payout rotator due to backlash and absorbs the rotation of the payout rotator due to backlash. Can do. Accordingly, since it is possible to prevent erroneous detection of the fixed position of the payout rotating body due to backlash, the rotational position of the payout rotating body can be correctly managed by the rotational position of the payout motor 744. In the present embodiment, the four timer interruption periods are 8 ms (= 2 ms × 4 times), and are set as the backlash absorption time.

  In step S634, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S632 match the lower 4 bits B3 to B0 of the fixed position determination value, the payout control program A value 1 is set to the fixed position determination skip flag SKP-FLG (step S636). Thereby, it can set so that the fixed position determination of the paying-out rotating body is not performed (skip). The payout control MPU 4120a sets the rotation position of the payout rotating body in step S636 to the fixed position of the payout rotating body.

  Subsequent to step S636, the payout control program sets the skip determination time to be valid (step S638), and ends this routine. Here, the number of detection slits is three, which is the same as the number of recesses of the payout rotating body, and is formed equally (every 120 degrees) on the outer periphery of the rotation detection board. Further, as described above, the rotation of the payout motor 744 is the rotation of the payout rotating body of the rotation detection board via the first gear, the second gear, and the third gear. In the present embodiment, the rotation between the detection slits (120 degrees) of the rotation detection board (dispensing rotary body) is designed to correspond to the 18-step rotation of the dispensing motor 744.

  The payout control program manages the rotational position of the payout rotating body based on the number of steps of the payout motor 744 under the control of the payout control MPU 4120a. Specifically, (1) a transition state in which the detection slit changes the optical axis of the rotation angle switch 752 from a cutoff state to a non-blocking state (referred to as an “edge detection state”), and (2) the detection slit has a rotation angle. A state in which the optical axis of the switch 752 has transitioned from a blocked state to a non-blocked state (referred to as a “fixed position determined state”), and (3) a detection slit shifts the optical axis of the rotation angle switch 752 from a non-blocked state to a blocked state. And three states (the “fixed position determination skip state”). The edge detection state of (1) corresponds to one step rotation of the payout motor 744, the fixed position determination state of (2) corresponds to four step rotation of the payout motor 744, and the fixed position determination skip state of (3). Corresponds to 13 steps of rotation of the payout motor 744, and the rotation position between the detection slits (120 degrees) of the rotation detection board, that is, the rotation position of the payout rotating body is managed by a total of 18 steps of rotation.

  In the fixed position determination skip state of (3), the detection slit is in a state where the optical axis of the rotation angle switch 752 has transitioned from the non-blocking state to the blocking state. Is set. As described above, since the timer interruption period is set to 2 ms, the skip determination time is 26 ms (= 2 ms × 13 steps).

  When the skip determination time becomes valid in step S638, the skip determination time is subtracted in the timer update process in step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. The payout control MPU 4120a subtracts the skip determination time, and when the subtraction result becomes 0, sets the initial value 0 to the fixed position determination skip flag SKP-FLG.

  On the other hand, when the fixed position determination skip flag SKP-FLG is not 0 (value 1) (when skipping) in step S630, that is, when the fixed position determination of the payout rotating body is not performed, or in step S634, step S632 is performed. When the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read out in step 4 do not match the lower 4 bits B3 to B0 of the fixed position determination value, the payout control program ends this routine as it is. . Note that the fixed position determination skip flag SKP-FLG set in step S636 is stored in the general-purpose storage element (general-purpose register) of the payout control MPU 4120a.

  The game balls supplied from the pachinko island facility are stored in the prize ball tank 720 and the tank rail 731, taken into the supply path of the prize ball device 740, and guided to the prize ball device 740. When the game balls rub against each other and are charged, electrostatic discharge is generated and noise is generated. For this reason, the prize ball device 740 is susceptible to noise and is in an environment. The rotation angle switch board 753 of the prize ball apparatus 740 shown in FIG. 3 is provided with a rotation angle switch 752, and the detection signal from the rotation angle switch 752 is affected by noise due to electrostatic discharge of the game ball. Cheap. In addition, the wiring (harness) for connecting the payout control board 4110 and the board 754 in the prize ball case 740 in the prize ball apparatus 740 shown in FIG. 3 is also affected by noise due to electrostatic discharge of the game ball. Cheap.

  Therefore, in this embodiment, in order to suppress erroneous detection due to the influence of noise, the fixed position determination skip state (3) described above, that is, the detection slit changes the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state. In the transitioned state, the fixed position determination of the payout rotating body is not performed. Thereby, the precision of the fixed position determination of the paying-out rotating body is increased. In addition, since the period and period required for detecting the fixed position of the payout rotating body can be obtained by calculation in advance as described above, the skip determination time can be easily set and adjusted.

[16-5. Spherical spot detection processing]
Next, the sphere collision determination process will be described. In this ball collision determination process, it is determined whether or not a ball collision state has occurred due to the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted.

  When the ball collision determination process is started, the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110, as shown in FIG. The switch detection history information RSW-HIST is read (step S640).

  Subsequent to step S640, the payout control program determines whether there is a detection signal from the rotation angle switch 752 described above (step S642). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S640 matches the home position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in this embodiment, is “00001111B (“ B ”represents a bit)”, and the upper 4 bits B7 to B4 are the same. The value 0 and the lower 4 bits B3 to B0 are the value 1. In the determination in step S642, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  In step S642, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S640 match the lower 4 bits B3 to B0 of the fixed position determination value, the payout control program This routine is finished as it is, assuming that the detection slit has changed the optical axis of the rotation angle switch 752 from the non-blocking state to the blocking state, that is, the payout rotating body is rotating, and no ball-spinning state has occurred. To do.

  On the other hand, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read out at step S640 and the lower 4 bits B3 to B0 of the fixed position determination value do not match in step S642, a sphere is seen. A value 1 is set in the middle flag PBE-FLG (step S644). This ball-spinning flag PBE-FLG is a flag indicating whether or not a ball-spinning state due to the payout rotating body has occurred. When no operation is performed, the value is set to 0.

  Subsequent to step S644, the payout control program sets the ball collision determination time to be valid (step S646), and ends this routine. When this ball stagnation determination time becomes valid, the sphere sag determination time is subtracted in the timer update process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. .

[16-6. Various prize ball stock addition processing]
Next, various prize ball stock number addition processing will be described. The prize ball stock number addition process includes a prize ball prize ball number addition process and a rental ball prize ball number addition process. The prize ball stock number addition process is performed from the main control board 4100. This is a process for adding the number of balls to be paid out based on a prize ball command, which will be described later. is there. First, the award ball stock number addition process for prize balls will be described, and then the award ball stock number addition process for rental balls will be described. In this embodiment, the prize ball stock number addition process for prize balls is set to be performed preferentially, and according to the number of prize balls stock added in this prize ball stock number addition process. After the game ball is paid out by the prize ball device 740, it is set so that the number of prize ball stock for lending is added.

[16-6-1. Prize ball stock number addition process for prize balls]
When the award ball stock number addition processing for the prize ball is started, the payout control unit 4120 in the payout control board 4110 executes a payout control program as shown in FIG. 54 under the control of the payout control MPU 4120a. It is determined whether or not there is (step S650). This determination is made based on the command analyzed in the command analysis process in step S560 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the analyzed command is stored as received command information in the received command information storage area of the payout control built-in RAM. In step S650, the payout control program reads the received command information from the received command information storage area and determines whether or not it is a prize ball command.

  When the received command information is not a prize ball command in step S650, the payout control program ends this routine as it is. On the other hand, when the received command information is a prize ball command in step S650, the payout control program receives the prize ball command. The corresponding prize ball number PBV is read from the prize ball number information table (step S652). The prize ball number information table, which will be described in detail later, is an information table stored in advance in the payout built-in ROM in association with the prize ball command and the prize ball number PBV.

  Subsequent to step S652, the payout control program reads the prize ball stock number PBS from the payout control built-in RAM (step S654). This award ball stock PBS represents the number of game balls that have not yet been paid out by the prize ball device 740, that is, the number of unpaid balls, and has a storage capacity of 2 bytes (16 bits) in this embodiment. ing. As a result, the award ball stock number PBS can store the number of unpaid balls from 0 to 32767. The prize ball stock PBS is stored in the prize ball information storage area of the payout control built-in RAM. In step S652, the prize ball stock number PBS is read from the prize ball information storage area.

  The payout control program adds the prize ball number PBV read in step S652 to the prize ball stock number PBS read in step S654 (step S656), and ends this routine. Note that after the addition in step S656, the prize ball command read in step S650 is erased from the received command information storage area.

[16-6-2. Addition of prize ball stock for rental balls]
Next, the processing for adding the number of winning ball stocks will be described. When the lending prize ball stock number addition process is started, the payout control unit 4120 in the payout control board 4110 executes a payout request as shown in FIG. 55 under the control of the payout control MPU 4120a. It is determined whether or not there is a signal (step S660). This determination is made based on the lending request signal from the CR unit 6 in the port input process of step S550 in the payout control part power-on process (payout control part main process) shown in FIG. Specifically, the lending request signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S660, the payout control program reads input information from the input information storage area and determines whether or not there is a lending request signal.

  When there is no lending request signal in step S660, the payout control program ends this routine as it is. On the other hand, when there is a lending request signal in step S660, the payout control program reads the prize ball information in the above-described payout control built-in RAM. The winning ball stock number PBS is read from the storage area (step S662), the rented ball number RBV is added to the winning ball stock number PBS (step S664), and this routine is finished. The number of rented balls RBV is a fixed value and is stored in advance in the payout built-in ROM. In the present embodiment, the value 25 is set as the number of rented balls RBV. In addition, after adding in step S664, the payout control program deletes the ball rental request signal read in step S660 from the input information storage area. Further, in this embodiment, the winning ball is prioritized (the winning ball and the lending are managed separately), so even if there is a lending request signal, the lending request signal is held. When a prize ball is paid out, a rental ball is paid out. Therefore, in this embodiment, the payout of the rented ball is performed after the prize ball stock PBS reaches the value 0.

[16-7. Stock monitoring process]
Next, the stock monitoring process will be described. This stock monitoring process monitors whether or not the player continues playing the game in a state where the storage space of the foul cover unit 540 shown in FIG. It is processing to do.

  When the stock monitoring process is started, the payout control unit 4120 in the payout control board 4110 causes the payout control program to display the award ball information in the payout control built-in RAM as shown in FIG. 56 under the control of the payout control MPU 4120a. The prize ball stock number PBS is read from the storage area (step S670), and it is determined whether or not the read prize ball stock number PBS is equal to or greater than the careful threshold value TH (step S672). The caution threshold TH is a fixed value and is stored in advance in the payout built-in ROM. In the present embodiment, the value 50 is set as the caution threshold TH.

  When the winning ball stock number PBS is greater than or equal to the caution threshold TH in step S672, the payout control program sets a value 1 to the caution flag CA-FLG (step S674), and the routine is terminated. This caution flag CA-FLG indicates that the player starts stocking of game balls in the storage space of the foul cover unit 540, and the number of game balls not paid out (the number of prize balls described above) exceeds the caution threshold TH. It is a flag indicating that it has been reached, and is set to a value of 1 when the threshold value exceeds the alert threshold value TH, and to a value of 0 when it does not reach the alert threshold value TH or more.

  On the other hand, when the winning ball stock number PBS is less than the caution threshold TH in step S672, the payout control program sets a value 0 to the caution flag CA-FLG (step S676), and this routine is ended.

  The game state becomes a big hit, and the player relaxes and sees the effects unfolded by the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d and the upper plate side liquid crystal display device 470 shown in FIG. If the player is inadvertent, the player may not inadvertently remove the game ball paid out as a prize ball for one round by operating the lower plate ball removal button 354 from the lower plate 302 shown in FIG. is there. When the game is continued in this state, the lower plate 302 is filled with game balls, and the game balls are accumulated in the accommodation space of the foul cover unit 540. When the storage space of the foul cover unit 540 is filled with game balls, as described above, the value of the award ball stock PBS increases to exceed the caution threshold TH, and is provided in the door frame 5 as a caution effect. A plurality of LEDs on various decorative boards blink. By this blinking, for example, it is possible to inform a hall clerk of paying attention to the player's game. As a result, the hall clerk can tell the player that he / she wants to remove the game ball from the lower plate 302, and the player fills the lower plate 302 (the storage space of the foul cover unit 540) with the game ball full. It is possible to prevent the game from continuing.

  In the present embodiment, the careful threshold value TH is set to a value 50 corresponding to about one fifth of the upper limit value 255 that can be represented by 1 byte (8 bits). As a result, it is possible to inform the hall clerk that the player should be alerted to the game as early as possible.

[16-8. Dispensing ball edge motion determination setting process]
Next, the payout ball engagement operation determination setting process will be described. This paying ball sliding motion determination setting processing is performed by paying out the game ball to the upper plate 301 or the lower plate 302 shown in FIG. This is a process for setting whether or not to discharge or not.

  When the payout ball engagement operation determination setting process is started, the payout control unit 4120 in the payout control board 4110 has the payout control program built in the payout control described above as shown in FIG. 57 under the control of the payout control MPU 4120a. The rotation angle switch detection history information RSW-HIST is read from the rotation angle switch history information storage area of the RAM (step S680).

  Subsequent to step S680, the payout control program determines whether there is a detection signal from the rotation angle switch 752 shown in FIG. 13 (step S682). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S680 matches the home position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in this embodiment, is “00001111B (“ B ”represents a bit)”, and the upper 4 bits B7 to B4 are the same. The value 0 and the lower 4 bits B3 to B0 are the value 1. In the determination in step S682, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  In step S682, when the payout control program matches the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read out in step S680 and the lower 4 bits B3 to B0 of the fixed position determination value, It is determined whether or not the retry error flag RTERR-FLG is 1 (step S684). The retry error flag RTERR-FLG is a flag indicating whether or not a retry operation described later is operating abnormally. The value is 1 when the retry operation is operating abnormally, and the retry operation is not operating abnormally (retry operation). When the operation is normal), the value is set to 0.

  If it is determined in step S682 that the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S680 do not match the lower 4 bits B3 to B0 of the fixed position determination value, or in step S684. When the retry error flag RTERR-FLG is not a value 1 (value 0), that is, when the retry operation is not operating abnormally, the payout control program determines whether or not the ball colliding flag PBE-FLG is a value 1. Is determined (step S686). This in-between-ball flag PBE-FLG is a flag that indicates whether or not a ball-bending state due to the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. A value of 1 is set when the motion is being performed, and a value of 0 is set when the ball motion is not performed.

  When the ball-picking flag PEB-FLG is not the value 1 (value 0) in step S686, that is, when the ball-pushing operation is not performed, the payout control program stores the award ball information stored in the above-described payout control built-in RAM. The prize ball stock number PBS is read from the area (step S688), and it is determined whether or not the read prize ball stock number PBS is larger than 0 (step S690). In this determination, it is determined whether or not there are unpaid balls in the payout of game balls by the payout motor 744.

  When the winning ball stock number PBS is greater than 0 in step S690, that is, when there is an unpaid ball number, the payout control program determines whether or not the game ball in which the accommodation space of the foul cover unit 540 is stored is full. Is determined (step S692). This determination is made based on the full tank information stored in the full tank and ball-out check process in step S556 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the full tank information is stored in the state information storage area of the payout control built-in RAM described above. In step S692, the full tank information is read from the state information storage area to determine whether or not the storage space of the foul cover unit 540 is full with the stored game balls.

  When the storage space of the foul cover unit 540 is not full in step S692, the payout control program performs payout setting processing (to be described later) (step S694), and this routine is ended. In this payout setting process, a payout operation for paying out game balls to the upper plate 301 and the lower plate 302 is performed.

  On the other hand, when the game ball in which the accommodation space of the foul cover unit 540 is stored is full in step S692, the payout control program ends this routine as it is. In the pachinko gaming machine 1 of the present embodiment, the payout motor 744 is forcibly stopped when the storage space of the foul cover unit 540 is full with the stored game balls. When a prize ball is generated while the payout motor 744 is forcibly stopped, the number of unpaid balls by the payout motor 744 increases, and the prize ball stock number PBS is added by the prize ball prize ball number addition process shown in FIG. Will increase.

  On the other hand, when the winning ball stock number PBS is not greater than 0 (value 0) in step S690, that is, when there is no unpaid ball number, the payout control program ends this routine as it is. As a result, game balls are not paid out.

  On the other hand, when the ball bending flag PBE-FLG is 1 in step S686, that is, when the ball bending operation is being performed, the payout control program performs a ball bending operation setting process described later (step S700). Exit. In this ball-spinning operation setting process, a ball-spinning operation that cancels the ball-spinning state by the payout rotating body of the prize ball device 740 is performed.

  On the other hand, when the retry error flag RTERR-FLG is 1 in step S684, that is, when the retry operation is abnormally performed, the payout control program sets the output stop (stop) of the drive signal to the payout motor 744. (Step S702). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM described above.

  Subsequent to step S702, the payout control program sets an error status output to the CR unit 6 (step S704), and ends this routine. In step S704, when the payout control program is not communicating with the CR unit 6 under the control of the payout control MPU 4120a in order to inform the CR unit 6 that the ball lending is not possible at present (CR unit 6). The logic of the PRDY signal from LOW, that is, held down and held), the logic of the PRDY signal is held LOW, that is, the state of falling is held, and the logic state of the PRDY signal is set in the PRDY signal output setting information And stored in the CR communication information storage area. Thus, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is transferred from the output terminal of a predetermined output port of the payout control MPU 4120a of the payout control unit 4120 to the game ball lending device connection terminal plate 869. Output to unit 6. On the other hand, when communicating with the CR unit 6 (when the BRDY logic from the CR unit 6 is HI, that is, rises and is held), the logic state of the EXS signal is maintained and the logic state of the EXS signal is maintained. Is set in the EXS signal output setting information and stored in the CR communication information storage area. Thus, the EXS signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read EXS signal output setting information, that is, the EXS signal whose logic is maintained is output from the output terminal of a predetermined output port of the payout control MPU 4120a to the CR unit 6 via the gaming ball lending device connection terminal plate 869. . Note that “maintain the logic state of the EXS signal” means that when the logic of the EXS signal is LOW (when the EXS signal falls and is held), the logic of the EXS signal is HI. In some cases (when the EXS signal is held up), the logic HI is maintained.

[16-8-1. Withdrawal setting process]
Next, the payout setting process will be described. In this payout setting process, the payout motor 744 is driven to make a setting for paying out game balls.

  When the payout setting process is started, the payout control unit 4120 in the payout control board 4110 causes the payout control program to set the drive command number DRV from the payout control built-in RAM as shown in FIG. 58 under the control of the payout control MPU 4120a. Read (step S710). This drive command number DRV commands the number of game balls to be paid out by the payout motor 744, and is equivalent to the prize ball stock number PBS. The drive command number DRV is stored in the prize ball information storage area of the payout control built-in RAM. In step S710, the drive command number DRV is read from the prize ball information storage area.

  Subsequent to step S710, the payout control program determines whether or not the drive command number DRV is 0 (step S712). This determination is made based on the drive command number DRV as to whether or not the number of game balls to be paid out by the payout motor 744 remains.

  When the drive command number DRV is 0 in step S712, that is, when the number of game balls to be paid out by the payout motor 744 is zero, the payout control program stops outputting (stopping) the drive signal to the payout motor 744. ) Is set (step S714). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the above-described payout control built-in RAM.

  Subsequent to step S714, the payout control program reads the prize ball stock number PBS from the prize ball information storage area of the payout control built-in RAM (step S716), and reads the real ball count PB (step S718). The actual ball count PB is obtained by counting the number of game balls actually paid out by the payout motor 744. This count will be described later in detail, but in the port input process in step S550 in the payout control unit power-on process (payout control unit main process) shown in FIG. This is performed based on the detection signal. The real ball count PB is stored in the prize ball information storage area of the payout control built-in RAM. In step S718, the real ball count PB is read from this prize ball information storage area.

  Subsequent to step S718, the payout control program sets a value obtained by subtracting the actual ball count PB read in step S718 from the prize ball stock number PBS read in step S716 to the prize ball stock number PBS and the drive command number DRV. (Step S720), the real ball count PB is set to 0 (step S722), and this routine is terminated. When the drive command number DRV and the real ball count PB are 0, in step S722, the value of the prize ball stock number PBS read in step S716 is set as the drive command number DRV as it is.

  On the other hand, when the drive command number DRV is not 0 in step S712, that is, when there is a number of game balls to be paid out by the payout motor 744, the payout control program sets an output of a drive signal to the payout motor 744. (Step S724). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

  Subsequent to step S724, the payout control program subtracts 1 from the drive command number DRV (decrements, step S726), and determines whether there is a detection signal from the count switch 751 (step S728). This determination is made based on the detection signal from the count switch 751 in the port input process of step S550 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the detection signal is stored as input information in the input information storage area of the payout control built-in RAM. In step S728, the payout control program reads input information from the input information storage area and determines whether or not there is a detection signal from the counting switch 751.

  When there is a detection signal from the counting switch 751 in step S728, the payout control program adds 1 to the actual ball count PB (increments, step S730), and this routine is terminated. In step S730, the real ball count PB is incremented by incrementing the real ball count PB.

  On the other hand, when there is no detection signal from the counting switch 751 in step S728, the payout control program ends this routine as it is. As described above, the payout control program is a case where the drive command number DRV is decremented in step S726 under the control of the payout control MPU 4120a, and when there is no detection signal from the counting switch 751 in the determination in step S728, that is, If the ball count PB is not incremented, one game ball could not be paid out because the game ball was not received in the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 was transmitted. to decide. Therefore, the payout control program sets the value obtained by subtracting the real ball count PB from the prize ball stock number PBS to the drive command number DRV in step S720 described above in order to pay out one ball that should be paid out again. Thereby, when there is no detection signal from the counting switch 751 in the determination of step S728, that is, when the actual ball count PB is not incremented, the value 1 which is one ball that should be paid out is included in the prize ball stock number PBS. In other words, since the value 1 which is one ball to be paid out can be rounded into the winning ball stock number PBS, a retry operation of paying out the one ball to be paid out again can be performed. By performing this retry operation, the possibility of unpaid game balls to the player can be extremely reduced, and a player's disadvantage due to unpaid game balls can be prevented.

[16-8-2. Spherical motion setting process]
Next, the spherical cornering operation setting process will be described. This ball-spinning operation setting process is a process for performing a setting for canceling the ball-spinning state by the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 of the prize ball device 740 is transmitted.

  When the ball staking operation setting process is started, the payout control unit 4120 in the payout control board 4110 causes the payout control program to pass the ball scouring determination time as shown in FIG. 59 under the control of the payout control MPU 4120a. It is determined whether or not (step S750). This determination is made on the basis of the ball detection time subtracted in the timer update process in step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the ball collision determination time is stored as time management information in the time management information storage area of the above-described payout control built-in RAM. In step S750, the time management information is read from the time management information storage area to determine whether or not the ball stagnation determination time has elapsed.

  When it is determined in step S750 that the ball collision determination time has not elapsed, the payout control program reads the rotation angle switch detection history information RSW-HIST from the rotation angle switch history information storage area of the payout control built-in RAM (step S752). .

  Subsequent to step S752, the payout control program determines whether there is a detection signal from the rotation angle switch 752 described above (step S754). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S752 matches the home position determination value. As described above, this fixed position determination value is stored in the payout built-in ROM, and in this embodiment, is “00001111B (“ B ”represents a bit)”, and the upper 4 bits B7 to B4 are the same. The value 0 and the lower 4 bits B3 to B0 are the value 1. In the determination in step S754, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  In step S754, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S752 do not match the lower 4 bits B3 to B0 of the fixed position determination value, the payout control program The output of the drive signal to the payout motor 744 is set so as to perform the ball collapsing operation (step S756), and this routine is finished. In this setting, drive information for outputting a drive signal to the payout motor 744 is set and stored in the output information storage area of the payout control built-in RAM described above.

  On the other hand, in step S754, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S752 and the lower 4 bits B3 to B0 of the fixed position determination value match, the payout control program Sets the stop of the drive signal to the payout motor 744 (step S758). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

  Subsequent to step S758, the payout control program sets a value of 0 to the in-ball flag PBE-FLG as the end of the ball-bending operation (step S760), and ends this routine. This ball-spinning flag PBE-FLG is a flag indicating whether or not a ball-spinning state due to the payout rotating body has occurred. When no operation is being performed (end of the ball collapsing operation), the value is set to 0, respectively.

  On the other hand, when the ball collision determination time has elapsed in step S750, the payout control program sets stop of the drive signal to the payout motor 744 (step S762). In this setting, drive information for stopping the drive signal is set in the payout motor 744 and stored in the output information storage area of the payout control built-in RAM.

  Subsequent to step S762, the payout control program sets an error state output to the CR unit 6 (step S764). Here, in order to notify the CR unit 6 that the ball lending is not possible at present, the payout control MPU 4120a is not communicating with the CR unit 6 (the logic of BRDY from the CR unit 6 is LOW, that is, The logic of the PRDY signal is LOW, that is, the state of falling is held, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. To do. Thus, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is transferred from the output terminal of a predetermined output port of the payout control MPU 4120a of the payout control unit 4120 to the game ball lending device connection terminal plate 869. Output to unit 6. On the other hand, when communicating with the CR unit 6 (when the BRDY logic from the CR unit 6 is HI, that is, rises and is held), the logic state of the EXS signal is maintained and the logic state of the EXS signal is maintained. Is set in the EXS signal output setting information and stored in the CR communication information storage area. Thus, the EXS signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read EXS signal output setting information, that is, the EXS signal whose logic is maintained is output from the output terminal of a predetermined output port of the payout control MPU 4120a to the CR unit 6 via the gaming ball lending device connection terminal plate 869. . As described above, “maintaining the logic state of the EXS signal” means that the logic LOW is maintained when the logic of the EXS signal is LOW (the EXS signal is held down), and the EXS signal is maintained. When the logic of HI is HI (the EXS signal is held high), the logic HI is maintained.

  Subsequent to step S764, the payout control program sets a value “0” to the ball-balling flag PBE-FLG as the ball-balling operation ends (step S766), and the routine is terminated.

[16-9. Retry operation monitoring process]
Next, the retry operation monitoring process will be described. This retry operation monitoring process is a process for monitoring whether or not a retry operation for paying out a game ball that should be paid out is performed normally.

  When the retry operation monitoring process is started, the payout control unit 4120 in the payout control board 4110 causes the payout control program to execute the rotation angle of the above-described payout control built-in RAM as shown in FIG. 60 under the control of the payout control MPU 4120a. The rotation angle switch detection history information RSW-HIST is read from the switch history information storage area (step S770).

  Subsequent to step S770, the payout control program determines whether there is a detection signal from the rotation angle switch 752 described above (step S772). In this determination, it is determined whether or not the rotation angle switch detection history information RSW-HIST read in step S770 matches the home position determination value. As described above, this fixed position determination value is stored in the payout control built-in ROM, and in this embodiment, is “00001111B (“ B ”represents a bit)”, and B7 to B4 of the upper 4 bits. Is the value 0, and the lower 4 bits B3 to B0 are the value 1. In the determination in step S772, it is determined whether or not the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST match the lower 4 bits B3 to B0 of the fixed position determination value.

  In step S772, when the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read in step S770 match the lower 4 bits B3 to B0 of the fixed position determination value, the payout control program The value 1 is added to the inconsistency counter INCC (increment, step S774). The inconsistency counter INCC includes the number of game balls received and paid out by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, the number of balls detected by the counting switch 751, The number of game balls received and paid out by the recess of the payout rotor coincides with the number of balls detected by the counting switch 751. The value is 0. The payout control program performs a retry operation in the payout installation process shown in FIG. 58, so that the number of game balls received and paid out by the concave portion of the payout rotating body by this retry operation and the actual counting switch Whether or not paying out game balls that do not match with the number of balls detected in 751 is repeatedly performed is determined by monitoring with the inconsistency counter INCC. The inconsistency counter INCC is stored in the prize ball information storage area of the payout control built-in RAM. In step S774, the payout control program increments the inconsistency counter INCC stored in the prize ball information storage area.

  Subsequent to step S774 or in step S772, the lower 4 bits B3 to B0 of the rotation angle switch detection history information RSW-HIST read out in step S770 do not match the lower 4 bits B3 to B0 of the fixed position determination value. Sometimes, the payout control program determines whether there is a detection signal from the counting switch 751 (step S776). This determination is performed based on the detection signal from the count switch 751 in the port input process in step S550 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, as described above, the detection signal is stored as input information in the input information storage area of the above-described payout control built-in RAM. In step S776, the payout control program reads input information from the input information storage area and determines whether or not there is a detection signal from the counting switch 751.

  When there is a detection signal from the counting switch 751 in step S776, the payout control program subtracts 1 from the inconsistency counter INCC stored in the award ball information storage area of the payout control built-in RAM (decrements, step S778). .

  Subsequent to step S778 or when there is no detection signal from the counting switch 751 in step S776, the payout control program determines whether or not the value of the mismatch counter INCC is smaller than the mismatch threshold INCTH (step S780). ). In the pachinko gaming machine 1, it has been experimentally obtained that the probability that one game ball that does not fit due to the retry operation is paid out is about one millionth, and in this embodiment, the mismatch threshold value The value 5 is set as INCTH.

  In the process of setting the work area of the payout control built-in RAM in step S530 in the payout control unit power-on process of FIG. Information used for the retry operation monitoring process is set based on the inconsistency counter INCC stored in the prize ball information storage area. By this processing, for example, even if there is a momentary power failure or a power failure, the value of the inconsistency counter INCC at the time of power recovery is restored to the value of the inconsistency counter INCC just before the momentary power failure or power failure stored as payout backup information Can be done. As a result, in the determination in step S780, the game ball payout operation (retry operation) performed by the prize ball device 740, which has been performed until immediately before a momentary power failure or power failure, can be continued from the time of power recovery. ing. Therefore, for example, immediately before a momentary power failure or power failure, if the value of the mismatch counter INCC is smaller than the mismatch threshold INCTH in the determination of step S780, it is determined that the retry operation is operating normally, that is, a prize ball It is determined that the game ball payout operation by the device 740 is in a normal state, and it can be determined that the game ball payout operation by the prize ball device 740 is in a normal state by the determination in step S780 even during power recovery. On the other hand, when the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in the determination in step S780, it is determined that the retry operation is abnormal, that is, the game ball payout operation by the prize ball device 740 is abnormal. Even when power is restored, it can be determined in step S780 that the game ball payout by the prize ball device 740 is in an abnormal state.

  If the value of the inconsistency counter INCC is smaller than the inconsistency threshold INCTH in step S780, this routine is terminated as it is. On the other hand, when the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in step S780, that is, when the value of the mismatch counter INCC is equal to or greater than the mismatch threshold INCTH, the payout control program displays “Retry error”. In order to notify that “there is a payout control built-in RAM, retry error information for displaying the number“ 5 ”is set on the error LED indicator 860b, which is a segment indicator mounted on the payout control board 4110. Is set (stored) in the state information storage area (step S782). On the other hand, when notifying that “the prize ball is in stock”, the payout control program sets the information in the prize ball stock to display the number “9” on the error LED indicator 860b and incorporates the above-described payout control. It is set (stored) in the status information storage area of the RAM (step S782).

  Subsequent to step S782, the payout control program sets a value 0 (initial value 0) to the inconsistency counter INCC stored in the prize ball information storage area of the payout control built-in RAM (step S784). In step S784, the mismatch counter INCC determines that the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in step S780, that is, the value of the mismatch counter INCC is greater than or equal to the mismatch threshold INCTH. Initialization is triggered by the occurrence of this internal factor. When the operation switch 860a is operated to clear the RAM when the power is turned on, the inconsistency counter INCC is initialized when the external factor occurs. When the operation switch 860a is operated when the power is turned on, as described above, an operation signal corresponding to the operation is input to the main control MPU 4100a of the main control board 4100 shown in FIG. 12 as a RAM clear signal. The main control program described above erases all the various information stored in the main control built-in RAM as described above under the control of the main control MPU 4100a, and displays the RAM clear notification command in the peripheral control board shown in FIG. 4140. Thereby, the RAM clear notification sound flows from the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the speaker 130 provided in the door frame 5 shown in FIG.

  Subsequent to step S784, the retry error flag RTERR-FLG is set to 1 (step S786), and this routine is terminated. This retry error flag RTERR-FLG is a flag indicating whether or not the retry operation is operating abnormally. The value is 1 when the retry operation is operating abnormally, and the retry operation is not operating abnormally (retry operation is not performed). It is set to a value of 0 when operating normally).

  Note that the payout control program shows the retry error information (or information in the prize ball stock) set (stored) in the output information storage area of the payout control built-in RAM in step S782 under the control of the payout control MPU 4120a, as shown in FIG. In the payout control unit power-on process (payout control unit main process), a retry error status command is created and transmitted to the main control board 4100 in the command transmission process in step S566, and LED display data creation in step S564 in the process is performed. In the process, display data to be displayed on the error LED display 860b is created and stored as LED display information in the output information storage area, and the LED display information stored in the output information storage area in the port output process of step S548 in the process is stored. Based on the error LED indicator 860b, To display the number "5" on the error LED display device 860b. In the main control board 4100 that has received the status command, the main control program transmits it to the peripheral control board 4140 in the peripheral control board command transmission process of step S120 in the main control timer interrupt process shown in FIG. The peripheral control board 4140 emits a plurality of LEDs on various decorative boards provided on the door frame 5 in a predetermined color (in this embodiment, red), and outputs a lighting signal on the door frame side. Are output to the frame decoration drive amplifier board 194, and a plurality of LEDs are caused to emit light in a predetermined color. As described above, the store clerk or the like who notices the light emission of the plurality of LEDs opens the main body frame 3 with respect to the outer frame 2 to thereby display the number "" on the error LED display 860b mounted on the payout control board 4110. By visually observing that “5” is displayed, it can be confirmed that a “retry error” has occurred. Thereby, in order to investigate the cause of the occurrence, the store clerk of the hall, etc., confirms the malfunction of the counting switch 751, the disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, the contact failure of various connectors, and the like. Compared with the case where the light emission of the plurality of LEDs and the display content of the error LED indicator 860b are not notified, it can be performed very quickly.

  In addition, it has been described above that it is difficult to detect the game ball that is received by the concave portion of the payout rotating body to which the rotation of the rotary shaft of the payout motor 744 is transmitted by intentionally disabling the counting switch 751. Even if an illegal act of forcibly generating a retry operation and illegally acquiring a game ball paid out by the retry operation is performed, the value of the inconsistency counter INCC is equal to or greater than the inconsistency threshold INCTH. Since the plurality of LEDs on the various decorative boards provided on the door frame 5 emit light, a hall clerk or the like rushes to confirm the state of the pachinko gaming machine 1. If it does so, the player who performs a fraudulent act will have to be interrupted so that the act may not be discovered, and the illegal game ball by a fraudulent act cannot be continuously acquired. Even if the value of the inconsistency counter INCC coincides with the inconsistency threshold INCTH, the number of game balls that can be obtained by a player who performs an illegal act is the same as the inconsistency threshold INCTH, that is, 5 balls Therefore, damage to the hall due to the act of intentionally deactivating the counting switch 751 can be suppressed to an extremely low level.

  Further, as described above, the mismatch counter INCC determines that the value of the mismatch counter INCC is not smaller than the mismatch threshold INCTH in step S780, that is, the value of the mismatch counter INCC is greater than or equal to the mismatch threshold INCTH. Initialization is triggered by the occurrence of an internal factor. As a result, the inconsistency counter INCC is not initialized when an external factor occurs, for example, that the operation switch 860a is operated to cancel the error. Therefore, even if the operation switch 860a or the like is illegally modified and the operation signal is input to the payout control MPU 4120a, the inconsistency counter INCC may be forcibly initialized by such an illegal action. Absent.

[16-10. Inconsistency counter reset judgment process]
Next, the mismatch counter reset process will be described. In this inconsistency counter reset process, the number of game balls received and paid out by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted, and the number of balls detected by the counting switch 751 This is a process for determining whether or not to reset the inconsistency counter INCC that calculates the difference between.

  When the inconsistency counter reset determination process is started, the payout control unit 4120 in the payout control board 4110 causes the payout control program to execute the inconsistency counter reset determination time as shown in FIG. 61 under the control of the payout control MPU 4120a. It is determined whether or not it has elapsed (step S790). This determination is performed based on the mismatch counter reset determination time updated in the timer update process of step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG. Specifically, the mismatch counter reset determination time is stored as time management information in the time management information storage area of the payout control built-in RAM described above. In step S790, the time management information is read from the time management information storage area to determine whether or not the mismatch counter reset determination time has elapsed.

  When the mismatch counter reset determination time has not elapsed in step S790, the payout control program ends this routine as it is. On the other hand, when the mismatch counter reset determination time has elapsed in step S790, the payout control program initializes the mismatch counter reset determination time (step S792). By this initialization, an initial value of 7000 s (about 2 hours) is set as the mismatch counter reset determination time.

  Subsequent to step S792, the payout control program sets a value 0 (initial value 0) to the inconsistency counter INCC stored in the award ball information storage area of the payout control built-in RAM described above (step S794). Exit. As described above, the inconsistency counter INCC is detected by the counting switch 751 and the number of game balls received and received by the recess of the payout rotating body to which the rotation of the rotation shaft of the payout motor 744 is transmitted. It is a counter for calculating the difference between the number of balls, and the number of game balls received and paid out by the recess of the payout rotating body is usually equal to the number of balls detected by the counting switch 751. As a result, the value is 0. The payout control program performs a retry operation in the payout installation process shown in FIG. 58 under the control of the payout control MPU 4120a. The inconsistency counter INCC determines whether or not the game balls that are not consistent due to the discrepancy between the number and the number of balls actually detected by the counting switch 751 are repeatedly paid. In the pachinko gaming machine 1 of the present invention, it has been experimentally obtained that the probability that one game ball that does not fit in due to a retry operation is paid out is about one millionth.

  Here, as described above, the pachinko gaming machine 1 includes the game board 4 and a frame body such as the main body frame 3 to which the game board 4 is mounted, and the game board 4 is exchanged (new stand replacement). Since the game specifications can be changed, the payout control board 4110 for controlling the prize ball device 740, the power supply board 851 for generating the driving power for the prize ball device 740 and the control power for the payout control board 4110 are common. Equipped on the frame side as a function. In the payout control unit 4120 of the payout control board 4110, the payout control program monitors the inconsistency counter INCC as described above under the control of the payout control MPU 4120a to determine whether or not the retry operation is repeatedly performed. 49. In the payout control unit power-off process in the payout control unit power-on process shown in FIG. 49, the inconsistency counter INCC immediately before shutting down is stored when the power is shut off. In the process of step S530 in the payout control unit power-on process shown in FIG. 48 (setting of the RAM work area when power is restored), the process is started again from the stored inconsistency counter INCC when the power is turned on.

  Then, when the game board 4 mounted on the pachinko gaming machine 1 is switched to a game board 4 'having a different game specification different from the game board 4 and turned on, the payout control is performed. The payout control MPU 4120a of the payout control unit 4120 on the substrate 4110 starts processing again from the mismatch counter INCC stored when the game board 4 is mounted on the pachinko gaming machine 1. That is, when the player plays the pachinko gaming machine 1 with the game board 4 ′ attached thereto, the mismatch counter INCC in the pachinko gaming machine 1 with the game board 4 before replacement is inherited as it is. For this reason, when a player plays the pachinko gaming machine 1 with the game board 4 ′ mounted, the probability of 1 / million million happens, and the number of game balls that do not match is generated and the inconsistency counter INCC When the inconsistency counter INCC becomes equal to or greater than the inconsistency threshold INCTH, the game board 4 is replaced with the game board 4 'and is determined as an abnormal operation of the retry operation by the payout control MPU 4120a in a short period. There is a risk. That is, in a short period of time after the game board 4 is replaced with the game board 4 ′, a malfunction of the counting switch 751, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, contact failure of various connectors, and the like. In spite of this, there is a possibility that it is suddenly determined as an abnormal operation of the retry operation.

  As described above, when the game board 4 is replaced with the game board 4 ′ and it is determined as an abnormal operation of the retry operation in a short period of time, the impression that the replaced game board 4 ′ is new and easily breaks down. May be given to players. The probability of a millionth of a game ball being paid out due to a retry operation is one millionth of the time when a pachinko machine 1 is installed in the hall and operated continuously for one week during the hall's business hours. Since the probability that one game ball that does not match due to the retry operation is paid out is the same, the probability of 1 / million from the inconsistency counter INCC in the processing of step S778 in the retry operation monitoring process shown in FIG. Thus, the value 1 is not subtracted. Then, the value 1 is incremented to the mismatch counter INCC in one week and the mismatch counter INCC becomes the value 1, and the value 1 is further incremented in the mismatch counter INCC and the mismatch counter INCC becomes the value 2 in 2 weeks. In week, value 1 is further incremented in inconsistency counter INCC, value in inconsistency counter INCC becomes value 3, in value 4 in inconsistency counter INCC is further incremented, value in inconsistency counter INCC becomes value 4, and in week 5 The value 1 is further incremented in the inconsistency counter INCC, and the inconsistency counter INCC becomes the value 5, which coincides with the inconsistency threshold INCTH described above. That is, when five weeks have elapsed, the inconsistency counter INCC matches the inconsistency threshold INCTH, and therefore the payout control program performs the control in step S776 in the retry operation monitoring process shown in FIG. 60 under the control of the payout control MPU 4120a. In the determination, it is determined that there is no detection signal from the counting switch 751, and a malfunction of the counting switch 751, disconnection of various harnesses extending from the counting switch 751 to the payout control board 4110, poor contact of various connectors, and the like occur. 60 is a segment display device mounted on the payout control board 4110 in order to notify the “retry error” in the processing of step S782 in the retry operation monitoring processing shown in FIG. Retryer to display number “5” on error LED indicator 860b Set the information so that the set (stored) in the status information storage area of the payout control chip RAM.

  Therefore, when the payout control MPU 4120a determines that the inconsistency counter reset determination time has elapsed in the determination of step S790 in the inconsistency counter reset determination processing, that is, every 7000 s (about 2 hours), the inconsistency counter reset is repeated. By forcibly setting the inconsistency counter INCC to 0, that is, forcibly resetting the inconsistency counter INCC in the process of step S794 in the determination process, the inconsistency counter INCC that is generated with the probability of 1 / million million is increased. Invalidated. As a result, there is an error in the retry operation even though the malfunction of the counting switch 751, the disconnection of various harnesses from the counting switch 751 to the payout control board 4110, the contact failure of various connectors, and the like have not occurred. Can be prevented from being set (stored) in the status information storage area of the payout control built-in RAM.

  Note that the game ball that is received by the recess of the payout rotating body to which the rotation of the rotary shaft of the payout motor 744 is transmitted by deliberately disabling the counting switch 751 is difficult to detect. In the case where the counting switch 751 is intentionally repeatedly deactivated for a short time even if an illegal act of forcibly generating a retry operation and illegally acquiring a game ball paid out by the retry operation is performed, In this way, when the value of the mismatch counter INCC is equal to or greater than the mismatch threshold INCTH, a plurality of LEDs on various decorative boards provided on the door frame 5 emit light, so that the store clerk or the like of the hall changes the state of the pachinko gaming machine 1 I will rush to confirm. If it does so, the player who performs a fraudulent act will have to be interrupted so that the act may not be discovered, and the illegal game ball by a fraudulent act cannot be continuously acquired. On the other hand, when the count switch 751 is intentionally repeatedly inactivated for a long time so that the value of the mismatch counter INCC does not become the mismatch threshold INCTH or more, the mismatch counter INCC is set every 7000 s (about 2 hours). Although reset, the number of game balls that can be acquired by a player who performs fraudulent action is that the inconsistency counter INCC is up to the inconsistency threshold INCTH and the count switch 751 is intentionally set as described above. Even if the player is repeatedly inactivated for a long time, the number of game balls that can be acquired by a player who performs an illegal act can be extremely reduced.

[16-11. Error release operation determination process]
Next, the error release operation determination process will be described. In this error release operation determination process, it is determined whether or not the operation switch 860a shown in FIG. 13 is being operated.

  When the error release operation determination process is started, the payout control unit 4120 of the payout control board 4110 causes the payout control program to release the error of the operation switch 860a as shown in FIG. 62 under the control of the payout control MPU 4120a. It is determined whether or not it has been operated (step S800). This determination is made based on the operation signal from the operation switch 860a in the port input process in step S550 in the payout control part power-on process (payout control part main process) shown in FIG. Specifically, the operation signal is stored as input information in the input information storage area of the payout control built-in RAM described above. In step S800, the payout control program reads the input information from the input information storage area, and determines that the error cancellation is not instructed when the logical value of the operation signal from the operation switch 860a is HI. When the operation switch 860a is determined not to be operated, when the logical value of the operation signal from the operation switch 860a is LOW, the operation switch 860a is operated by determining that the error cancellation is instructed. It is determined that

  When the operation switch 860a is not operated in step S800, the payout control program ends this routine as it is. On the other hand, when the operation switch 860a is operated in step S800, the payout control program performs error flag state confirmation processing. This is performed (step S802). In this error flag state determination process, the state of the error flag corresponding to various types of error information regarding the prize ball device 740 is confirmed. For example, the state of the retry error flag RTERR-FLG indicating whether or not the retry operation is abnormal is confirmed. As described above, the retry error flag RTERR-FLG has a value of 1 when the retry operation is operating abnormally and a value of 0 when the retry operation is not operating abnormally (retry operation is operating normally), respectively. Since the payout control program is set, the payout control program checks whether the value of the retry error flag RTERR-FLG is 0 or 1 under the control of the payout control MPU 4120a.

  Subsequent to step S802, the payout control program performs state information setting processing (step S804). In this status information setting process, if the status of the error flag indicates that an error has occurred based on the error flag confirmed in step S802, the status information corresponding to the error flag is described above. Is set (stored) in the status information storage area of the payout control built-in RAM. As a result, various information (state information) is read from the state information storage area in the command transmission process of step S566 in the payout control unit power-on process (payout control unit main process) shown in FIG. Based on the information, a status command is created and transmitted to the main control board 4100. For example, when the retry error flag RTERR-FLG indicating whether or not the retry operation described above is operating abnormally is 1, that is, when the retry operation is operating abnormally, it indicates that an error has occurred in the retry operation. When the retry error information to be transmitted is set (stored) in the status information storage area of the payout control built-in RAM, the command transmission process in step S566 in the payout control unit power-on process (payout control part main process) shown in FIG. A retry error status command is created and transmitted to the main control board 4100.

  The main control board 4100 that has received the retry error information transmits the main control program to the peripheral control board 4140 in the peripheral control board command transmission process in step S120 in the main control timer interrupt process shown in FIG. In the control board 4140, the sub-control program performs a retry operation error notification process for reporting that an error has occurred in the retry operation. In this retry operation error notification process, the error notification announcement of the retry operation “Check the prize ball unit.” And “Check the payout control board harness.” 2 times) By repeatedly flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the speaker 130 provided in the door frame 5 shown in FIG. It is supposed to be. The clerk of the hall, etc. who heard the error notification announcement of the retry operation, such as the malfunction of the counting switch 751 shown in FIG. Compared to the case where the error notification announcement of the retry operation does not flow from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, it can be confirmed very quickly. In the retry operation error notification process, a plurality of LEDs on various decorative boards provided on the door frame 5 are caused to emit light in a predetermined color (in this embodiment, red).

  Subsequent to step S804, the payout control program performs release setting processing (step S806). In this cancellation setting process, when the error flag state indicates that an error has occurred based on the error flag corresponding to the various types of error information confirmed in step S802, the error flag corresponds to the error flag. The CR unit 6 indicates that the error is forcibly stopped or the ball can be lent out by the error LED indicator 860b which is a segment indicator already mounted on the payout control board 4110. In this case, the logic of the PRDY signal described above is held at HI, that is, the state where the PRDY signal is raised, and the lending device connection terminal plate 869 such as a game ball is connected from the output terminal of the payout control MPU 4120a of the payout control unit 4120. Or output to the CR unit 6. For example, when the retry error flag RTERR-FLG indicating whether or not the retry operation described above is operating abnormally, that is, when the retry operation is operating abnormally, the error LED indicator 860b has already displayed. The retry error information stored in the status information storage area of the payout control built-in RAM is “normal” in order to forcibly stop the number “5” for informing that the “retry error” is present. This is forcibly overwritten on the information on which the graphic “-” for informing the effect is displayed. Further, in order to inform the CR unit 6 that the ball can be rented, the logic of the PRDY signal is held at HI, that is, the rising state is maintained, and the game ball is output from the output terminal of the predetermined output port of the payout control MPU 4120a. Output to the CR unit 6 through the equal lending device connection terminal plate 869.

  Subsequent to step S806, the payout control program performs error flag initialization processing (step S808), and this routine is terminated. In this error flag initialization process, if the error flag status indicates that an error has occurred based on the error flag corresponding to the various error information confirmed in step S802, the error flag is set. initialize. For example, when the retry error flag RTERR-FLG indicating whether or not the retry operation described above is operating abnormally is 1, that is, when the retry operation is operating abnormally, the retry error flag RTERR-FLG is set to 0. Set and initialize. At this time, the logic of the PRDY signal described above is held at HI, that is, the rising state is maintained, and the logic state of the PRDY signal is set in the PRDY signal output setting information and stored in the CR communication information storage area. Thus, the PRDY signal output setting information is read from the CR communication information storage area stored in the payout control built-in RAM in the CR communication process of step S554 in the payout control part main process of the payout control part power-on process of FIG. The read PRDY signal output setting information, that is, the PRDY signal whose logic is LOW, is output to the CR unit 6 from the output terminal of the predetermined output port of the payout control MPU 4120a through the gaming ball lending device connection terminal plate 869. .

  As described above, when the retry error flag RTERR-FLG is determined in step S780 in the retry operation monitoring process shown in FIG. 60 and the value of the mismatch counter INCC is greater than or equal to the mismatch threshold INCTH, the internal factor In response to the occurrence of the error, the retry error flag RTERR-FLG is set to a value of 1 in the process of step S786 of the same process. When this occurs, the retry error flag RTERR-FLG is set to 0 and initialized. The retry error flag RTERR-FLG is operated to clear the RAM when the operation switch 860a is operated to clear the RAM when the power is turned on, that is, the operation switch 860a clears the RAM to release the error. Similar to the case where the switch 860a is operated, the initialization is triggered by the occurrence of this external factor.

  As described above, in the pachinko gaming machine 1, the main process on the main control side is executed from the time of power-on to the operation switch 860a (operation switch) that should have been originally used to cancel the error that has occurred regarding the payout operation. Instead, for the predetermined time until the operation is performed, an operation for exhibiting a RAM clear function for starting initialization of the main control built-in RAM (game storage unit) and the payout control built-in RAM (payout storage unit) instead. It functions as a part. Further, the pachinko gaming machine 1 causes the operation switch 860a to function as an operation unit for canceling an error that has occurred with respect to the game ball payout operation after the predetermined time has elapsed. Here, even if the hall clerk is not familiar with the operation of the pachinko machine, as long as he remembers the position of the operation switch 860a on the back of the gaming machine, If a predetermined time has elapsed since the power was turned on, the function of canceling the error that occurred in relation to the game ball payout operation is exhibited, while the predetermined time from the time the power is turned on according to the timing of operating the operation switch 860a. If it is within the time, the function of initializing the storage unit can be exhibited. Therefore, even if an error occurs in such a gaming machine, the hall clerk can take appropriate action without hesitating the switch operation by improving the efficiency of the switch operation at the time of error handling, so the game is interrupted. The game can be resumed before the played player loses his willingness to play.

[16-12. Exchange of various signals with CR unit]
Next, the CR communication process of step S554 in the payout control unit main process of the payout control part power-on process of FIG. 49 will be described using a timing chart. In this CR communication process, various signals are exchanged between the payout control board 4110 and the CR unit 6 shown in FIG. First, signal processing at the time of payout operation by ball lending will be described, and subsequently input signal confirmation processing from the CR unit 6 will be described. Here, the number of game balls of 200 yen as the amount (in this embodiment, 50 balls, and the payout operation of 25 balls of 100 yen as the amount is performed twice) is used as the number of rented balls. The case of paying out to the upper plate 301 and the lower plate 302 shown in FIG. 7 will be described. The BRQ signal, the BRDY signal, and the CR connection signal from the CR unit 6 are read out from the input information storage area of the payout control built-in RAM and stored in the read input information. Confirms the logical state of the BRQ signal, the BRDY signal, and the CR connection signal from the input information every 2 ms that is the interrupt timer period.

[16-12-1. Signal processing during payout by ball lending]
The payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 reads out the PRDY signal output setting information from the CR communication information storage area of the payout control built-in RAM, and the read PRDY signal output setting information pays out a rental ball. If the logic state of the PRDY signal that indicates that the payout operation is possible is set, as shown in FIG. 63 (d), the payout operation for paying out the rented ball is possible. In order to transmit the signal, the logic of the PRDY signal is set to HI, that is, raised and held, and output from the output terminal of the predetermined output port of the payout control unit MPU4120a of the payout control unit 4120. It outputs to CR unit 6 via board 869 (timing H0). In this state, for example, when the player pushes the ball rental button 361 of the ball rental unit 360 shown in FIG. 2, the ball rental switch 365b is switched on (turned on). The operation signal is input as a TDS shown in FIG. 14 from the frequency display board 365 to the CR unit 6 via the game ball lending device connection terminal board 869. Since the CR unit 6 to which this TDS is input pays out the number of game balls of 200 yen as the amount of money to the upper plate 301 or the lower plate 302 as the number of lent balls, as shown in FIG. The ball request signal BRDY is output from the CR unit 6 to the payout control board 4110 (payout control MPU 4120a) via the gaming ball lending device connection terminal plate 869, and the signal is raised and held (timing H1). . This BRDY is input as a BRDY signal to an input terminal of a predetermined input port of the payout control MPU 4120a.

  As shown in FIG. 63 (b), the payout control MPU 4120a to which the BRDY signal is input has a payout control program that starts from the timing H1 to the lending request monitoring time HA (in this embodiment, 20 milliseconds (ms) to 58 ms. A predetermined number of balls (in this embodiment, 25 balls) in one payout operation from the CR unit 6 through the gaming device lending device connection terminal plate 869 until the time elapses. , Which corresponds to 100 yen as a monetary amount) is monitored whether or not a BRQ which is a single payout operation start request signal for paying out the money rises.

  Since the CR unit 6 pays out the number of game balls of 100 yen out of the number of game balls of 200 yen as the amount of money to the upper plate 301 and the lower plate 302 as the number of rented balls, FIG. ), The BRQ is output from the CR unit 6 to the CR unit 6 via the lending device connection terminal plate 869 such as a game ball until the rental request monitoring time HA elapses from the timing H1, and the signal is Start up and hold (timing H2). This BRQ is input as a BRQ signal to an input terminal of a predetermined input port of the payout control MPU 4120a.

  As shown in FIG. 63 (c), the payout control MPU 4120a, when the BRQ signal rises from the timing H1 until the lending request monitoring time HA elapses, from the timing H2 to the BRQ request acknowledgment ACK monitoring time HB (in this embodiment, Is set to 20 ms ± 1 ms), the payout control MPU 4120a holds the logic of the EXS signal HI, that is, keeps the raised state, in order to notify that one payout operation has started. Is output from the output terminal of the predetermined output port and output to the CR unit 6 as EXS via the lending device connection terminal plate 869 such as a game ball (timing H3).

  As shown in FIG. 63 (b), the CR unit 6 to which this EXS is input has a lending instruction monitoring time HC (in this embodiment, set to 20 ms to 58 ms) from the timing H3. The BRQ that has been started up and held from timing H2 is output from the CR unit 6 to the payout control board 4110 via the gaming ball lending device connection terminal plate 869, and the signal is lowered and held (timing H4).

  As shown in FIG. 63 (c), the payout control MPU 4120a performs one payout operation from the timing H4 until the payout monitoring time HD (in this embodiment, the ball payout time is set) elapses. Then, only the predetermined number of rented balls, that is, the number of game balls for 100 yen is paid out to the upper plate 301 and the lower plate 302 as the number of lent balls. When the payout monitoring time HD elapses, the EXS signal that has been raised and held from the timing H3 is output from the output terminal of a predetermined output port of the payout control MPU 4120a while keeping its logic at LOW, that is, in the lowered state. , EXS is output to the CR unit 6 via the gaming ball rental device connecting terminal plate 869 (timing H5).

  Since the CR unit 6 pays out the remaining number of game balls of 100 yen out of the number of game balls of 200 yen as the amount of money to the upper plate 301 and the lower plate 302 as the rented number, FIG. ), The BRQ is transferred from the CR unit 6 to the lending device connection terminal board such as a game ball until the next request confirmation timing HE (in this embodiment, the maximum is set to 268 ms) from the timing H5. 869 is output to the payout control board 4110 (payout control MPU 4120a), and the signal is raised and held (timing H6).

  Similarly, when the payout control MPU 4120a pays out the remaining 100 yen of game balls to the upper plate 301 or the lower plate 302 using the above-described method, as shown in FIG. 63 (c). The EXS signal that has been raised and held is set to the logic level LOW, that is, held in the lowered state, and is output from the output terminal of the predetermined output port of the payout control MPU 4120a. It outputs to CR unit 6 via board 869 (timing H7).

  As shown in FIG. 63 (a), the CR unit 6 starts from the timing H1 until the CR unit lending completion monitoring time HF (in this embodiment, the maximum is set to 268 ms) elapses from the timing H7. The raised BRDY is output from the CR unit 6 to the payout control board 4110 (payout control MPU 4120a) via the gaming ball lending device connection terminal plate 869, and the signal is lowered and held (timing H8).

  The above-described lending request monitoring time HA, BRQ request acknowledgment ACK monitoring time HB, lending instruction monitoring time HC, payout monitoring time HD, next request confirmation timing HE, CR unit lending completion monitoring time HF are the payout control shown in FIG. The time is counted by the timer update process in step S552 in the power-on process (payout control part main process).

  The payout control MPU 4120a does not communicate with the CR unit 6 when a ball breakage, ball rounding, counting switch error, retry error, full tank, etc. occurs (the logic of BRDY from the CR unit 6). Is held LOW, that is, when it is held down, as shown in FIG. 63 (d), the PRDY signal raised and held from the timing H1 is set to the logic LOW, that is, the state is lowered. It is held and output from the output terminal of a predetermined output port of the payout control MPU 4120a, and is output as PRDY to the CR unit 6 via the game ball lending device connection terminal plate 869 (timing H9). On the other hand, when communicating with the CR unit 6 (when the BRDY logic from the CR unit 6 is HI, that is, rising and being held), although not shown, the logic state of the EXS signal is maintained and paid out. It outputs from the output terminal of the predetermined | prescribed output port of control MPU4120a, and outputs to CR unit 6 via the lending apparatus connection terminal board 869, such as game balls, as EXS. “Keep the logic state of the EXS signal” means that when the logic of the EXS signal is LOW (the EXS signal is held down), the logic of the EXS signal is HI. The logical HI is maintained when the EXS signal is held up.

  In this way, the CR unit 6 exchanges various signals with the payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110, and the payout control MPU 4120a sets the number of game balls for 200 yen as the amount of money as 100. By performing the payout operation of 25 balls for the yen twice, the game balls having the number of lent out balls of 50 are paid out to the upper plate 301 and the lower plate 302. A hall clerk or the like operates a setting unit (not shown) provided on the front side of the CR unit 6, and for example, the number of game balls for 100 yen as the amount of money is used for the upper plate 301 or When set to pay out to the lower plate 302, the payout control MPU 4120a performs a payout operation of 25 balls for 100 yen as a monetary amount, and the number of game balls for 500 yen as a monetary number When set to pay out to the upper plate 301 and the lower plate 302, the payout control MPU 4120a performs the payout operation of 25 balls of 100 yen as the amount of money five times, and sets the number of game balls of 1000 yen as the amount of money. When the number of rented balls is set to be paid out to the upper plate 301 or the lower plate 302, the payout control MPU 4120a performs the payout operation of 25 balls for 100 yen as the amount of money 10 times.

[16-12-2. Checking input signal from CR unit]
The payout control MPU 4120a of the payout control unit 4120 in the payout control board 4110 is configured such that the CR unit 6 performs BRQ via the CR unit 6 via the lending device connection terminal board 869 such as a game ball even when the lending request monitoring time HA has elapsed. When the signal is not started up or when the above-described lending instruction monitoring time HC elapses, the CR unit 6 connects BRDY to the lending device such as a game ball from the CR unit 6. The CR unit 6 outputs the BRQ from the CR unit 6 to the payout control board 4110 via the terminal board 869, even when the signal has not fallen or when the next request confirmation timing HE described above has elapsed. A ball or other lending device connection terminal board 869 is used to output to the payout control board 4110 and the signal is not started up, or as described above. Even after the R unit lending completion monitoring time HF has elapsed, the CR unit 6 outputs BRDY to the payout control board 4110 from the CR unit 6 via the lending device connection terminal board 869 such as a game ball, and the signal is lowered. If not, the above-described PRDY and EXS are used to check whether BRQ and BRDY are normal. Specifically, as shown in FIGS. 63 (e) and 63 (f), the payout control MPU 4120a determines that BRQ and BRDY are not normal (timing J0), and starts a predetermined period JA (in this embodiment) from this timing J0. , 200 ms ± 1 ms), the logic of the PRDY signal is set to LOW, that is, the state of being lowered is held and output from the output terminal of the predetermined output port of the payout control MPU 4120a of the payout control unit 4120 Then, PRDY is output to the CR unit 6 through the gaming ball lending device connection terminal plate 869, and the logic of the EXS signal is set to LOW, that is, the state of being lowered is held and the predetermined output port of the payout control MPU 4120a Is output to the CR unit 6 through the rental device connection terminal plate 869 such as a game ball. To force (timing J1).

  Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal held down and held from the timing J1 after the elapse of a predetermined period JB (in this embodiment, 200 ms ± 1 ms) from the timing J1 as the logic HI. In other words, it is held in the raised state, output from the output terminal of a predetermined output port of the payout control MPU 4120a, and output as PRDY to the CR unit 6 via the gaming ball lending device connection terminal plate 869 (timing J2 ).

  Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal raised and held from the timing J2 after the elapse of a predetermined period JC from the timing J2 (in this embodiment, 100 ms ± 1 ms) as its logic LOW. In other words, it is held in a lowered state, outputted from the output terminal of a predetermined output port of the payout control MPU 4120a, and outputted as PRDY to the CR unit 6 via the game ball lending device connection terminal plate 869 (timing J3). ).

  Subsequently, after the elapse of a predetermined period JD (in this embodiment, 100 ms ± 1 ms) from the timing J3, the payout control MPU 4120a sets the logic of the PRDY signal held down from the timing J3 as HI. In other words, it is held in the raised state, output from the output terminal of the predetermined output port of the payout control MPU 4120a, and output as PRDY to the CR unit 6 via the game ball lending device connection terminal plate 869 (timing J4). ).

  Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal raised and held from the timing J4 after the elapse of a predetermined period JE (in this embodiment, 100 ms ± 1 ms) from the timing J4 as its logic LOW. In other words, it is held in a lowered state, outputted from the output terminal of a predetermined output port of the payout control MPU 4120a, and outputted as PRDY to the CR unit 6 via the gaming ball lending device connection terminal plate 869 (timing J5). ).

  Subsequently, the payout control MPU 4120a sets the logic of the PRDY signal held down and held from the timing J5 after the elapse of a predetermined period JF from the timing J5 (in this embodiment, 10000 ms ± 1 ms) as the logic HI. In other words, it is held in the raised state, output from the output terminal of a predetermined output port of the payout control MPU 4120a, and output as PRDY to the CR unit 6 via the gaming ball lending device connection terminal plate 869 (timing J6). ).

  The above-described predetermined period JA to predetermined period JF are timed by the timer update process in step S552 in the payout control unit power-on process (payout control unit main process) shown in FIG.

[17. Various control processing of peripheral control board]
Next, various processes of the peripheral control board 4140 that receive various commands from the main control board 4100 (main control MPU 4100a) shown in FIG. 12 will be described with reference to FIGS. FIG. 64 is a flowchart showing an example of the peripheral control unit power-on process, FIG. 65 is a flowchart showing an example of the peripheral control unit V blank interrupt process, and FIG. 66 shows an example of the peripheral control unit 1 ms timer interrupt process. 67 is a flowchart showing an example of the peripheral control unit command reception interrupt process, FIG. 68 is a flowchart showing an example of the peripheral control unit power failure warning signal interrupt process, and FIG. 69 shows the transition to the power saving mode during power recovery. FIG. 70 is a flowchart showing an example of the power consumption monitoring process. FIG. 71 shows the relationship between the value set as the master volume value for power suppression and the power consumption suppression stage. The figure (a) to show, the relationship between the brightness | luminance set as a brightness | luminance for electric power suppression, and an electric power consumption suppression stage is shown FIG. 72 is a flowchart showing an example of the LOCKN signal history creation process, FIG. 73 is a flowchart showing an example of the connection failure determination process, and FIG. 74 is a flowchart showing an example of the connection recovery process. FIG. 75 is a timing chart for explaining the timing for outputting a connection confirmation signal to the INIT terminal of the upper plate side liquid crystal transmitter IC.

  As shown in FIG. 15, the peripheral control board 4140 includes a peripheral control unit 4150 and a liquid crystal and sound control unit 4160. Here, various control processes of the peripheral control unit 4150 will be described. First, the peripheral control unit power-on process will be described, followed by peripheral control unit V blank interrupt processing, peripheral control unit 1 ms timer interrupt processing, peripheral control unit command reception interrupt processing, peripheral control unit power failure warning signal interrupt processing, power recovery The power saving mode transition determination processing, power consumption monitoring processing, LOCKN signal history creation processing, connection failure determination processing, and connection recovery processing will be described. The power saving power saving mode transition determination process is the process of step S1004 in the peripheral control unit power-on process described later, and the power consumption monitoring process is in the peripheral control unit steady process of the peripheral control unit power-on process described later. The LOCKN signal history creation process, which is the process of step S1027, is executed as one process of the drawing state information acquisition process of step S1110 in the peripheral control unit 1 ms timer interrupt process described later. The connection failure determination process and the connection recovery process are described later. This is executed as one of the warning processes in step S1024 in the peripheral control part steady process of the peripheral control part power-on process, and the connection recovery process is executed following the connection failure determination process. In the present embodiment, the peripheral control unit power failure warning signal interrupt processing is set as the highest priority as the interrupt processing priority, followed by power consumption suppression signal interrupt processing, peripheral control unit 1 ms timer interrupt processing, peripheral control unit command reception. Interrupt processing and peripheral control section V blank interrupt processing are set in this order.

[17-1. Various control processes of peripheral control unit]
[17-1-1. Peripheral control unit power-on processing]
First, the peripheral control unit power-on process will be described with reference to FIG. When the pachinko gaming machine 1 is powered on, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 performs a peripheral control unit power-on process as shown in FIG. When the peripheral control unit power-on process is started, the effect control program performs an initial setting process under the control of the peripheral control MPU 4150a (step S1000). In this initial setting process, the production control program performs a process of initializing the peripheral control MPU 4150a itself, a hot start / cold start determination process, a process of setting a wait timer after reset, and the like. The peripheral control MPU 4150a first performs a process of initializing itself. The time required for the process of initializing the peripheral control MPU 4150a is on the order of microseconds (μs), and the peripheral control MPU 4150a is initialized in a very short time. be able to. As a result, the peripheral control MPU 4150a is output from the main control board 4100 in, for example, a peripheral control unit command reception interrupt process to be described later, as shown in FIGS. 41 and 42 when the interrupt permission is set. Various commands such as commands relating to the control of game effects and commands relating to the state of the pachinko gaming machine 1 can be received.

  In the hot start / cold start determination process, for the peripheral control RAM 4150c shown in FIG. 16, in the backup first area 4150cb, production backup information (1fr) that is backed up in Bank1 (1fr) and Bank2 (1fr). ) And the production backup information (1 ms), which is the contents backed up in Bank 1 (1 ms) and Bank 2 (1 ms), are compared, and Bank 3 (1 fr) and Bank 4 (1 fr) in the backup second area 4150 cc are compared. The production backup information (1fr), which is the content that is backed up at the same time, is compared, and the production backup information (the content that is backed up in Bank3 (1 ms) and Bank4 (1 ms)) ( ms), and when the compared contents match, the contents stored in Bank1 (1fr) with respect to Bank0 (1fr), which is a normally used storage area of the peripheral control RAM 4150c shown in FIG. The production backup information (1fr) and the production backup information (1ms) stored in Bank1 (1ms) with respect to Bank0 (1ms) are copied back to make a hot start, When the contents do not match (that is, when they do not match), the value 0 is forcibly written to Bank0 (1fr) and Bank0 (1 ms), which are normally used storage areas of the peripheral control RAM 4150c. And cold start.

  In the hot start / cold start determination processing, the effect backup information which is the contents backed up in the Bank 1 (SRAM) and the Bank 2 (SRAM) in the backup first area 4150 db also for the peripheral control SRAM 4150 d shown in FIG. (SRAM) is compared, and production backup information (SRAM), which is the contents backed up in Bank 3 (SRAM) and Bank 4 (SRAM), in the backup second area 4150 dc is compared. When the compared contents match, the production backup information (SRAM) which is the contents stored in Bank 0 (SRAM) with respect to Bank 0 (SRAM) which is the storage area normally used in the peripheral control SRAM 4150d shown in FIG. ) Is copied back to make a hot start, while when the compared contents do not match (that is, when they do not match), the value is relative to Bank0 (SRAM), which is a storage area normally used by the peripheral control SRAM 4150d. A 0 is forcibly written to make a cold start. Following such a hot start or cold start, the value 0 is forcibly written to the backup unmanaged work area 4150cf of the peripheral control RAM 4150c shown in FIG. Then, the peripheral control MPU 4150a outputs a clear signal to the peripheral control MPU 4150a by outputting a clear signal to the peripheral control built-in WDT 4150af shown in FIG. 16 and the peripheral control external WDT 4150e shown in FIG. It is made so that it won't be applied.

  Subsequent to step S1000, the effect control program performs current time information acquisition processing (step S1002). In this current time information acquisition process, calendar information specifying the date and time and time information specifying the hour, minute, and second are acquired from the RTC built-in RAM 4165aa of the RTC 41654a of the RTC control unit 4165 shown in FIG. In the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. 4, the current calendar information is set in the calendar information storage unit and the current time information is set in the time information storage unit. In the current time information acquisition process, the brightness setting process of the liquid crystal display device is also performed. In the brightness setting process of the liquid crystal display device, the peripheral control MPU 4150a acquires the brightness setting information from the RTC built-in RAM 4165aa of the RTC control unit 4165, and the game board so that the brightness of the LED included in the acquired brightness setting information is obtained. A process of lighting the backlight of the side liquid crystal display device 1900 is performed. As described above, the brightness setting information includes brightness adjustment information for adjusting the range of the brightness of the LED, which is the backlight of the game board side liquid crystal display device 1900, from 100% to 70% in increments of 5%, The brightness of the LED which is the backlight of the game board side liquid crystal display device 1900 that has been set is included.

  In the brightness setting process of the liquid crystal display device, specifically, the brightness of the LED included in the brightness setting information stored in the RTC built-in RAM 4165aa of the RTC control unit 4165 is 75%, and the backlight of the game board side liquid crystal display device 1900 is displayed. Is turned on by adjusting the backlight brightness of the game board side liquid crystal display device 1900 based on the brightness adjustment information included in the brightness setting information, and the brightness stored in the RTC built-in RAM 4165aa of the RTC control unit 4165. When the backlight of the game board side liquid crystal display device 1900 is turned on when the luminance of the LED included in the setting information is 80%, the backlight of the game board side liquid crystal display device 1900 is turned on based on the luminance adjustment information included in the luminance setting information. Lights with the brightness adjusted. In this liquid crystal display device luminance setting process, the same correction as the above-described luminance correction program for correcting the luminance of the game board side liquid crystal display device 1900 according to the usage time of the game board side liquid crystal display device 1900 is performed. It is not done at all. This is because the brightness setting process of the liquid crystal display device incorporates a correction program similar to the brightness correction program, so that the brightness of the LED is corrected toward 100% each time the brightness setting process of the liquid crystal display device is executed. This is to prevent it from being done.

  In the present embodiment, the peripheral control MPU 4150a acquires calendar information and time information from the RTC built-in RAM 4165aa of the RTC 4165a only once when the power is turned on. In addition, the peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e after performing this current time information acquisition processing so that the peripheral control MPU 4150a is not reset.

  Subsequent to step S1002, a power saving power saving mode transition determination process is performed (step S1004). This power saving power saving mode transition determination process will be described in detail later. Based on the power consumption status history information stored in the power consumption status history RAM 4150f shown in FIG. Immediately before disconnection), the power situation consumed by the pachinko machine 1 is ascertained at the time of power recovery, and it is determined whether or not to enter the power saving mode at the time of power recovery that suppresses the power consumed by the pachinko machine 1. When shifting to the power saving mode, the door frame 5 is provided with a setting for reducing the volume of the production sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. Settings for reducing the brightness of various LEDs mounted on various decorative boards provided in the game board 4 and the LEDs for light emitting decoration are made.

  Subsequent to step S1004, the effect control program sets a value 0 to the V blank signal detection flag VB-FLG (step S1006). This V blank signal detection flag VB-FLG is a flag for determining whether or not to execute a peripheral control unit steady process to be described later. Is set to 0 when not executing. The V blank signal detection flag VB-FLG, which will be described later, is executed when a V blank signal indicating that the screen data from the peripheral control MPU 4150a can be received is input from the sound source built-in VDP 4160a. The value 1 is set in the part V blank signal interrupt processing. In step S1006, the V blank signal detection flag VB-FLG is initialized once by setting the value 0 to the V blank signal detection flag VB-FLG. The peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e after setting the value 0 to the V blank signal detection flag VB-FLG so that the peripheral control MPU 4150a is not reset. Yes.

  Subsequent to step S1006, the effect control program determines whether or not the V blank signal detection flag VB-FLG is 1 (step S1008). When the V blank signal detection flag VB-FLG is not 1 (value 0), the process returns to step S1008 and it is repeatedly determined whether or not the V blank signal detection flag VB-FLG is 1. By repeating such a determination, the process waits until the peripheral control unit steady process is executed. The peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e after determining whether or not the V blank signal detection flag VB-FLG is 1, and resets to the peripheral control MPU 4150a. It is made so that it won't be applied.

  When the V blank signal detection flag VB-FLG has a value of 1 in step S1008, that is, when the peripheral control unit steady process is executed, a value 1 is first set to the steady process flag SP-FLG (step S1009). The steady processing flag SP-FLG is set to a value of 1 when the peripheral control unit steady processing is being executed, and to a value of 0 when the peripheral control unit steady processing is completed.

  Subsequent to step S1009, the effect control program performs 1 ms interrupt timer activation processing (step S1010). In this 1 ms interrupt timer starting process, a 1 ms interrupt timer for executing a later-described peripheral control unit 1 ms timer interrupt process is started, and the number of times this 1 ms interrupt timer is started and the peripheral control unit 1 ms timer interrupt process is executed. The value 1 is set in the 1 ms timer interrupt execution count STN for counting the 1 ms timer interrupt execution count STN. This 1 ms timer interrupt execution count STN is updated by the peripheral control unit 1 ms timer interrupt processing.

  Subsequent to step S1010, the effect control program performs lamp data output processing (step S1012). In this lamp data output process, the effect control program performs DMA serial continuous transmission to the lamp driving board 4170 shown in FIG. Here, serial transmission of the serial I / O port for the lamp driving board is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. When the serial I / O port continuous transmission for the lamp driving board is started, the lamp driving board side transmission data storage area 4150caa of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. The game board side light emission data SL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs of various decorative boards provided in the game board 4 is created by a lamp data creation process described later. Is set.

  The peripheral control CPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 16 designates the transmission of the lamp drive board serial I / O port as the request factor of the peripheral control DMA controller 4150ac, and stores the lamp drive board side transmission data storage area 4150caa. The first 1 byte of the game board side light emission data SL-DAT stored at the top address is transferred to the serial I / O port for the lamp driving board via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer and write to the send buffer register. As a result, the serial I / O port for the lamp driving board transfers the written data in the transmission buffer register to the transmission shift register, and synchronizes with the light emission clock signal SL-CLK on the game board side to 1 byte of the transmission shift register. The data starts to be transmitted bit by bit.

  The peripheral control DMA controller 4150ac is triggered by a transmission interrupt request for the lamp drive board serial I / O port (in this embodiment, in the transmission buffer register of the lamp drive board serial I / O port). The written 1-byte data is transferred to the transmission shift register, and the transmission buffer register is empty because the 1-byte data disappears.), The peripheral control CPU core 4150aa is using the bus. If not, the remaining game board side light emission data SL-DAT stored in the lamp drive board side transmission data storage area 4150caa is byte by byte via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transmit serial I / O port for lamp drive board By transferring and writing to the buffer register, the lamp drive board serial I / O port transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the light emission clock signal SL-CLK on the game board side. Transmission of 1-byte data of the transmission shift register is started bit by bit, and continuous transmission is performed through the serial I / O port for the lamp driving board.

  In the lamp data output process, the effect control program performs a DMA serial continuous transmission process to the frame decoration drive amplifier board 194 shown in FIG. Also here, the frame I / O port LED serial I / O port continuous transmission is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a. When this frame decoration drive amplifier board LED serial I / O port continuous transmission starts, the frame decoration drive amplifier board side LED transmission data storage area of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. In 4150cab, door side light emission data STL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to a plurality of LEDs of various decorative boards provided on the door frame 5 is created by a lamp data creation process described later. Is set.

  The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates the transmission of the frame decoration drive amplifier board LED serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and transmits the frame decoration drive amplifier board side LED transmission data storage area. The first one byte of the door-side light emission data STL-DAT stored at the head address of 4150cab is serialized for the frame decoration drive amplifier board LED via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer and write to the I / O port transmit buffer register. As a result, the frame decoration drive amplifier board LED serial I / O port transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the door side light emission clock signal STL-CLK. Transmission of 1-byte data is started bit by bit.

  The peripheral control DMA controller 4150ac is triggered every time a transmission interrupt request for the serial I / O port for frame decoration drive amplifier board LED is generated (in this embodiment, the serial I / O for frame decoration drive amplifier board LED). 1 byte data written in the transmission buffer register of the port is transferred to the transmission shift register, and the transmission buffer register is empty because the 1 byte data disappears.), Peripheral control CPU core 4150aa Is not using the bus, the remaining door side light emission data STL-DAT stored in the frame decoration drive amplifier board side LED transmission data storage area 4150cab is stored byte by byte in the external bus 4150h and the peripheral control bus controller 4150ad. And frame decoration via peripheral bus 4150ai By transferring and writing to the transmission buffer register of the serial amplifier I / O port for the dynamic amplifier board LED, the serial I / O port for frame decoration drive amplifier board LED writes the data of the written transmission buffer register to the transmission shift register Transfer and start transmitting 1-byte data of the transmission shift register bit by bit in synchronization with the door side light emission clock signal STL-CLK, and perform continuous transmission by the serial I / O port for frame decoration drive amplifier board LED Yes.

  Subsequent to step S1012, the effect control program performs an operation unit monitoring process (step S1014). In this operation unit monitoring process, in the operation unit information acquisition process in the peripheral control unit 1 ms timer interruption process described later, the dial operation unit 401 is based on detection signals from various detection switches provided in the operation unit 400 shown in FIG. Rotation (rotation direction) and various information obtained by operating the pressing operation unit 405 (for example, rotation of the dial operation unit 401 created based on detection signals from various detection switches provided in the operation unit 400 (rotation direction) ) History information, operation history information of the pressing operation unit 405, etc.) Based on the operation unit information acquisition storage area 4150cai of the peripheral control RAM 4150c shown in FIG. Monitor the presence or absence of operation of the unit 405, Appropriately determined whether to reflect the state of operation of the pressure operation unit 405 to the game effects.

  Subsequent to step S1014, the effect control program performs display data output processing (step S1016). In this display data output processing, the drawing data for one screen (one frame) generated on the built-in VRAM of the sound source built-in VDP 4160a in the display data creation processing described later is transmitted from the channels CH1 and 2 shown in FIG. The data is output to the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. Specifically, the peripheral control MPU 4150a, for example, executes the peripheral control unit steady process this time, the display data creation process to be described later, the game board side liquid crystal display device 1900 and the movable liquid crystal display device with the built-in VRAM frame buffer MVD. In the case where drawing data for one screen (one frame) to be drawn on the screens 1925a to 1925d is generated and held, the display data creation processing described later when the previous peripheral control unit steady processing is executed has already been performed. The drawing data for one screen (one frame) to be drawn on the screens of the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d generated and held by the frame buffer MVD ′ of the built-in VRAM is read and the frame is read. Of the drawing data generated and held in the buffer MVD ′, the game board side liquid crystal display device 190 Control is performed for the VDP 4160a with built-in sound source, and control is performed on the movable liquid crystal display devices 1925a to 1925d. Control for outputting (transmitting) drawing data from the odd channel of channel CH1 to the movable liquid crystal display devices 1925a to 1925d via the liquid crystal output substrate 3420 is performed on the VDP 4160a with built-in sound source (that is, output from the even channel of channel CH1). (Transmission) and output (transmission) from the odd channel of channel CH1 are performed simultaneously). In addition, the peripheral control MPU 4150a, for example, performs one screen for drawing on the screen of the upper plate side liquid crystal display device 470 in one frame buffer of the built-in VRAM in the display data creation processing described later when executing the current peripheral control unit steady process. When (1 frame) of drawing data is generated and held, it is already generated and held in the other frame buffer of the built-in VRAM in the display data creation process described later when the previous peripheral control unit steady process was executed. The drawing data for one screen (one frame) to be drawn on the screen of the upper plate side liquid crystal display device 470 is read, and the drawing data for the upper plate side liquid crystal display device 470 is sent from the channel CH2 to the frame peripheral relay terminal board 868. The peripheral door relay terminal plate 882 and the touch panel drive board 450 accommodated in the dish unit 300 of the door frame 5 To performs control to output to the upper tray side liquid crystal display device 470 (transmission) with respect to the sound source built VDP4160a. Thereby, various screens are drawn on the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470. In the display data output process, when drawing exceeding the drawing capability of the sound source built-in VDP 4160a is performed, the generated drawing data for one screen (one frame) is used as the game board side liquid crystal display device 1900 and the movable liquid crystal display device. Output to 1925a to 1925d and the upper plate side liquid crystal display device 470 is canceled. This can prevent the processing time from being delayed, but although a so-called frame drop occurs, the various decorative boards provided in the game board 4 shown in FIG. 8 by the ramp data output processing in step S1012. A speaker housed in a speaker box 820 provided in the main body frame 3 shown in FIG. 5 by an effect by a plurality of LEDs and a plurality of LEDs of various decorative boards provided in the door frame 5, and a sound data output process described later, and It is a mechanism that can give priority to the synchronization with effects produced by music, sound effects, etc. according to various effects from the speaker 130 provided on the door frame 5 shown in FIG.

  Subsequent to step S1016, the effect control program performs sound data output processing (step S1018). In this sound data output process, the effect control program outputs to the audio data transmission IC 4160c as audio data obtained by serializing sound data such as music and sound effects set in the sound source built-in VDP 4160a in the sound data creation process described later, In addition to music and sound effects, the sound data of notification sound and notification sound is output to the audio data transmission IC 4160c as serialized audio data. When the audio data transmission IC 4160c receives serialized audio data from the sound source built-in VDP 4160a, the audio data transmission IC 4160c is directed toward the frame decoration drive amplifier board 194 as differential serial data using the right audio data as a plus signal and a minus signal. At the same time, the left audio data is transmitted toward the frame decoration drive amplifier board 194 as differential serial data having a plus signal and a minus signal. As a result, in addition to the stereo reproduction of music, sound effects and the like adapted to various effects from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, the notification sound and the notification sound Is also played in stereo.

  Subsequent to step S1018, the effect control program performs scheduler update processing (step S1020). In this scheduler update process, the effect control program updates various schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. For example, in the scheduler update process, among the screen data arranged in time series constituting the screen generation schedule data set in the schedule data storage area 4150cae, what number screen data from the top screen data is stored in the sound source built-in VDP 4160a. The pointer is updated to indicate whether to output.

  Also, in the scheduler update process, among the light emission data arranged in time series constituting the light emission mode generation schedule data set in the schedule data storage area 4150cae, the number of the light emission data from the first light emission data is emitted from the various LEDs. The pointer is updated to indicate whether the mode is set.

  In the scheduler update processing, sound data such as music and sound effects, sound data of notification sound and notification sound, which are arranged in time series constituting the sound generation schedule data set in the schedule data storage area 4150cae, are instructed. Of the sound command data, the pointer is updated in order to indicate what number of sound command data from the head sound command data is to be output to the built-in sound source VDP 4160a.

  In the scheduler update process, the drive data of the electric drive sources such as motors and solenoids arranged in time series constituting the electric drive source schedule data set in the schedule data storage area 4150cae is used from the head drive data. The pointer is updated to indicate what number of drive data is to be output. The drive data of the electric drive sources such as motors and solenoids arranged in time series constituting the electric drive source schedule data is a peripheral control unit 1 ms timer interrupt which is repeatedly executed every time a 1 ms timer interrupt described later occurs. It is updated by the motor and solenoid drive process in the process. In the motor and solenoid drive processing that is repeatedly executed each time this 1 ms timer interrupt occurs, an electric drive source such as a motor or solenoid is driven according to the drive data indicated by the pointer, and the next drive specified in time series is performed. The pointer is updated to the data, and the pointer is updated every time its own processing is executed. In other words, the drive data indicated by the pointer updated in the motor and solenoid drive processing is forcibly updated in the scheduler update processing. Even when other drive data is instructed from the drive data that should be performed, it is forcibly updated to instruct the drive data that should be instructed originally in the scheduler update processing.

  Also, in the scheduler update process, the number of game balls to be paid out as prize balls arranged in time series constituting the schedule data for the main prize ball information output signal set in the schedule data storage area 4150cae is 10 balls. The number of output waveform data from the first output waveform data to be output among the output waveform data for generating a main prize ball information output signal that informs the hall computer as main prize ball information that the current value has been reached. The pointer is updated to indicate. The output waveform data arranged in time series constituting the schedule data for the main prize ball information output signal is the number of main prize balls in the peripheral control unit 1 ms timer interrupt process that is repeatedly executed every time a 1 ms timer interrupt occurs, which will be described later. Updated by information output process. In the main prize ball number information output process that is repeatedly executed every time this 1 ms timer interrupt occurs, the main prize ball information output signal is output to the external terminal board 784 in accordance with the output waveform data indicated by the pointer, and is specified in time series. The pointer is updated to the next output waveform data, and the pointer is updated every time its own processing is executed. That is, since the output waveform data indicated by the pointer updated in the main prize ball number information output process is forcibly updated in the scheduler update process, the pointer is temporarily changed in the main prize ball number information output process. Even if other output waveform data is instructed from the output waveform data that should be instructed for some reason, it is forcibly updated to instruct the output waveform data that should be instructed in the scheduler update processing. It has become.

  Subsequent to step S1020, the effect control program performs a received command analysis process (step S1022). In this received command analysis process, the effect control program receives information transmitted from the touch panel drive board 450 via the peripheral door relay terminal board 882 and the frame peripheral relay terminal board 868 shown in FIG. Touch position data indicating a position touched by a finger) is received in touch panel processing to be described later, and the received information is analyzed, and various commands transmitted from the main control board 4100 are subjected to peripheral control to be described later. It is received in the part command reception interrupt process (command receiving means) and the received various commands are analyzed (command analyzing means). Various commands from the main control board 4100 are received by the peripheral control unit command reception interrupt process (command receiving means) and stored in the received command storage area 4150cac of the peripheral control RAM 4150c. This received command analysis process Then, the effect control program analyzes various commands stored in the received command storage area 4150cac (command analysis means). The effect control program stores screen generation schedule data, light emission mode generation schedule data, sound generation schedule data, electrical drive source schedule data, and the like, based on the analyzed various commands, in the peripheral control ROM 4150b of the peripheral control unit 4150. Alternatively, it is extracted from various control data copy areas 4150ce of the peripheral control RAM 4150c and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c. Further, the effect control program is based on the information transmitted from the touch panel drive board 450 via the peripheral door relay terminal plate 882 and the frame peripheral relay terminal plate 868, screen generation schedule data, light emission mode generation schedule data, sound The generation schedule data, electrical drive source schedule data, and the like are extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c. .

  In addition, in the effect control program, the command from the main control board 4100 received in the peripheral control unit command interrupt process is, for example, a start opening prize command for instructing start of a starting opening prize effect, the number of ordinary symbols held A normal symbol storage command for identifying (0 to 4), a symbol synchronization effect start command for instructing the start of a symbol synchronization effect, a symbol storage command that is output when the number of start suspension changes, A winning prize 1 count display command (big winning prize count command) output each time a game ball is accepted, or a frame status 1 command (second error occurrence command) indicating the content of full as shown in FIG. It is analyzed whether or not it is a full error occurrence command (command analysis means), and it is recognized which gaming state is currently in effect.

  In addition, after the predetermined time has elapsed since the power was turned on, the effect control program is configured such that a command received by the peripheral control unit command reception interrupt process is a body frame opening command, a body frame closing command, a door opening command, or a door frame closing. Analyzes whether it is a command or not. Various commands from the main control board 4100 are received by the peripheral control unit command reception interrupt process and stored in the reception command storage area 4150cac of the peripheral control RAM 4150c shown in FIG. The effect control program analyzes various commands stored in the received command storage area 4150cac. The various commands shown in FIG. 41 are classified into various commands classified as related to the special figure 1 tuning effect, various commands classified as related to the special figure 2 synchronous effect, various commands classified as related to the jackpot, and power-on. , Various commands categorized as related to ordinary drawing effect, various commands categorized as related to ordinary electric character effect, various commands classified as notification display shown in FIG. 42, door frame opening command described above , Door frame closing command, body frame opening command and body frame closing command, error canceling navigation command (corresponding to the second error canceling command), frame state 1 command (corresponding to the second error occurrence command), and frame state 2 There are various commands classified into status displays such as commands, various commands classified into tests, and various commands classified into others.

  Here, in the effect control program, the command analyzed in the received command analysis process (step S1022) is the frame status 1 command (second error occurrence command) or the big winning mouth 1 count display command (big winning mouth count command). ), It is suggested that the upper operation side liquid crystal display device 470 (second display device) is used to prompt the user to press the pressing operation unit 405 (operation unit) as shown in FIG. For example, based on the suggested display object image data, display control is performed for an arrow-type icon in a display form in which, for example, “Please press a button to call a store clerk” is superimposed (operation prompting means). Subsequently, the effect control program starts displaying the arrow icon as a call control function, and then controls the call operation different from the most recent effect operation to the outside by the operation of the pressing operation unit 405 (calling). Control means), and a mode that makes it easy for the hall clerk to draw attention.

  In this way, a player who tries to call a hall clerk does not have to extend his arm or body to reach the data counter, which was often placed above the pachinko machine 1. Since it is only necessary to press the pressing operation unit 405 provided on the door frame 5 that is closer to the player, it is possible to suppress the physique inconvenience and the physical burden of calling the hall clerk. Even if the pachinko machine 1 is played for a long time, it becomes difficult to receive unnecessary stress. Therefore, according to such a structure, it can contribute to the improvement of an operation rate.

  By the way, the work by the hall clerk who appeared at the player in response to the above-mentioned call should be completed as soon as possible considering the player's psychological state that he wants to resume the game as soon as possible. You should have the desire to cooperate with the hall clerk as much as possible. On the other hand, in this pachinko machine 1, the effect control program analyzes the error content based on the frame state 1 command (second error occurrence command) received from the main control board 4100 (error content analysis means). Furthermore, the production control program is based on an error content management table (not shown) that manages whether or not the player should take his / her seat according to each error content, and performs complex handling work (for example, by the hall clerk according to the error content) When it is determined that the main body frame 3 or the door frame 5 needs to be opened / closed), as described above, only the standard message “Please press the button to call the store clerk” is superimposed on the arrow icon. On the other hand, if it is determined that there is no need for complex handling work by the hall clerk according to the error content, an additional message “Please leave your seat” is added to the arrow icon in addition to the standard message above. The display mode is superimposed. In this way, a player who encounters such an error will act immediately without hesitating whether he should take his seat off and wait for the hall clerk due to the presence of the additional message described above. It can be determined whether it should be done, and if necessary, the hall clerk can be given enough work space to complete the subsequent work.

  In addition, when the effect control program detects an operation signal output in response to the operation of the pressing operation unit 405, it determines whether or not an arrow icon is displayed, and when this arrow icon is displayed. Is considered that the pressing operation unit 405 is operated in response to the appearance of the arrow icon. On the other hand, when the effect control program detects the operation signal, if the arrow icon is not displayed, the operation signal is not the appearance of the arrow icon, but other factors (operation on the effect is prompted). It is considered that the pressing operation unit 405 has been operated in response to this.

  Here, when it is determined that the effect control program has shifted from the normal gaming state to the big hit gaming state (special gaming state) based on the command received from the main control board 4100, the suggestion read from the liquid crystal and sound control ROM 4160b thereafter. On the basis of the display object image data, the arrow-type icon is displayed on the upper-plate-side liquid crystal display device 470 (second display device), for example, “If you are about to overflow from the dollar box, please press the operation section to call the store clerk”. It is good also as a display mode superimposed on. In this way, if the player is likely to overflow from the storage box (corresponding to the dollar box) after the game ball discharged through the lower plate 302 after being paid out in the big hit gaming state, Since it is not necessary to extend an arm or body in order to operate a so-called data counter call button by hand, it is possible to concentrate more on the game and to suppress a reduction in operating rate.

  By the way, in order to call a hall clerk for a new storage box in the big hit gaming state in this way, the player is prompted to operate the pressing operation unit 405 according to the display mode of the upper plate side liquid crystal display device 470. At first glance, the control program seems to be difficult to distinguish the operation signal from the case where the player is actually prompted to operate the pressing operation unit 405 in terms of performance in the big hit gaming state itself. In other words, when the operation signal is detected, the effect control program determines whether the player has operated the pressing operation unit 405 in search of a new storage box, or the player performs a pressing operation in response to the effect in the big hit gaming state. It seems that it cannot be distinguished whether the part 405 has been operated.

  However, the effect control program uses the concept of time sharing, and in the jackpot game state (special game state), the player actually urges the player to perform an operation by the pressing operation unit 405 and performs the call operation by the call control function. And the clerk callable time zone in which the hall clerk can be called by the operation of the pressing operation unit 405 and the execution of the call operation by the call control function is permitted. (Time sharing control means). Specifically, the effect control program is found to be a frame state 1 command (second error occurrence command) indicating that the command analyzed in the received command analysis process (step S1022) is full. In this case, it is regarded as the clerk callable time zone, while other time zones are set as the participation operation available time zone. This effect control program is shown in FIG. 77 using an upper plate side liquid crystal display device 470 (second display device) displaying that it is a big hit when it is considered that it is the clerk callable time zone. Control the display of the word “Pull out the ball” at the top of the screen and control the display of the arrow-type icon with the display of “Please press the button to call the store clerk” ing. In this way, when the operation control signal is detected in the jackpot gaming state, the push operation unit responds to the jackpot gaming state effect when the detection timing is within the participation operation available time zone. On the other hand, when the detection timing is within the clerk callable time zone, it is determined that the pressing operation unit 405 has been operated to call the hall clerk. In the above-described effect control program, a touch panel is mounted on the surface of the upper plate side liquid crystal display device 470 so as to prompt the user to operate the buttons displayed on the upper plate side liquid crystal display device 470 instead of the pressing operation unit 405. good. By the way, the effect control program indicates that the command analyzed in the received command analysis process (step S1022) is the above-mentioned winning prize 1 count display command (big winning prize count command) and is full. If it is determined that it is a frame state 1 command (second error occurrence command), it is likely that the game ball will not fit in the storage box at the time of a big hit, and the above-mentioned is an opportunity for the player to call the hall clerk. The screen shown in FIG. 77 is displayed.

  By the way, this effect control program determines that the command analyzed in the received command analysis process (step S1022) is a door opening command or a body frame opening command (that is, the door frame 5 is not connected to the body frame 3). When opened or when the main body frame 3 is opened with respect to the outer frame 2), the upper plate side liquid crystal display device 470 (second display device) is caused to display in the following display mode. That is, the production control program gives an instruction to display the service mode screen (see FIG. 78) for the work by the hall clerk on the upper plate side liquid crystal display device 470, and then the player dial operation unit 401 ( When it is detected that “meal break setting” is selected by the pressing operation of the pressing operation unit 405 (operation unit) after the rotation operation of the operating unit), the operation for setting the operation stop time that does not allow the above-described operation An instruction to display a break timer setting screen (see FIG. 79) corresponding to the setting screen is given (operation setting screen display control means). In this way, by using a door opening command or a body frame opening command that can only be generated by the operation of a hall clerk, it is difficult to display such a break timer setting screen by a player operation. Can do.

  In addition, the production control program stores time information (for example, 60 minutes) input to the break timer setting screen (operation setting screen) in accordance with the operation of the hall clerk using the dial operation unit 401 (operation unit) and the press operation unit 405. The operation stop time is set (operation stop time setting means). Furthermore, the production control program sets the operation stop time set in the upper liquid crystal display device 470 (second display device) when the operation stop time is set in the break timer setting screen (operation setting screen). The remaining time is displayed as shown in FIG. 80 (remaining time display control means). In addition, the effect control program may make at least a part of the effect operations performed by the peripheral control board 4140 in a stopped state or a suppressed state (remaining time display control means). This production control program suppresses at least the display operation of the game board side liquid crystal display device 1900 (first display device) by the peripheral control board 4140 over the set operation stop time, for example, a blackout display mode and the like You may make it do (1st display control suppression means). If it does in this way, the power consumption of the game board side liquid crystal display device 1900 can be suppressed over the operation stop time which a player does not play.

  In addition, the effect control program determines whether the remaining time of the operation stop time is in a predetermined state, for example, the count is zero, or the command analyzed in the received command analysis process (step S1022) described above is the door closing command or the main body. When it is determined that the command is a frame closing command, the display control of the remaining time of the operation stop time shown in FIG. 80 is ended and the stop state or the suppression state of the part of the rendering operations is canceled (stop state canceling means). In this way, by using the door closing command or the main body frame closing command that can be generated only by the operation of the hall clerk as described above, it is difficult for the player to perform such release. Can do.

  By the way, in the effect control program, the remaining time of the operation stop time is counted as zero (predetermined state), and the command analyzed in the received command analysis process (step S1022) described above is the door closing command or the body frame. If it is not a closing command, the game board side liquid crystal display device 1900 is controlled in a specific manner different from the most recent presentation operation, for example, and a notification operation to the effect that the remaining operation stop time has ended is executed (notification operation). Starting means). In this way, not only the hall clerk but also the player who is waiting for the pachinko machine 1 to be opened to a third party can be immediately and easily notified that the break allowable time has ended. it can. Further, the effect control program, after starting the notification operation, determines that the command analyzed in the received command analysis process (step S1022) described above is a door closing command or a body frame closing command (that is, the door). When the frame 5 is closed with respect to the main body frame 3 or when the main body frame 3 is closed with respect to the outer frame 2), the above-described notification operation is stopped (notification operation stop means). If it does in this way, time when pachinko machine 1 based on a player's intention, such as a break, cannot operate can be shortened as much as possible.

  In this case, since it is necessary to open and close the main body frame 3 or the door frame 5 in order to suspend or resume the operation of the pachinko machine 1, only the hall clerk who possesses the key necessary for opening and closing the pachinko machine 1 will The operation 1 can be suspended and resumed. In addition, a certain hall clerk suspends the operation of the pachinko machine 1 for a while because it is taking a break and then pays attention to each pachinko machine 1 and each player by receiving calls from many players. Even if the operation cannot be performed, the pachinko machine 1 that has suspended the operation immediately enters the state in which it is easily recognizable by the third party that the operation low time has elapsed as soon as the operation stop time has elapsed. . For this reason, even if the player does not come back from the break, the hall clerk can make this pachinko machine 1 ready for play by other players at an early stage. The operating rate related to the machine 1 can be increased as much as possible, and the operating rate of each pachinko machine 1 installed in each island facility can be increased as a whole.

  By the way, the production control program is based on the calendar information and time information stored in the RTC built-in RAM 4165aa of the RTC control unit 4165 mounted on the peripheral control board 4140, according to the time zone in which the player takes a break. When setting the operation stop time, the unit time that can be changed per operation (hereinafter referred to as “variable unit time”) is changed from 5 minutes to a desired unit time (for example, 15 minutes) as shown in FIG. May be. If such a change is possible, the operation stop time can be flexibly set according to the time zone of the day or the day of the week. ) To keep the operating rate as high as possible by shortening the variable unit time, and to improve the hall service as a longer variable unit time during times when it is difficult to originally expect a high operating rate (weekday daytime) Thus, it is possible to prevent the player's willingness to play again in the hall next time from being impaired.

  On the other hand, if the command analyzed in the received command analysis process (step S1022) is an error cancellation navigation command (second error occurrence command) as described above, the effect control program executes this error cancellation navigation command. The error occurrence position information included in is extracted and acquired (error occurrence location specifying means).

  Subsequent to step S1022, the effect control program performs warning processing (step S1024). In this warning process, when the command analyzed by the effect control program in the received command analysis process in step S1022 as described above includes various commands classified into the notification display shown in FIG. The screen generation schedule data, the light emission mode generation schedule data, the sound generation schedule data, the electrical drive source schedule data, and the like set in the abnormality display mode for executing the abnormality notification are stored in the peripheral control unit 4150. It is extracted from the various control data copy areas 4150ce of the peripheral control ROM 4150b or the peripheral control RAM 4150c and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c. In the warning process, when multiple abnormalities occur simultaneously, the abnormality notification is performed in the order of the priority registered in advance, and the abnormality is automatically resolved and the remaining abnormality notifications are automatically transitioned to. It is supposed to be. This allows you to monitor multiple anomalies at the same time without losing the information that an anomaly has occurred due to the occurrence of another anomaly after the occurrence of the anomaly but before resolving the anomaly Can do.

  Furthermore, in this warning process, after a predetermined time has elapsed since the power was turned on, the command analyzed by the effect control program in the received command analysis process (step S1022) described above is classified into the status display shown in FIG. For example, a game board can be obtained by controlling the liquid crystal and sound control unit 4160 in a mode different from the normal production mode accompanying the production operation, for example, an error cancellation navigation command (second error cancellation command). The side liquid crystal display device 1900 (effect device), the upper plate side liquid crystal display device 470 (effect device), and a lamp (effect device) are used to visually warn the outside, and a pair of side speakers 130 (effect device) are used. To audibly warn the outside (error notification means). In this way, when a malicious player attempts to input an error cancellation navigation command to the main control board 4100 by operating the operation switch 860a of the payout control board 4110 in spite of being in a gaming state. Since the pachinko machine 1 is configured to warn the outside, fraudulent acts on the main control board 4100 that may affect the progress of the game are suppressed.

  When notified to the outside as described above, the presentation control program reads the main body frame rear image data from the liquid crystal and sound control ROM 4160b (data storage unit), and this read main frame rear image. Based on the data, the main body frame rear surface image specified on the upper plate side liquid crystal display device 470 (second display device) based on the error occurrence position information included in the frame state 1 command (second error occurrence command) A maintenance screen with the upper specific area as a default display mode is displayed as shown in FIG. 76 (error occurrence position suggesting means).

  In the maintenance screen shown in FIG. 76, the error number and the error content are displayed in the horizontal direction at the top of the maintenance screen, and in addition to the arrow-shaped icon described above, for example, “Insufficient payout”. The details of the error are displayed. Furthermore, on the maintenance screen, a main body frame rear image is displayed on the right half. This main body frame rear image is a schematic view of the pachinko machine 1 viewed from the rear, that is, the arrangement of the respective parts on the rear side of the main body frame 3 on which the game board 4 is mounted. The effect control program described above corresponds to a specific area (area 740Z) on the main body frame rear image based on the error occurrence position information included in the frame state 1 command (second error occurrence command) received from the main control board 4100. ) And a display mode (default display mode) in which the specific area 740Z blinks on the back image of the main body frame.

  In this way, the hall clerk who arrives at the player in response to the player's call opens the main frame 3 with respect to the outer frame 2 and attaches the game to the main frame 3 as in the prior art. Without checking the error contents of the error LED indicator 860c provided on the payout control board 4110 of the panel 4, the upper side liquid crystal display device 470 (second display device) provided in a part of the door frame 5 If the area 740Z on the main body frame rear image on the maintenance screen is confirmed, it is possible to immediately know which part of the pachinko machine 1 has an error by visually recognizing the blinking mode of the area 740Z. For this reason, according to the configuration of the present embodiment, even in a situation where the pachinko machine 1 is complicated as in recent years, it is possible to suppress an increase in the time required for error handling, and the pachinko machine 1 having a complicated configuration. In this case, the hall clerk can complete the error handling as soon as possible, and it is possible to prevent the player from being impatient or dissatisfied during the error handling.

  Here, the production control program not only erases the error occurrence position suggestion image from the upper-plate-side liquid crystal display device 470 upon receipt of the error cancellation navigation command (second error cancellation command), but instead When the main body frame closing command is received prior to the error canceling navigation command, the main body frame closing command is regarded as an error canceling navigation command, and when the main body frame closing command is received, the upper side liquid crystal display device The main body frame maintenance image is erased from 470 (second display device) (screen return means). In this way, even if the hall clerk who has completed the error handling forgets to operate the operation switch 860a, the main body frame closing command is regarded as a substitute for the error canceling navigation command, not only canceling the error notification but also the upper plate side The maintenance screen display of the liquid crystal display device 470 can be turned off. In this case, even if the hall clerk forgets to turn off the maintenance screen of the upper plate side liquid crystal display device 470 after handling the error, the hall clerk automatically turns off by closing the main body frame 3 with respect to the outer frame 2, and then the player feels uncomfortable. The game can be continued without feeling.

  Next, following step S1024 described above, the effect control program performs main prize ball number information output determination processing (step S1025). In the main prize ball number information output determination process, when the effect control program is a main prize ball number information output command classified into the other shown in FIG. 42, the command analyzed in the received command analysis process in step S1022 is: Based on the value of the peripheral control side main award ball number information output determination counter, the main award that informs the hall computer as main award ball information that the number of game balls to be paid out as 10 award balls has reached 10 It is determined whether or not to output a sphere information output signal to the external terminal board 784. This peripheral control side main prize ball number information output determination counter is used as a prize ball based on the other main prize ball number information output command shown in FIG. 42 analyzed by the received command analysis process in step S1022. The number of game balls to be paid out is counted and is updated in a prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c. Since the main prize ball number information output command classified into others shown in FIG. 42, as described above, reports that the number of game balls scheduled to be paid out as a prize ball has reached 10 balls. When this main prize ball number information output command is received, the value 10 is added to the value of the peripheral control side main prize ball number information output determination counter, and the value is stored and updated in a prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c. It has become so.

  In the main prize ball number information output determination process, the effect control program is for determining the main prize ball number information output at power-on when the command analyzed in the received command analysis process in step S1022 is classified into the power-on shown in FIG. When it is a counter notification command, the main control board 4100 is provided on the game board 4 based on the contents designated by the power-on main prize ball number information output determination counter notification command. The main prize ball which counted the number of game balls to be paid out as prize balls based on the game balls entered in various prize openings such as the lower start opening 2102, the general prize opening 2104, 2201 and the big prize opening 2103 The value of the number information output determination counter is set as the initial value of the peripheral control side main prize ball number information output determination counter, while step S10. When the command analyzed in the received command analysis process of No. 2 is a main prize ball number information output command classified as shown in FIG. 42, the main prize ball number information output command is a game scheduled to be paid out as a prize ball. Since the number of balls has reached ten, the value 10 is added to the value of the peripheral control side main prize ball number information management counter.

  In the main prize ball number information output determination process, the effect control program determines whether the command analyzed in the received command analysis process in step S1022 is classified into the power-on state shown in FIG. 8, the main control board 4100 is provided in the game board 4 on the basis of the contents designated by the power-on main prize ball number information output determination counter notification command. Main prize which counted the number of game balls to be paid out as prize balls based on game balls entered in various prize openings such as 2101, lower start opening 2102, general prize opening 2104, 2201 and big prize opening 2103 When setting the value of the counter for determining the number of balls information output as the initial value of the counter for determining the number of main prize balls on the peripheral control side, In order to start business of the hall based on the time information acquired in the current time information acquisition process of S1002 and set in the time information storage unit in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. When it is determined that the power to the pachinko gaming machine 1 is turned on (or the power to the pachinko island facility where the pachinko gaming machine 1 is installed), the peripheral control side main prize ball number information management By forcibly resetting the counter value and setting it to the default value, the initial value is returned to the value 0 (zero), and stored and updated in the award ball schedule information storage area (not shown) of the peripheral control RAM 4150c (for example, in step S1022). The command analyzed in the received command analysis process is classified into the power-on shown in FIG. Main prize ball number information output determination counter notification command. When the power is turned on, the main prize ball number information output determination counter notification command indicates that the value of the main prize ball number information output determination counter is value 9. In the case of the contents, even if this value 9 is set as the initial value of the peripheral control side main prize ball number information output determination counter, it is reset and returned to the default value 0 (zero) as the initial value. As a result, if the command analyzed in the received command analysis process in step S1022 is the main prize ball number information output command classified into the other shown in FIG. Each time, the value 10 is added to the value of the peripheral control side main award ball number information output determination counter, that is, on the main control board 4100 side. The new main prize ball number information output determination counter value and the peripheral control side main prize ball number information output determination counter value updated on the peripheral control board 4140 side have the same value. ) On the other hand, when it is determined that the power supply to the pachinko machine 1 is not turned on to start the hall operation, but the power is restored due to a power failure or a momentary power interruption during the hall operation. The value of the peripheral control side main prize ball number information management counter is not reset to the initial value by resetting the value of the peripheral control side main prize ball number information management counter to the default value, and the value of the peripheral control side main prize ball number information management counter (For example, the command analyzed in the received command analysis process in step S1022 is the power-on main prize ball number information output determination counter notification command classified into power-on shown in FIG. When the main prize ball number information output determination counter notification command is the content indicating that the value of the main prize ball number information output determination counter is the value 9 This value 9 is set as the initial value of the peripheral control side main prize ball number information output determination counter, whereby the command analyzed in the received command analysis process in step S1022 is classified into the other shown in FIG. When it is a main prize ball number information output command, every time this main prize ball number information output command is received, a main prize ball number information output judgment value which is the value of the peripheral control side main prize ball number information output judgment counter The value 10 is added to the value 9 set as the counter value, that is, the value of the main prize ball number information output judgment counter updated on the main control board 4100 side and the peripheral control board 4140 side. The value of the updated peripheral control side main prize ball number information output determination counter is not the same value).

  In the main prize ball number information output determination process, the effect control program determines the value of the peripheral control side main prize ball number information management counter based on the added value of the peripheral control side main prize ball number information management counter. When the number exceeds 10, that is, when the number of game balls to be paid out as a prize ball has reached ten, a main prize ball information output signal is transmitted to the hall computer as main prize ball information. The main prize ball information output signal schedule data to be output to the external terminal board 784 is set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. As a value of the control side main prize ball number information management counter, a prize ball schedule information storage area (not shown) of the peripheral control RAM 4150c is shown. It is adapted to store updated.

  Here, in the main award ball number information output determination process, a main award ball information output signal that informs the hall computer as main award ball information that the number of game balls to be paid out as award ball has reached 10 The point of maintaining or resetting the value of the peripheral control side main prize ball number information output determination counter for determining whether or not to output to the external terminal board 784 at the time of power recovery will be described. First of all, at the time of power recovery, it is always determined in step S1022 without determining whether the power is turned on from the state where the power is cut off or whether the power is restored after a power failure or instantaneous power failure. If the command analyzed in the received command analysis process is the power-on main prize ball number information output determination counter notification command shown in FIG. 8 is provided on the game board 4 based on the content designated by the counter notification command for the upper start port 2101, the lower start port 2102, the general winning port 2104, 2201, and the big winning port 2103 shown in FIG. The main prize ball number information output judgment card that counts the number of game balls to be paid out as prize balls based on the game balls entered in various prize winning openings such as The issues will be described in the case of directly setting the values of the printer as the initial value of the peripheral control side main prize ball number information output determining counter.

  First, as described above, the main control MPU 4100a of the main control board 4100 enters the general winning ports 2104 and 2201 shown in FIG. 8 in the switch input process of step S104 in the main control timer interrupt process shown in FIG. 12. Detection signals from the general winning opening switches 3020 and 3020 shown in FIG. 12 for detecting the ball that has been balled, and the count switch 2110 shown in FIG. 12 for detecting the gaming balls that have entered the big winning opening 2103 shown in FIG. , A detection signal from the upper starter switch 3022 shown in FIG. 12 that detects a game ball that has entered the upper starter 2101 shown in FIG. 8, and a ball that enters the lower starter 2102 shown in FIG. The main control built-in RAM is read as input information for each detection signal from the lower start port switch 2109 shown in FIG. In the input information storage area, the input information is read from the input information storage area of the main control built-in RAM, and based on this input information, in the prize ball control process of step S108 in the same process, The number of game balls to be paid out is counted, the value of the main prize ball number information output judgment counter is updated and stored, and the main prize ball number information output is output based on the value of the main prize ball number information output judgment counter When the value of the determination counter has reached the value 10 (that is, when the number of game balls to be paid out as a prize ball has reached 10), FIG. In addition, a main prize ball number information output command classified into others is created and stored as transmission information in a transmission information storage area. Then, the main control MPU 4100a of the main control board 4100 transmits a main prize ball number information output command to the peripheral control board 4140 in the peripheral control board command transmission process of step S120 in the same process.

  A staff member such as a hall clerk may perform maintenance with the pachinko gaming machine 1 turned on until late at midnight across the day after the hall is closed. Even when the power to the pachinko island facility where the pachinko gaming machine 1 is installed is cut off, the power (power) stored in the capacitor BC0 as the backup power source provided in the power board 851 shown in FIG. However, power (electric power) is supplied to the main control board 4100 for a predetermined time. As a result, the power (power) stored in the capacitor BC0 is completely discharged from the time when the power to the pachinko island facility is turned on until the time when the power to the pachinko island facility is turned on again in order to start operating the hall. If not, the capacitor BC0 causes the main control MPU 4100a to store various information in the main control built-in RAM. Then, when a staff member such as a hall clerk does not operate the operation switch 860a of the payout control board 4110 in order to initialize the main control built-in RAM (game storage unit) for a predetermined time after the power is turned on, In the step S34 in the main control side power-on process shown in FIG. 44, various information is read from the game backup information, and various commands corresponding to the various information are stored in a predetermined storage area of the main control built-in RAM. In the peripheral control board command transmission process of step S120 in the main control timer interruption process shown in FIG. 46, the state is restored, and the value of the yesterday main prize ball number information output determination counter is inherited as it is. The problem of transmitting the main prize ball number information output command to the peripheral control board 4140 occurs.

  Therefore, in the present embodiment, the effect control program is a power source in which the command analyzed in the received command analysis process in step S1022 is classified into the power-on shown in FIG. 41 in the main prize ball number information output determination process in step S1025. When it is a counter notification command for determining the main prize ball number information output at the time of turning on, the main control board 4100 is provided on the game board 4 based on the contents instructed by the counter notification command for outputting the main prize ball number information at the time of power-on. Games to be paid out as prize balls based on the game balls entered in various prize openings such as the upper start opening 2101, the lower start opening 2102, the general winning opening 2104, 2201 and the large winning opening 2103 shown in FIG. The value of the main prize ball number information output judgment counter that counts the number of balls is used as the peripheral control side main prize ball number information output judgment counter. Is set as the initial value of the data, based on the time information acquired in the current time information acquisition process of step S1002 and set in the time information storage unit in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. This time information is set to a period before the start of business for starting business of the hall (or for starting maintenance of the pachinko machine 1) (in this embodiment, a period from 0:00 am to 9:00 am). And stored in advance in the peripheral control ROM 4150b.) The power to the pachinko gaming machine 1 is turned on (or the pachinko gaming machine 1 is installed to start the hall business). The peripheral control side main prize ball number information when it is determined that the power to the pachinko island facility is turned on) By forcibly resetting the value of the physical counter and setting it to the default value, the value is returned to the initial value 0 (zero), and is updated in the award ball schedule information storage area (not shown) of the peripheral control RAM 4150c. If the information is within the period before the start of business for starting the business of the hall (or for starting maintenance of the pachinko machine 1) (in this embodiment, during the business period of the hall) Peripheral control side main prize when it is determined that the power supply to pachinko machine 1 is not turned on to start business, and that power is restored due to a power outage or momentary power interruption during hall operation Peripheral control side main prize ball number information without resetting to 0 (zero) as the initial value by forcibly resetting the value of the ball number information management counter and setting it to the default value A system that maintains the value of the management counter is adopted.

  As a result, there is a very low probability of a power outage or momentary power failure between the start and end of the hall, but if a power outage or power outage occurs, the hall business has already started. FIG. 8 shows that the main control board 4100 is provided on the game board 4 based on the content of the counter notification command for main prize ball number information output determination at power-on from the main control board 4100 when power is restored. Counts the number of game balls to be paid out as prize balls based on the game balls entered in various winning openings such as the upper starting opening 2101, the lower starting opening 2102, the general winning opening 2104, 2201, and the big winning opening 2103 When the value of the main prize ball number information output determination counter is set as the initial value of the peripheral control side main prize ball number information output determination counter, The peripheral control-side main for determining whether or not to output to the external terminal board 784 a main prize ball information output signal that informs the hall computer as main prize ball information that the number of game balls has reached 10 Without forcibly resetting the value of the winning ball number information output judgment counter, the value of the main prize ball number information output judging counter immediately before the occurrence of a power failure or momentary power failure Alternatively, at the time of power recovery due to the recovery (recovery) of electric power after the momentary power failure, it is taken over as it is and set as the value of the peripheral control side main prize ball number information output determination counter.

  On the other hand, when the hall operation is ended and the hall operation is started again, the fact that the number of game balls scheduled to be paid out as a prize ball has reached 10 is sent to the hall computer as main prize ball information. To forcibly reset the value of the peripheral control side main prize ball number information output determination counter for determining whether or not to output the main prize ball information output signal to be transmitted to the external terminal board 784 and set it to the default value. Is returned to the initial value of 0 (zero), and when the hall is closed and the pachinko gaming machine 1 is turned off (or the pachinko island facility where the pachinko gaming machine 1 is installed is turned off) The value of the main prize ball number information output determination counter at the time of the power recovery to the pachinko machine 1 when the pachinko machine 1 is turned on to start the hall operation (or the pachinko machine 1 is installed) When the power of the pachinko island facility is restored), even if it is set as the value of the peripheral control side main prize ball number information output judgment counter, it is not taken over as it is, and this peripheral control side main prize ball number information output judgment Because the counter value is forcibly reset and set to the default value, it is reset to the initial value of 0 (zero), so it is updated from the start to the end of the hall operation. Based on the main prize ball number information output command from the main control board 4100 transmitted based on the stored value of the main prize ball number information output judgment counter, the peripheral control side main prize ball number information output judgment counter Whether or not to output the main prize ball number information to the external terminal board 784 based on the value of the peripheral control side main prize ball number information output determination counter by updating the value And it can now be determined. Thus, based on the value of the peripheral control side main prize ball number information output determination counter, accurate main prize ball information can be output from the peripheral control board 4140 to the hall computer via the external terminal board 784. As described above, the main prize ball number information is obtained from the output terminal PT10 provided in light blue on the external terminal board 784, from the upper start opening 2101, the lower start opening 2102, the general winning opening 2104, 2201, shown in FIG. As a main prize ball number information output signal that informs the player every time the number of game balls to be paid out as prize balls reaches 10 on the basis of game balls that have entered the various prize openings such as the big prize opening 2103 Output to hall computer. Therefore, the hall computer can accurately grasp the number of game balls to be paid out until the hall business is started and ended.

  Next, following step S1025 described above, the effect control program performs an RCT acquisition information update process (step S1026). In this RTC acquisition information update process, the effect control program stores in the calendar information storage unit acquired in the current time information acquisition process in step S1002 and set in the RTC information acquisition storage area 4150cad of the peripheral control RAM 4150c shown in FIG. The updated calendar information and the time information stored in the time information storage unit are updated. By this RCT acquisition information update process, the hour, minute and second as time information stored in the time information storage unit are updated, and the year and month as calendar information stored in the calendar information storage unit based on the updated time information. The day is updated.

  Subsequent to step S1026, the effect control program performs power consumption monitoring processing (step S1027). This power consumption monitoring process is a process for adjusting the sound volume and the brightness of various LEDs in order to suppress this power consumption in accordance with the power consumption in the pachinko gaming machine 1, and will be described in detail later. To do.

  Subsequent to step S1027, the effect control program performs lamp data creation processing (step S1028). In this lamp data creation process, the effect control program updates the pointer in the scheduler update process in step S1020, and the pointer indicates the light emission data arranged in time series constituting the light emission mode generation schedule data. Based on the light emission data to be played, the game board side light emission data SL- for outputting a lighting signal, a flashing signal, or a gradation lighting signal to a plurality of LEDs of various decorative boards provided in the game board 4 shown in FIG. DAT is extracted and created from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and is set in the lamp drive board side transmission data storage area 4150caa of the peripheral control RAM 4150c shown in FIG. In addition, the various decorative boards provided on the door frame 5 are duplicated. The door side light emission data STL-DAT for outputting a lighting signal, a blinking signal, or a gradation lighting signal to the LED is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c. And is set in the frame decoration drive amplifier board side LED transmission data storage area 4150cab of the peripheral control RAM 4150c shown in FIG.

  Subsequent to step S1028, the effect control program performs display data creation processing (step S1030). In this display data creation process, the presentation control program updates the pointer in the scheduler update process in step S1020, and the screen data indicated by the pointer among the screen data arranged in time series constituting the schedule data for screen generation. Are extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. When the screen data is input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a extracts character data from the liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data, thereby playing the game board side liquid crystal display device 1900, movable liquid crystal display devices 1925a to 1925d, and drawing data for one screen (one frame) to be displayed on the upper side liquid crystal display device 470 are generated on the built-in VRAM.

  For example, when executing the current peripheral control unit steady process, drawing data for one screen (one frame) displayed on the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d is stored in the built-in VRAM. When generating and holding in the frame buffer MVD, when the screen data is input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a extracts the character data from the liquid crystal and sound control ROM 4160b based on the input screen data. The sprite data is created, and in the frame buffer MVD shown in FIG. 32A, a large original image MVD0 for drawing in the display area of the game board side liquid crystal display device 1900 is displayed in the upper right part of FIG. As the origin, 600 dots downward from the origin of FIG. 32 (b), the origin of FIG. 32 (b) To create at 800 dots Luo left direction. Accordingly, the large original image MVD0 has a size of horizontal width: 800 dots and vertical width: 600 dots. Subsequently, the original image MVD0 is subjected to a process of extending the original image MVD0 from the first row constituting the 800 dots to the last row one by one in sequence (that is, doubled), thereby executing the original image MVD0. A stretched image MVD1 is created by stretching MVD0 twice in the horizontal direction (leftward in FIG. 32B). Horizontal width of the large original image MVD0: By performing a process of extending the original image MVD0 to two columns in order from the first column constituting the 800 dots to the last column (that is, doubled), the horizontal width of the large original image MVD0: If one column of the last column consisting of 800 dots is extended to two columns, one column is not overwritten by the two extended columns, and one of the other columns following the one column If one column of the original image MVD0 is extended by two columns, one column is overwritten by the two extended columns, and if the last column of the large original image MVD0 is extended to two columns, the extended two columns extend the end of the large original image MVD0. Is overwritten to delete the large original image MVD0 from the frame buffer MVD (that is, the frame buffer MVD0). The Omoto image MVD0 by stretching the Omoto image MVD0 stored in VD is generating while) stretched image MVD1 removed from the frame buffer MVD. Note that this enlargement is performed when the sound source built-in VDP 4160a creates the large original image MVD0, based on the screen data from the peripheral control MPU 4150a, character data is extracted from the liquid crystal and sound control ROM 4160b and enlarged and reduced to create sprite data. It is executed by the same command. The sound source built-in VDP 4160a creates the stretched image MVD1, and then performs mask processing to remove the image in the portion corresponding to the odd address of the frame buffer MVD, so that the odd mask dots shown in FIG. Using a predetermined slit-like odd-numbered mask pattern generated so as to be alternately arranged with blank dots, an image of a portion corresponding to each odd-numbered dot row that can be specified by an odd address shown in FIG. A grid-like processed image that is processed into a grid so that only a plurality of strip-shaped images corresponding to even-numbered dot rows that can be specified by even-numbered addresses remain by removing them in a grid (slit) along the vertical direction. Create MVD2.

  When the screen data is input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a extracts the character data from the liquid crystal and sound control ROM 4160b based on the input screen data, creates sprite data, and outputs the liquid crystal output board from the even channels. When drawing data for the game board side liquid crystal display device 1900 transmitted to 3420 is created in the frame buffer MVD, then drawing is performed in the display area of the movable liquid crystal display device 1925a in the frame buffer SVDA shown in FIG. A large original image SVDA0 is created with the upper right portion as the origin and 204 dots downward from the origin and 360 dots left from the origin. Thus, the large original image SVDA0 has a size of horizontal width: 360 dots and vertical width: 204 dots. Subsequently, the large original image SVDA0 is subjected to a process of extending the original image SVDA0 by extending the first row constituting the 360 dots from the first row to the last row in order of two rows (that is, twice). A stretched image SVDA1 is created by stretching SVDA0 twice in the horizontal direction (leftward in FIG. 32D). Width of the large original image SVDA0: By performing the process of extending the first row constituting 360 dots from the first row constituting the 360 dots to the last row one by one in order (that is, twice), the horizontal width of the large original image SVDA0: If one column of the last column constituting 360 dots is extended to two columns, one column is not overwritten by the two extended columns, and one of the other columns following the one column When one column of the original image SV2 is extended, the first row is overwritten by the two extended rows, and when the last row of the large original image SVDA0 is extended to two rows, the last two rows of the large original image SVDA0 are extended. Is overwritten to delete the large original image SVDA0 from the frame buffer SVDA (that is, the large original image SVDA0 stored in the frame buffer SVDA). It has generated while) stretched image SVDA1 remove frame buffer SVDA Omoto by stretching the Omoto image SVDA0 stored in the image SVDA0 from the frame buffer SVDA. As described above, this extension is performed by extracting character data from the liquid crystal and sound control ROM 4160b based on the screen data from the peripheral control MPU 4150a when the sound source built-in VDP 4160a creates the large original image MVD0 or the large original image SVDA0. Then, it is executed by the same command as the command that created the sprite data by scaling. The sound source built-in VDP 4160a performs mask processing on the extended image SVDA1 created by the frame buffer SVDA to remove an image at a portion corresponding to the even address of the frame buffer SVDA, as shown in FIG. Each even dot row that can be specified by an even address shown in FIG. 32 (f) using a predetermined slit-like even row mask pattern generated so that the even mask dots MD are alternately arranged with the blank dots BD. By removing the image of the portion corresponding to に in a lattice shape (slit shape) along the vertical direction, only a plurality of strip-like images of the portion corresponding to the odd dot rows that can be specified by odd addresses remain in a lattice shape. A processed grid-like processed image SVDA2 is created, and the frame buffer MVD shown in FIG. It is transferred to the area RGNA.

  The sound source built-in VDP 4160a is a large original image SVDB0 for drawing in the display area of the movable liquid crystal display device 1925b created in the frame buffer SVDB (the large original image SVDB0 has a size of horizontal width: 360 dots and vertical width: 204 dots). Is transferred to the frame buffer SVDA and arranged at the same position as the large original image SVDA0, and the horizontal width of the large original image SVDB0: from the first column constituting 360 dots toward the last column By performing the process of sequentially extending each column by two columns (that is, by double), the large image SVDB0 is expanded by a factor of two in the horizontal direction (leftward in FIG. 32 (d)). Create By executing again the enlargement process performed when the extended image SVDA1 is generated from the large original image SVDA0, the extended image SVDB1 is generated from the large original image SVDB0 in the frame buffer SVDA. As a result, the original image SVDB0 has a horizontal width of 360 dots, and the process of extending the original image SVDB0 from the first column to the last column one by one in order to two columns (that is, twice) is performed again. The width of the image SVDB0: If one column of the first column to the last column constituting 360 dots is extended to two columns, one column is not overwritten by the two extended columns, and the other columns following the one column are not overwritten. If any one of the columns is extended by two columns, one column is overwritten by the two extended columns, and if the last column of the large original image SVDB0 is extended to two columns, the expanded two columns are larger. By overwriting the last column of the original image SVDB0, the large original image SVDB0 stored in the frame buffer SVDA is extended and the large original image SVDB0 is deleted from the frame buffer SVDA. Together are generating stretched images SVDB1 (i.e., while deleting the Omoto image SVDB0 by stretching the Omoto image SVDB0 stored in the frame buffer SVDA from the frame buffer SVDA). As described above, this extension is performed by extracting character data from the liquid crystal and sound control ROM 4160b based on the screen data from the peripheral control MPU 4150a when the sound source built-in VDP 4160a creates the large original image MVD0 or the large original image SVDB0. Then, it is executed by the same command as the command that created the sprite data by scaling. The sound source built-in VDP 4160a performs the mask processing performed when creating the grid-processed image SVDA2 in order to remove the image in the portion corresponding to the even address of the frame buffer SVDA from the extended image SVDB1 created by the frame buffer SVDA. By performing again, when the grid-like processed image SVDB2 processed so as to leave only a plurality of strip-like images corresponding to odd-numbered dot rows that can be specified by odd addresses remains, this grid-like processed image The SVDB2 is transferred to the area RGNB of the frame buffer MVD shown in FIG.

  The sound source built-in VDP 4160a is a large original image SVDC0 for drawing in the display area of the movable liquid crystal display device 1925c created in the frame buffer SVDC (the large original image SVDC0 has a size of horizontal width: 360 dots and vertical width: 204 dots). Is transferred to the frame buffer SVDA and arranged at the same position as the large original images SVDA0 and SVDB0, and the horizontal width of the large original image SVDC0: from the first column constituting 360 dots to the last column By performing a process of sequentially stretching the original image SVDC0 by two columns (that is, doubled), the large image SVDC0 is stretched by a factor of two in the horizontal direction (leftward in FIG. 32D). An image SVDC1 is created. By executing again the enlargement processing performed when creating the enlarged images SVDA1 and SVDB1 from the large original images SVDA0 and SVDB0, the enlarged image SVDC1 is created from the large original image SVDC0 in the frame buffer SVDA. As a result, the original image SVDC0 has a horizontal width of 360 dots, and the process of extending the original image sequentially from the first column to the last column in two columns (that is, twice) is performed again. Width of image SVDC0: If one column is extended from the first column to the last column constituting 360 dots to two columns, one column is not overwritten by the two expanded columns, and the other columns following the one column If one of the columns is extended by two, one column is overwritten by the two extended columns, and when the last column of the large original image SVDC0 is extended to two columns, the two expanded columns are larger. By overwriting the last column of the original image SVDC0, the large original image SVDC0 stored in the frame buffer SVDA is extended and the large original image SVDC0 is deleted from the frame buffer SVDA. Together are generating stretched images SVDC1 (i.e., while deleting the Omoto image SVDC0 by stretching the Omoto image SVDC0 stored in the frame buffer SVDA from the frame buffer SVDA). As described above, this extension is performed by extracting character data from the liquid crystal and sound control ROM 4160b based on the screen data from the peripheral control MPU 4150a when the sound source built-in VDP 4160a creates the large original image MVD0 or the large original image SVDC0. Then, it is executed by the same command as the command that created the sprite data by scaling. The VDP 4160a with built-in tone generator performs mask processing performed when creating the grid-processed images SVDA2 and SVDB2 in order to remove the image in the portion corresponding to the even address of the frame buffer SVDA from the extended image SVDC1 created by the frame buffer SVDA. When the lattice-like processed image SVDC2 processed so as to leave only a plurality of strip-like images corresponding to the odd-numbered dot rows that can be specified by the odd-numbered addresses is created by performing the processing again, The processed image SVDC2 is transferred to the region RGNC of the frame buffer MVD shown in FIG.

  The sound source built-in VDP 4160a is a large original image SVDD0 for drawing in the display area of the movable liquid crystal display device 1925c created in the frame buffer SVDD (the large original image SVDD0 has a size of horizontal width: 360 dots, vertical width: 204 dots). Is transferred to the frame buffer SVDA and arranged at the same position as the large original images SVDA0, SVDB0, SVDC0, and the horizontal width of the large original image SVDD0: from the first column constituting 360 dots to the last By performing a process of extending the original image SVDD0 in the horizontal direction (leftward in FIG. 32 (d)) by executing the process of sequentially extending the data to each column in two columns (that is, twice). A stretched image SVDD1 is created. The frame buffer SVDA creates an image SVDD1 that is enlarged from the original image SVDD0 by performing again the enlargement processing performed when the enlarged images SVDA1, SVDB1, and SVDC1 are created from the large original images SVDA0, SVDB0, and SVDC0. As a result, the original image SVDD0 has a horizontal width of 360 dots, and the process of extending the original image sequentially from the first column to the last column in two columns (that is, twice) is performed again. Width of the image SVDD0: When one column of the first column to the last column constituting 360 dots is extended to two columns, one column is not overwritten by the two extended columns, and the other columns following the one column are not overwritten. If any one of the columns is extended by two columns, one column is overwritten by the two extended columns, and if the last column of the large original image SVDD0 is extended to two columns, the two expanded columns are larger. By overwriting the last column of the original image SVDD0, the large original image SVDD0 stored in the frame buffer SVDA is extended and the large original image SVDD0 is deleted from the frame buffer SVDA. Together are generating stretched images SVDD1 (i.e., while deleting the Omoto image SVDD0 by stretching the Omoto image SVDD0 stored in the frame buffer SVDA from the frame buffer SVDA). As described above, this extension is performed by extracting character data from the liquid crystal and sound control ROM 4160b based on the screen data from the peripheral control MPU 4150a when the sound source built-in VDP 4160a creates the large original image MVD0 or the large original image SVDD0. Then, it is executed by the same command as the command that created the sprite data by scaling. The sound source built-in VDP 4160a is executed when creating the grid-processed images SVDA2, SVDB2, and SVDC2 in order to remove the image in the portion corresponding to the even address of the frame buffer SVDA from the stretched image SVDD1 created by the frame buffer SVDA. By performing the mask processing again, a grid-like processed image SVDD2 that is processed into a grid so that only a plurality of strip-like images corresponding to odd-numbered dot rows that can be specified by odd-numbered addresses remains is created. The grid-processed image SVDD2 is transferred to the region RGND of the frame buffer MVD shown in FIG.

  In this way, in the display data creation processing, when drawing data for the game board side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output board 3420 is created in the frame buffer MVD, subsequently, in this frame buffer MVD, Since drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted from the odd channel to the liquid crystal output substrate 3420 is created, the game board side liquid crystal display device 1900 transmitted to the liquid crystal output substrate 3420 from the even channel. FIG. 32 (h) shows the drawing data for the image data and the drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted from the odd channels to the liquid crystal output board 3420 in the same frame buffer called the frame buffer MVD. Like Images in which the grid-like processed image MVD2 shown in FIG. 32C and the grid-like processed image SVD2 shown in FIG. 32G are alternately arranged without interfering with each other (in other words, FIG. 32C). And the comb teeth of the grid pattern processed image MVD2 shown in FIG. 32 (g) and the comb teeth of the grid pattern processed image SVD2 shown in FIG. The image drawing data generated and held in the frame buffer MVD in this way is generated and held in the frame buffer MVD in the display data output process in step S1016 described above when the next peripheral control unit steady process is executed. The drawing data of one screen (one frame) to be drawn on the screens of the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d is read out of the drawing data generated and held in the frame buffer MVD In addition, control for outputting (transmitting) drawing data for the game board side liquid crystal display device 1900 from the even channel of channel CH1 to the game board side liquid crystal display device 1900 via the liquid crystal output substrate 3420 is performed for the built-in sound source VDP 4160a. Drawing on movable liquid crystal display devices 1925a to 1925d Is output to the movable liquid crystal display devices 1925a to 1925d via the liquid crystal output substrate 3420 from the odd channel of the channel CH1 to the built-in sound source VDP 4160a (that is, output from the even channel of the channel CH1). (Transmission) and output (transmission) from the odd channel of channel CH1 are performed simultaneously). Note that the peripheral control MPU 4150a, for example, executes the current peripheral control unit steady process this time for one screen (one frame) to be drawn on the screen of the upper plate side liquid crystal display device 470 with one frame buffer of the built-in VRAM. When the next drawing data is generated and held, the upper side liquid crystal generated and held in one frame buffer in the display data output process in step S1016 described above when the next peripheral control unit steady process is executed. The drawing data for one screen (one frame) to be drawn on the screen of the display device 470 is read, and the drawing data for the upper plate side liquid crystal display device 470 is sent from the channel CH2 to the frame peripheral relay terminal plate 868 and the peripheral door relay terminal. The upper plate side liquid crystal surface is displayed through the plate 882 and the touch panel drive substrate 450 housed in the plate unit 300 of the door frame 5. A control output to device 470 (transmission) performed on the sound source built VDP4160a.

  Subsequent to step S1030, the effect control program performs touch panel processing (step S1031). In this touch panel process, the effect control program performs touch detection control of the capacitive touch panel 480 provided so as to cover the display area of the upper dish side liquid crystal display device 470 shown in FIG. Is a process of exchanging (transmitting and receiving) control commands and various information (various data). For example, as a control command, a detection control start command for starting detection control of the touch state of the touch panel 480, a contact position data request command for requesting a position where the finger touches the touch panel 480 (contact position data), There is a power saving mode shift command for shifting to the power mode. The effect control program acquires the coordinate value of the contact surface of the touch panel 480 indicating the center of the contact portion touched by the finger based on the contact position data from the touch panel drive substrate 450, and the position represented by the coordinate value is obtained. It is specified as a detection point (detection point acquisition means). In addition, this effect control program may acquire not only such coordinate values but also a range of the contact surface (hereinafter referred to as a contact range).

  Subsequent to step S1031, the effect control program performs sound data creation processing (step S1032). In the sound data creation process, the effect control program updates the pointer in the scheduler update process in step S1020, and the pointer indicates the sound command data arranged in time series constituting the sound generation schedule data. The sound command data is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c and output to the sound source built-in VDP 4160a. When sound command data is input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a extracts sound data such as music and sound effects stored in the liquid crystal and sound control ROM 4160b and controls the sound source by controlling the sound source. In addition to incorporating sound data such as music and sound effects according to the track number defined in the data, an output channel to be used is set according to the output channel number.

  In the sound data creation process, every time this sound data creation process is performed (that is, every time the peripheral control unit steady process is performed), the peripheral control A / D converter 4150ak shown in FIG. The voltage divided by the resistance value at the rotation position of the knob portion of 4140a is converted into a value of 1024 steps from 0 to 1023. In this embodiment, the value of 1024 steps is divided into seven and managed as substrate volumes 0 to 6, and the sound volume is set to the substrate volume 0, the maximum volume is set to the substrate volume 6, and the substrate volume 0 to the substrate volume are set. Each volume is set to increase toward the volume 6. By controlling the liquid crystal and the built-in sound source VDP 4160a of the sound control unit 4160 so that the volume is set to the substrate volume 0 to 6, audio data is obtained as audio data obtained by serializing the sound data in the sound data output process of step S1018 described above. By outputting to the transmission IC 4160 c, music and sound effects flow from the speakers housed in the speaker box 820 provided in the main body frame 3 and the speakers 130 provided in the door frame 5.

  In addition, the notification sound and the notification sound flow without depending on the volume adjustment based on the turning operation of the knob part. The built-in VDP 4160a can be controlled and adjusted. The volume adjusted by this program can be smoothly changed from the mute to the maximum volume, unlike the substrate volume divided into the above seven stages. For example, even when a store clerk or the like of the hall rotates the knob portion of the volume adjustment volume 4140a to set the volume to a low level, the hall and the door frame 5 are accommodated in the speaker box 820 provided in the main body frame 3. Although the production sound such as music and sound effects flowing from the provided speaker 130 is reduced, when the malfunction occurs in the pachinko gaming machine 1 or when the player is cheating, the volume is high (in this embodiment, The notification sound set to (maximum volume) can be played. Therefore, even if the volume of the production sound is reduced, it is possible to prevent the hall clerk or the like from becoming difficult to notice the occurrence of a malfunction or the player's cheating due to the notification sound. Also, based on the current board volume set by volume adjustment based on the turning operation of the knob part, the volume of the advertisement sound is reduced so as not to interfere with the music and sound effects. In addition to music and sound effects, the screen unfolded by the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 is made more powerful. It is also possible to produce an announcement or to announce that there is a high possibility of shifting to a gaming state advantageous to the player.

  Subsequent to step S1032, the effect control program performs backup processing (step S1034). In this backup process, the effect control program stores the contents stored in the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. 16 into the backup first area 4150cb and the backup second area 4150cc. The contents are copied and backed up, and the contents stored in the peripheral control SRAM 4150d attached to the peripheral control MPU 4150a are copied and backed up in the backup first area 4150db and the backup second area 4150dc, respectively.

  Specifically, in the backup process, the peripheral control RAM 4150c is backed up every frame (1 frame) in the backup target work area 4150ca shown in FIG. 16, that is, every time the peripheral control unit steady process is executed. Included in Bank 0 (1fr), lamp drive board side transmission data storage area 4150caa, frame decoration drive amplifier board side LED transmission data storage area 4150cab, reception command storage area 4150cac, RTC information acquisition storage area 4150cad, and The production information (1fr), which is the content stored in the schedule data storage area 4150cae, is used as production backup information (1fr), and Bank1 (1fr) and Bank2 (1f) of the backup first area 4150cb. Peripheral control DMA controller 4150ac in) is copied at high speed, and backup Bank3 second area 4150cc (1fr) and peripheral control DMA controller 4150ac to Bank4 (1FR) is copied at high speed.

  The high-speed copy of the contents stored in Bank0 (1fr) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. The content stored in Bank0 (1fr) is designated to be copied to Bank1 (1fr) in the backup first area 4150cb, and the content stored in the first address of Bank0 (1fr) is changed to the end address of Bank0 (1fr) The stored contents are all copied in sequence starting from the first address of Bank 1 (1fr) in the backup first area 4150cb in succession by a predetermined number of bytes (for example, 1 byte), and the peripheral control MPU core 4150aa performs peripheral control D The content stored in Bank0 (1fr) is designated as the request factor of the A controller 4150ac, the copy to Bank2 (1fr) of the backup first area 4150cb is designated, and the content stored in the first address of Bank0 (1fr) is used as Bank0 The contents stored at the end address of (1fr) are all copied in order from the start address of Bank2 (1fr) in the backup first area 4150cb in succession by a predetermined number of bytes (for example, 1 byte).

  Subsequently, the peripheral control MPU core 4150aa designates the content stored in Bank0 (1fr) as the request factor of the peripheral control DMA controller 4150ac, specifies the copy of the backup second area 4150cc to Bank3 (1fr), and Bank0 (1fr) ) To the content stored at the end address of Bank0 (1fr) to the content stored at the end address of Bank0 (1fr), the first address of Bank3 (1fr) in the backup second area 4150cc continuously by a predetermined byte (for example, 1 byte) The peripheral control MPU core 4150aa specifies the contents stored in Bank0 (1fr) as the request factor of the peripheral control DMA controller 4150ac, and specifies that the backup second area 4150cc is copied to Bank4 (1fr). Shi From the content stored at the beginning address of Bank0 (1fr) to the content stored at the end address of Bank0 (1fr), bank 4 (1fr) in the backup second area 4150cc is continuously provided by a predetermined number of bytes (for example, 1 byte). Copy everything starting from the first address.

  In the backup process, the peripheral control SRAM 4150d is a backup target every frame (1 frame) in the backup target work area 4150da shown in FIG. 16, that is, every time the peripheral control unit steady process is executed. The peripheral control DMA controller 4150ac operates at high speed in the bank 1 (SRAM) and the bank 2 (SRAM) of the backup first area 4150db by using the production information (SRAM) stored in the Bank 0 (SRAM) as production backup information (SRAM). The peripheral control DMA controller 4150ac copies the data to the bank 3 (SRAM) and the bank 4 (SRAM) in the backup second area 4150dc at high speed.

  The high-speed copy of the contents stored in Bank 0 (SRAM) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. The content stored in Bank0 (SRAM) is designated to be copied to Bank1 (SRAM) in backup first area 4150db, and the content stored at the beginning address of Bank0 (SRAM) is changed to the end address of Bank0 (SRAM). The stored contents are all copied in sequence starting from the first address of Bank 1 (SRAM) in the backup first area 4150db in order of predetermined bytes (for example, 1 byte), and the peripheral control MPU core 4150aa The content stored in Bank0 (SRAM) as the request factor of the peripheral control DMA controller 4150ac, the copy to the Bank2 (SRAM) of the backup first area 4150db is designated, and the content stored in the first address of Bank0 (SRAM) To the contents stored at the end address of Bank 0 (SRAM) are copied in order from the start address of Bank 2 (SRAM) in the backup first area 4150 db in succession by a predetermined number of bytes (for example, 1 byte).

  Subsequently, the peripheral control MPU core 4150aa designates the contents stored in the Bank 0 (SRAM) as the request factor of the peripheral control DMA controller 4150ac, specifies the copy of the backup second area 4150dc to the Bank 3 (SRAM), and the Bank 0 (SRAM). ) To the content stored at the end address of Bank0 (SRAM) to the content stored at the end address of Bank0 (SRAM) by a predetermined number of bytes (for example, 1 byte) continuously, the top address of Bank3 (SRAM) in backup second area 4150dc The peripheral control MPU core 4150aa copies the contents stored in the bank 0 (SRAM) as the request factor of the peripheral control DMA controller 4150ac to the bank 4 (SRAM) of the backup second area 4150dc. P2 is specified, and the content stored in the bank 0 (SRAM) start address to the content stored in the bank 0 (SRAM) end address is continuously backed up by a predetermined byte (for example, 1 byte) in a second backup area 4150dc. Are all copied in order from the top address of Bank 4 (SRAM).

  Subsequent to step S1034, WDT clear processing is performed (step S1036). In this WDT clear processing, a clear signal is output to the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e so that the peripheral control MPU 4150a is not reset.

  Subsequent to step S1036, the effect control program sets the value 0 in the steady processing flag SP-FLG as completion of execution of the peripheral control unit steady processing (step S1038), returns to step S1006 again, and V blank signal detection flag VB -FLG is initialized by setting value 0, and the determination in step S1008 is repeated until value 1 is set in V blank signal detection flag VB-FLG in the peripheral control unit V blank signal interrupt processing described later. That is, in step S1008, the process waits until a value 1 is set in the V blank signal detection flag VB-FLG. If it is determined in step S1008 that the V blank signal detection flag VB-FLG is 1, the process proceeds from step S1009 to step S1009. The process of S1038 is performed, and the process returns to step S1006 again. As described above, when it is determined in step S1008 that the V blank signal detection flag VB-FLG has a value of 1, processing in steps S1009 to S1038 is performed. The processing in steps S1009 to S1038 is referred to as “peripheral control unit steady processing”.

  The peripheral control unit steady process starts from the fact that the effect control program first sets the value 1 in the steady processing flag SP-FLG, assuming that the peripheral control unit steady process is being executed in step S1009, and 1 ms in step S1010. An interrupt timer activation process is performed, and each process of steps S1012, S1014,..., And step S1036 is performed. Set to to complete. The peripheral control unit steady process is executed when the V blank signal detection flag VB-FLG is 1 in step S1008. As described above, the V blank signal detection flag VB-FLG is executed when the V blank signal that indicates that the screen data from the peripheral control MPU 4150a can be received is input from the sound source built-in VDP 4160a. The value 1 is set in the peripheral control unit V blank signal interrupt processing described later. In this embodiment, as described above, the frame frequency (number of screen updates per second) of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 is approximately seconds as described above. Since it is set to 30 fps, the interval at which the V blank signal is input is about 33.3 ms (= 1000 ms ÷ 30 fps). That is, the peripheral control unit steady process is repeatedly executed about every 33.3 ms.

[17-1-2. Peripheral control unit V blank signal interrupt processing]
Next, a V blank signal indicating that the screen data from the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 can be received is input from the VDP 4160a with built-in sound source of the liquid crystal and sound control unit 4160. The peripheral control unit V blank signal interrupt processing executed with this as an opportunity will be described. When the peripheral control unit V blank signal interrupt processing is started, the peripheral control MPU 4150a of the peripheral control unit 4150 determines whether the steady processing flag SP-FLG is 0 as shown in FIG. S1045). As described above, the steady processing flag SP-FLG has a value of 1 when the peripheral control unit steady processing in steps S1009 to S1038 in the peripheral control unit power-on processing of FIG. It is set to a value of 0 when execution of the process is completed.

  If the steady process flag SP-FLG is not 0 (value 1) in step S1045, that is, if the peripheral control unit steady process is being executed, this routine is terminated. On the other hand, when the steady processing flag SP-FLG is 0 in step S1045, that is, when the execution of the peripheral control unit steady processing is completed, the value 1 is set to the V blank signal detection flag VB-FLG (step S1050). This routine ends. As described above, the V blank signal detection flag VB-FLG is a flag for determining whether or not to execute the peripheral control unit steady process. When the part steady process is not executed, the value is set to 0.

  In this embodiment, it is determined in step S1045 whether or not the steady processing flag SP-FLG is 0, that is, whether or not the peripheral control unit steady processing has been completed, and the peripheral control unit steady processing has been completed. Sometimes the value 1 is set to the V blank signal detection flag VB-FLG in step S1050. This is because the V blank signal is input and the V blank signal is input when the peripheral control unit steady processing is being executed. When the value 1 is set to the signal detection flag VB-FLG, it is assumed that the peripheral control unit steady process is executed in step S1008 in the peripheral control unit power-on process of FIG. Since the peripheral control unit steady processing is started from the beginning by forcibly canceling in the middle, the peripheral control unit in FIG. 64 is turned on for the purpose of preventing this. The peripheral control unit V blank signal, which is this routine, indicates that the peripheral control unit steady processing is being executed by setting the value 1 to the steady processing flag SP-FLG in step S1009 in the processing (peripheral control unit steady processing). In addition to notifying the interrupt processing, the peripheral control portion steady processing is completed by setting the steady processing flag SP-FLG to 0 in step S1038 in the peripheral control portion power-on processing (peripheral control portion steady processing) of FIG. This is communicated to the peripheral control unit V blank signal interrupt process, which is this routine, so that the steady processing flag SP-FLG is 0 in the determination of step S1045 in the peripheral control unit V blank signal interrupt process, which is this routine. It is determined whether or not there is, that is, whether or not the peripheral control unit steady process has been executed. In other words, this is a measure for the case where the peripheral control unit steady-state processing cannot be completed before the next V blank signal is input and the next V blank signal is input, so-called processing failure.

  As a result, in the current peripheral control unit steady process, if the process cannot be completed in about 33.3 ms and the process is dropped, the next determination is made in step S1008 in the peripheral control unit power-on process of FIG. It is in a state of waiting until the V blank signal is input. That is, the time required to execute the current peripheral control unit steady process that has been dropped is about 66.6 ms. Normally, a peripheral control unit 1 ms timer interrupt process, which will be described later, is repeatedly executed every time a 1 ms interrupt timer is generated by starting the 1 ms interrupt timer in step S1010 of the peripheral control unit power-on process (peripheral control unit steady process) in FIG. Is executed only 32 times for one peripheral control unit steady process. However, if there is a current peripheral control unit steady process that has been dropped as described above, the peripheral control unit 1 ms timer interrupt process is not performed 64 times. No, it is executed only 32 times. In other words, even if the peripheral control unit steady process has failed, the consistency between the presentation progress state by the peripheral control unit steady process and the presentation progress state by the peripheral control unit 1 ms timer interrupt process, which is timer interrupt control, is consistent. It is designed not to collapse. Therefore, even if the peripheral control unit steady process is lost, it is possible to reliably match the progress state of the performance.

[17-1-3. Peripheral control unit 1ms timer interrupt processing]
Next, the peripheral control unit 1 ms timer interrupt process that is repeatedly executed every time the 1 ms interrupt timer is generated by starting the 1 ms interrupt timer in step S1010 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. 64 will be described. . When this peripheral control unit 1 ms timer interrupt process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 determines whether the 1 ms timer interrupt execution count STN is smaller than 33 times as shown in FIG. Is determined (step S1100). As described above, this 1 ms timer interrupt execution count STN is determined by this routine when the 1 ms interrupt timer is activated in the 1 ms interrupt timer activation process of step S1010 in the peripheral control unit steady process of the peripheral control unit power-on process of FIG. It is a counter that counts the number of times a peripheral control unit 1 ms timer interrupt process is executed. In this embodiment, as described above, the frame frequency (number of screen updates per second) of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 is approximately seconds as described above. Since it is set to 30 fps, the interval at which the V blank signal is input is about 33.3 ms (= 1000 ms ÷ 30 fps). That is, since the peripheral control unit steady process is repeatedly executed about every 33.3 ms, after starting the 1 ms interrupt timer in step S1010 in the peripheral control unit steady process, the next peripheral control unit steady process is performed. The peripheral control unit 1 ms timer interrupt process is executed only 32 times before. Specifically, when the 1 ms interrupt timer is started in step S1010 in the peripheral control unit steady process, the first 1 ms timer interrupt is generated first, then the second,... Will occur.

  When the 1 ms timer interrupt execution count STN is not smaller than 33 times in step S1100, that is, when the 33 ms 1 ms timer interrupt is generated and the peripheral control unit 1 ms timer interrupt processing is started, this routine is ended as it is. In the present embodiment, when the 33rd 1 ms timer interrupt occurs accidentally before the next generation of the V blank signal, in the present embodiment, the peripheral control unit 1 ms timer interrupt process is the peripheral control unit V as the priority of interrupt processing. Although set higher than the blank interrupt process, the start of the peripheral control unit 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. In other words, in the present embodiment, the V blank signal is a signal that dominates the entire system of the peripheral control board 4140. Therefore, when the occurrence of the 1st timer interrupt for the 33rd time happens to precede the generation of the next V blank signal. In order to execute the peripheral control unit V blank interrupt process, the start of the peripheral control unit 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. Then, after the 1 ms interrupt timer is started again in step S1010 in the peripheral control unit steady process due to the generation of the V blank signal, the peripheral control unit 1 ms timer interrupt process is newly started by the first 1 ms timer interrupt generation. ing.

  On the other hand, when the 1 ms timer interrupt execution count STN is smaller than 33 in step S1100, the value 1 is added to the 1 ms timer interrupt execution count STN (increment, step S1102). By adding 1 to this 1 ms timer interrupt execution count STN, the 1 ms interrupt timer is activated in the 1 ms interrupt timer activation process in step S1010 in the peripheral control unit steady process of the peripheral control unit power-on process in FIG. The number of times that the peripheral control unit 1 ms timer interrupt process, which is this routine, is executed is increased by one.

  Subsequent to step S1102, motor and solenoid drive processing is performed (step S1104). In this motor and solenoid drive processing, the electric drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MP4150a and the externally attached peripheral control RAM 4150c shown in FIG. 16 are arranged in time series. According to the drive data indicated by the pointer among the drive data of the electrical drive sources such as the motor and the solenoid, the electrical drive sources such as the motor and the solenoid of the frame decoration drive amplifier board 194 and the motor drive board 4180 shown in FIG. In addition to driving an electric drive source called two stepping motors (total of eight stepping motors) provided in each of the movable devices 1925aa, 1925ba, 1925ca, and 1925da shown in FIG. Pointer to the driving data New, each time you run the motor and the solenoid driving processing, and updates the pointer.

  Specifically, in the motor and solenoid drive processing, for example, DMA serial continuous transmission processing to the frame decoration drive amplifier board 194 is performed. Here, the frame I / O port motor serial I / O port continuous transmission is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. When this frame decoration drive amplifier board motor serial I / O port continuous transmission starts, first, the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the externally attached peripheral control RAM 4150c is stored. A drive signal to the dial drive motor 414 of the operation unit 400 shown in FIG. 7 based on drive data indicated by a pointer among drive data of electric drive sources such as motors and solenoids arranged in time series. 16 is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c, and the peripheral control RAM 4150c shown in FIG. Frame decoration It is set to send a dynamic amplifier board-side motor data storage area 4150Caf. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates transmission of the frame decoration drive amplifier board motor serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and stores frame decoration drive amplifier board side motor transmission data. Frame decoration drive amplifier board motor via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai with the first byte of the door side motor drive data STM-DAT stored in the head address of the area 4150caf Transfer and write to the transmission buffer register of the serial I / O port. As a result, the frame decoration drive amplifier board motor serial I / O port transfers the written data of the transmission buffer register to the transmission shift register, and synchronizes with the door side motor drive clock signal STM-CLK. The 1-byte data starts to be transmitted bit by bit.

  The peripheral control DMA controller 4150ac is triggered every time a transmission interrupt request for the frame decoration drive amplifier board motor serial I / O port is generated (in this embodiment, the frame decoration drive amplifier board motor serial I / O 1 byte data written in the transmission buffer register of the port is transferred to the transmission shift register, and the transmission buffer register is empty because the 1 byte data disappears.), Peripheral control CPU core 4150aa When the bus does not use the bus, the remaining door side motor drive data STM-DAT stored in the frame decoration drive amplifier board side motor transmission data storage area 4150caf is stored byte by byte, external bus 4150h, peripheral control bus controller 4150ad, and via peripheral bus 4150ai, By transferring and writing to the transmission buffer register of the decorative drive amplifier board motor serial I / O port, the frame decoration drive amplifier board motor serial I / O port transmits the data of the written transmission buffer register to the transmission shift register. 1 byte data of the transmission shift register is started bit by bit in synchronization with the door side motor drive clock signal STM-CLK, and the frame decoration drive amplifier board motor serial I / O port continuously transmits. Is going.

  In the motor and solenoid drive processing, for example, DMA serial continuous transmission processing to the motor drive board 4180 is performed. Also here, serial transmission of the motor drive board serial I / O port is performed using the peripheral control DMA controller 4150ac of the peripheral control MPU 4150a shown in FIG. When the serial I / O port continuous transmission for the motor drive board is started, first, when configuring the electrical drive source schedule data set in the schedule data storage area 4150cae of the peripheral control MPU 4150a and the peripheral control RAM 4150c attached externally A motor for moving various movable bodies provided in the game board 4 shown in FIG. 8 based on drive data indicated by a pointer among drive data of electric drive sources such as motors and solenoids arranged in series. The game board side motor drive data SM-DAT for outputting the drive signal to the solenoid and the solenoid is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c and created. Peripheral control RAM 415 shown in FIG. Set to the motor drive board side transmission data storage area 4150cag of c. The peripheral control CPU core 4150aa of the peripheral control MPU 4150a designates transmission of the motor drive board serial I / O port as a request factor of the peripheral control DMA controller 4150ac, and stores it in the head address of the motor drive board side transmission data storage area 4150cag. The first 1 byte of the game board side motor drive data SM-DAT thus obtained is transmitted to the serial I / O port for the motor drive board via the external bus 4150h, the peripheral control bus controller 4150ad, and the peripheral bus 4150ai. Transfer and write to register. As a result, the serial I / O port for the motor drive board transfers the written data of the transmission buffer register to the transmission shift register, and 1 of the transmission shift register is synchronized with the game board side motor drive clock signal SM-CLK. Start transmitting byte data bit by bit.

  The peripheral control DMA controller 4150ac is triggered by the transmission interrupt request for the motor drive board serial I / O port (in this embodiment, in the transmission buffer register of the motor drive board serial I / O port). The written 1-byte data is transferred to the transmission shift register, and the transmission buffer register is empty because the 1-byte data disappears.), The peripheral control CPU core 4150aa is using the bus. If not, the remaining game board side motor drive data SM-DAT stored in the motor drive board side transmission data storage area 4150cag is transferred byte by byte via the external bus 4150h, peripheral control bus controller 4150ad, and peripheral bus 4150ai. , Serial I / O port for motor drive board By transferring and writing to the transmission buffer register, the motor drive board serial I / O port transfers the written data of the transmission buffer register to the transmission shift register, and the game board side motor drive clock signal SM-CLK and Synchronously, transmission of 1-byte data of the transmission shift register is started bit by bit, and continuous transmission is performed by the serial I / O port for the motor drive board.

  Following step S1104, movable body information acquisition processing is performed (step S1106). In this movable body information acquisition process, it is determined whether or not detection signals from various detection switches provided on the game board 4 are input, thereby history information (for example, original position history information) of detection signals from the various detection switches. , The movable position history information, etc.) is created and set in the movable body information acquisition storage area 4150cah of the peripheral control MPU 4150a and the peripheral control RAM 4150c externally shown in FIG. From the history information of the detection signals from the various detection switches set in the movable body information acquisition storage area 4150cah, the original positions and the movable positions of the various movable bodies provided on the game board 4 can be acquired.

  Subsequent to step S1106, an operation unit information acquisition process is performed (step S1108). In this operation unit information acquisition process, it is determined whether or not detection signals from various detection switches provided in the operation unit 400 are input, whereby history information of detection signals from various detection switches (for example, a dial operation unit) Rotation (rotation direction) history information 401, operation history information of the pressing operation unit 405, etc.) is created, and the operation unit information acquisition storage area of the peripheral control MPU 4150a and the peripheral control RAM 4150c externally shown in FIG. Set to 4150cai. The rotation direction of the dial operation unit 401 and the presence / absence of the operation of the pressing operation unit 405 can be acquired from history information of detection signals from various detection switches set in the operation unit information acquisition storage area 4150cai.

  Following step S1108, drawing state information acquisition processing is performed (step S1110). In this drawing state information acquisition process, the history information of the LOCKN signal output from the LOCKN terminal of the receiver ICSDIC0 for the upper plate side liquid crystal provided in the touch panel drive substrate 450 shown in FIG. 36 is created, and the peripheral control shown in FIG. It is set in the drawing state information acquisition storage area 4150cak of the MPU 4150a and the peripheral control RAM 4150c attached externally. As described above, the LOCKN signal determines that the drawing data received from the upper plate-side liquid crystal transmitter IC 4160d included in the peripheral control substrate 4140 by the upper-plate-side liquid crystal receiver ICSDIC0 included in the touch panel drive substrate 450 is abnormal data. Then, it is a signal that is output to convey that fact, specifically, an upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 and an upper plate side liquid crystal receiver IC SDIC0 provided in the touch panel drive board 450, This signal is output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection between the connections, that is, the connection between the transmitter and the receiver. The upper dish side liquid crystal display device 470 acquires the frequency of defects and the occurrence state of defects between the connection between the peripheral control board 4140 and the touch panel drive board 450 from the history information of the LOCKN signal set in the drawing state information acquisition storage area 4150cak. The drawing state can be acquired.

  Subsequent to step S1110, a main winning ball number information output process is performed (step S1112). In the main prize ball number information output process, when the schedule data for the main prize ball information output signal set in the schedule data storage area 4150cae of the peripheral control RAM 4150c and the peripheral control RAM 4150c externally shown in FIG. Output waveform data for generating a main prize ball information output signal that informs the hall computer as main prize ball information that the number of game balls to be paid out as a prize ball has reached 10 balls arranged in a series The main prize ball information output signal is output to the external terminal board 784 shown in FIG. 30 according to the output waveform data indicated by the pointer, and the pointer is updated to the next output waveform data defined in time series. Each time the main prize ball number information output process is executed, the pointer is updated.

  Subsequent to step S1112, power consumption status history information creation processing is performed (step S1113). In this power consumption status history information creation processing, the value (power consumption suppression stage) transmitted by the power consumption suppression signal from the power supply board 851 is sampled and the power consumption of the peripheral control unit 4150 shown in FIG. Sequentially stored in the status history RAM 4150f. As described above, the power consumption suppression signal is output from the power consumption monitoring circuit 855da. As shown in FIG. 19A, the power consumption monitoring circuit 855da includes a power measurement circuit 855daa and a power consumption suppression stage determination circuit 855dab. + 37V supplied from the smoothing circuit 855c is supplied to the + 5V power generation circuit 855db, the + 12V power generation circuit 855dc, and the + 24V power supply generation circuit 855dd via the power measurement circuit 855daa. The power measurement circuit 855daa measures the power consumption of + 37V supplied from the smoothing circuit 855c in real time and outputs it to the power consumption suppression stage determination circuit 855dab. The power consumption suppression stage determination circuit 855dab determines a power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption measured by the power measurement circuit 855daa. By setting the value of the power consumption suppression signal configured as a signal wiring and outputting it to the frame peripheral relay terminal plate 868, the power consumption suppression signal is input to the peripheral control unit 4150 via the frame peripheral relay terminal plate 868. It has come to be. As described above, the power consumption suppression signal is configured as three signal wirings (that is, configured as three parallel signals), and transmits eight values from 0 to 7. Can be done.

  As described above, the power consumption suppression stage determination circuit 855dab determines that it is stage 0 as the power consumption suppression stage when the power consumption of + 37V measured by the power measurement circuit 855daa is 0% or more and less than 10%. When the value of 0 is set as the value of the suppression signal and the power consumption of + 37V measured by the power measurement circuit 855daa is 10% or more and less than 20%, it is determined as stage 1 as the power consumption suppression stage and the power consumption suppression signal The value 1 is set as the value, and when the power consumption of +37 V measured by the power measuring circuit 855daa is 20% or more and less than 30%, it is determined as the stage 2 as the power consumption suppression stage and the value as the value of the power consumption suppression signal 2 and when the power consumption of + 37V measured by the power measurement circuit 855daa is 30% or more and less than 40%, When the power consumption suppression signal is determined to be stage 3 as the suppression stage and the value 3 is set as the value of the power consumption suppression signal and the power consumption of +37 V measured by the power measurement circuit 855daa is 40% or more and less than 50%, the power consumption suppression stage When the power consumption suppression signal is determined to be step 4 and the value 4 is set as the value of the power consumption suppression signal and the power consumption of + 37V measured by the power measurement circuit 855daa is 50% or more and less than 60%, the power consumption suppression step is performed in step 5 If a value 5 is set as the value of the power consumption suppression signal after determination and the power consumption of +37 V measured by the power measurement circuit 855daa is 60% or more and less than 70%, it is determined that the power consumption suppression stage is stage 6. When the value 6 is set as the value of the power consumption suppression signal, the power consumption of +37 V measured by the power measurement circuit 855daa is 70% or more. It is adapted to set the value 7 as the value of the power consumption suppression signal to determine a phase 7 as a power consumption inhibiting step for.

  Thus, in the power consumption status history information creation process, every time this routine is executed, that is, every 1 ms, the value (value 0 to value 7) transmitted by the power consumption suppression signal from the power supply board 851 is sampled. By sequentially storing in the power consumption status history RAM 4150f of the peripheral control unit 4150 as the power consumption suppression steps (step 0 to step 7), the power consumption suppression steps are arranged as power consumption status history information in time series.

  Subsequent to step S1113, backup processing is performed (step S1114), and this routine is terminated. In this backup processing, the contents stored in the peripheral control MPU 4150a and the externally attached peripheral control RAM 4150c shown in FIG. 16 are copied to the backup first area 4150cb and the backup second area 4150cc, respectively. At the same time, the contents stored in the peripheral control MPU 4150a and the externally attached peripheral control SRAM 4150d are copied to the backup first area 4150db and the backup second area 4150dc for backup.

  Specifically, in the backup process, the peripheral control RAM 4150c executes the peripheral control unit 1ms timer interrupt process, which is this routine, every time the 1ms interrupt timer is generated in the backup target work area 4150ca shown in FIG. Each time, the frame decoration drive amplifier board-side motor transmission data storage area 4150caf, the motor drive board-side transmission data storage area 4150cag, and the movable body information acquisition storage area 4150cah included in Bank0 (1 ms) to be backed up. The production information (1 ms), which is the content stored in the operation unit information acquisition storage area 4150cai, is used as production backup information (1 ms), and Bank 1 (1 ms) and Bank 2 (1) of the backup first area 4150 cb Peripheral control DMA controller 4150ac in s) is copied at high speed, and backup Bank3 second area 4150cc (1ms) and peripheral control DMA controller 4150ac to Bank4 (1 ms) is copied at high speed.

  The high-speed copy of the contents stored in Bank 0 (1 ms) by the peripheral control DMA controller 4150ac will be briefly described. The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. The content stored in Bank0 (1 ms) is designated to be copied to Bank1 (1 ms) in backup first area 4150cb, and the content stored at the beginning address of Bank0 (1 ms) is changed to the end address of Bank0 (1 ms). The stored contents are all copied in sequence starting from the first address of Bank 1 (1 ms) in the backup first area 4150cb in succession to a predetermined byte (for example, 1 byte), and the peripheral control MPU core 4150aa performs peripheral control D. The content stored in Bank 0 (1 ms) as the request factor of the A controller 4150ac is designated to be copied to Bank 2 (1 ms) in the backup first area 4150cb, and the content stored in the first address of Bank 0 (1 ms) is used as Bank 0 The contents stored at the end address of (1 ms) are all copied in order from the start address of Bank 2 (1 ms) of the backup first area 4150cb in succession by predetermined bytes (for example, 1 byte).

  Subsequently, the peripheral control MPU core 4150aa designates the contents stored in Bank0 (1 ms) as the request factor of the peripheral control DMA controller 4150ac, specifies the copy of the second backup area 4150cc to Bank3 (1 ms), and Bank0 (1 ms) ) To the content stored at the end address of Bank 0 (1 ms) from the content stored at the head address of) in the backup second area 4150 cc of bank 3 (1 ms) The peripheral control MPU core 4150aa specifies the contents stored in Bank0 (1ms) as the request factor of the peripheral control DMA controller 4150ac, and specifies the copy to Bank4 (1ms) in the backup second area 4150cc. Shi Bank 4 (1 ms) in the backup second area 4150 cc from the content stored at the beginning address of Bank 0 (1 ms) to the content stored at the end address of Bank 0 (1 ms) continuously by a predetermined byte (for example, 1 byte) Copy everything starting from the first address.

  As described above, in the peripheral control unit 1 ms timer interruption process, various processes related to the effects in steps S1104 to S1108 are executed as the progress of the effects within a period of 1 ms. On the other hand, in the peripheral control unit steady-state process in the peripheral control unit power-on process of FIG. 64, the various processes related to the effects in steps S1012 to S1032 described above are performed as the progress of the effects within a period of about 33.3 ms. doing. In the peripheral control unit 1 ms timer interrupt process, when the 1 ms timer interrupt execution count STN is not smaller than the value 33 in step S1100, that is, when the first 1 ms timer interrupt is generated and the peripheral control unit 1 ms timer interrupt process is started. Since this routine is ended as it is, even if the occurrence of the 33rd 1 ms timer interrupt happens to happen before the next V blank signal, the peripheral control unit by this 33rd 1 ms timer interrupt. The start of the 1 ms timer interrupt process is forcibly canceled, and after the 1 ms interrupt timer is started again in step S1010 in the peripheral control unit steady process due to the generation of the V blank signal, the peripheral control is newly performed by the first 1 ms timer interrupt. 1ms timer division It is adapted to start the actual processing. That is, the consistency between the progress state of the effect by the peripheral control unit steady process and the progress state of the effect by the peripheral control unit 1 ms timer interrupt process which is the timer interrupt control is not lost. Therefore, it is possible to reliably match the progress of the production.

  Further, as described above, the interval at which the V blank signal is output varies slightly depending on the liquid crystal sizes of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470, Even in the manufacturing lot of the peripheral control board 4140 on which the peripheral control MPU 4150a and the built-in sound source VDP 4160a are mounted, the interval at which the V blank signal is output may vary somewhat. In this embodiment, since the V blank signal is a signal that dominates the entire system of the peripheral control board 4140, if the occurrence of the first 1 ms timer interrupt happens to precede the next generation of the V blank signal, the peripheral control is performed. In order to execute the part V blank interrupt process, the start of the peripheral control part 1 ms timer interrupt process by the 33rd 1 ms timer interrupt is forcibly canceled. In other words, in the present embodiment, even if the interval at which the V blank signal is output changes slightly, by forcibly canceling the start of the peripheral control unit 1 ms timer interrupt process by the 33rd 1 ms timer interrupt, A time shift due to a slight change in the interval at which the V blank signal is output can be absorbed.

[17-1-4. Peripheral control unit command reception interrupt processing]
Next, the peripheral control unit command reception interrupt process for receiving various commands from the main control board 4100 will be described. The peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 starts to transmit main commands as serial data when various commands from the main control board 4100 are started as main data. One byte (8 bits) of information is taken into the reception buffer at the board serial I / O port, and when this fetching is completed, an interrupt is generated as a trigger, and peripheral control unit command reception interrupt processing is performed. The main circumference serial data is composed of 3 bytes per packet, the status is assigned as the first byte, the mode is assigned as the second byte, and the status and mode are regarded as numerical values as the third byte and the total The sum value that is calculated is assigned.

  When the peripheral control unit command reception interrupt process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 determines whether or not the 1-byte reception period timer has timed out as shown in FIG. 67 (step S1200). The 1-byte reception period timer sets a period during which 1-byte (8-bit) information can be received from the main peripheral serial data transmitted from the main control board 4100.

  When the 1-byte reception period timer has not timed out in step S1200, that is, when it is within a period in which 1-byte (8-bit) information can be received from the main peripheral serial data transmitted from the main control board 4100, the peripheral The 1-byte information received from the reception buffer of the main I / O port for the main control board incorporated in the control MPU 4150a is fetched (step S1202), and the value 1 is added to the reception counter SRXC (increment, step S1204). This reception counter SRXC is a counter indicating the number of times the data has been extracted from the reception buffer. When the status, which is the first byte of the main peripheral serial data, is extracted from the reception buffer, the value is 1, and the mode is the second byte of the main peripheral serial data. The value is 2 when extracted from the reception buffer, and the value is 3 when the sum value, which is the third byte of the main serial data, is extracted from the reception buffer. The reception counter SRXC is set to an initial value 0 when the power is turned on.

  Subsequent to step S1204, it is determined whether or not the reception counter SRXC has a value of 3, that is, whether or not the sum value that is the third byte of the main peripheral serial data has been extracted from the reception buffer (step S1206). In this determination, the status that is the first byte of the main peripheral serial data, the mode that is the second byte of the main peripheral serial data, and the sum value that is the third byte of the main peripheral serial data are sequentially received from the reception buffer. It is determined whether or not it has been taken out.

  When the reception counter SRXC is not the value 3 in step S1206, that is, following the status that is the first byte of the main peripheral serial data, the mode that is still the second byte of the main peripheral serial data, and the third byte of the main peripheral serial data When the sum values are not sequentially taken out from the reception buffer, the 1-byte reception period timer is set (step S1208), and this routine is terminated. By setting the 1-byte reception period timer in step S1208, a mode in which the mode which is the second byte of the main circumference serial data or the sum value which is the third byte of the main circumference serial data can be received is set.

  On the other hand, when the reception counter SRXC has a value of 3 in step S1206, that is, following the status that is the first byte of the main peripheral serial data, the mode that is the second byte of the main peripheral serial data, and the main peripheral serial data 3 When the sum value which is the byte is taken out from the reception buffer in order, the initial value 0 is set in the reception counter SRXC (step S1210), and the sum value is calculated (step S1212). In this calculation, the status that is the first byte of the main circumference serial data and the mode that is the second byte of the main circumference serial data, which have already been extracted from the reception buffer in step S1202, are regarded as numerical values and the sum (sum value). ) Is calculated.

  Subsequent to step S1212, it is determined whether or not the sum value, which is the third byte of the main serial data already extracted from the reception buffer in step S1202, matches the sum value calculated in step S1212 (step S1212). S1214). The sum value that is the third byte of the main circumference serial data already extracted from the reception buffer in step S1202 is the sum value allocated as the third byte of the main circumference serial data from the main circumference serial data from the main control board 4100. Therefore, it should match the sum value calculated in step S1212. However, the pachinko gaming machine 1 is supplied with game balls from the pachinko island facility, and when the game balls rub against each other and are charged, electrostatic discharge is generated to generate noise, so the pachinko gaming machine 1 is affected by noise. The environment is susceptible. Therefore, in this embodiment, the peripheral controller 4150 side regards the status assigned as the first byte of the received main circumference serial data and the mode assigned as the second byte of the main circumference serial data as numerical values. The sum (sum value) is calculated, and the calculated sum value matches the sum value allocated as the third byte of the main circumference serial data among the main circumference serial data from the main control board 4100. It is determined whether or not. As a result, the peripheral control MPU 4150a determines whether or not the main peripheral serial data is changed to the main peripheral serial data different from the normal due to the influence of noise between the main control board 4100 and the peripheral control board 4140. be able to.

  In step S1214, if the sum value that is the third byte of the main circumference serial data already extracted from the reception buffer in step S1202 matches the sum value calculated in step S1212, the received main circumference serial data is received. 16 shows the status allocated as the first byte and the mode allocated as the second byte of the main peripheral serial data, as shown in FIG. (Step S1216), and this routine is terminated. The reception command storage area 4150cac is used as a ring buffer, and the status allocated as the first byte of the main circumference serial data and the mode allocated as the second byte of the main circumference serial data are: It is stored in the peripheral control unit reception ring buffer of 4150cac. This "peripheral control unit reception ring buffer" is a buffer that is used so that the end and the top of the buffer are connected. Data is sequentially stored from the beginning of the buffer, and when it reaches the end of the buffer, it returns to the beginning. Remember. When storing the peripheral control MPU 4150a in the peripheral control unit reception ring buffer in step S1216, the peripheral control MPU 4150a is allocated as the received status of the main peripheral serial data as the first byte and the main peripheral serial data as the second byte. Are stored in association with each other, and the sum value allocated as the third byte is discarded.

  On the other hand, when the 1-byte reception period timer has not timed out in step S1200, that is, it exceeds the period in which 1-byte (8-bit) information can be received from the main peripheral serial data transmitted from the main control board 4100. Sometimes, or in step S1214, if the sum value that is the third byte of the main peripheral serial data already extracted from the reception buffer in step S1202 and the sum value calculated in step S1212 do not match, this routine is directly executed. finish.

[17-1-5. Peripheral control unit power failure warning signal interrupt processing]
Next, the peripheral control unit power failure warning signal executed when the power failure warning signal (peripheral power failure warning signal) from the power failure monitoring circuit 4100e of the main control board 4100 shown in FIG. 18 is input from the main control board 4100. The interrupt process will be described. When the peripheral control unit power failure warning signal interrupt process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 first activates a 2 microsecond timer (step S1300), and a power failure notification signal (peripheral power failure notification). It is determined whether or not a signal is input (step S1302). If no power failure warning signal (peripheral power failure warning signal) is input in this determination, this routine is terminated as it is.

  On the other hand, when a power failure warning signal is input in step S1302, it is determined whether or not 2 microseconds have elapsed (step S1304). In this determination, it is determined whether or not the timer started in step S1300 has passed 2 microseconds. If 2 macroseconds have not elapsed in step S1304, the process returns to step S1302, where it is determined whether or not a power failure warning signal has been input. If no power failure warning signal has been input, this routine is terminated. If a signal is input, it is determined again in step S1304 whether 2 microseconds have elapsed. That is, in the determination in step S1304, it is determined whether or not the power failure warning signal is continuously input for 2 microseconds after the peripheral control unit power failure warning signal interrupt processing, which is this routine, is started.

  When the peripheral control unit power failure warning signal interrupt processing, which is this routine, is started in step S1304 and the power failure warning signal is continuously input for 2 microseconds, power saving processing is performed (step S1306). In this power saving process, the backlights of the game board side liquid crystal display device 1900, the movable liquid crystal display devices 1925a to 1925d, and the upper plate side liquid crystal display device 470 are turned off, the motors and solenoids provided in the game board 4 are turned off, By suppressing the power consumption of the entire system of the pachinko gaming machine 1 by sequentially turning off the LEDs, etc., the peripheral control MPU 4150a can operate for 20 milliseconds even when the power of the pachinko gaming machine 1 is cut off. Stable operation is ensured only for a period.

  Subsequent to step S1306, command reception standby processing is performed (step S1308). In this command reception standby process, assuming that there are various commands being transmitted by the main control board 4100, the peripheral control MPU 4150a can receive at least a period of 17 milliseconds so that the command being transmitted can be received. It is supposed to wait. When a command is received, the peripheral control unit command reception interrupt process described above is started, and the received command storage area 4150cac (peripheral control unit reception ring buffer of the peripheral control RAM 4150c externally attached to the peripheral control MPU 4150a shown in FIG. ) Stores the received command.

  Subsequent to step S1308, command backup processing is performed (step S1310). In the backup process of this command, the contents stored in the received command storage area 4150cac included in the Bank0 (1fr) in the backup target work area 4150ca shown in FIG. 16 are changed to the Bank1 (1fr) and the backup first area 4150cb. The peripheral control DMA controller 4150ac copies to Bank2 (1fr) at high speed, and the peripheral control DMA controller 4150ac copies to Bank3 (1fr) and Bank4 (1fr) in the backup second area 4150cc at high speed.

  The peripheral control MPU core 4150aa of the peripheral control MPU 4150a shown in FIG. 16 is the peripheral control MPU 4150aa shown in FIG. Specify the contents stored in the received command storage area 4150cac included in Bank0 (1fr) as the request factor of the control DMA controller 4150ac, and copy to the received command storage area included in Bank1 (1fr) of the backup first area 4150cb Then, from the contents stored at the head address of the received command storage area 4150cac included in Bank0 (1fr), the end address of the received command storage area 4150cac included in Bank0 (1fr) is stored. Are copied in order from the start address of the received command storage area included in Bank1 (1fr) of the backup first area 4150cb in succession to a predetermined byte (for example, 1 byte), and the peripheral control MPU core The content stored in the received command storage area 4150cac included in Bank0 (1fr) as the request factor of the peripheral control DMA controller 4150ac is transferred to the received command storage area included in Bank2 (1fr) of the backup first area 4150cb. From the content stored at the start address of the received command storage area 4150cac included in Bank0 (1fr) to the content stored at the end address of the received command storage area 4150cac included in Bank0 (1fr) by designating copy , A predetermined number of bytes (e.g., 1 byte) all copies sequentially from the start address of the received command storage area included in the Bank2 (1FR) of the backup successively by the first area 4150Cb.

  Subsequently, the peripheral control MPU core 4150aa includes the contents stored in the received command storage area 4150cac included in Bank0 (1fr) as a request factor of the peripheral control DMA controller 4150ac in Bank3 (1fr) of the backup second area 4150cc. To the received command storage area 4150cac included in Bank0 (1fr) from the contents stored in the start address of the received command storage area 4150cac included in Bank0 (1fr). All the contents up to the specified contents are copied in order from the start address of the received command storage area included in Bank 3 (1fr) of the backup second area 4150cc in succession by a predetermined byte (for example, 1 byte), and peripheral control is performed. The PU core 4150aa uses the contents stored in the received command storage area 4150cac included in Bank0 (1fr) as a request factor of the peripheral control DMA controller 4150ac, and the received command storage area included in Bank4 (1fr) of the backup second area 4150cc. From the content stored at the start address of the received command storage area 4150cac included in Bank0 (1fr) to the content stored at the end address of the received command storage area 4150cac included in Bank0 (1fr) All the data are copied sequentially from the start address of the received command storage area included in Bank4 (1fr) of the backup second area 4150cc successively by a predetermined byte (for example, 1 byte).

  Subsequent to step S1310, it is determined whether a power failure warning signal (peripheral power failure warning signal) is input (step S1312). If a power failure warning signal is input in this determination, WDT clear processing is performed (step S1314). In this WDT clear processing, the peripheral control MPU 4150a outputs a clear signal to the peripheral control built-in WDT 4150af shown in FIG. 16 and the peripheral control external WDT 4150e shown in FIG. 15 so that the peripheral control MPU 4150a is not reset. .

  On the other hand, when the power failure warning signal is not input in step S1312, or following step S1314, the process returns to step S1312, and it is determined whether the power failure warning signal is input. That is, it is determined indefinitely whether or not a power failure warning signal (peripheral power failure warning signal) is input. By continuing the determination infinitely in this way, when the power failure warning signal (peripheral power failure warning signal) is not input in step S1312, the peripheral control MPU 4150a clears the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e. Cannot be output and the peripheral control MPU 4150a is reset. On the other hand, when a power failure warning signal is input in step S1312, the WDT clear process is performed in step S1314, and the peripheral control MPU 4150a is not reset. If the peripheral control MPU 4150a is reset, the peripheral control unit power-on process shown in FIG. 64 is started again.

  As described above, when the power failure warning signal (peripheral power failure warning signal) continues to be input in the infinite loop as determined in step S1312, the peripheral control is performed immediately before the power failure state is established by executing the WDT clear process in step S1314. The MPU 4150a is not reset. On the other hand, when the input of the power failure warning signal is not continued in the infinite loop and is canceled in the determination in step S1312, the WDT clear process is not executed, so the peripheral control built-in WDT 4150af and the peripheral control external WDT 4150e are The output of the clear signal is interrupted. As a result, even if the peripheral control unit power failure warning signal interrupt processing, which is this routine, is started erroneously due to noise or the like and the noise is generated beyond the period of 2 microseconds, the determination of step S1302 is passed. If the input of the power failure warning signal (peripheral power failure warning signal) is canceled without being continued in the infinite loop as determined in S1312, the peripheral control MPU 4150a is reset because the WDT clear process in step S1314 is not executed. Therefore, it is possible to cope with such noise by automatically resetting and returning.

[17-1-6. Power saving mode transition judgment process at power recovery]
Next, when the power is turned off (immediately before the power is turned off), the power state consumed by the pachinko gaming machine 1 is grasped at the time of power restoration, and the power saving mode is switched to the power saving mode for suppressing power consumed by the pachinko gaming machine 1 In the case of shifting to the power saving mode at the time of power recovery, the volume of the effect sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5 is reduced. The power saving mode transition determination process at the time of power recovery will be described in which the setting for reducing the luminance of the LEDs for light emitting decoration provided on the door frame 5 and the various LEDs mounted on the various decorative boards provided on the game board 4 is performed. This power saving mode transition determination process at the time of power recovery is performed in the process of step S1004 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG.

  When the power saving power saving mode transition determination process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 identifies the power consumption suppression stage based on the power consumption status history information as shown in FIG. (Step S1350). As described above, the power consumption status history information is a value (which is transmitted by the power consumption suppression signal from the power supply board 851 in the power consumption status history information generation processing in step S1113 in the peripheral control unit 1 ms timer interrupt processing shown in FIG. By sampling values 0 to 7) and sequentially storing them in the power consumption status history RAM 4150f of the peripheral control unit 4150 shown in FIG. 15 as the power consumption suppression stage (stage 0 to stage 7), the power consumption suppression stage is timed. Arranged in series. The power consumption status history RAM 4150f stores the power consumption status history information of the power consumption status history storage unit 4150f by supplying backup power from the battery 4150g of the peripheral control unit 4150 shown in FIG. It has come to be.

  In step S1350, among the power consumption status history information in which the values sampled and stored by the peripheral control MPU 4150a are arranged in time series, the power of the pachinko gaming machine 1 is turned off (power failure or momentary power failure due to power consumption of the pachinko gaming machine 1). For example, in addition to power outages due to lightning strikes and momentary power outages due to lightning strikes, power outages supplied to halls, momentary power outages due to instability of power supplied to halls, pachinko machines by hall staffs, etc. Including the power shutdown to 1.) The value sampled and stored immediately before is extracted, and the power consumption suppression stage immediately before the power shutdown is specified. Thereby, the power consumption suppression stage immediately before the power-off of the pachinko gaming machine 1 can be grasped.

  Following step S1350, it is determined whether the power consumption suppression stage has reached a threshold value (step S1352). In this determination, it is determined whether or not the power consumption suppression stage immediately before the power-off of the pachinko gaming machine 1 specified in step S1350 has reached a threshold value. In the present embodiment, stage 7 is set as the threshold value.

  When the power consumption suppression stage has not reached the threshold value in step S1352, the power saving mode transition flag ECO-FLG at power recovery is set to 0 (step S1354), and this routine is terminated, while power consumption is performed in step S1352. When the suppression stage has reached the threshold value, the power-saving power saving mode transition flag ECO-FLG is set to a value 1 (step S1356), and power-saving power saving mode timer activation processing is performed (step S1358). Exit.

  The power saving mode transition flag ECO-FLG at the time of power recovery indicates that the effect sound flowing from the speaker housed in the speaker box 820 provided on the main body frame 3 and the speaker 130 provided on the door frame 5 when the pachinko gaming machine 1 is restored. Whether to shift to the power saving mode at the time of power recovery in which the setting for decreasing the volume, the setting for decreasing the brightness of the various LEDs mounted on the various decorative boards provided in the game board 4 This value is set to 0 when not entering the power saving mode during power recovery, and set to 0 when entering the power saving mode during power recovery.

  The power-saving power-saving mode timer activated in step S1358 measures the power-saving power-saving mode state maintenance period during which the pachinko gaming machine 1 is activated as the power-saving power-saving mode. In the embodiment, 5 minutes is set as the power saving mode state maintenance period at the time of power recovery. When the power saving power saving mode timer is activated and the time of the power saving power saving mode state maintenance period is started and the power saving power saving mode state maintenance period elapses, the power saving power saving mode timer is stopped, and FIG. In order to suppress this power consumption according to the power consumption in the pachinko gaming machine 1 by the power processing amount monitoring process in step S1027 in the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG. 3 is mounted on the speaker housed in the speaker box 820 and the volume of the effect sound flowing from the speaker 130 provided on the door frame 5, the LED for light emitting decoration provided on the door frame 5, and various decorative boards provided on the game board 4. The brightness of various LEDs is adjusted.

[17-1-7. Power consumption monitoring process]
Next, the power consumption monitoring process for adjusting the volume and the brightness of various LEDs in order to suppress the power consumption according to the power consumption in the pachinko gaming machine 1 will be described. This power consumption monitoring process is performed in the process of step S1027 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG.

  When the power consumption monitoring process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 illustrated in FIG. 15 specifies the power consumption suppression stage based on the power consumption suppression signal as illustrated in FIG. 70 (step S1400). ). As described above, the power consumption suppression signal is output from the power consumption monitoring circuit 855da. As shown in FIG. 19A, the power consumption monitoring circuit 855da includes a power measurement circuit 855daa and a power consumption suppression stage determination circuit 855dab. + 37V supplied from the smoothing circuit 855c is supplied to the + 5V power generation circuit 855db, the + 12V power generation circuit 855dc, and the + 24V power supply generation circuit 855dd via the power measurement circuit 855daa. The power measurement circuit 855daa measures the power consumption of + 37V supplied from the smoothing circuit 855c in real time and outputs it to the power consumption suppression stage determination circuit 855dab. The power consumption suppression stage determination circuit 855dab determines a power consumption suppression stage indicating how much power consumption should be suppressed based on the power consumption measured by the power measurement circuit 855daa. By setting the value of the power consumption suppression signal configured as a signal wiring and outputting it to the frame peripheral relay terminal plate 868, the power consumption suppression signal is input to the peripheral control unit 4150 via the frame peripheral relay terminal plate 868. It has come to be. As described above, the power consumption suppression signal is configured as three signal wirings (that is, configured as three parallel signals), and transmits eight values from 0 to 7. Can be done.

  As described above, the power consumption suppression stage determination circuit 855dab determines that it is stage 0 as the power consumption suppression stage when the power consumption of + 37V measured by the power measurement circuit 855daa is 0% or more and less than 10%. When the value of 0 is set as the value of the suppression signal and the power consumption of + 37V measured by the power measurement circuit 855daa is 10% or more and less than 20%, it is determined as stage 1 as the power consumption suppression stage and the power consumption suppression signal The value 1 is set as the value, and when the power consumption of +37 V measured by the power measuring circuit 855daa is 20% or more and less than 30%, it is determined as the stage 2 as the power consumption suppression stage and the value as the value of the power consumption suppression signal 2 and when the power consumption of + 37V measured by the power measurement circuit 855daa is 30% or more and less than 40%, When the power consumption suppression signal is determined to be stage 3 as the suppression stage and the value 3 is set as the value of the power consumption suppression signal and the power consumption of +37 V measured by the power measurement circuit 855daa is 40% or more and less than 50%, the power consumption suppression stage When the power consumption suppression signal is determined to be step 4 and the value 4 is set as the value of the power consumption suppression signal and the power consumption of + 37V measured by the power measurement circuit 855daa is 50% or more and less than 60%, the power consumption suppression step is performed in step 5 If a value 5 is set as the value of the power consumption suppression signal after determination and the power consumption of +37 V measured by the power measurement circuit 855daa is 60% or more and less than 70%, it is determined that the power consumption suppression stage is stage 6. When the value 6 is set as the value of the power consumption suppression signal, the power consumption of +37 V measured by the power measurement circuit 855daa is 70% or more. It is adapted to set the value 7 as the value of the power consumption suppression signal to determine a phase 7 as a power consumption inhibiting step for.

  In step S1400, the value of the power consumption suppression signal set by the power consumption suppression level determination circuit 855dab can be acquired, and the power consumption suppression level can be identified from the acquired value.

  Subsequent to step S1400, it is determined whether or not the power saving mode transition flag ECO-FLG at the time of power recovery is a value 1 (step S1402). As described above, the power saving power saving mode transition flag ECO-FLG is set in the power saving power saving mode transition determination process in step S1004 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG. At the time of power recovery of the pachinko gaming machine 1, a setting for reducing the volume of the production sound flowing from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5, and the light emission provided in the door frame 5 This is to set whether or not to shift to the power-saving power saving mode for setting the brightness of various LEDs mounted on the decorative LEDs and various decorative boards provided in the game board 4 to be reduced. A value of 0 is set when the mode is not shifted to, and a value of 0 is set when the mode is shifted to the power saving mode during power recovery.

  When the power saving power saving mode transition flag ECO-FLG is not a value 1 (value 0) in step S1402, that is, when the power saving power saving mode is not entered, a normal power suppression volume setting process is performed (step S1404). . In this normal power suppression volume setting process, the master volume value for adjusting the volume of the output channel specified in the sound command data constituting the sound generation schedule data is forcibly changed to the master volume value for power suppression. Change to

  The value set as the master volume value for power suppression will be briefly described. As shown in FIG. 71 (a), the peripheral control MPU 4150a uses the stage 0 to stage 7 as the power consumption suppression stage on the horizontal axis, Ratio to master volume value (hereinafter referred to as “sound command data default master volume value”) for adjusting the volume of the output channel specified in the command data (that is, as a master volume value for power suppression) Assuming that the set value) is the vertical axis, when the power consumption suppression stage is stage 0 or stage 1, that is, when the power consumption suppression stage acquired in step S1400 is stage 0 or stage 1, the master volume for power suppression The volume is 100% of the master volume value defined in the sound command data (in other words, power suppression When the power consumption suppression stage is stage 2 or stage 3, that is, the power consumption suppression stage acquired in step S1400 is stage 2 or When it is stage 3, the volume of 90% is set as the master volume value for the sound command data as the master volume value for power suppression, and when the power consumption suppression stage is stage 4, that is, the power acquired in step S1400 When the consumption suppression stage is stage 4, a volume of 80% is set as the master volume value for power control as the master volume value for power suppression, and when the power consumption suppression stage is stage 5, that is, step S1400. When the power consumption suppression step acquired in step 5 is step 5, When the volume level is set to 70% with respect to the master volume value defined in the sound command data as the volume value and the power consumption suppression stage is stage 6, that is, when the power consumption suppression stage acquired in step S1400 is stage 6. As a master volume value for power suppression, a volume of 60% is set with respect to the master volume value defined in the sound command data, and when the power consumption suppression stage is stage 7, that is, the power consumption suppression stage acquired in step S1400 is staged. When it is 7, the volume of 50% is set as the master volume value for power suppression with respect to the master volume value defined by the sound command data.

  The plurality of output channels in the built-in sound source of the built-in sound source VDP 4160a include the sound data of the effect sound incorporated in the track to be used and the effect sound incorporated in the track to be used among the plurality of tracks in the sound source built-in the VDP 4160a. The sub volume value for adjusting the volume is synthesized, and the volume of the synthesized performance sound is actually obtained from the speaker housed in the speaker box 820 provided in the main body frame 3 and the speaker 130 provided in the door frame 5. Amplification is performed up to a master volume value for power suppression, which is a flowing volume, and the amplified effect sound is serialized and output as audio data to the audio data transmission IC 4160c. In other words, when the normal power suppression volume setting process is performed, the content of the effect by the effect sound does not change, but the sound volume of the effect sound is the master volume defined by the sound command data in the power consumption suppression steps from stage 0 to stage 1. While the value itself becomes the volume, the volume set as the master volume value for power suppression becomes substantially smaller as the power consumption suppression stage proceeds from stage 2 to stage 7, so the volume of the production sound Has become smaller.

  Returning to FIG. 70, following step S1404, a normal power suppression luminance setting process is performed (step S1406). In this normal power suppression luminance setting process, the luminance of various LEDs in the light emission mode of the various LEDs defined in the light emission data constituting the light emission mode generation schedule data is forcibly changed and set from the power suppression luminance.

  The brightness set as the power suppression brightness will be briefly described. As shown in FIG. 71 (b), the peripheral control MPU 4150a uses the steps 0 to 7 as the power consumption suppression steps on the horizontal axis to generate the light emission data. When the vertical axis represents the ratio (that is, the luminance set as the luminance for power suppression) to the luminance of various LEDs (hereinafter referred to as “luminance specified for light emission data”) in the light emission mode of the various LEDs specified, When the power consumption suppression stage is one of stage 0, stage 1, stage 2, stage 3, and stage 4, that is, the power consumption suppression stage acquired in step S1400 is stage 0, stage 1, stage 2, Of the stage 3 and stage 4, when it is one stage, the brightness for power suppression is 100% of the brightness specified in the emission data (in other words, the brightness for power suppression). When the power consumption suppression stage is stage 5, that is, when the power consumption suppression stage acquired in step S1400 is stage 5, the brightness of the emission data regulations is set as the brightness for power suppression. On the other hand, when the luminance of 70% is set and the power consumption suppression stage is stage 6, that is, when the power consumption suppression stage acquired in step S1400 is stage 6, the luminance for power suppression is set to the luminance specified in the emission data. When the power consumption suppression stage is stage 7, that is, when the power consumption suppression stage acquired in step S1400 is stage 7, the brightness of the emission data is defined as the brightness for power suppression. Set the brightness to 50%.

  When the brightness setting processing for power suppression at normal time is performed, although the contents of effects by the light emission modes of the various LEDs mounted on the various decorative boards provided in the game board 4 and the LEDs for the light emitting decoration provided in the door frame 5 are not changed, The brightness of the LED is set as the brightness for power suppression as the power consumption suppression stage proceeds from stage 5 to stage 7 while the power consumption suppression stage reaches the brightness specified in the light emission data from stage 0 to stage 4. Since the brightness is reduced, the brightness of various LEDs is reduced.

  Subsequent to step S1406, the power saving mode transition notification LED 4150k shown in FIG. 15 is set to the non power saving notification mode (step S1407a). As described above, the power saving mode transition notification LED 4150k employs a high-luminance single color light emitting in green. The non-power-saving notification mode is to notify a staff member such as a hall clerk that the mode does not shift to the power saving mode at the time of power recovery, and is in a lighting state (that is, a lighting state in which light is emitted in green). The power saving mode transition notification LED 4150k set in step S1407a is configured so that the non power saving notification mode (that is, the lighting state in which the LED emits green light) is directly defined (set) every time this routine is executed. The light emission modes of the various LEDs described above are different in that they are configured to be defined by the light emission data constituting the light emission mode generation schedule data. An attendant such as a hall clerk inserts a key into the cylinder lock 1010 of the lock device 1000 shown in FIGS. 1 and 5 and rotates to release the closed state of the main body frame 3 with respect to the outer frame 2. 2. Opening the main body frame 3 for 2 and grasping that the light-emitting mode of the power-saving mode transition notification LED 4150k does not shift to the power-saving mode during power recovery by visually observing the non-power-saving notification mode (that is, the green lighting state). can do.

  Subsequent to step S1407a, the output of the power saving mode information output signal is set to stop (step S1407b), and this routine ends. As described above, the power saving mode information output signal is used to notify the hall computer of the state of transition to the power saving mode during power recovery via the external terminal board 784 shown in FIG. 15, and in step S1402 If not, the power saving mode information output signal is set not to be output in step S1407b.

  On the other hand, when the power saving power saving mode transition flag ECO-FLG is 1 (not 0) in step S1402, that is, when shifting to the power saving power saving mode, the power saving power saving mode timer has reached the upper limit time. It is determined whether or not (step S1408). As described above, the power-saving power-saving mode timer measures the power-saving power-saving mode state maintenance period during which the pachinko machine 1 is maintained in the power-saving power-saving mode. Then, 5 minutes is set as the power-saving power saving mode state maintenance period. The upper limit time used for the determination is 5 minutes of the power saving mode state maintenance period at the time of power recovery.

  In step S1408, when the power saving power saving mode timer has not reached the upper limit time, that is, when the power saving power saving mode timer has not reached 5 minutes of the power saving power saving mode state maintaining period, Setting processing is performed (step S1410). In this power reduction volume setting process for power recovery, similarly to the normal power suppression volume setting process in step S1404 described above, the volume of the output channel specified in the sound command data constituting the sound generation schedule data is set. Although it is forcibly changed from the master volume value for adjustment to the master volume value for power suppression, the volume level is always set to 50% of the master volume value specified in the sound command data as the master volume value for power suppression. It is different in point to do. In other words, in the power suppression volume setting process for power recovery, the master volume value for power suppression set when the power consumption suppression stage is stage 7 in the normal power suppression volume setting process is always set. ing.

  When the power reduction volume setting process at power recovery is performed, the content of the effect by the effect sound is not changed, but the sound volume of the effect sound is set to the lowest power consumption suppression stage of Step 7. (In other words, the volume of the effect sound is set such that the power consumption suppression stage is stage 7 and the power consumption is minimized).

  Subsequent to step S1410, power-reduction power suppression brightness setting processing is performed (step S1412). In the power setting luminance setting process for power recovery, in the light emission mode of various LEDs defined in the light emission data constituting the light emission mode generation schedule data, similarly to the normal power suppression luminance setting process in step S1406 described above. Although it is forcibly changed from the brightness of various LEDs to the brightness for power suppression, the difference is that the brightness of 50% is always set as the brightness for power suppression with respect to the brightness specified for the light emission data. That is, in the power setting luminance setting process for power recovery, the luminance for power suppression set when the power consumption suppression stage is stage 7 in the power setting luminance setting process for normal power is always set. .

  When the brightness setting process for power suppression at the time of power recovery is performed, although the effect contents according to the light emission mode of the various LEDs mounted on the various decorative boards included in the LED and the decorative board provided in the door frame 5 are not changed, The brightness of various LEDs is set to the lowest power consumption suppression level of 7 (in other words, the brightness of each LED has the lowest power consumption of the power consumption suppression stage of 7). Stuff is set).

  Subsequent to step S1412, the power saving mode transition notification LED 4150k is set to a power saving notification mode (step S1413a). In the power saving notification mode, a staff member such as a store clerk in the hall is notified that the power saving mode is to be entered when power is restored, and the power saving notification mode is turned off. The power-saving mode transition notification LED 4150k set in step S1413a is configured to be directly defined (set) every time this routine is executed, and thus the various LEDs described above. Are different from each other in that the light emission modes are defined by the light emission data constituting the light emission mode generation schedule data. An attendant such as a hall clerk inserts a key into the cylinder lock 1010 of the lock device 1000 shown in FIGS. 1 and 5 and rotates to release the closed state of the main body frame 3 with respect to the outer frame 2. 2, the main body frame 3 is opened, and the light-emitting mode of the power-saving mode transition notification LED 4150k is grasped to be in the power-saving mode upon power recovery by visually observing the power-saving notification mode (that is, the light-off state). it can. In the present embodiment, as the light emission mode of the power saving mode transition notification LED 4150k, the lighting state is set when the power saving mode is not shifted to the power recovery mode, while the light emitting mode is set to the off state when the power saving mode is restored. However, since it is necessary to suppress the power consumption in the power saving mode at the time of power recovery, the power saving mode transition notification LED 4150k is turned on when the power saving mode is not shifted to at the time of power recovery. When shifting to the power saving mode, the power saving mode transition notification LED 4150k is turned off.

  Subsequent to step S1413a, the output of the power saving mode information output signal is set to start (step S1413b), and this routine ends. When the power saving mode information output signal is output in step S1413b when the power saving mode is set in the power recovery mode in step S1402, the power saving mode timer is set to the upper limit in step S1408 every time this routine is executed. In step S1413b, the state where the power saving mode information output signal is output is maintained until the time is reached, that is, until the power saving power saving mode timer reaches 5 minutes of the power saving power saving mode state maintaining period. Is output to the external terminal board 784 and transmitted to the hall computer via the external terminal board 784, and the hall computer recognizes that the pachinko gaming machine 1 is in a state of shifting to the power saving mode upon power recovery.

  On the other hand, when the power saving power saving mode timer reaches the upper limit time in step S1408, that is, when the power saving power saving mode timer reaches 5 minutes of the power saving power saving mode state maintenance period, the power saving power saving motor In order to end the transition, the power saving power saving mode transition flag ECO-FLG is set to 0 (step S1414), the power saving power saving mode timer is stopped (step S1416), and this routine is terminated. In the power saving power saving mode timer stop process, only the process of stopping the power saving power saving mode timer is performed, and the process of initializing (resetting) the power saving power saving mode timer is not included. This is because even if the power saving mode shift flag ECO-FLG during power recovery changes from the value 0 to the value 1 due to some cause (for example, due to the influence of noise), the process proceeds to step S1408 as determined in step S1402. In the power-saving power-saving mode timer stop process, the power-saving power-saving mode timer is stopped for 5 minutes of the power-saving power-saving mode state maintenance period, which is the upper-limit time. By maintaining the state that has reached the power saving power saving mode state maintenance period of 5 minutes, the process proceeds to step S1414 in the determination of step S1408, and the power saving power saving mode transition flag is set in step S1414. This is because the value of ECO-FLG can be forcibly returned to the normal value 0. In the initial setting process in step S1000 in the peripheral controller power-on process shown in FIG. 64, the power saving power saving mode timer is initialized (reset).

  In step S1408, the power saving power saving mode timer reaches the upper limit time, and in step S1414, the power saving power saving mode transition flag ECO-FLG is set to 0 in order to end the power saving power saving mode transition flag. As a result, when this routine is executed again, the process proceeds from the step S1404 to the step 1407b in order by the determination in the step S1402, and the output state of the power saving mode information output signal is stopped in the step S1407b. That is, when the power saving power saving mode timer reaches the upper limit time in step S1408, the output state of the power saving mode information output signal is maintained every time this routine is executed again, and the power saving mode The state in which the information output signal is not output to the external terminal board 784 is transmitted to the hall computer via the external terminal board 784, and the pachinko gaming machine 1 in the hall computer has finished the state of shifting to the power saving mode at the time of power recovery. Will be grasped. At the time of power recovery, if it is determined in step S1402 that the power saving mode does not shift to power recovery mode, a state in which a power saving mode information output signal is not output to the external terminal board 784 is transmitted to the hall computer via the external terminal board 784 in step S1407b. In the hall computer, it is grasped that the pachinko gaming machine 1 is not in the power saving mode at the time of power recovery.

  As described above, in the power saving power saving mode transition determination process in step S1004 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG. 64, when the pachinko gaming machine 1 is restored, the main frame 3 Setting for reducing the volume of the production sound flowing from the speaker housed in the provided speaker box 820 and the speaker 130 provided in the door frame 5, the LED for light emitting decoration provided in the door frame 5, and various decorative boards provided in the game board 4 When it is determined whether or not to shift to the power saving power saving mode for performing settings such as reducing the brightness of the various LEDs mounted, and this determination result is not to shift to the power saving power saving mode, In step S1400, the value of the power consumption suppression signal set by the power consumption suppression stage determination circuit 855dab is acquired, and the power consumption is calculated from the acquired value. Since the control stage can be specified, according to the power consumption in the pachinko gaming machine 1, the power consumption suppression stage is specified from among the stage 0 to the stage 7, The master volume value for power suppression forcibly changed and set in the above-described normal power suppression volume setting process in step S1404 corresponding to the stage, and the normal power suppression brightness setting in step S1406 corresponding to each stage. The progress of the production can be controlled by the power consumption luminance that is forcibly changed and set by the process, and with less power consumption. Therefore, it is possible to prevent a power failure from occurring due to the power consumption of the pachinko gaming machine 1 itself. Moreover, it is possible to prevent the game from being interrupted due to a power failure caused by the power consumption of the pachinko gaming machine 1 itself.

  On the other hand, in the power saving power-saving mode transition determination process in step S1004 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG. 64, the pachinko gaming machine 1 is provided with the main body frame 3 when the power is restored. It is mounted on the speaker housed in the speaker box 820 and the setting for reducing the volume of the effect sound flowing from the speaker 130 provided on the door frame 5, the light emitting decoration LED provided on the door frame 5, and various decorative boards provided on the game board 4. If it is determined whether or not to shift to the power saving power saving mode for setting the brightness of various LEDs to be reduced, and the determination result is to shift to the power saving power saving mode, the above-described steps are performed. Master volume value for power suppression forcibly changed and set in the power setting volume setting process for power reduction at S1410 (that is, volume setting process for normal power suppression) Power suppression master volume value set when the power consumption suppression stage is stage 7) and the power suppression brightness forcibly changed and set in the power recovery brightness suppression brightness setting process in step S1412 described above. (That is, the brightness for power suppression set when the power consumption suppression stage is stage 7 in the normal power suppression brightness setting process) The timer can be controlled until it reaches 5 minutes of the power saving power saving mode state maintenance period, which is the upper limit time. This does not cause a power outage or a momentary power failure due to power consumption of the pachinko gaming machine 1, but a power failure due to a lightning strike or a momentary power failure due to a lightning strike, for example. In addition, when the power supply of the pachinko gaming machine 1 is cut off due to a power outage of the power supplied to the hall or instability of the power supplied to the hall, and the staff of the hall or the like takes the pachinko gaming machine 1 to the pachinko gaming machine 1 Even when the power is shut off and the power is cut off, the power situation consumed by the pachinko gaming machine 1 at the time of power off (immediately before the power off) can be grasped at the time of power restoration. In step S7, the pachinko gaming machine 1 can be started in a state in which the performance can proceed with the smallest power consumption of step 7. Therefore, it is possible to prevent a power outage from occurring due to the power consumption of the pachinko gaming machine 1 itself even during power recovery. Moreover, it is possible to prevent the game from being interrupted due to a power failure caused by the power consumption of the pachinko gaming machine 1 itself.

  Also, in the present embodiment, when the normal power suppression volume setting process in step S1404 described above is performed, the content of the effect by the effect sound does not change, but the effect sound volume is changed from the power consumption suppression stage from stage 0 to stage 0. The volume of the master volume value stipulated by the sound command data is up to 1 while the volume set as the master volume value for power suppression is substantially reduced as the power consumption suppression stage proceeds from stage 2 to stage 7. Therefore, when the volume of the effect sound is reduced and the normal power suppression brightness setting process in step S1406 is performed, the LED for light emitting decoration provided in the door frame 5 and various decorations provided in the game board 4 are provided. Although the content of the effect by the light emission mode of various LEDs mounted on the board does not change, the brightness of each LED is the power consumption suppression stage. While the luminance of the emission data is defined from step 0 to step 4, the luminance set as the power suppression luminance decreases as the power consumption suppression step proceeds from step 5 to step 7. The brightness of various LEDs is reduced. In this embodiment, when the power consumption suppression stage proceeds to stage 2, the volume of the effect sound is controlled to be smaller than the brightness of various LEDs first. This is because multiple types of pachinko machines are installed in the hall and each produces various production sounds at a high volume, so even if the production sound volume is reduced, the player is not aware of the production sound. The player's willingness to play is not reduced due to the decrease in the volume of the game, and the power consumed by the pachinko gaming machine 1 can be suppressed by reducing the volume of the effect sound.

[17-1-8. LOCKN signal history creation process]
Next, the LOCKN signal history creation process executed as one process of the drawing state information acquisition process of step S1110 in the peripheral control unit 1 ms timer interrupt process shown in FIG. 66 will be described. In this LOCKN signal history creation process, a history of the LOCKN signal output from the LOCKN terminal of the upper plate-side liquid crystal receiver ICSDIC0 provided in the touch panel drive substrate 450 shown in FIG. 36 is created. As described above, the LOCKN signal indicates that the drawing data received by the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive substrate 450 from the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control substrate 4140 shown in FIG. If the data is determined to be correct data, it is a signal that is output to convey the fact, and specifically, an upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 and an upper plate side liquid crystal provided in the touch panel drive board 450. This signal is output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection between the receiver receiver ICSDDIC0, that is, the connection between the transmitter and the receiver.

  When the LOCKN signal history creation process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 is connected to the peripheral control MPU 4150a externally attached to the peripheral control MPU 4150a shown in FIG. LOCKN signal detection history information LOCKN-HIST is read out from the drawing state information acquisition storage area 4150cak (step S1500). This LOCKN signal detection history information LOCKN-HIST is stored in 1 byte (8 bits: most significant bits B7, B6, B5, B4, B3, B2, B1, and least significant bit B0, "B" represents a bit). The history of the LOCKN signal output from the LOCKN terminal of the receiver ICSDIC0 for the upper plate side liquid crystal provided in the touch panel drive substrate 450 is stored in the drawing state information acquisition storage area 4150cak as LOCKN signal detection history information LOCKN-HIST. Has been.

  Subsequent to step S1500, it is determined whether or not there is a LOCKN signal output from the LOCKN terminal of the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive substrate 450 (step S1502). In this determination, when there is a LOCKN signal from the upper plate side liquid crystal receiver IC SDIC0, the upper plate side liquid crystal receiver IC SDIC0 determines that the drawing data received from the upper plate side liquid crystal transmitter IC 4160d is abnormal data. A transmission request is made for a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection between the upper plate side liquid crystal transmitter IC 4160d and the upper plate side liquid crystal receiver IC ICDIC0, that is, the connection between the transmitter and the receiver. On the other hand, if there is no LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0, the drawing data received by the upper plate side liquid crystal receiver ICSDIC0 from the upper plate side liquid crystal transmitter IC4160d is not abnormal data (normal The data) There is no transmission request for a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection between the dish-side liquid crystal transmitter IC 4160d and the upper-plate liquid crystal receiver IC SDIC0, that is, the connection between the transmitter and the receiver. Is determined.

  If there is a LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 in step S1502, the LOCKN signal detection history information is shifted (step S1504). In this LOCKN signal detection history information shift process, when there is a LOCKN signal from the upper-plate-side liquid crystal receiver ICSDIC0, the LOCKN signal detection history information LOCKN-HIST read in step S1500 is converted into the most significant bits B7 ← B6, B6 ←. B5, B5 ← B4, B4 ← B3, B3 ← B2, B2 ← B1, B1 ← the least significant bit B0 and so on are shifted bit by bit from the least significant bit B0 toward the most significant bit B7.

  When the LOCKN signal detection history information LOCKN-HIST is shifted in step S1504, the value 1 is set to the least significant bit B0 of the LOCKN signal detection history information LOCKN-HIST (step S1506), and this routine is terminated.

  On the other hand, when there is no LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 in step S1502, the LOCKN signal detection history information is shifted (step S1508). In this LOCKN signal detection history information shift processing, the same processing as the LOCKN signal detection history information shift processing in step S1504 is performed, and when there is no LOCKN signal from the upper LCD receiver ICSDIC0, the LOCKN read in step S1500 The signal detection history information LOCKN-HIST includes the most significant bit B7 ← B6, B6 ← B5, B5 ← B4, B4 ← B3, B3 ← B2, B2 ← B1, B1 ← the least significant bit B0. 1 bit to the most significant bit B7.

  When the LOCKN signal detection history information LOCKN-HIST is shifted in step S1508, the value 0 is set to the least significant bit B0 of the LOCKN signal detection history information LOCKN-HIST (step S1510), and this routine is ended.

  Thus, each time this LOCKN signal history creation process is executed, the LOCKN signal detection history information LOCKN-HIST is shifted bit by bit from the least significant bit B0 toward the most significant bit B7, and then the least significant bit B0. Since the value 1 or the value 0 is set, the history of the LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 can be created.

[17-1-9. Connection failure judgment process]
Next, a connection failure determination process executed as one process of the warning process in step S1024 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG. 64 will be described. In this connection failure determination processing, the upper plate side liquid crystal provided in the peripheral control board 4140 is based on the history of the LOCKN signal output from the LOCKN terminal of the receiver ICSDIC0 for the upper plate side liquid crystal provided in the touch panel drive substrate 450 shown in FIG. It is determined whether or not there is a problem between the connection between the transmitter IC 4160d and the upper plate side liquid crystal receiver ICSDIC0 provided on the touch panel drive substrate 450, that is, between the transmitter and the receiver.

  When the connection failure determination process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 is connected to the peripheral control MPU 4150a externally attached to the peripheral control MPU 4150a shown in FIG. The LOCKN signal detection history information LOCKN-HIST is read from the drawing state information acquisition storage area 4150cak (step S1520). In the LOCKN signal detection history information LOCKN-HIST, as described above, the history of the LOCKN signal output from the LOCKN terminal of the upper plate side liquid crystal receiver ICSDIC0 provided in the touch panel drive substrate 450 is stored. As described above, the LOCKN signal indicates that the drawing data received from the upper plate side liquid crystal transmitter IC 4160d included in the peripheral control board 4140 by the upper plate side liquid crystal receiver ICSDIC0 included in the touch panel drive substrate 450 is abnormal data. When it is determined, it is a signal that is output to convey the fact, specifically, an upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140, and an upper plate side liquid crystal receiver IC SDIC0 provided in the touch panel drive board 450, This signal is output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection between the two connections, that is, the connection between the transmitter and the receiver.

  Subsequent to step S1520, it is determined whether there is a LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 (step S1522). In this determination, it is determined whether or not the LOCKN signal detection history information LOCKN-HIST read in step S1520 matches the connection confirmation determination value. This connection confirmation determination value is stored in advance in the peripheral control ROM 4150b shown in FIG. 15. In this embodiment, it is “00001111B (“ B ”represents a bit)”, and the upper 4 bits B7 to B4. Is the value 0, and the lower 4 bits B3 to B0 are the value 1. In the determination in step S1522, it is determined whether or not the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST match the lower 4 bits B3 to B0 of the connection confirmation determination value.

  In step S1522, when the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST read in step S1520 do not match the lower 4 bits B3 to B0 of the connection confirmation determination value, the peripheral control board 4140 is provided. It is determined that there is no problem between the connection between the upper plate side liquid crystal transmitter IC 4160d and the upper plate side liquid crystal receiver IC ICDIC0 provided on the touch panel drive substrate 450, that is, between the transmitter and the receiver. Then, this routine is finished as it is.

  On the other hand, in step S1522, if the lower 4 bits B3 to B0 of the LOCKN signal detection history information LOCKN-HIST read in step S1520 match the lower 4 bits B3 to B0 of the connection confirmation determination value, the peripheral control board 4140 If there is a problem in the connection between the upper plate side liquid crystal transmitter IC 4160d provided on the touch panel drive substrate 450 and the upper plate side liquid crystal receiver IC SDIC0 provided on the touch panel drive substrate 450, that is, the connection between the transmitter and the receiver. Determination is made and 1 is added to the communication check counter CC-CNT (increment, step S1524). Each time this routine is executed, the communication check counter CC-CNT counts up the number of times determined in step S1522 that the connection between the transmitter and the receiver is defective. (Counting the cumulative number of times). Note that the communication check counter CC-CNT is reset when the pachinko gaming machine 1 is turned on and is set to 0, but is not reset by an instantaneous power failure or a power failure. The power is restored to the value of the communication check counter CC-CNT just before the moment or power failure occurs during power transmission.

  Subsequent to step S1524, it is determined whether the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit CC-LMT (step S1526). In this determination, when the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit value CC-LMT, the cumulative number determined to be in a state where a connection between the transmitter and the receiver is in trouble is the cumulative number. While it is determined that the upper limit value CC-LMT has not been reached, if the value of the communication check counter CC-CNT is not smaller (larger) than the cumulative number upper limit value CC-LMT, a problem has occurred in the connection between the transmitter and the receiver. It is determined that the cumulative number of times determined to be in the state has reached the cumulative number upper limit CC-LMT.

  When the value of the communication check counter CC-CNT is smaller than the cumulative number upper limit value CC-LMT in step S1526, that is, the cumulative number determined that the connection between the transmitter and the receiver is defective is the cumulative number. When the upper limit value CC-LMT has not been reached, the communication abnormality flag CC-FLG is set to 0 (step S1528), and this routine is terminated. On the other hand, when the value of the communication check counter CC-CNT is not smaller (larger) than the cumulative number upper limit value CC-LMT in step S1526, that is, it is determined that there is a problem in the connection between the transmitter and the receiver. When the accumulated number of times reaches the accumulated number upper limit CC-LMT, a value of 1 is set in the communication abnormality flag CC-FLG (step S1530), and this routine is terminated. The communication abnormality flag CC-FLG indicates that the accumulated number of times determined that the connection between the transmitter and the receiver is in trouble has reached the accumulated number upper limit CC-LMT, and the connection between the transmitter and the receiver. This flag indicates whether or not a failure has occurred. Value 1 when the connection between the transmitter and the receiver is definitely defective. A failure has occurred in the connection between the transmitter and the receiver. When the accumulated number of times determined to be in the state is not reaching the accumulated number upper limit CC-LMT, the value is set to 0, respectively. Note that the communication abnormality flag CC-FLG is reset when the pachinko gaming machine 1 is turned on and is reset with a value of 0. It is restored to the value of the communication abnormality flag CC-FLG immediately before the moment or power failure occurs during power transmission.

[17-1-10. Connection recovery process]
Next, the connection recovery process executed as one process of the warning process in step S1024 in the peripheral control part steady process of the peripheral control part power-on process shown in FIG. 64 will be described. In this connection recovery process, an upper dish side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 and an upper dish side liquid crystal receiver IC SDIC0 provided in the touch panel drive board 450 are executed following the connection failure determination process shown in FIG. Outputs a predetermined data pattern (SYNC pattern) to confirm (recover) the connection between the transmitter and the receiver, that is, when the connection between the transmitter and the receiver is abnormal. Inform the effect.

  When the connection recovery process is started, the peripheral control MPU 4150a of the peripheral control unit 4150 shown in FIG. 15 performs the peripheral control unit power-on process shown in FIG. In the scheduler update process in step S1020, it is determined whether the schedule data for screen generation is being activated among the various schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. S1540). In this determination, in the scheduler update process, out of the screen data arranged in time series constituting the screen generation schedule data, the number of the screen data from the top screen data is to be output to the built-in sound source VDP 4160a. Then, it is determined whether or not the pointer has been updated. In other words, in the scheduler update process, when the pointer is being updated, the presentation is progressing along the screen generation schedule data, so it is determined that the screen generation schedule data is being activated, while the screen generation schedule is When the presentation is completed along with the data and all the pointer updates are completed, it is determined that the screen generation schedule data is not activated. In this determination, the game board side liquid crystal display device 1900 performs a demonstration during a period when the start-up screen at the time of power-on of the pachinko gaming machine 1 is displayed on the game board side liquid crystal display device 1900 or in a waiting state. It is possible to determine whether or not the current period is based on the screen generation schedule data, and the game board side liquid crystal display device 1900 displays a startup screen when the pachinko gaming machine 1 is turned on. If the game board is in a waiting state or a period during which the game board side liquid crystal display device 1900 is demonstrating, the process proceeds to step S1542 described later, while the startup screen when the pachinko gaming machine 1 is turned on is displayed. The period displayed on the game board side liquid crystal display device 1900 and the game board side liquid crystal display device in a waiting state If it is not a period that is doing a demonstration by 1900 the (mere, is when in the standby state of the customer wait), which is as it is to terminate this routine.

  When the production is progressing along the screen generation schedule data in step S1540, that is, when the screen generation schedule data is being activated, this routine is finished as it is, while in step S1540, the screen generation schedule data is followed. When the presentation is completed and the updating of all the pointers is completed, that is, when the screen generation schedule data is not activated, it is determined whether or not the value of the communication check counter CC-CNT is not 0 (step) S1542). As described above, this communication check counter CC-CNT is used for the upper plate side liquid crystal provided in the peripheral control board 4140 in the determination of step S1522 in the process every time the connection failure determination process shown in FIG. 73 is executed. Counts up the number of times that it is determined that there is a problem between the connection between the transmitter IC 4160d and the receiver ICSDIC0 for the upper plate side liquid crystal provided on the touch panel drive substrate 450, that is, the connection between the transmitter and the receiver. (Counting the cumulative number of times). In this determination, it is determined whether or not the number of times when it is determined that the connection between the transmitter and the receiver is in a state where a failure has occurred is even one.

  When the value of the communication check counter CC-CNT is 0 in step S 1542, that is, when the number of times determined that the connection between the transmitter and the receiver is in trouble is not once, this is left as it is. While the routine is finished, the number of times when it is determined in step S1542 that the value of the communication check counter CC-CNT is not 0, that is, the connection between the transmitter and the receiver is in trouble is even once. If there is, it is determined whether or not the value of the communication abnormality flag CC-FLG is 0 (step S1544). As described above, the communication abnormality flag CC-FLG indicates that the cumulative number of times determined that there is a problem in the connection between the transmitter and the receiver has reached the cumulative number upper limit CC-LMT, This flag indicates whether or not there is a problem with the connection between the receiver and the value 1 when the connection between the transmitter and the receiver is definitely defective. When the cumulative number of times determined to be in a state in which the connection has not reached the cumulative number upper limit CC-LMT, the value is set to 0.

  When the value of the communication abnormality flag CC-FLG is 0 in step S1544, that is, the accumulated number of times determined that the connection between the transmitter and the receiver is defective is the accumulated number upper limit value CC-LMT. If not, SYNC pattern output processing is performed (step S1546), and this routine is terminated. In this SYNC pattern output process, the peripheral control MPU 4150a outputs a connection confirmation signal to the INIT terminal of the upper plate-side liquid crystal transmitter IC 4160d provided on the peripheral control board 4140, whereby the upper plate-side liquid crystal provided on the peripheral control board 4140 is provided. The transmitter IC 4160d outputs a predetermined data pattern (SYNC pattern) to the upper plate-side liquid crystal receiver IC SDIC0 provided on the touch panel drive substrate 450. The predetermined data pattern (SYNC pattern) is stored in advance in the upper plate side liquid crystal transmitter IC 4160d and is output to the upper plate side liquid crystal receiver ICSDIC0. The connection between the transmitter IC 4160d and the receiver ICSDIC0 for the upper plate side liquid crystal, that is, the connection between the transmitter and the receiver is recovered.

  On the other hand, when the value of the communication abnormality flag CC-FLG is not 0 (value 1) in step S1544, that is, when there is a certain failure in the connection between the transmitter and the receiver, communication error display processing is performed. (Step S1548), and this routine is finished. In this communication error display processing, the display area of the game board side liquid crystal display device 1900 provided in the game board 4 shown in FIG. 8 is used to notify that the connection between the transmitter and the receiver is surely defective. Process to draw on. For example, in the display area of the game board side liquid crystal display device 1900, a message “A problem has occurred in the upper plate side liquid crystal display device. Please call a clerk” is displayed. Further, in the communication error display process, a period during which the start-up screen at the time of power-on of the pachinko gaming machine 1 is displayed on the game board side liquid crystal display device 1900, or a demonstration by the game board side liquid crystal display device 1900 in a waiting state. Between the connection between the upper plate-side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 and the upper plate-side liquid crystal receiver IC SDIC0 provided in the touch panel drive board 450, that is, the connection between the transmitter and the receiver. In order to confirm whether or not a malfunction has occurred, the operation confirmation request for the upper plate side liquid crystal display device 470 is received from the serial I / O port for the touch panel drive substrate built in the peripheral control MPU 4150a as LOCKN signal output request data. And the receiver ICSDIC0 for the upper plate side LCD As a response signal to the transmission of the OCKN signal output request data, the LOCKN signal is output from the LOCKN terminal to the peripheral control MPU 4150a, and when this LOCKN signal is not input, there is a problem in the connection between the transmitter and the receiver. It is determined that a problem has occurred in the upper plate side liquid crystal display device 470, and a notification image (for example, “There has been a problem with the upper plate side liquid crystal display device. Please call the store clerk”). In addition to performing processing to display in the display area of the game board side liquid crystal display device 1900, a speaker 130 provided on the door frame 5 with a notification sound (for example, “a defect has occurred in the upper plate side liquid crystal display device”), Processes that repeatedly flow from 222, 262, etc. are performed. At this time, you may make it perform the process which lights all the various LEDs mounted in the various decoration board | substrates with which the LED for light emission decoration provided in the door frame 5 and the game board 4 are equipped.

  Next, the timing at which the peripheral control MPU 4150a outputs a connection confirmation signal to the INIT terminal of the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 shown in FIG. 17 will be described with reference to the timing chart of FIG.

  First, the decorative symbols variably displayed in the display area of the game board side liquid crystal display device 1900 provided in the game board 4 shown in FIG. 8 will be briefly described. Peripheral control of the peripheral control unit power-on process shown in FIG. The decorative symbol variation display is executed by a part steady process or the like, and the main control side of the main control side power-on process shown in FIG. 45 by the main control MPU 4100a of the main control board 4100 shown in FIG. The first special lottery result drawn by accepting game balls to the upper start opening 2101 shown in FIG. 8 by the main process or the main control side timer interruption process shown in FIG. 46, or the lower start opening shown in FIG. When the result of the second special lottery drawn by accepting game balls to 2102 is “big hit”, the number of repetitions (number of rounds) of the opening / closing operation of the big prize opening 2103 shown in FIG. The total number of rounds is 15 rounds. In each round, when a game ball enters the winning prize opening 2103 within a predetermined time (for example, 30 seconds), the number of balls reaches a predetermined number (for example, 9). The round is digested, and a predetermined number (for example, 15 balls) of game balls are paid out each time one game ball enters the big prize opening 2103.

  The first special lottery result drawn by accepting the game balls to the upper start port 2101 or the second special lottery result drawn by accepting the game balls to the lower start port 2102 is used as a command from the main control board 4100. Based on this, the peripheral control unit 4150 of the peripheral control board 4140 controls the liquid crystal and sound control unit 4160, so that the left decorative pattern is on the left side of the display area of the game board side liquid crystal display device 1900, the central decorative pattern is in the center, On the right side, the change display of the right decorative design is started, and after the predetermined time has passed, the display of the left decorative design, the central decorative design, and the right decorative design is stopped and the first special lottery result or the second special lottery result is displayed. At this time, the player can recognize the upper special symbol indicator 1185 or the lower special symbol table of the function display unit 1180 shown in FIG. Also in the first special symbol or the second special symbol displayed in vessel 1186 so that the user can confirm the first special lottery result or the second special lottery result. When the left decorative symbol, the central decorative symbol, and the right decorative symbol are displayed variably, the left decorative symbol, the central decorative symbol, and the right decorative symbol are translucent so that the background image can be visually recognized. From the upper left to the lower left of the area, the central decorative symbol rotates from the upper center of the display area to the lower central, and the right decorative pattern rotates from the upper right to the lower right of the display area. When the left decorative symbol, the central decorative symbol, and the right decorative symbol are stopped, the left decorative symbol, the central decorative symbol, and the right decorative symbol correspond to the stopped decorative display. The left decorative design, the central decorative design, and the right decorative design are opaque so that the background image at the position is difficult to see. As described above, the first special symbol or the second special symbol that is displayed in the upper special symbol display 1185 or the lower special symbol display 1186 shown in FIG. The left decorative symbol, the central decorative symbol, and the right decorative symbol that are started and stopped in the display area of the side liquid crystal display device 1900 are synchronized.

  The peripheral control unit 4150 of the peripheral control board 4140 has the first special lottery result drawn by receiving the game ball in the upper start port 2101 or the second special lottery drawn by receiving the game ball in the lower start port 2102. When a command is transmitted from the main control board 4100 that conveys the result, the liquid crystal and sound control unit 4160 is controlled based on the received command, and as shown in FIG. 75, the game board side liquid crystal shown in FIG. When the variable display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started in the display area of the display device 1900 (timing K0), the peripheral control unit steady process of the peripheral control unit power-on process shown in FIG. In the scheduler update process of step S1020 in FIG. 16, the schedule data storage area 4150c of the peripheral control RAM 4150c shown in FIG. Among the screen data arranged in time series constituting the screen generation schedule data set in e, the pointer is used to indicate what number of screen data from the top screen data is to be output to the sound source built-in VDP 4160a. Because it is updated, that is, in the scheduler update process, when the pointer is updated, the production is progressing along the screen generation schedule data, so the screen generation schedule data is being activated, and the screen generation schedule While the data is being activated, that is, until the display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started and stopped, the peripheral control unit power-on process shown in FIG. Connection recovery shown in FIG. 74 in the warning process in step S1024 in the peripheral control unit steady process of FIG. Be executed sense, it is determined in step S1540 in this connection restoration process, and it so as to end the routine forcibly.

  As a result, the communication check counter CC-CNT of the communication check counter CC-CNT is displayed in the display area of the game board side liquid crystal display device 1900 until the variable display of the left decorative design, the central decorative design, and the right decorative design is started and stopped. Even when the value is not 0, that is, between the connection between the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 and the upper plate side liquid crystal receiver IC SDIC0 provided in the touch panel drive board 450 (that is, between the transmitter and the receiver). Connection) between the transmitter and the receiver without performing the SYNC pattern output process of step S1546 in the connection recovery process even if the number of times determined to be in a state where a problem has occurred is one. The connection recovery process is not performed, and the connection recovery process In step S1548, the communication error display process is not performed, and for example, the message “A problem has occurred in the upper liquid crystal display device. Please call the store clerk” is not displayed in the display area of the game board liquid crystal display device 1900. Therefore, the LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 that informs that the drawing data received from the upper plate side liquid crystal transmitter IC 4160d is abnormal data is invalidated, and the upper plate side liquid crystal display The device 470 displays an image based on the drawing data received from the upper plate side liquid crystal transmitter IC 4160d by the upper plate side liquid crystal receiver ICSDIC0.

  When the display of the left decorative symbol, the central decorative symbol, and the right decorative symbol is started and stopped in the display area of the game board side liquid crystal display device 1900 (timing K1), the peripheral control unit shown in FIG. 64 is turned on. In the scheduler update process of step S1020 in the peripheral control unit steady process of the time process, the presentation is completed along the screen generation schedule data set in the schedule data storage area 4150cae of the peripheral control RAM 4150c shown in FIG. Since all the updates have been completed, that is, in the scheduler update process, while the screen generation schedule data is not started and the screen generation schedule data is not started, the peripheral control unit shown in FIG. 64 is turned on. Warning in step S1024 in the peripheral processing unit steady process of time processing In the determination of step S1540 in the connection recovery process shown in FIG. 74 executed as one process of the process, the process proceeds to the process of step S1542 in the process, and when the value of the communication check counter CC-CNT is 0, that is, the transmitter When it is determined that there is no failure in the connection with the receiver, the routine is terminated as it is, but when the value of the communication check counter CC-CNT is not 0, that is, the transmitter If the number of times that the connection between the receiver and the receiver is determined to be in a state where there is a failure is one, the process proceeds to step S1544 in the same process, and the value of the communication abnormality flag CC-FLG is 0. That is, the connection between the transmitter and receiver is faulty. When the accumulated number of times determined to have not reached the accumulated number upper limit value CC-LMT, the process proceeds to step S1546 in the process, the above-described SYNC pattern output process is performed, and the routine ends, while the communication abnormality flag CC-FLG When the value of is not 0 (value 1), that is, when there is a certain failure in the connection between the transmitter and the receiver, the process proceeds to step S1548 in the process, and the communication error display process described above is performed. To complete the routine. In other words, while the left decorative symbol, the central decorative symbol, and the right decorative symbol are stopped and displayed in the display area of the game board side liquid crystal display device 1900, the upper plate side liquid crystal transmitter IC 4160d and the upper plate side liquid crystal receiver are displayed. When there is a failure in the connection between ICSDIC0, that is, between the transmitter and the receiver, even when there is a failure in the connection between the transmitter and the receiver. When the cumulative number determined to be not reached the cumulative number upper limit CC-LMT, the SYNC pattern output process is always performed, so that the connection between the upper plate side liquid crystal transmitter IC 4160d and the upper plate side liquid crystal receiver IC ICDIC0, This means that the connection between the transmitter and receiver is restored, while the transmitter is When the cumulative number of times determined that there is a problem in the connection between the receiver and the receiver has reached the cumulative number upper limit CC-LMT (that is, the connection between the transmitter and the receiver is definitely defective) For example, in the display area of the game board side liquid crystal display device 1900, “There is a problem with the upper plate side liquid crystal display device. Please call the store clerk. LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 that indicates that the drawing data received from the upper plate side liquid crystal transmitter IC 4160d is abnormal data. Has been activated.

  In the display area of the game board-side liquid crystal display device 1900, the left decorative pattern, the central decorative pattern, and the right decorative pattern are started and stopped, and the left decorative symbol, the central decorative symbol, and the right decorative symbol are displayed again. Since the left decorative pattern, the central decorative pattern, and the right decorative pattern are stopped and displayed in the display area of the game board side liquid crystal display device 1900 in the interval period until the game starts, as described above, The LOCKN signal from the receiver ICSDIC0 for the upper plate side liquid crystal that notifies that the drawing data received from the upper plate side liquid crystal transmitter IC 4160d is abnormal data is validated, and the upper plate side liquid crystal transmitter IC 4160d and the upper plate side liquid crystal Trouble occurs between the connection with the receiver ICSDIC0, that is, the connection between the transmitter and the receiver. If the cumulative number of times determined that the connection between the transmitter and the receiver is defective has not reached the cumulative number upper limit CC-LMT. By performing the pattern output process without fail, the process of recovering the connection between the upper side liquid crystal transmitter IC 4160d and the upper side liquid crystal receiver IC ICDIC0, that is, the connection between the transmitter and the receiver is performed. When the cumulative number of times that it is determined that there is a fault in the connection between the two has reached the cumulative number upper limit CC-LMT (that is, the fault between the transmitter and the receiver has definitely occurred) The communication error display process must be performed, so that, for example, the game board side liquid crystal display device 1900 The display region "problem with the upper tray side liquid crystal display device has occurred. Please call your clerk." Displays a message that to have so as to perform the process of informing.

  When the display of the left decorative design, the central decorative design, and the right decorative design is started again (timing K2), as described above, since the screen generation schedule data is being activated, the left decorative design and the central decorative design are activated. And until the right decorative symbol is stopped and displayed (timing K3), even when the value of the communication check counter CC-CNT is not 0, that is, for the upper plate side liquid crystal provided in the peripheral control board 4140. The number of times that it is determined that there is a problem between the connection between the transmitter IC 4160d and the receiver ICSDIC0 for the upper plate side liquid crystal provided in the touch panel drive substrate 450 (that is, the connection between the transmitter and the receiver) is once. Even in this case, the SYNC pattern output process of step S1546 in the connection recovery process is performed. Therefore, the process of recovering the connection between the transmitter and the receiver is not performed, and the communication error display process of step S1548 in the connection recovery process is not performed. For example, the display on the game board side liquid crystal display device 1900 is displayed. Since the message “There was a problem with the upper LCD monitor. Please call the store clerk” is not displayed in the area, the drawing data received from the upper LCD transmitter IC4160d is abnormal data. , The LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 is invalidated, and the upper plate side liquid crystal display device 470 draws the upper plate side liquid crystal receiver ICSDIC0 received from the upper plate side liquid crystal transmitter IC 4160d. Display an image based on the data.

  In this way, the left decorative symbol, the central decorative symbol, and the right decorative symbol are started and stopped in the display area of the game board side liquid crystal display device 1900, and then the left decorative symbol, the central decorative symbol, and the right decorative symbol are displayed again. In the interval period until the change display of the symbol is started, the LOCKN signal from the upper plate side liquid crystal receiver ICSDIC0 is activated to notify that the drawing data received from the upper plate side liquid crystal transmitter IC 4160d is abnormal data. On the other hand, in the display area of the game board side liquid crystal display device 1900, until the variable display of the left decorative design, the central decorative design, and the right decorative design is started and stopped, the transmitter for the upper plate side liquid crystal is displayed. LCD-side receiver ICSD for reporting that drawing data received from IC4160d is abnormal data LOCKN signal from the C0 is adapted to be disabled. This is because the combination result in which the left decorative symbol, the central decorative symbol, and the right decorative symbol are stopped and displayed in the display area of the game board side liquid crystal display device 1900 is the information most interesting to the player, which is beneficial to the player. Since the player can determine whether or not the big hit gaming state to which the game is given is generated, the left decorative design, the central decorative design, and the right decorative design are displayed in a variable manner in the display area of the game board side liquid crystal display device 1900. Then, until the left decorative symbol, the central decorative symbol, and the right decorative symbol are stopped and displayed, the effect image drawn in the display area of the upper dish side liquid crystal display device 470 is disturbed correctly due to the influence of noise or the like. Even if the drawing becomes impossible, the rendering is not interrupted and the process of recovering the drawing correctly is not performed, but the display area of the game board side liquid crystal display device 1900 is left. Decorative symbol, central decorative pattern, and by stopping displaying the right decorative design, and the most interesting of information of the player to complete the drawing.

  In this regard, the peripheral control MPU 4150a of the peripheral control unit 4150 of the peripheral control board 4140 displays a start-up screen when the pachinko gaming machine 1 is turned on on the game board side liquid crystal display device 1900, or a waiting state During the period of demonstration by the game board side liquid crystal display device 1900, the LOCKN signal output request data from the built-in serial I / O port for touch panel drive board is sent to the differential circuit 4160e provided in the peripheral control board 4140. This is very different from the transmission. This LOCKN signal output request data is a demonstration by the game board side liquid crystal display device 1900 during the period when the start-up screen at the time of power-on of the pachinko gaming machine 1 is displayed on the game board side liquid crystal display device 1900, In the period during which the peripheral control MPU 4150a performs, the touch panel drive board serial I / O port built in the peripheral control board 4140 includes the upper plate side liquid crystal transmitter IC 4160d and the touch panel drive board 450. In order to confirm whether or not there is a problem in the connection between the receiver ICSDIC0 for the upper plate side liquid crystal provided in the apparatus, that is, the connection between the transmitter and the receiver, an operation check request for the upper plate side liquid crystal display device 470 Is sent as

  The LOCKN signal output request data, which is serial data output from the serial I / O port for the touch panel drive board built in the peripheral control MPU 4150a, is different from the plus signal and the minus signal in the differential circuit 4160e provided in the peripheral control board 4140. When activated, as described above, the two signals differentiated into the plus signal and the minus signal in the differencing circuit 4160e are input to the forced switching circuit 4160f provided in the peripheral control board 4140. The forcible switching circuit 4160f is connected to the circuit so as to transmit the two signals that are differentiated into the plus signal and the minus signal in the differentiation circuit 4160e. Two signals are transmitted from the peripheral control board 4140 to the touch panel drive board 450 accommodated in the dish unit 300 of the door frame 5. When the receiver ICSDIC0 for the liquid crystal module circuit 450V provided on the touch panel drive board 450 determines that the two received signals are LOCKN signal output request data from the serial I / O port for the touch panel drive board. In the first place, the LOCKN signal output request data is determined to be abnormal data because the data format is different from that of the signal output from the upper plate side liquid crystal transmitter IC 4160d as described above. The data is output to the peripheral control MPU 4150a of the peripheral control unit 4150 of the control board 4140. As a result, the peripheral control MPU 4150a has a problem with the touch panel drive board 450 that the connection between the transmitter and the receiver is not defective when the LOCKN signal is input as a response signal to the transmission of the LOCKN signal output request data. On the other hand, when the LOCKN signal is not input, it is determined that a failure has occurred in the touch panel drive substrate 450 as a failure has occurred in the connection between the transmitter and the receiver. Then, a notification image (for example, “There is a problem with the upper plate side liquid crystal display device. Please call the store clerk”) is transmitted to the game board side liquid crystal display device 1900 by controlling the built-in sound source VDP 4160a. And a notification sound (for example, “ The side liquid crystal display device has a malfunction. ”) Is output to the audio data transmission IC 4160c by controlling the sound source built-in VDP 4160a, and the notification sound flows from the speakers 130, 222, 262, etc. provided on the door frame 5. . Thus, notification can be performed by the notification image displayed in the display area of the game board side liquid crystal display device 1900 and the notification sound that repeatedly flows from the speakers 130, 222, 262, etc. provided on the door frame 5. It has become. At this time, all of the LEDs for light emitting decoration provided in the door frame 5 and the various LEDs mounted on various decoration boards provided in the game board 4 may be turned on.

  As described above, when the peripheral control MPU 4150a of the peripheral control unit 4150 transmits the LOCKN signal output request data that is serial data from the built-in serial I / O port for the touch panel drive substrate, the forced switching circuit 4160f causes the LOCKN signal output request data to be transmitted. Is connected to the upper plate side liquid crystal receiver ICSDIC0, and the upper plate side liquid crystal receiver ICSDIC0 receiving the LOCKN signal output request data receives a response signal from the LOCKN terminal of the upper plate side liquid crystal receiver ICSDIC0. Since the LOCKN signal is output to the peripheral control MPU 4150a, it is assumed that there is no problem in the connection between the transmitter and the receiver when the LOCKN signal is input. Occur On the other hand, when the LOCKN signal is not input, it is determined that a problem has occurred in the connection between the transmitter and the receiver, and a problem has occurred in the upper plate side liquid crystal display device 470. be able to. Then, the peripheral control MPU 4150a can execute the communication error display process of step S1548 in the connection recovery process of FIG. 74 as a notification process when it is determined that a problem has occurred in the upper dish side liquid crystal display device 470. It has become. In other words, when the peripheral control MPU 4150a finds a defect in the upper dish side liquid crystal display device 470, it can notify the store clerk or the like to that effect by executing a notification process. Hall clerk and the like can very easily check whether there is a problem with the upper plate side liquid crystal display device 470 before the player plays a game, and the check does not take time. ing. Therefore, it is possible to find out the trouble of the upper dish side liquid crystal display device 470 without taking time and effort.

  Further, as described above, the LOCKN signal is data in which the drawing data received from the upper plate side liquid crystal transmitter IC 4160d included in the peripheral control board 4140 by the upper plate side liquid crystal receiver ICSDIC0 included in the touch panel drive substrate 450 is abnormal data. If it is determined, it is a signal that is output to notify that, specifically, an upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140, and an upper plate side liquid crystal receiver IC SDIC0 provided in the touch panel drive board 450, , That is, a signal output to request transmission of a predetermined data pattern (SYNC pattern) for confirming (recovering) the connection between the transmitter and the receiver. Is the LCD IC transmitter 416 When the image transmitted from d cannot be received normally, a communication failure occurs between the image communication between the upper plate side liquid crystal receiver ICSDIC0 and the upper plate side liquid crystal transmitter IC 4160d, and the received drawing data becomes abnormal data. Therefore, the LOCKN signal can be output to the peripheral control MPU 4150a of the peripheral control unit 4150. As a result, the peripheral control MPU 4150a to which the LOCKN signal is input outputs a connection confirmation signal indicating that transmission of a predetermined data pattern (SYNC pattern) is started from the upper plate side liquid crystal transmitter IC 4160d to the upper plate side liquid crystal receiver IC ICDIC0. By outputting to the dish-side liquid crystal transmitter IC 4160d, it is possible to eliminate communication problems between image communications. In other words, the peripheral control MPU 4150a can detect the malfunction of the upper dish side liquid crystal display device 470 due to the communication malfunction between the image communications at an early stage, and can act on the upper dish liquid crystal transmitter IC 4160d so as to eliminate the malfunction. It is like that. Therefore, it is possible to suppress a decrease in the player's gaming motivation by discovering and solving the problem of the upper dish side liquid crystal display device 470.

  Furthermore, the receiver ICSDIC0 for the upper plate side liquid crystal that receives the image transmitted from the upper plate side liquid crystal transmitter IC 4160d and outputs the image to the upper plate side liquid crystal display device 470 receives the image transmitted from the upper plate side liquid crystal transmitter IC 4160d. When the reception cannot be performed normally, the effect control microprocessor outputs a LOCKN signal, which is a communication failure occurrence signal indicating that a communication failure has occurred between image communication between the upper plate side liquid crystal receiver ICSDIC0 and the upper plate side liquid crystal transmitter IC 4160d. Since the peripheral control MPU 4150a to which the LOCKN signal is inputted can control the liquid crystal and sound source built-in VDP 4160a in the peripheral control MPU 4150a of a certain peripheral control unit 4150, there is a communication problem. That it has occurred The message “A problem has occurred in the liquid crystal display device on the upper plate. Please call the store clerk” is generated, and the generated image is displayed in the display area of the liquid crystal display device 1900 on the game board for notification. Can be done. In other words, the peripheral control MPU 4150a discovers a failure of the upper plate side liquid crystal display device 470 due to a communication failure between image communications at an early stage, and notifies the player sitting on the front surface of the pachinko gaming machine 1 to that effect. The player can tell the hall clerk, etc., or directly notify the hall clerk who passed by in front of the pachinko machine 1, so that the hall clerk etc. At an early stage, work can be started to solve the problem. Therefore, it is possible to suppress a decrease in the player's willingness to play the game by discovering and solving the problem of the upper plate side liquid crystal display device 470 at an early stage.

  Furthermore, the peripheral control MPU 4150a of the peripheral control unit 4150 includes the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 and the upper plate side provided in the touch panel drive board 450 in the period (interval period) from timing K1 to timing K2. This is a case where there is a failure in the connection between the receiver ICSDIC0 for the liquid crystal, that is, the connection between the transmitter and the receiver even once, and there is a problem in the connection between the transmitter and the receiver. When the accumulated number of times determined to be in the state does not reach the accumulated number upper limit CC-LMT, a predetermined data pattern (SYNC pattern) for validating the LOCKN signal and eliminating a communication malfunction between image communications is displayed. Transmitter IC 4160d for LCD on the upper plate side It is possible to continue to output a connection confirmation signal indicating that transmission is to be started to the upper plate side liquid crystal receiver ICSDIC0 to the upper plate side liquid crystal transmitter IC 4160d until the cumulative number reaches the cumulative number upper limit CC-LMT. It has become. As a result, the peripheral control MPU 4150a of the peripheral control unit 4150 starts changing the first special symbol or the second special symbol game in the upper special symbol display 1185 or the lower special symbol display 1186 by the main control MPU 4100a of the main control board 4100. Since the connection confirmation signal can be continuously output only during the period in which the game is not stopped and the game is not being executed, the communication failure can be solved.

  Then, the peripheral control MPU 4150a of the peripheral control unit 4150 includes the upper plate side liquid crystal transmitter IC 4160d provided in the peripheral control board 4140 and the upper plate side liquid crystal provided in the touch panel drive board 450 in the period (interval period) from timing K1 to timing K2. The connection between the receiver ICSDIC0 and the connection between the transmitter and the receiver has occurred even once, and the connection between the transmitter and the receiver has failed. When the accumulated number of times determined to be in the state does not reach the accumulated number upper limit CC-LMT, the LOCKN signal is validated to increase a predetermined data pattern (SYNC pattern) for eliminating communication problems between image communications. From the dish-side LCD transmitter IC 4160d When the connection confirmation signal that tells the dish-side liquid crystal receiver ICSDIC0 to start transmission is repeatedly output to the upper-plate-side liquid crystal transmitter IC 4160d until the cumulative number reaches the cumulative number upper limit CC-LMT, When the main control MPU 4100a of the main control board 4100 starts changing the first special symbol or the second special symbol game in the upper special symbol display 1185 or the lower special symbol display 1186, and starts executing the game again, a connection confirmation signal When the connection confirmation signal output from the peripheral control MPU 4150a is stopped and no connection confirmation signal is input, the upper plate side liquid crystal transmitter IC 4160d outputs a predetermined data pattern (SYNC pattern) on the upper plate side. LCD and sound control by stopping transmission to the receiver ICSDIC0 for liquid crystal And it is capable of sound built VDP4160a of 4160 to output an image generated on the upper tray side LCD receiver ICSDIC0. As a result, the peripheral control MPU 4150a of the peripheral control unit 4150 starts changing the first special symbol or the second special symbol game in the upper special symbol display 1185 or the lower special symbol display 1186 by the main control MPU 4100a of the main control board 4100. By continuing to output the connection confirmation signal, which is a problem resolution signal, only during the period when the game is not stopped and the progress of the game is not executed, it is possible to move toward a direction in which the communication problem is resolved. Therefore, the main control MPU 4100a of the main control board 4100 starts changing the first special symbol or the second special symbol game on the upper special symbol display 1185 or the lower special symbol display 1186, and stops the display. When the connection confirmation signal is repeatedly output only during the period of not being executed, the main control board 4100 Even if the control MPU 4100a starts to fluctuate the first special symbol or the second special symbol game in the upper special symbol display 1185 or the lower special symbol display 1186 and starts to execute the game again, the upper plate side liquid crystal display device 470 Each time the main control MPU 4100a of the main control board 4100 starts executing the game again and ends (the period from timing K1 to timing K2 (interval period)) It can be made to go in the direction to cancel.

  According to the embodiment as described above, the pachinko gaming machine 1 includes the main control board 4100 of FIG. 12 and the payout control board 4110 of FIG. The main control board 4100 is a start area in which a game ball fired by the hitting ball launcher 650 in FIG. 5 is provided in the game area 1100 toward the game area 1100 defined in the game board 4 in FIG. The main control MPU 4100a of FIG. 12 which is a game control microprocessor for controlling the progress of the game based on the intrusion into the upper start port 2101 and the lower start port 2102 is mounted. The payout control board 4110 controls payout of the game balls by the prize ball device 740 in FIG. 5 based on the prize ball commands in FIGS. 40A and 40B which are payout commands from the main control board 4100. The payout control MPU 4120a of FIG. 13 which is a processor is mounted.

  The main control MPU 4100a, which is a game control microprocessor, includes at least a RAM (main control built-in RAM) built in the main control MPU 4100a. The main control built-in RAM can store information related to the game even after the power is shut off.

  The payout control MPU 4120a, which is a payout control microprocessor, includes at least a RAM (payout control built-in RAM) built in the payout control MPU 4120a. The payout control built-in RAM can store information related to payout even after the power is shut off.

  The pachinko gaming machine 1 of this embodiment further includes an operation switch 860a shown in FIG. If the operation switch 860a is operated within the period during which the determination process of step S16 in the main control side power on process of FIG. 44 is performed after the power is turned on, the information regarding the game stored in the main control built-in RAM is erased. 21 is output from the main control MPU 4100a, which is a game control microprocessor, and the operation is performed during the period in which the determination process of step S512 in the payout control unit power-on process of FIG. 26, a RAM clear function for outputting the RWMCLR signal of FIG. 26 to the payout control MPU 4120a as a payout control microprocessor as a RAM clear signal for erasing information related to payout stored in the payout control built-in RAM, and power-on 44, the main control side power-on process in FIG. When the period of time during which the determination process of step S16 is performed (or the period of time during which the determination process of step S512 in the payout control unit power-on process in FIG. 47 is performed from when the power is turned on) has passed, the prize ball device 740 An error canceling function for outputting the RWMCLR signal of FIG. 26 to the payout control MPU 4120a as the payout control microprocessor without outputting the RWMCLR signal of FIG. It is something that combines.

  As described above, when the operation switch 860a is operated within the period in which the determination process of step S16 in the main control-side power-on process of FIG. 44 is performed from when the power is turned on, the game stored in the main control built-in RAM. 21 is output to the main control MPU 4100a, which is a game control microprocessor, and the determination process of step S512 in the payout control unit power-on process of FIG. 47 is performed from power-on. 26, the RAM clear signal for outputting the RWMCLR signal in FIG. 26 to the payout control MPU 4120a serving as the payout control microprocessor is output as a RAM clear signal for erasing the payout information stored in the payout control built-in RAM. Function and power-on process of main control side in Fig. 44 from power-on Is operated after the period during which the determination process in step S16 is performed (or the period during which the determination process in step S512 in the payout control unit power-on process in FIG. 47 is performed from when the power is turned on) elapses. An error canceling function for outputting the RWMCLR signal of FIG. 26 to the payout control MPU 4120a as the payout control microprocessor without outputting the RWMCLR signal of FIG. Thus, the pachinko gaming machine 1 can be provided with two different functions, a RAM clear function and an error release function, by an operation with one operation switch 860a. Therefore, a RAM clear function and an error cancel function can be provided while contributing to cost reduction.

  By the way, in the pachinko machine 1, as described above, the touch panel 480 is provided on the door frame 5 that can be opened and closed with respect to the main body frame 3 so that the operation surface overlaps the display area of the upper dish side liquid crystal display device 470. The effect control program includes each selected display object image data and operation menu background image data used to display the read selected display object stored in advance in the liquid crystal and sound control ROM 4160b by the sound source built-in VDP 4160a controlled by the peripheral control MPU 4140a. Based on the above, the operation menu screen is displayed on the upper plate side liquid crystal display device 470 (second display device) in a display mode in which at least one selection display object is superimposed on the operation menu background image as shown in FIG. Display object display control means). Specifically, in this operation menu screen, mainly, for example, a volume / light quantity selection display for resetting the volume / light quantity, a bonus selection display object imitating a violent man named “bomb king” wearing sunglasses, and In addition to the word “first pachinko” that draws the line of sight of an unfamiliar pachinko beginner, a selection display for beginners that imitates a game ball is arranged and arranged at almost equal intervals along the horizontal direction, and is arranged almost at the center. The selected display object is displayed slightly larger than the other selected display objects.

  As shown in FIG. 82, the operator touches the contact surface of the touch panel 480 with the finger F at the position of the display area for the beginner-side liquid crystal display device 470 and the selection display object for beginners displayed on the right side, from right to left. When it is slid toward the screen, the effect control program displays the bonus selection display object in a reduced size based on the contact state of the contact surface of the touch panel 480 and expands the selection display object for beginners as a candidate to be selected next, for example. In addition, as shown in FIG. 83, each selected display object is displayed so as to move toward the left.

  Subsequently, when the operator touches the first pachinko selection display object KHB with the finger F as shown in FIG. 84 (hereinafter referred to as “tap”), the effect control program is displayed as described above. Based on the contact position data from the touch panel drive substrate 450 shown in 37, the detection point is specified based on the contact portion corresponding to the contact state of the contact surface of the touch panel 480 (detection point acquisition means). Further, the effect control program is based on the first image based on the annular image data read from the liquid crystal and sound control ROM 4160b (effect control storage unit) at the corresponding detection point in the display area of the upper dish side liquid crystal display device 470. A small initial annular display KHB is displayed at the position of the pachinko selection display (initial display control means).

  Next, as shown in FIG. 86, the effect control program enlarges and displays the word “first pachinko” described above, and allows the player to visually recognize that the first pachinko selection display item has been selected. As shown in FIG. 87, the effect control program reduces the density while leaving an afterimage of the annular display object in the middle of the display mode in which the initial annular display object is continuously enlarged as time passes at the detection point. The next transition destination screen associated with the first pachinko selection display object is displayed while the last annular display object is displayed while being continuously enlarged while the first pachinko selection display object corresponding to the detection point is erased. Display (afterimage display control means).

  In this way, the operator of the touch panel 480 can visually recognize the annular display object KHB displayed on the display area of the upper dish side liquid crystal display device 470 through the contact surface according to his / her own operation. . Here, it is now possible to display precise performances. Generally, even if the touch panel's slow reaction remains, the player is not responding to his / her own operation. It is likely that it will be difficult to work with the psychology of actively participating in the player participation type production. However, according to the present embodiment, even if a fine presentation display is possible, an afterimage of the annular display object KHB remains according to the operation of the operator, so that the operator can operate even if the response to the operation is slightly delayed. It can be visually confirmed that the response to is reliably made.

  By the way, the afterimage display as described above is not always performed on the upper platen side liquid crystal display device 470, but the effect control program executes an error canceling navigation command (second error message associated with the operation of the payout control board 4110 operation switch 860a). When the release command is received from the main control board 4100, it may be temporarily switched to a test mode for confirming the operation of the upper plate side liquid crystal display device 470 and then executed. That is, the effect control program normally does not execute the afterimage display using the upper plate side liquid crystal display device 470, but when the operation switch 860a is operated, the operation switch 860a is then switched to the test mode to execute the afterimage display. You may do it. In this case, the effect control program controls to switch from the test mode to the normal mode when the operation switch 860a is operated again. In this manner, according to the convenience of the operator, the display operation of the upper plate side liquid crystal display device 470 is temporarily tested (for example, at the time of shipment of the pachinko machine 1) in the test mode, or the upper plate side liquid crystal display device 470 is operated. Afterimage display can be performed constantly as part of the production using the.

  On the other hand, on the operation menu screen as shown in FIG. 88, the operator touches the touch panel 480 corresponding to the volume adjustment selection display displayed in the display area of the upper plate side liquid crystal display device 470 as shown in FIG. When the face is selected by tapping, the effect control program displays a small initial annular display KHB as shown in FIG. 90 based on the contact portion based on the contact state. The effect control program displays the final annular display object KHB as shown in FIG. 91 through the annular display object KHB in the middle of the display mode in which the initial annular display object KHB is continuously enlarged (final display). Control means). That is, the production control program expands the annular display object KHB from the initial annular display object KHB to the final annular display object KHB, for example, in a stepless manner, or, for example, displays the annular display in stages in 10 steps. You may make it enlarge the thing KHB.

  If it does in this way, as above-mentioned, the operator of the touch panel 480 will permeate | transmit the contact surface according to own operation, and will visually recognize the cyclic | annular display thing displayed on the display area of the upper side liquid crystal display device 470. be able to. Here, if there is still a dull response in the present day where precise production display is possible, when it becomes possible to realize more precise production display in the future, such detailed production display and On the other hand, at first glance, it may be possible to give the player a relatively uncomfortable feeling. However, according to the present embodiment, the appearance (display) of the annular display object displayed on the display area of the upper dish side liquid crystal display device 470 triggered by touching the contact surface of the touch panel 480 is used to accurately detect vision. Therefore, even if it becomes possible to realize a more detailed presentation display in the future, it is possible to make it difficult for the operator to feel uncomfortable by a direct response to the operation.

  On the other hand, similarly, on the operation menu screen as shown in FIG. 88, the operator touches the volume adjustment selection display displayed in the display area of the upper dish side liquid crystal display device 470 as shown in FIG. When the contact surface 480 is selected by tapping, the effect control program determines that the contact area of the contact portion based on the contact state is larger than a predetermined contact area (that is, when the pressing force is strong), FIG. As shown in FIG. 91, after displaying or without displaying the small initial annular display KHB, at least a part of the intermediate annular display KHB is omitted, and the final annular display KHB is displayed as shown in FIG. You may make it display. When the pressing force is strong as described above, the initial annular display object KHB in the display area that is visible through the contact surface of the touch panel 480 by the operator's finger, or further, the partial annular display object in the middle of the part. Although the KHB is also hidden, the production control program reduces the wasteful display that the player cannot visually recognize and reduces the processing burden by omitting the display control of some of the annular display objects KHB in this way. can do.

  After the final annular display object KHB is displayed as described above, the effect control program reads the volume from 1 to 6 as shown in FIG. 92 based on the tone adjustment background image data read from the liquid crystal and the sound control ROM 4160b. A volume adjustment background image including the scale VSCL and a volume adjustment icon OCI with a musical note mark based on the volume setting icon image data read out from the liquid crystal and sound control ROM 4160b is slidably superimposed along the volume scale VSCL. The mode volume adjustment screen is displayed.

  When the operator taps the volume adjustment icon OCI on the volume adjustment screen with his / her finger F and slides it to the left as shown in FIG. 92, the effect control program drives the touch panel shown in FIG. 37 as described above. Based on the contact position data from the substrate 450, a detection point is specified based on the contact portion based on the contact state (detection point acquisition means), and the corresponding point in the display area of the upper plate side liquid crystal display device 470 (second display device). Based on the annular image data read from the liquid crystal and sound control ROM 4160b, a small initial annular display object KHB is first displayed at the detection point (initial display control means).

  Further, when the operator slides the volume adjustment icon OCI with the finger F along the volume scale VSC as shown in FIG. 93, the effect control program causes the touch from the touch panel drive board 450 as shown in FIG. Based on the position data, a movement locus of a position where the contact portion based on the contact state is present (hereinafter referred to as an initial position) is detected for each movement detection point (movement locus acquisition means). Next, as shown in FIG. 93, the production control program continuously and independently expands the initial annular display object KHB with the passage of time at each movement detection point along the detected movement trajectory. The final annular display object KHB is displayed via the intermediate display object KHB in the display mode (movement trajectory display control means). At this time, as shown in FIG. 94, the effect control program moves and displays the volume adjustment icon OCI to slide along the volume scale according to the slide of the finger F tapping the volume adjustment icon OCI, and finally displays it. As shown in FIG. 95, similarly, the display mode is such that the volume adjustment icon OCI is moved to the position of the finger F that has been slid through the display of the annular display object in the middle. When the operator removes the finger F from the contact surface of the touch panel 480, the presentation control program eliminates any contact object based on the contact position data from the touch panel drive board 450, and as shown in FIG. In the vicinity of the contact surface, a final enlarged display object is displayed.

  In this way, as described above, the operator of touch panel 480 visually recognizes annular display object KHB that is transmitted through the contact surface and displayed in the display area of upper plate side liquid crystal display device 470 according to his / her own operation. can do. Therefore, at each movement detection point along the movement trajectory of the contact portion on the contact surface by the operation of the operator, the final display is performed via the annular display object KHB in the middle each represented as an afterimage of the initial annular display object KHB. Since the annular display object KHB is displayed, it is not necessary for the operator to memorize the latest operation history along the movement locus one by one, and it becomes difficult to feel stress during operation.

  By the way, the above-described effect control program may be controlled so as to increase the size of the final annular display object KHB in proportion to the maximum width of the contour area of the contact portion based on the touch state of the touch panel 480 described above. Good (final display control means, afterimage display control means, movement trajectory display means). Specifically, the effect control program relatively increases the size of the final annular display object KHB when the contour area is relatively large, whereas the final control display program finalizes when the contour area is relatively small. The size of the annular display object KHB is relatively reduced. In this case, the size of the final annular display KHB is proportional to the pressing force of the contact surface by the operator. Can be recognized.

  Instead or in combination, this effect control program controls, for example, the enlargement mode of the final annular display object KHB in proportion to the change per unit time of the contour area in the contact portion based on the touch state of the touch panel 480 described above. You may make it (final display control means, afterimage display control means, movement locus display means). Specifically, when the change in the contour area per unit time is large, the size of the annular display object KHB on the way is changed in a relatively short time, while the contour area per unit time is changed. When the change is small, the size of the annular display object KHB on the way is changed in a relatively long time. In this way, when the operator touches the contact surface in a relatively short time, the annular display KHB expands relatively quickly, whereas when the operator touches the contact surface in a relatively long time, the annular display The object KHB expands relatively slowly, so that the response of the touch panel 480 according to the operation mode of the operator can be more accurately inspected, and the player operates an object in the real world. A feeling of operation closer to the feeling of operation at the time can be obtained.

[18. Screen displayed in the display area of the liquid crystal display device on the game board side]
Next, a screen displayed in the display area of the game board side liquid crystal display device 1900 provided in the game board 4 shown in FIG. 8 will be briefly described with reference to FIG. 97 and FIG. The screen displayed in the display area of the game board side liquid crystal display device 1900 is the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 shown in FIG. Displayed by executing the control unit steady process or the like. Thereby, various effects are advanced in the display area of the game board side liquid crystal display device 1900. Here, first, an effect such as a variable display displayed in the display area of the game board side liquid crystal display device 1900 will be described, and then a firing operation defect notification effect displayed in the display area of the game board side liquid crystal display device 1900 will be described. explain. FIG. 97 is a diagram showing an example of a variable display effect displayed in the display area of the game board side liquid crystal display device, and FIG. 98 is an example of a firing operation defect notification effect displayed in the display area of the game board side liquid crystal display device. FIG.

[18-1. Effects such as variable display displayed in the display area of the liquid crystal display device on the game board side]
First, an image such as a variable display displayed in the display area of the game board side liquid crystal display device 1900 will be described with reference to FIG. FIG. 8 shows the main control side main process of the main control side power-on process shown in FIG. 45 by the main control MPU 4100a of the main control board 4100 shown in FIG. 12, the main control side timer interrupt process shown in FIG. The first special lottery result drawn by receiving the game ball into the upper start opening 2101 or the second special lottery result drawn by receiving the game ball into the lower start opening 2102 shown in FIG. Then, the number of repetitions (number of rounds) of the opening / closing operation of the grand prize opening 2103 shown in FIG. 8 is 15 rounds from 1 round to 15 rounds, and in each round within a predetermined time (for example, 30 seconds), When a game ball enters the big prize opening 2103 and the number of balls reaches a predetermined number (for example, nine), the round is digested. There every 1 sphere entering sphere, a predetermined number (e.g., 15 balls) so that the game balls are paid out for.

  The first special lottery result drawn by accepting game balls to the upper start port 2101 or the second special lottery result drawn by accepting game balls to the lower start port 2102 is shown in FIG. 41 from the main control board 4100. 97 (a), the peripheral control unit 4150 of the peripheral control board 4140 shown in FIG. 15 controls the liquid crystal and sound control unit 4160 based on the effect commands related to the game effects, which are various commands shown in FIG. As described above, the display of the decorative pattern 1950a is started on the left side of the display area of the gaming board side liquid crystal display device 1900, the decorative pattern 1950b is started in the center, and the decorative pattern 1950c is started on the right side. The fluctuation display of ˜1950c is stopped, and the player can recognize the first special lottery result or the second special lottery result. At this time, even in the first special symbol or the second special symbol displayed on the upper special symbol indicator 1185 or the lower special symbol indicator 1186 shown in FIG. Two special lottery results can be confirmed. When the decorative symbols 1950a to 1950c are variably displayed, the decorative symbols 1950a to 1950c are translucent to the extent that the background image can be visually recognized, and the decorative symbol 1950a extends from the upper left to the lower left of the display area. Is displayed variably from the upper center of the display area toward the lower center, and the decorative pattern 1950c is variably displayed as if the reels are rotating from the upper right to the lower right of the display area. Yes.

  Specifically, in the peripheral control unit command reception interrupt processing of FIG. 67, the effect control program executed by the peripheral control MPU 4150a receives various commands from the main control board 4100. Then, in the received command analysis process of step S1022 in the peripheral control part steady process of the peripheral control part power-on process of FIG. 64, the effect control program analyzes various commands received in the peripheral control part command reception interrupt process of FIG. I do. If the analyzed command is, for example, a special figure 1 synchronized production start command classified as related to the special figure 1 synchronous production shown in FIG. 41, the production pattern shown in FIG. The display control schedule data, the light emission mode generation schedule data, the sound generation schedule data, the electrical drive source schedule data, etc., set in the variable display mode of the decorative symbols 1950a to 1950b shown in FIG. The data is extracted from the various control data copy areas 4150ce of the peripheral control ROM 4150b or the peripheral control RAM 4150c of 4150 and set in the schedule data storage area 4150cae of the peripheral control RAM 4150c.

  For example, the screen generation schedule data set in the variable display mode of the decorative symbols 1950a to 1950b is extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c, and the schedule of the peripheral control RAM 4150c. When set in the data storage area 4150cae, the pointer is updated in the scheduler update process in step S1020 in the peripheral control part steady process of the peripheral control part power-on process in FIG. 64, and in the display data creation process in step S1030 in the same process Of the screen data arranged in time series constituting the screen generation schedule data, the screen data indicated by the pointer is used as the peripheral control ROM 4150b or the peripheral control RAM of the peripheral control unit 4150. Extracted from 150c various control data copy area 4150ce outputs to the tone generator built VDP4160a. When the screen data is input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a extracts character data from the liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data, thereby playing the game board side liquid crystal display device Drawing data for one screen (one frame) to be displayed on 1900 is generated on the built-in VRAM. Then, in the display data output process of step S1016 in the same process, the effect control program stores the drawing data for one screen (one frame) generated on the built-in VRAM of the built-in sound source VDP 4160a by the above-described display data creation process. The VDP 4160a outputs to the game board side liquid crystal display device 1900 from the channel CH1 shown in FIG. Accordingly, the variable display screens of the decorative symbols 1950a to 1950b are displayed as the game effects shown in FIG. 97A in the display area of the game board side liquid crystal display device 1900.

  As shown in FIG. 97 (a), after the predetermined time has elapsed since the change display of the decorative symbols 1950a to 1950c is started, the stop symbols of the decorative symbols 1950a to 1950c are stopped and displayed with the same decorative symbol. It becomes "big hit". On the other hand, as shown in FIG. 97 (a), after the predetermined time has elapsed since the change display of the decorative symbols 1950a to 1950c is started, as shown in FIG. 97 (b), the stop symbols of the decorative symbols 1950a to 1950c are displayed. If it is not stopped and displayed with the same decorative design, it will be “out”.

  When a state in which the game ball does not enter the upper start opening 2101 and the lower start opening 2102 continues and the state where the retained balls are digested to become zero is continued for a predetermined time (for example, in this embodiment, 60 seconds) In FIG. 97 (c), a demonstration screen, which is a screen waiting for customers, is displayed in the display area of the game board side liquid crystal display device 1900. At this time, sound effects and music are set to mute. Then, when the demonstration screen is displayed in the display area of the game board side liquid crystal display device 1900 by a predetermined number of times (for example, 15 times in the present embodiment), the display proceeds to the power saving mode, and the game board side liquid crystal is displayed. A state in which nothing is displayed in the display area of the display device 1900 (that is, a state in which a black screen is formed) is achieved. At this time, various lamps provided on the door frame 5 shown in FIG. 2 and various lamps provided on the game board 4 are also turned off.

[18-2. Launching operation failure notification effect displayed in the display area of the game board side liquid crystal display device]
Next, the firing operation defect notification effect displayed in the display area of the game board side liquid crystal display device 1900 will be described. When the player sits on the front surface of the pachinko gaming machine 1 and starts the game by rotating the front of the rotary handle body 506 shown in FIG. 7, for some reason, the payout control shown in FIG. The status acquired by the payout control MPU 4120a from the fired ball feed failure monitoring circuit 4120ah, which indicates that a failure has occurred in the fired ball feed control circuit 4120ag built in the payout control MPU 4120a of the payout control unit 4120 of the substrate 4110. If it discriminate | determines from information, in order to forcibly stop the launch control of the game ball by the launch ball feed control circuit 4120ag, a launch operation prohibition is set for the launch ball feed control circuit 4120ag, and a message to that effect is sent to the main control board 4100. I have come to tell you. The main control board 4100 informs the peripheral control board 4140 that it is in a firing operation prohibited state, so that the peripheral control board 4140 has a launch operation failure in the display area of the game board side liquid crystal display device 1900 as shown in FIG. As a notification effect, a screen for notification of a firing operation failure is displayed.

  Specifically, the payout control program in the payout control unit error check process in step S557 of the payout control unit main process in the payout control unit power-on process of FIG. Status information is acquired from the monitoring circuit 4120ah, and it is determined whether or not a problem has occurred in the firing ball feed control circuit 4120ag. As described above, the firing ball feed failure monitoring circuit 4120ah determines whether or not a failure has occurred in the firing ball feed control circuit 4120ag that performs the launch control by the launch solenoid 654 and the ball feed control by the ball solenoid 585. Monitoring is performed, and the monitoring result (whether or not a defect occurs) can be stored and held as status information. The payout control program obtains status information from the launching ball sending defect monitoring circuit 4120ah to determine whether or not the launching ball sending control circuit 4120ag has a problem. When the payout control program obtains the status information from the launching ball feed failure monitoring circuit 4120ah and determines that there is no malfunction in the launching ball feed control circuit 4120ag, the launch ball sending control circuit 4120ag performs the launch control of the game ball. In order to start, the launching operation permission is set for the launching ball feed control circuit 4120ag, and the launching operation permission information indicating that the launching operation is permitted is stored in the state information storage area of the payout control built-in RAM. When it is determined that a problem has occurred in the ball-feeding control circuit 4120ag, the launching ball-feeding control circuit 4120ag is prohibited from launching in order to forcibly stop the game ball launch control by the launching ball-feeding control circuit 4120ag. Built-in discharge control prohibition information that informs you that the launch operation is prohibited It is stored in the state information storage area of the AM.

  And in the command transmission process of step S566 in the process, when the payout control program reads the firing operation permission information from the state information storage area of the payout control built-in RAM, it is shown in FIG. A 1-byte (8-bit) frame status 2 command (set to 0 in B0 to notify that there is no error in the shot-ball feeding control circuit) that is divided into status indications is created and transmitted to the main control board 4100 If the firing operation prohibition information is read from the state information storage area of the payout control built-in RAM, the frame state 2 of 1 byte (8 bits) divided into the state display shown in FIG. 43 based on the launch operation prohibition information. Create a command (set a value of 1 to B0 to indicate that it is a shot ball feed control circuit error) and send it to the main control board 4100

  In the frame command reception process of step S110 in the main control timer interrupt process of FIG. 46, when the main control program receives a 1-byte (8-bit) frame state 2 command classified into the status display shown in FIG. A 2-byte (16-bit) command is formed into a frame status 2 command that is divided into status displays shown in FIG.

  In the peripheral control board command transmission process of step S120 in the same process, the main control program reads the transmission information from the transmission information storage area of the main control built-in RAM and transmits this transmission information to the peripheral control board 4140.

  In the peripheral control unit command reception interrupt process of FIG. 67, the effect control program receives various commands from the main control board 4100. Then, in the received command analysis process of step S1022 in the peripheral control part steady process of the peripheral control part power-on process of FIG. 64, the effect control program analyzes various commands received in the peripheral control part command reception interrupt process of FIG. I do. If the analyzed command is a frame state 2 command that is divided into the status display shown in FIG. 42, and if it is a message that informs that there is no error in the firing ball feed control circuit, then While the process proceeds to step S1024, which is a step, if it is to notify that there is an error in the firing ball transport control circuit, it is set to the firing operation failure notification mode for executing the firing operation failure notification, for screen generation Schedule data, light emission mode generation schedule data, sound generation schedule data, electrical drive source schedule data, and the like are extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c Schedule data storage area 41 of the control RAM 4150c It is set to 0cae.

  For example, the screen generation schedule data and sound generation schedule data set in the firing operation failure notification mode are extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or various control data copy areas 4150ce of the peripheral control RAM 4150c, and the peripheral control RAM 4150c. When the schedule data storage area 4150cae is set, the pointer is updated in the scheduler update process in step S1020 in the peripheral control part steady process of the peripheral control part power-on process in FIG. 64, and the display data creation in step S1030 in the process is performed. In the processing, among the screen data arranged in time series constituting the screen generation schedule data, the screen data indicated by the pointer is used as the peripheral control ROM 4150b of the peripheral control unit 4150 or the peripheral control. Extracted from various control data copy area 4150ce of AM4150c outputs to the tone generator built VDP4160a. When the screen data is input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a extracts character data from the liquid crystal and sound control ROM 4160b based on the input screen data to create sprite data, thereby playing the game board side liquid crystal display device Drawing data for one screen (one frame) to be displayed on 1900 is generated on the built-in VRAM. Then, in the display data output process of step S1016 in the same process, the effect control program stores the drawing data for one screen (one frame) generated on the built-in VRAM of the built-in sound source VDP 4160a by the above-described display data creation process. The VDP 4160a outputs to the game board side liquid crystal display device 1900 from the channel CH1 shown in FIG. As a result, a firing operation failure notification screen is displayed as a launch operation failure notification effect shown in FIG. 98 in the display area of the game board-side liquid crystal display device 1900.

  Also, the screen generation schedule data and sound generation schedule data set in the firing operation failure notification mode are extracted from the peripheral control ROM 4150b of the peripheral control unit 4150 or the various control data copy areas 4150ce of the peripheral control RAM 4150c, and the peripheral control RAM 4150c. Is set in the schedule data storage area 4150cae, the pointer is updated in the scheduler update process in step S1020 in the process, and in the sound data creation process in step S1032 in the process, the time series constituting the sound generation schedule data Of the arranged sound command data, the sound command data pointed to by the pointer is copied to various control data copy areas of the peripheral control ROM 4150b or the peripheral control RAM 4150c of the peripheral control unit 4150. Extracted from 150ce output to the sound source built VDP4160a. In the sound data output process of step S1018 in the same process, the sound data such as music and sound effects set in the sound source built-in VDP 4160a in the sound data creation process described above is output to the audio data transmission IC 4160c as serialized audio data. In addition to music and sound effects, the sound data of notification sound and notification sound is output to the audio data transmission IC 4160c as serialized audio data. As a result, a voice saying “A launch failure has occurred. Please call a staff member” is received by the speaker housed in the speaker box 820 provided in the main body frame 3 shown in FIG. 5 and the door frame 5 shown in FIG. It will flow repeatedly from the provided speaker 130.

  In this manner, the payout control MPU 4120a determines whether or not a malfunction has occurred in the built-in launching ball feed control circuit 4120ag from the status information stored and held by the built-in launching ball feed malfunction monitoring circuit 4120ah. When it is determined that a problem has occurred in the firing ball feed control circuit 4120ag, the firing ball feed control circuit 4120ag is set in a firing operation prohibited state, and via the main control board 4100 (main control MPU 4100a). 42, since it can be transmitted to the peripheral control MPU 4150a as a frame state 2 command shaped into 2 bytes (16 bits) divided into the status display of FIG. 42, the peripheral control MPU 4150a is displayed by the game board side liquid crystal display device 1900 as shown in FIG. You can now control the progress of the launch operation failure notification effect You have me. As described above, it is difficult to adjust the drive current for launching (launching) the game ball toward the game area 1100 based on the operation signal from the potentiometer 512, as described above, as a problem in the shot ball feed control circuit 4120ag. In this case, the operation signal from the potentiometer 512 is changed into a highly turbulent signal due to the influence of noise, and it is not possible to specify the drive current for launching (launching) the game ball toward the game area 1100. When it is difficult to adjust the drive current, the detection signal from the touch switch 516 is changed into a very distorted signal due to the influence of noise, and the palm or finger of the player touches the front 506 of the rotating handle body. If it is difficult to determine whether or not the detection signal from the firing stop switch 518 is In addition to the case where it becomes difficult to determine whether or not the launching (launching) of the game ball has been forcibly stopped by the player's will due to the influence of the player, When the sending control circuit 4120ag itself is destroyed for some reason and cannot be used, or when the number of game balls launched (launched) toward the game area 1100 per predetermined time exceeds a predetermined number ( In this embodiment, the number of game balls launched (launched) per 1 minute toward the game area 1100 may exceed 100.

  As a malfunction in the shot ball feed control circuit 4120ag, for example, a driving current for launching (shooting) a game ball toward the game area 1100 by converting the operation signal from the potentiometer 512 into a signal that is extremely disturbed by the influence of noise. 8 cannot be specified and it is difficult to adjust the drive current, it becomes impossible to obtain a stable firing intensity. Therefore, the upper start port provided in the game area 1100 shown in FIG. The entrance rate of game balls to 2101 cannot be stabilized, and the game is continued in a disadvantageous state for the player. Therefore, in the present embodiment, when a problem occurs in the launch ball feeding control circuit 4120ag built in the payout control MPU 4120a and the game ball is fired by the hitting ball launching device 650, it becomes a disadvantageous state for the player. The pachinko gaming machine 1 continues the game by automatically stopping the launching by the hitting ball launching device 650 by setting the launching operation prohibited state to the launching ball feeding control circuit 4120ag built in the payout control MPU 4120a. Can be difficult. Therefore, it is possible to prevent the game from continuing while being in a disadvantageous state for the player that a problem has occurred.

  According to the pachinko gaming machine 1 of the present embodiment described above, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 in FIG. The peripheral control MPU 4150a can display effect images based on various commands shown in FIGS. 41 and 42 from the main control MPU 4100a on the main control board 4100 in FIG. 12 as main control means for controlling the progress of the game. The progress of effects by the game board side liquid crystal display device 1900 of FIG. 10 and the movable liquid crystal display devices 1925a to 1925d of FIG. 10 can be controlled as display means.

  In the pachinko gaming machine 1 of the present embodiment, the liquid crystal and sound control ROM 4160b of the liquid crystal and sound control unit 4160 in the peripheral control board 4140 in FIG. 17 as the material image data storage means, and the peripheral control board 4140 in FIG. 31 as the image generation means. And a sound source built-in VDP 4160a of the sound control unit 4160. The liquid crystal and sound control ROM 4160b is a game board side character data as a plurality of material image data constituting an effect image to be respectively displayed on the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d as a plurality of display means. Can be stored in advance. The sound source built-in VDP 4160a generates rendering data of the effect image and stores it as a storage means in the built-in VRAM of the sound source built-in VDP 4160a. This can be simultaneously output to the even channel of channel CH1 in VDP 4160a and the odd channel of channel CH1 in built-in sound source VDP 4160a as the second signal transmission path.

  The peripheral control MPU 4150a uses the first of the game board-side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d as a plurality of display means in the display data creation processing in step S1030 in the peripheral control unit power-on processing of FIG. Drawing data of effect images to be displayed on the game board side liquid crystal display device 1900 as display means included in the system is necessary material image data from a plurality of material image data stored in advance in the liquid crystal and sound control ROM 4160b as material image data storage means. By extracting the game board side character data as follows, the vertical width of the large original image MVD0 for drawing in the display area of the game board side liquid crystal display device 1900 of FIG. 32A as the first system vertical width: 600 dots The horizontal width for the first system of the game board side liquid crystal display device 1900 of FIG. The large original image MVD0 for drawing in the display area has a horizontal width of 800 dots. The large drawing for drawing in the display area of the game board side liquid crystal display device 1900 in FIG. The control for generating the original image MVD0 and storing it in the built-in VRAM of the built-in sound source VDP 4160a as the storage means can be performed on the built-in sound source VDP 4160a as the image generating means, and the game board side serves as a plurality of display means. Drawing of effect images to be displayed on the movable liquid crystal display devices 1925a to 1925d as the display means included in the remaining second system excluding the display means included in the first system among the liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d. Data is stored in advance in the liquid crystal and sound control ROM 4160b as material image data storage means. By extracting the game board side character data as necessary material image data from a number of material image data, the vertical width for the second system is drawn in the display area of the movable liquid crystal display devices 1925a to 1925d in FIG. Each of the original images SVDA0 to SVDD0 has a vertical width of 204 dots, and the original images SVDA0 to SVDD0 to be drawn in the display area of the movable liquid crystal display devices 1925a to 1925d in FIG. Large original images SVDA0 to SVDD0 to be drawn in the display areas of the movable liquid crystal display devices 1925a to 1925d in FIG. 32 as second-system original drawing data each having a horizontal width of 360 dots are generated, and a sound source is incorporated as a storage means. A sound source built-in VDP 41 using the control stored in the built-in VRAM of the VDP 4160a as an image generating means. 60a (original drawing data generation control means).

  The peripheral control MPU 4150a uses the horizontal width of the large original image MVD0 as the horizontal width for the first system of the large original image MVD0 as the original drawing data for the first system in the display data creation process in step S1030 in the peripheral controller power-on process of FIG. : Among the 800 dots, the horizontal width of the large original image MVD0 as the width for the first system: 2 rows (in other words, two or more predetermined rows in order from the first row to the last row constituting the 800 dots) As the first drawing original drawing data, the width of the large original image MVD0 as the total number of columns constituting the first original horizontal width of the large original image MVD0: As a plurality of columns determined in advance to a value 800 of 800 dots The extension shown in FIG. 32 (b) as the extension drawing data for the first system having 1600 dots as the number of columns obtained by multiplying two columns (that is, twice). An image MVD1 is generated and the predetermined slit-like odd-numbered mask pattern of FIG. 33 (d) is masked as a predetermined slit-like odd-numbered mask pattern. The sound source built-in VDP 4160a can be controlled as an image generating means so as to store the even-numbered addresses, and the large original image as the horizontal width for the second system of the large original images SVDA0 to SVDD0 as the original drawing data for the second system Each horizontal width of SVDA0 to SVDD0: 360 dots among the horizontal widths for the second system, each horizontal width of large original images SVDA0 to SVDD0: 360 dots in order from the first column to the last column The original drawing for the second system by extending it to 2 rows (ie, 2 times) as a predetermined number of rows The horizontal width of each of the large original images SVDA0 to SVDD0 as the total number of columns constituting the horizontal width for the second system of the large original images SVDA0 to SVDD0 as data: Multiply two columns as a plurality of predetermined columns by a value 360 of 360 dots (that is, The stretched images SVDA1 to SVDD1 of FIG. 32 (e) are generated as the extended drawing data for the second system having 720 dots as the number of columns multiplied by 2), and FIG. The image forming means controls the VDP 4160a with built-in sound source so as to store the odd-numbered columns remaining after masking the predetermined slit-shaped even-numbered line mask patterns as the storing means at the odd addresses in the built-in VRAM of the sound source VDP 4160a. (Expanded drawing data generation control means).

  Peripheral control MPU 4150a, in the display data output process of step S1016 in the peripheral controller power-on process of FIG. 64, stretched image as the first system stretched drawing data stored in the even address of the built-in VRAM of sound source built-in VDP 4160a The MVD1 is output from the even channel of the channel CH1 in the sound source built-in VDP 4160a as the first signal transmission path as the rendering data of the effect image displayed on the game board side liquid crystal display device 1900 as the display means included in the first system. Is displayed on the game board side liquid crystal display device 1900 as the display means, and the effect image stored in the even address of the built-in VRAM of the built-in sound source VDP 4160a as the storage means is displayed on the sound source built-in VDP 4160a as the image generating means. In addition, the expanded images SVDA1 to SVDD1 can be used as the display means included in the second system as the second system extended drawing data stored in the odd address of the built-in VRAM of the sound source built-in VDP 4160a as the storage means. Movable liquid crystal display devices 1925a to 1925a as display means included in the second system are output as odd-numbered channels of channel CH1 in sound source built-in VDP 4160a as the second signal transmission path as rendering data for rendering images displayed on liquid crystal display devices 1925a to 1925d. In 1925d, control for displaying the effect image stored in the odd address of the built-in VRAM of the sound source built-in VDP 4160a as the storage means can be performed on the sound source built-in VDP 4160a as the image generation means (drawing data). Data output control means).

  The peripheral control MPU 4150a uses the horizontal width of the large original image MVD0 as the horizontal width for the first system of the large original image MVD0 as the original drawing data for the first system in the display data creation process in step S1030 in the peripheral controller power-on process of FIG. : Out of 800 dots, the horizontal width of the large original image MVD0 as the first system width: When extending from the first row constituting the 800 dots to the last row one by one in order as a plurality of predetermined rows The width of the original image MVD0 as the width for the first system: When one column of the last column constituting 800 dots is extended to two columns as a plurality of predetermined columns, a plurality of expanded columns (that is, One column is not overwritten by two extended columns), and one of the other columns following the one column is set as a predetermined plurality of columns. When extended to a column, one column is overwritten by a plurality of extended columns (that is, two extended columns), and the horizontal width of the large original image MVD0: the last column constituting 800 dots is previously set as the first system horizontal width. When extending to two columns as a predetermined plurality of columns, the last column constituting 800 pixels is overwritten as the width of the first original image MVD0 as the first system width by the extended plurality of columns (that is, two extended columns). Thus, the large original image MVD0 is extended as the first drawing original drawing data stored in the built-in VRAM of the sound source built-in VDP 4160a as the storage means, and the large original image MVD0 is stored as the first drawing original drawing data in the sound generator built-in VDP 4160a. In addition to deleting from the built-in VRAM (that is, to the built-in VRAM of the sound source built-in VDP 4160a as a storage means) Extending the large original image MVD0 as the original original drawing data for the first system and deleting the large original image MVD0 as the first original drawing data from the built-in VRAM of the sound source built-in VDP 4160a) A stretched image MVD1 is generated as the drawing data, and the predetermined slit-like odd-numbered mask pattern of FIG. 33 (d) is overlaid and masked as a predetermined slit-like odd-numbered-mask pattern as shown in FIG. 32 (c). The grid-processed image MVD2 processed into a grid shape so that only a plurality of strip-shaped images corresponding to the even-numbered dot rows that can be specified by the even-numbered address remain as the storage means to the even-numbered address of the built-in VRAM of the built-in sound source VDP 4160a Control the VDP 4160a with a built-in sound source as an image generation means so that it is memorized. The horizontal width of each of the large original images SVDA0 to SVDD0 as the horizontal width for the second line of the large original images SVDA0 to SVDD0 as the second drawing original drawing data: The horizontal width of each of the large original images SVDA0 to SVDD0 as the horizontal width for the second system, when extending to two rows as a predetermined number of rows one by one from the first row constituting the 360 dots toward the last row The horizontal width of each of the large original images SVDA0 to SVDD0: When one column of the last column constituting 360 dots is extended to two columns as a predetermined plurality of columns, a plurality of expanded columns (that is, the expansion) Multiple columns in which any one of the other columns following the one column is not overwritten. Then, when extending to two rows, one row is overwritten with the extended plurality of rows (that is, two extended rows), and the horizontal width of each of the large original images SVDA0 to SVDD0 is set to 360 dots as the horizontal width for the second system. When the last column to be configured is extended to two columns as a predetermined plurality of columns, the horizontal width of each of the large original images SVDA0 to SVDD0 is 360 dots as the horizontal width for the second system by the extended plurality of columns (that is, two extended columns). Is overwritten as the original drawing data for the second system stored in the built-in VRAM of the sound source built-in VDP 4160a as the storage means and the original drawing for the second system is extended. The built-in VR of the sound source built-in VDP 4160a using the large original images SVDA0 to SVDD0 as storage means In other words, the large original images SVDA0 to SVDD0 are extended as the second drawing original drawing data stored in the built-in VRAM of the sound source built-in VDP 4160a as the storage means, and the large original image SVDA0 is used as the second drawing original drawing data. 33. (Deleted from the built-in VRAM of the sound source built-in VDP 4160a using SVDD0 as the storage means) The expanded images SVDA1 to SVDD1 are generated as the extended drawing data for the second system, and the predetermined slit-shaped even-numbered mask pattern shown in FIG. A lattice is formed so that only a plurality of strip-like images of portions corresponding to odd-numbered dot rows that can be specified by odd-numbered addresses in FIG. Grid processed image SVD2 (SVDA2 to S It is possible to control the sound source built-in VDP 4160a as the image generation means so as to store the grid-like processed image SVD2) composed of VDD2 as the storage means at odd addresses of the built-in VRAM of the sound source built-in VDP 4160a. .

  Specifically, the peripheral control MPU 4150a repeats the peripheral control unit steady process, which is the process of steps S1009 to S1038 in the peripheral control unit power-on process of FIG. 64, every 33.3 ms, and the peripheral control unit of FIG. In the display data creation process in step S1030 in the power-on process (display data creation process in step S1030 in the peripheral control part steady process), when the current peripheral control part steady process is executed, When generating drawing data for one screen (one frame) to be displayed on the movable liquid crystal display devices 1925a to 1925d on the built-in VRAM, the sound source built-in VDP 4160a receives screen data from the peripheral control MPU 4150a. Based on the input screen data, liquid crystal and sound control R Character data is extracted from M4160b to create sprite data, and a large original image MVD0 for drawing in the display area of the game board side liquid crystal display device 1900 in the frame buffer MVD shown in FIG. Using the upper right part of 32 (b) as the origin, the image is created with 600 dots downward from the origin of FIG. 32 (b) and 800 dots leftward from the origin of FIG. 32 (b). Accordingly, the large original image MVD0 has a size of horizontal width: 800 dots and vertical width: 600 dots. Subsequently, the original image MVD0 is subjected to a process of extending the original image MVD0 from the first row constituting the 800 dots to the last row one by one in sequence (that is, doubled), thereby executing the original image MVD0. A stretched image MVD1 is created by stretching MVD0 twice in the horizontal direction (leftward in FIG. 32B). Horizontal width of the large original image MVD0: By performing a process of extending the original image MVD0 to two columns in order from the first column constituting the 800 dots to the last column (that is, doubled), the horizontal width of the large original image MVD0: If one column of the last column consisting of 800 dots is extended to two columns, one column is not overwritten by the two extended columns, and one of the other columns following the one column If one column of the original image MVD0 is extended by two columns, one column is overwritten by the two extended columns, and if the last column of the large original image MVD0 is extended to two columns, the extended two columns extend the end of the large original image MVD0. Is overwritten to delete the large original image MVD0 from the frame buffer MVD (that is, the frame buffer MVD0). The Omoto image MVD0 by stretching the Omoto image MVD0 stored in VD is generating while) stretched image MVD1 removed from the frame buffer MVD. The sound source built-in VDP 4160a creates the stretched image MVD1, and then performs mask processing to remove the image in the portion corresponding to the odd address of the frame buffer MVD, so that the odd mask dots shown in FIG. Using a predetermined slit-like odd-numbered mask pattern generated so as to be alternately arranged with blank dots, an image of a portion corresponding to each odd-numbered dot row that can be specified by an odd address shown in FIG. A grid-like processed image that is processed into a grid so that only a plurality of strip-shaped images corresponding to even-numbered dot rows that can be specified by even-numbered addresses remain by removing them in a grid (slit) along the vertical direction. Create MVD2.

  When the screen data is input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a extracts the character data from the liquid crystal and sound control ROM 4160b based on the input screen data, creates sprite data, and outputs the liquid crystal output board from the even channels. When drawing data for the game board side liquid crystal display device 1900 transmitted to 3420 is created in the frame buffer MVD, then drawing is performed in the display area of the movable liquid crystal display device 1925a in the frame buffer SVDA shown in FIG. A large original image SVDA0 is created with the upper right portion as the origin and 204 dots downward from the origin and 360 dots left from the origin. Thus, the large original image SVDA0 has a size of horizontal width: 360 dots and vertical width: 204 dots. Subsequently, the large original image SVDA0 is subjected to a process of extending the original image SVDA0 by extending the first row constituting the 360 dots from the first row to the last row in order of two rows (that is, twice). A stretched image SVDA1 is created by stretching SVDA0 twice in the horizontal direction (leftward in FIG. 32D). Width of the large original image SVDA0: By performing the process of extending the first row constituting 360 dots from the first row constituting the 360 dots to the last row one by one in order (that is, twice), the horizontal width of the large original image SVDA0: If one column of the last column constituting 360 dots is extended to two columns, one column is not overwritten by the two extended columns, and one of the other columns following the one column When one column of the original image SV2 is extended, the first row is overwritten by the two extended rows, and when the last row of the large original image SVDA0 is extended to two rows, the last two rows of the large original image SVDA0 are extended. Is overwritten to delete the large original image SVDA0 from the frame buffer SVDA (that is, the large original image SVDA0 stored in the frame buffer SVDA). It has generated while) stretched image SVDA1 remove frame buffer SVDA Omoto by stretching the Omoto image SVDA0 stored in the image SVDA0 from the frame buffer SVDA. The sound source built-in VDP 4160a performs mask processing on the extended image SVDA1 created by the frame buffer SVDA to remove an image at a portion corresponding to the even address of the frame buffer SVDA, as shown in FIG. Each even dot row that can be specified by an even address shown in FIG. 32 (f) using a predetermined slit-like even row mask pattern generated so that the even mask dots MD are alternately arranged with the blank dots BD. By removing the image of the portion corresponding to に in a lattice shape (slit shape) along the vertical direction, only a plurality of strip-like images of the portion corresponding to the odd dot rows that can be specified by odd addresses remain in a lattice shape. A processed grid-like processed image SVDA2 is created, and the frame buffer MVD shown in FIG. It is transferred to the area RGNA.

  The sound source built-in VDP 4160a is a large original image SVDB0 for drawing in the display area of the movable liquid crystal display device 1925b created in the frame buffer SVDB (the large original image SVDB0 has a size of horizontal width: 360 dots and vertical width: 204 dots). Is transferred to the frame buffer SVDA and arranged at the same position as the large original image SVDA0, and the horizontal width of the large original image SVDB0: from the first column constituting 360 dots toward the last column By performing the process of sequentially extending each column by two columns (that is, by double), the large image SVDB0 is expanded by a factor of two in the horizontal direction (leftward in FIG. 32 (d)). Create By executing again the enlargement process performed when the extended image SVDA1 is generated from the large original image SVDA0, the extended image SVDB1 is generated from the large original image SVDB0 in the frame buffer SVDA. As a result, the original image SVDB0 has a horizontal width of 360 dots, and the process of extending the original image SVDB0 from the first column to the last column one by one in order to two columns (that is, twice) is performed again. The width of the image SVDB0: If one column of the first column to the last column constituting 360 dots is extended to two columns, one column is not overwritten by the two extended columns, and the other columns following the one column are not overwritten. If any one of the columns is extended by two columns, one column is overwritten by the two extended columns, and if the last column of the large original image SVDB0 is extended to two columns, the expanded two columns are larger. By overwriting the last column of the original image SVDB0, the large original image SVDB0 stored in the frame buffer SVDA is extended and the large original image SVDB0 is deleted from the frame buffer SVDA. Together are generating stretched images SVDB1 (i.e., while deleting the Omoto image SVDB0 by stretching the Omoto image SVDB0 stored in the frame buffer SVDA from the frame buffer SVDA). The sound source built-in VDP 4160a performs the mask processing performed when creating the grid-processed image SVDA2 in order to remove the image in the portion corresponding to the even address of the frame buffer SVDA from the extended image SVDB1 created by the frame buffer SVDA. By performing again, when the grid-like processed image SVDB2 processed so as to leave only a plurality of strip-like images corresponding to odd-numbered dot rows that can be specified by odd addresses remains, this grid-like processed image The SVDB2 is transferred to the area RGNB of the frame buffer MVD shown in FIG.

  The sound source built-in VDP 4160a is a large original image SVDC0 for drawing in the display area of the movable liquid crystal display device 1925c created in the frame buffer SVDC (the large original image SVDC0 has a size of horizontal width: 360 dots and vertical width: 204 dots). Is transferred to the frame buffer SVDA and arranged at the same position as the large original images SVDA0 and SVDB0, and the horizontal width of the large original image SVDC0: from the first column constituting 360 dots to the last column By performing a process of sequentially stretching the original image SVDC0 by two columns (that is, doubled), the large image SVDC0 is stretched by a factor of two in the horizontal direction (leftward in FIG. 32D). An image SVDC1 is created. By executing again the enlargement processing performed when creating the enlarged images SVDA1 and SVDB1 from the large original images SVDA0 and SVDB0, the enlarged image SVDC1 is created from the large original image SVDC0 in the frame buffer SVDA. As a result, the original image SVDC0 has a horizontal width of 360 dots, and the process of extending the original image sequentially from the first column to the last column in two columns (that is, twice) is performed again. Width of image SVDC0: If one column is extended from the first column to the last column constituting 360 dots to two columns, one column is not overwritten by the two expanded columns, and the other columns following the one column If one of the columns is extended by two, one column is overwritten by the two extended columns, and when the last column of the large original image SVDC0 is extended to two columns, the two expanded columns are larger. By overwriting the last column of the original image SVDC0, the large original image SVDC0 stored in the frame buffer SVDA is extended and the large original image SVDC0 is deleted from the frame buffer SVDA. Together are generating stretched images SVDC1 (i.e., while deleting the Omoto image SVDC0 by stretching the Omoto image SVDC0 stored in the frame buffer SVDA from the frame buffer SVDA). The VDP 4160a with built-in tone generator performs mask processing performed when creating the grid-processed images SVDA2 and SVDB2 in order to remove the image in the portion corresponding to the even address of the frame buffer SVDA from the extended image SVDC1 created by the frame buffer SVDA. When the lattice-like processed image SVDC2 processed so as to leave only a plurality of strip-like images corresponding to the odd-numbered dot rows that can be specified by the odd-numbered addresses is created by performing the processing again, The processed image SVDC2 is transferred to the region RGNC of the frame buffer MVD shown in FIG.

  The sound source built-in VDP 4160a is a large original image SVDD0 for drawing in the display area of the movable liquid crystal display device 1925c created in the frame buffer SVDD (the large original image SVDD0 has a size of horizontal width: 360 dots, vertical width: 204 dots). Is transferred to the frame buffer SVDA and arranged at the same position as the large original images SVDA0, SVDB0, SVDC0, and the horizontal width of the large original image SVDD0: from the first column constituting 360 dots to the last By performing a process of extending the original image SVDD0 in the horizontal direction (leftward in FIG. 32 (d)) by executing the process of sequentially extending the data to each column in two columns (that is, twice). A stretched image SVDD1 is created. The frame buffer SVDA creates an image SVDD1 that is enlarged from the original image SVDD0 by performing again the enlargement processing performed when the enlarged images SVDA1, SVDB1, and SVDC1 are created from the large original images SVDA0, SVDB0, and SVDC0. As a result, the original image SVDD0 has a horizontal width of 360 dots, and the process of extending the original image sequentially from the first column to the last column in two columns (that is, twice) is performed again. Width of the image SVDD0: When one column of the first column to the last column constituting 360 dots is extended to two columns, one column is not overwritten by the two extended columns, and the other columns following the one column are not overwritten. If any one of the columns is extended by two columns, one column is overwritten by the two extended columns, and if the last column of the large original image SVDD0 is extended to two columns, the two expanded columns are larger. By overwriting the last column of the original image SVDD0, the large original image SVDD0 stored in the frame buffer SVDA is extended and the large original image SVDD0 is deleted from the frame buffer SVDA. Together are generating stretched images SVDD1 (i.e., while deleting the Omoto image SVDD0 by stretching the Omoto image SVDD0 stored in the frame buffer SVDA from the frame buffer SVDA). The sound source built-in VDP 4160a is executed when creating the grid-processed images SVDA2, SVDB2, and SVDC2 in order to remove the image in the portion corresponding to the even address of the frame buffer SVDA from the stretched image SVDD1 created by the frame buffer SVDA. By performing the mask processing again, a grid-like processed image SVDD2 that is processed into a grid so that only a plurality of strip-like images corresponding to odd-numbered dot rows that can be specified by odd-numbered addresses remains is created. The grid-processed image SVDD2 is transferred to the region RGND of the frame buffer MVD shown in FIG.

  In this way, the even address in the built-in VRAM of the sound source built-in VDP 4160a as one storage means has the display area of the game board side liquid crystal display device 1900 of FIG. 32A as the horizontal width for the first line of the original drawing data for the first line. The horizontal width of the large original image MVD0 for drawing in the horizontal direction: Of 800 dots, the first row constituting the first system width is extended from the first row to the last row one by one in order as a plurality of predetermined rows. Accordingly, the enlarged image MVD1 of FIG. 32B is generated in advance as the first drawing extended drawing data while deleting the large original image MVD0 as the first drawing original drawing data from the built-in VRAM of the sound source built-in VDP 4160a. As the predetermined slit-like odd-numbered mask pattern, the predetermined slit-like odd-numbered-mask pattern shown in FIG. A grid-like processed image MVD2 processed into a grid so that only a plurality of strip-like images corresponding to the even-numbered dot rows that can be specified by the even-numbered addresses in FIG. The odd-numbered addresses in the built-in VRAM of the sound source built-in VDP 4160a as one storage means can be stored in the movable liquid crystal display devices 1925a to 1925d in FIG. The width of each of the large original images SVDA0 to SVDD0 to be drawn in the display area: 360 dots, a plurality of predetermined numbers in order from the first column to the last column constituting the horizontal width for the second system among 360 dots. Built-in sound source with large original images SVDA0 to SVDD0 as storage means as original drawing data for the second system by extending to two columns The extended images SVDA1 to SVDD1 shown in FIG. 32 (e) are generated as the extended drawing data for the second system while being deleted from the built-in VRAM of the DP 4160a, and the predetermined slits shown in FIG. An even-numbered row mask pattern is overlaid and masked to form an odd-numbered row so that only a plurality of strip-like images corresponding to the odd-numbered dot rows that can be specified by the odd-numbered addresses in FIG. Since the grid-processed image SVD2 (lattice-processed image SVD2 made up of SVDA2 to SVDD2) can be stored, the sound source built-in VDP 4160a is used as the image generation means, and the sound source built-in VDP 4160a is used as the storage means. Extension for the first system stored in the even address of the built-in VRAM Then, even-numbered columns that remain after masking a predetermined slit-shaped odd-numbered mask pattern on the drawing data (that is, even-numbered columns that remain after masking the stretched image MVD1 with a predetermined slit-shaped odd-numbered mask pattern) are masked. By outputting from the even channel of the channel CH1 of the built-in sound source VDP 4160a as the first signal transmission path as rendering data of the effect image, the game board side liquid crystal display device 1900 includes the sound source as the storage means and the display means included in the first system. The effect image stored in the even-numbered address of the built-in VRAM of the VDP 4160a can be displayed, and the extended drawing data for the second system stored in the odd-numbered address of the built-in VRAM of the built-in sound source VDP 4160a as the storage means Overlapping column mask patterns The remaining odd-numbered columns (that is, the odd-numbered columns remaining after masking the stretched images SVDA1 to SVDD1 by overlaying the predetermined slit-shaped even-numbered mask pattern) are used as drawing data of the effect image as the second signal transmission path. By outputting from the built-in VRAM of the built-in VDP 4160a, the movable liquid crystal display devices 1925a to 1925d are displayed as the display means included in the second system, and the effect image stored in the odd address of the built-in VRAM of the sound source built-in VDP 4160a is displayed as the storing means. (In other words, the built-in sound source VDP 4160a as the image generation means is a built-in VRAM of the sound source built-in VDP 4160a as the storage means for the game board side liquid crystal display device 1900 as the display means included in the first system by the dual link method. Even addresses The first drawing of the extended drawing data for the first system is masked by overlaying a predetermined slit-like odd-numbered mask pattern, and the remaining even-numbered mask (that is, the stretched image MVD1 is masked by overlaying a predetermined slit-like odd-numbered mask pattern). The output of the remaining even-numbered column) and the drawing drawing data for the second system stored in advance in the odd addresses of the built-in VRAM of the built-in sound source VDP 4160a as the storage means for the movable liquid crystal display devices 1925a to 1925d as the display means included in the second system. The output of the remaining odd numbered columns (that is, the odd numbered columns remaining after masking the stretched images SVDA1 to SVDD1 by overlaying the predetermined slit-shaped even numbered mask pattern) masked by overlapping the defined slit-shaped even-numbered mask pattern; Can be done at the same time). Thereby, the progress of the effect image of the plurality of display means by the game board side liquid crystal display device 1900 as the display means included in the first system and the movable liquid crystal display devices 1925a to 1925d as the display means included in the second system. The dual link method that has been used for displaying one display means in the past is used as a display means included in the first system, and the game board side liquid crystal display device 1900, The present invention can be applied to a gaming machine as an unprecedented novel method for displaying an effect image on a plurality of display means using movable liquid crystal display devices 1925a to 1925d as display means included in the two systems. Therefore, a plurality of display means for a single link output without breaking the synchronism of the progress of the effect image by the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d as a plurality of display means. It is possible to display the effect images on the plurality of display means by associating with each other.

  Also, the width of the large original image MVD0 for drawing in the display area of the game board side liquid crystal display device 1900 of FIG. 32A as the width of the first line of the original drawing data for the first line: When extending from the first row constituting the horizontal width for one system to two rows as a predetermined plurality of rows in order from the first row to the last row, of the first row to the last row constituting the first horizontal width If one column is extended to two columns as a predetermined number of columns, one of the other columns following the one column is not overwritten by the plurality of extended columns (that is, two extended columns). When one column is extended to two columns as a plurality of predetermined columns, the last column is overwritten with one column by the extended plurality of columns (that is, two extended columns) and constitutes the width for the first system A plurality of predetermined columns and Is extended to two rows, the last row constituting the first system width is overwritten by a plurality of extended rows (that is, the two extended rows), and is stored in the built-in VRAM of the sound source built-in VDP 4160a as the storage means. As the first system original drawing data, the large original image MVD0 is extended as the first system original drawing data, and as the first system original drawing data, the large original image MVD0 is deleted from the built-in VRAM of the sound source built-in VDP 4160a as the storage means. Since the extended image MVD1 of FIG. 32B can be generated, the large original image MVD0 itself is generated as the first drawing original drawing data as the first drawing drawing data MVD1. It does not get in the way.

  In addition, each of the original images SVDA0 to SVDD0 for drawing in the display area of the movable liquid crystal display devices 1925a to 1925d in FIG. 32D as the horizontal width for the second system of the original drawing data for the second system has a horizontal width of 360 dots. Of these, when extending from the first row constituting the second system width to the last row one by one in order as a plurality of predetermined rows, the first row constituting the second system width is last If one of the columns is extended to two columns as a plurality of predetermined columns, the one column is not overwritten by the extended plurality of columns (that is, two extended columns), and the other columns following the one column are not overwritten. If one of the columns is extended to two as a plurality of predetermined columns, the one column is overwritten by the extended plurality of columns (that is, two extended columns), and the width for the second system is configured. As the storage means, the last column constituting the horizontal width for the second system is overwritten by the extended plurality of columns (that is, the two extended columns). The large original images SVDA0 to SVDD0 are extended as the second drawing original drawing data stored in the built-in VRAM of the sound source built-in VDP 4160a, and the large original images SVDA0 to SVDD0 are stored as the second drawing original drawing data in the built-in sound generator VDP 4160a. Since the extended images SVDA1 to SVDD1 of FIG. 32E can be generated as the second system extended drawing data while being deleted from the VRAM, the large original images SVDA0 to SVDA0 are used as the second system original drawing data. SVDD0 itself is the extended drawing data for the second system. Not to interfere in the generation of SVDA1~SVDD1.

  Further, according to the pachinko gaming machine 1 of the present embodiment described above, the peripheral control MPU 4150a of the peripheral control unit 4150 in the peripheral control board 4140 of FIG. The peripheral control MPU 4150a can display effect images based on various commands shown in FIGS. 41 and 42 from the main control MPU 4100a on the main control board 4100 in FIG. 12 as main control means for controlling the progress of the game. The progress of effects by the game board side liquid crystal display device 1900 of FIG. 10 and the movable liquid crystal display devices 1925a to 1925d of FIG. 10 can be controlled as display means.

  The pachinko gaming machine 1 of the present embodiment further includes the liquid crystal and sound source built-in VDP 4160a of the peripheral control board 4140 in FIG. 31 as image generation means. The built-in sound source VDP 4160a generates rendering data of the effect image and stores it as storage means in the built-in VRAM of the built-in sound source VDP 4160a. It is possible to simultaneously output to the even channel of channel CH1 in the built-in VDP 4160a and the odd channel of channel CH1 in the sound source built-in VDP 4160a as the second signal transmission path.

  The peripheral control MPU 4150a uses the first of the game board-side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d as a plurality of display means in the display data creation processing in step S1030 in the peripheral control unit power-on processing of FIG. Control for generating rendering data for effect images to be displayed on the game board side liquid crystal display device 1900 as display means included in the system and storing it as an even address in the built-in VRAM of the built-in sound source VDP 4160a as storage means. The game board side liquid crystal display device 1900 as a plurality of display means and the game board side liquid crystal as display means included in the first system among the movable liquid crystal display devices 1925a to 1925d. The remaining second system excluding the display device 1900 Control for generating rendering data of effect images to be displayed on the movable liquid crystal display devices 1925a to 1925d as display means included therein and storing the rendering data in odd addresses of the built-in VRAM of the built-in sound source VDP 4160a as storage means is performed on the built-in sound source VDP 4160a as image generation means. Can be done. The peripheral control MPU 4150a performs the display data output process in step S1016 in the peripheral controller power-on process in FIG. 64 in the drawing data output control means, and the display data creation process in step S1030 in the peripheral controller power-on process in FIG. The drawing data of the effect image to be displayed on the game board side liquid crystal display device 1900 as the display means included in the first system stored in the even address of the built-in VRAM of the built-in sound source VDP 4160a as the storage means generated by the built-in sound source VDP 4160a as the image generating means. Output from the even channel of the channel CH1 in the VDP 4160a with built-in sound source as the first signal transmission path and display in the game board side liquid crystal display device 1900 as display means included in the first system, and even number in the built-in VRAM in the sound source VDP 4160a as storage means Control for displaying the effect image stored in the dress can be performed on the sound source built-in VDP 4160a as an image generation means, and the display data generation in step S1030 in the power-on processing of the peripheral control unit in FIG. Drawing of effect images to be displayed on the movable liquid crystal display devices 1925a to 1925d as display means included in the second system stored in odd addresses of the built-in VRAM of the built-in sound source VDP 4160a as the storage means generated by the sound source built-in VDP 4160a as the image generating means by processing Data is output from the odd number channel of channel CH1 in the built-in sound source VDP 4160a as the second signal transmission path, and is displayed in the movable liquid crystal display devices 1925a to 1925d as display means included in the second system, and in the sound source built-in VDP 4160a as storage means. The effect image stored in the odd address Kura VRAM, so that the can be made to sound the built VDP4160a as an image generating means control to display.

  Specifically, the peripheral control MPU 4150a repeats the peripheral control unit steady process, which is the process of steps S1009 to S1038 in the peripheral control unit power-on process of FIG. 64, every 33.3 ms, and the peripheral control unit of FIG. In the display data creation process in step S1030 in the power-on process, in the display data creation process in step S1030 in the peripheral control part steady process, when the current peripheral control part steady process is executed, the game board side liquid crystal display device 1900 When generating drawing data for one screen (one frame) to be displayed on the movable liquid crystal display devices 1925a to 1925d on the built-in VRAM, the sound source built-in VDP 4160a receives screen data from the peripheral control MPU 4150a. Liquid crystal and sound control based on this input screen data Character data is extracted from the OM 4160b to create sprite data, and a large original image MVD0 for drawing in the display area of the game board side liquid crystal display device 1900 in the frame buffer MVD shown in FIG. The original image MVD0 is created horizontally by creating 600 dots downward from the origin in FIG. 32B and 800 dots left from the origin in FIG. A stretched image MVD1 that is doubled in the direction (leftward in FIG. 32B) is created. The sound source built-in VDP 4160a creates the stretched image MVD1, and then performs mask processing to remove the image in the portion corresponding to the odd address of the frame buffer MVD, so that the odd mask dots shown in FIG. Using a predetermined slit-like odd-numbered mask pattern generated so as to be alternately arranged with blank dots, an image of a portion corresponding to each odd-numbered dot row that can be specified by an odd address shown in FIG. A grid-like processed image that is processed into a grid so that only a plurality of strip-shaped images corresponding to even-numbered dot rows that can be specified by even-numbered addresses remain by removing them in a grid (slit) along the vertical direction. Create MVD2.

  When the screen data is input from the peripheral control MPU 4150a, the sound source built-in VDP 4160a extracts the character data from the liquid crystal and sound control ROM 4160b based on the input screen data, creates sprite data, and outputs the liquid crystal output board from the even channels. When drawing data for the game board side liquid crystal display device 1900 transmitted to 3420 is created in the frame buffer MVD, then drawing is performed in the display area of the movable liquid crystal display device 1925a in the frame buffer SVDA shown in FIG. A large original image SVDA0 is created with the upper right as the origin and 204 dots downward from the origin and 360 dots left from the origin, and then the large original image SVDA0 in the horizontal direction (FIG. 32 (d)). (Left direction) Pulled twice Place to create the image SVDA1. The sound source built-in VDP 4160a performs mask processing on the extended image SVDA1 created by the frame buffer SVDA to remove an image at a portion corresponding to the even address of the frame buffer SVDA, as shown in FIG. Each even dot row that can be specified by an even address shown in FIG. 32 (f) using a predetermined slit-like even row mask pattern generated so that the even mask dots MD are alternately arranged with the blank dots BD. By removing the image of the portion corresponding to に in a lattice shape (slit shape) along the vertical direction, only a plurality of strip-like images of the portion corresponding to the odd dot rows that can be specified by odd addresses remain in a lattice shape. A processed grid-like processed image SVDA2 is created, and the frame buffer MVD shown in FIG. It is transferred to the area RGNA.

  The sound source built-in VDP 4160a transfers the large original image SVDB0 to be drawn in the display area of the movable liquid crystal display device 1925b created in the frame buffer SVDB to the frame buffer SVDA, and the large original image SVDB0 is displayed in the horizontal direction (FIG. 32). A stretched image SVDB1 that is doubled toward (leftward in (d)) is created. The sound source built-in VDP 4160a performs the mask processing performed when creating the grid-processed image SVDA2 in order to remove the image in the portion corresponding to the even address of the frame buffer SVDA from the extended image SVDB1 created by the frame buffer SVDA. By performing again, when the grid-like processed image SVDB2 processed so as to leave only a plurality of strip-like images corresponding to odd-numbered dot rows that can be specified by odd addresses remains, this grid-like processed image The SVDB2 is transferred to the area RGNB of the frame buffer MVD shown in FIG.

  The built-in sound source VDP 4160a transfers the large original image SVDC0 created in the frame buffer SVDC to the display area of the movable liquid crystal display device 1925c to the frame buffer SVDA, and the large original image SVDC0 is displayed in the horizontal direction (FIG. 32). A stretched image SVDC1 that is doubled toward (leftward in (d)) is created. The VDP 4160a with built-in tone generator performs mask processing performed when creating the grid-processed images SVDA2 and SVDB2 in order to remove the image in the portion corresponding to the even address of the frame buffer SVDA from the extended image SVDC1 created by the frame buffer SVDA. When the lattice-like processed image SVDC2 processed so as to leave only a plurality of strip-like images corresponding to the odd-numbered dot rows that can be specified by the odd-numbered addresses is created by performing the processing again, The processed image SVDC2 is transferred to the region RGNC of the frame buffer MVD shown in FIG.

  Then, the sound source built-in VDP 4160a transfers the large original image SVDD0 created in the frame buffer SVDD to the display area of the movable liquid crystal display device 1925c to the frame buffer SVDA, and the large original image SVDD0 is displayed in the horizontal direction (FIG. 32). A stretched image SVDD1 that is doubled toward (leftward in (d)) is created. The sound source built-in VDP 4160a is executed when creating the grid-processed images SVDA2, SVDB2, and SVDC2 in order to remove the image in the portion corresponding to the even address of the frame buffer SVDA from the stretched image SVDD1 created by the frame buffer SVDA. By performing the mask processing again, a grid-like processed image SVDD2 that is processed into a grid so that only a plurality of strip-like images corresponding to odd-numbered dot rows that can be specified by odd-numbered addresses remains is created. The grid-processed image SVDD2 is transferred to the region RGND of the frame buffer MVD shown in FIG.

  In this way, in the display data creation processing, when drawing data for the game board side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output board 3420 is created in the frame buffer MVD, subsequently, in this frame buffer MVD, Since drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted from the odd channel to the liquid crystal output substrate 3420 is created, the game board side liquid crystal display device 1900 transmitted to the liquid crystal output substrate 3420 from the even channel. FIG. 32 (h) shows the drawing data for the image data and the drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted from the odd channels to the liquid crystal output board 3420 in the same frame buffer called the frame buffer MVD. Like Images in which the grid-like processed image MVD2 shown in FIG. 32C and the grid-like processed image SVD2 shown in FIG. 32G are alternately arranged without interfering with each other (in other words, FIG. 32C). The comb-teeth of the grid-like processed image MVD2 shown in FIG. 32 and the comb-teeth of the grid-like processed image SVD2 shown in FIG.

  The peripheral control MPU 4150a performs the display of step S1016 in the peripheral control unit steady process every time a predetermined time of 33.3 ms elapses in the display data output process of step S1016 in the peripheral controller power-on process of FIG. In the data output process, for example, when the current peripheral control part steady process is executed, the game board side liquid crystal display device 1900 and the movable liquid crystal are displayed by the built-in VRAM frame buffer MVD in the display data creation process in step S1030 in the peripheral control part steady process. When drawing data for one screen (one frame) to be drawn on the screens of the display devices 1925a to 1925d is generated and held, in the peripheral control unit steady process when the previous peripheral control unit steady process is executed Already built in display data creation processing in step S1030 The drawing data for one screen (one frame) to be drawn on the screen of the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d generated and held by the RAM frame buffer MVD ′ is read out, and the frame buffer is read out. Among drawing data generated and held in MVD ′, drawing data for the game board side liquid crystal display device 1900 is output (transmitted) from the even channel of channel CH1 to the game board side liquid crystal display device 1900 via the liquid crystal output board 3420. Control is performed on the VDP 4160a with a built-in sound source, and drawing data for the movable liquid crystal display devices 1925a to 1925d is output (transmitted) from the odd channel of the channel CH1 to the movable liquid crystal display devices 1925a to 1925d via the liquid crystal output substrate 3420. VDP416 with built-in sound source Performed on a (i.e., output from the even channels of the channel CH1 (transmission) is performed the output from the odd channels of the channel CH1 (transmission), at the same time) (drawing data output control means).

  In this way, rendering data for effect images to be displayed on the game board side liquid crystal display device 1900 is generated and stored in the even address in the built-in VRAM of the sound source built-in VDP 4160a as one storage means. In addition, the odd-numbered address in the built-in VRAM of the sound source built-in VDP 4160a can be generated and stored as rendering data for effect images to be displayed on the movable liquid crystal display devices 1925a to 1925d as display means included in the second system. Therefore, the built-in sound source VDP 4160a as the image generation means has a built-in sound source as the first signal transmission path with rendering data stored in the even address of the built-in VRAM of the built-in sound source VDP 4160a as the storage means by the dual link method. In VDP4160a By outputting from the even channel of the channel CH1, the effect image stored in the even address of the built-in VRAM of the sound source built-in VDP 4160a is displayed on the game board side liquid crystal display device 1900 as the display means included in the first system. In addition, the effect image stored in the odd address of the built-in VRAM of the sound source built-in VDP 4160a as the storage means is output from the odd channel of the channel CH1 in the sound source built-in VDP 4160a as the second signal transmission path, thereby being included in the second system. It is possible to display the effect image stored in the odd address of the built-in VRAM of the built-in sound source VDP 4160a as the storage means on the movable liquid crystal display devices 1925a to 1925d as the means (that is, sound as the image generation means). The built-in VDP 4160a outputs the rendering data of the rendering image stored in the even address of the built-in VRAM of the sound source built-in VDP 4160a as the storage means for the game board side liquid crystal display device 1900 as the display means included in the first system by the dual link method, As the display means included in the second system, the drawing data of the effect image stored in the odd address of the built-in VRAM of the built-in sound source VDP 4160a as the storage means for the movable liquid crystal display devices 1925a to 1925d can be simultaneously output. ing). Thereby, the progress of the effect image of the plurality of display means by the game board side liquid crystal display device 1900 as the display means included in the first system and the movable liquid crystal display devices 1925a to 1925d as the display means included in the second system. The dual link method that has been used for displaying one display means in the past is used as a display means included in the first system, and the game board side liquid crystal display device 1900, The present invention can be applied to a gaming machine as an unprecedented novel method for displaying an effect image on a plurality of display means using movable liquid crystal display devices 1925a to 1925d as display means included in the two systems. Therefore, a plurality of display means for a single link output without breaking the synchronism of the progress of the effect image by the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d as a plurality of display means. It is possible to display the effect images on the plurality of display means by associating with each other.

  Further, according to the pachinko gaming machine 1 of the present embodiment described above, the game board side liquid crystal display device 1900 of FIG. 10 as the first display means, and the movable liquid crystal display device 1925a to 1925a of FIG. 10 as the second display means. 1925d, and a plurality of display devices including a game board side liquid crystal display device 1900 and movable liquid crystal display devices 1925a to 1925d. The game board side liquid crystal display device 1900 can display effect images. The movable liquid crystal display devices 1925a to 1925d are provided separately from the game board side liquid crystal display device 1900 and can display effect images.

  The pachinko gaming machine 1 according to the present embodiment further includes the built-in sound source VDP 4160a shown in FIG. The sound source built-in VDP 4160a can generate an effect image and store it in the built-in VRAM, and can output the stored effect image by a dual link method.

  The built-in sound source VDP 4160a stores at least the rendering data of the rendering image displayed on the game board side liquid crystal display device 1900 in the even address of the built-in VRAM, and the rendering data of the rendering image displayed on the movable liquid crystal display devices 1925a to 1925d. After storing the odd-numbered address of the VRAM, output the rendering data of the effect image stored at the even-numbered address of the built-in VRAM for the game board side liquid crystal display device 1900 and store it at the odd-numbered address of the built-in VRAM for the movable liquid crystal display devices 1925a to 1925d. It is possible to simultaneously output the rendering data of the rendered effect image.

  Specifically, drawing data for the game board-side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output substrate 3420 and drawing for the four movable liquid crystal display devices 1925a to 1925d transmitted from the odd channel to the liquid crystal output substrate 3420. The data is created in the frame buffer MVD (or frame buffer MVD ′) on the built-in VRAM of the liquid crystal and sound source built-in VDP 4160a of the sound control unit 4160 in the peripheral control board 4140, respectively.

  As described above, the channel CH1 in the sound source built-in VDP 4160a employs the dual link method as the LVDS. The first signal transmission path is an even channel, the second signal transmission path is an odd channel, and drawing data for the game board side liquid crystal display device 1900 is transmitted from the even channel to the liquid crystal output board 3420, while the odd channel has four channels. Drawing data for the movable liquid crystal display devices 1925a to 1925d is transmitted to the liquid crystal output substrate 3420. Drawing data is transmitted simultaneously for even and odd addresses by the dual link method. When drawing data for the game board side liquid crystal display device 1900 created in the frame buffer MVD (or frame buffer MVD ′) is transmitted from the even channel of the channel CH1 in the sound source built-in VDP 4160a to the liquid crystal output substrate 3420, the liquid crystal output substrate 3420 is displayed. The large original image MVD0 is output to the game board side liquid crystal display device 1900 through the display area of the game board side liquid crystal display device 1900, and the liquid crystal output board created in the frame buffer MVD (or frame buffer MVD ′). When drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted to 3420 is transmitted to the liquid crystal output board 3420 from the odd channel of the channel CH1 in the sound source built-in VDP 4160a, the liquid crystal output board 3420 Solutions and expanded by moving the liquid crystal display device 1925A～1925d to be outputted by Omoto image SVDA0~SVDD0 is drawn respectively in the display area of the movable liquid crystal display device 1925A～1925d.

  As described above, the built-in sound source VDP 4160a outputs the rendering data of the effect image stored at the even address of the built-in VRAM for the game board side liquid crystal display device 1900 and the built-in VRAM for the movable liquid crystal display devices 1925a to 1925d by the dual link method. Since it is possible to simultaneously output rendering data of rendering images stored at odd addresses, the dual link method conventionally used for displaying one display device is displayed on a plurality of display devices. Therefore, the present invention can be applied to the pachinko gaming machine 1 as an unprecedented novel method. Therefore, by displaying a plurality of display devices of the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d with respect to one output by the dual link method, an effect image is displayed on each of the plurality of display devices. Can do.

  Further, according to the pachinko gaming machine 1 of the present embodiment described above, the game board side liquid crystal display device 1900 in FIG. 10 and the movable liquid crystal display device 1925a in FIG. 10 as a plurality of display means capable of displaying effect images. To 1925d. The pachinko gaming machine 1 according to the present embodiment further includes a built-in sound source VDP 4160a in FIG. 31 and signal division circuits 3420y and 3420z in FIG. The sound source built-in VDP 4160a generates rendering data for the effect image and stores it in the built-in VRAM, and simultaneously stores the rendered image rendering data on the first signal transmission path and the second signal transmission path by the dual link method. It can be output. The signal dividing circuits 3420y and 3420z can divide and output the rendering data of the effect image from the built-in sound source VDP 4160a.

  The built-in sound source VDP 4160a displays at least the game board side liquid crystal display device 1900 as a plurality of display means and the game board side liquid crystal display device 1900 as display means included in the first system among the movable liquid crystal display devices 1925a to 1925d. The game board side liquid crystal display device 1900 as image drawing data or a plurality of display means, and the remaining second except for the game board side liquid crystal display device 1900 as display means included in the first system among the movable liquid crystal display devices 1925a to 1925d. One of the rendering data of the effect images displayed on the movable liquid crystal display devices 1925a to 1925d as display means included in the system is stored in the even address of the built-in VRAM, and the other is stored in the odd address of the built-in VRAM. , Rendering of the effect image stored in the even address of the built-in VRAM The output to the first signal transmission path of the data and the output to the second signal transmission path of the rendering data of the rendering image stored in the odd address of the built-in VRAM can be performed simultaneously. .

  Specifically, as described above, the built-in sound source VDP 4160a outputs drawing data for the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d from the channel CH1 among the drawing data generated on the built-in VRAM. The data is output to the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d via the output board 3420. As described above, the channel CH1 in the sound source built-in VDP 4160a employs the dual link method as the LVDS. The first signal transmission path is an even channel, the second signal transmission path is an odd channel, and drawing data for the game board side liquid crystal display device 1900 is transmitted from the even channel to the liquid crystal output board 3420, while the odd channel has four channels. Drawing data for the movable liquid crystal display devices 1925a to 1925d is transmitted to the liquid crystal output substrate 3420. Drawing data is transmitted simultaneously for even and odd addresses by the dual link method. The drawing data for the game board side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output substrate 3420 and the drawing data for the four movable liquid crystal display devices 1925a to 1925d transmitted from the odd channel to the liquid crystal output substrate 3420 are: It is created in the frame buffer MVD (or frame buffer MVD ′) on the built-in VRAM of the liquid crystal and sound source built-in VDP 4160a of the sound control unit 4160 on the peripheral control board 4140.

  The signal dividing circuits 3420y and 3420z receive drawing data of an effect image transmitted from at least the first signal transmission path or the second signal transmission path, and the input effect. When the drawing data of the image is for the movable liquid crystal display devices 1925a to 1925d as the display means included in the second system, the movable liquid crystal display device using the input rendering data of the effect image as the display means included in the second system. Each of the images is divided so as to correspond to the effect images displayed on 1925a to 1925d, and can be output to the movable liquid crystal display devices 1925a to 1925d as display means included in the second system.

  Specifically, when drawing data (serial signal) for the movable liquid crystal display devices 1925a to 1925d from odd addresses is received (input) by the RGB conversion circuit 3420x in FIG. 31, the RGB conversion circuit 3420x The received drawing data (input serial signal) is converted into three video signals such as a red video signal, a green video signal, and a blue video signal, and three synchronization signals such as a horizontal synchronization signal, a vertical synchronization signal, and a clock signal, Is converted into a parallel signal. The parallel signals converted by the RGB conversion circuit 3420x are input to the signal division circuits 3420y and 3420z.

  When the control signal from the sound source built-in VDP 4160a indicates that the drawing data for the movable liquid crystal display devices 1925a and 1925b should be received and taken in, the signal dividing circuit 3420y takes in the drawing data and moves the movable liquid crystal display device 1925a. , 1925b, the size is adjusted for drawing in the display area and output to the movable liquid crystal display devices 1925a and 1925b. When the control signal from the sound source built-in VDP 4160a indicates that the drawing data for the movable liquid crystal display devices 1925c and 1925d should be received and taken in, the signal dividing circuit 3420z takes in the drawing data and moves the movable liquid crystal display device 1925c. , 1925d is adjusted in size for drawing in the display area and output to the movable liquid crystal display devices 1925c and 1925d.

  When drawing data for the game board side liquid crystal display device 1900 created in the frame buffer MVD (or frame buffer MVD ′) is transmitted from the even channel of the channel CH1 in the sound source built-in VDP 4160a to the liquid crystal output substrate 3420, the liquid crystal output substrate 3420 is displayed. The large original image MVD0 is output to the game board side liquid crystal display device 1900 through the display area of the game board side liquid crystal display device 1900, and the liquid crystal output board created in the frame buffer MVD (or frame buffer MVD ′). When drawing data for the movable liquid crystal display devices 1925a to 1925d transmitted to 3420 is transmitted to the liquid crystal output board 3420 from the odd channel of the channel CH1 in the sound source built-in VDP 4160a, the liquid crystal output board 3420 Solution (split) and expanded by moving the liquid crystal display device 1925A～1925d to be outputted by Omoto image SVDA0~SVDD0 is drawn respectively in the display area of the movable liquid crystal display device 1925A～1925d.

  As described above, the built-in sound source VDP 4160a excludes the game board side liquid crystal display device 1900 as a plurality of display means and the game board side liquid crystal display device 1900 as display means included in the first system among the movable liquid crystal display devices 1925a to 1925d. Drawing data of effect images to be displayed on the movable liquid crystal display devices 1925a to 1925d as display means included in the remaining second system can be stored in odd addresses of the built-in VRAM. The sound source built-in VDP 4160a outputs the rendering data of the rendering image stored in the even address of the built-in VRAM to the first signal transmission path and the rendering data of the rendering image stored in the odd address of the built-in VRAM by the dual link method. Since the output to the second signal transmission path can be performed simultaneously, the game board side liquid crystal display device 1900 as the display means included in the first system and the display means included in the second system As described above, the dual-link method has been used to display one display means, while maintaining the synchronism of the progress of the effect images of the plurality of display means by the movable liquid crystal display devices 1925a to 1925d as Is applied to the pachinko gaming machine 1 as an unprecedented novel method for displaying effect images on a plurality of display means. It can be. Therefore, a plurality of display means for a single link output without breaking the synchronism of the progress of the effect image by the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d as a plurality of display means. As the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d are associated with each other, the effect images can be displayed on the plurality of display means, respectively.

  In addition, the signal dividing circuits 3420y and 3420z receive rendering data of the rendering image transmitted from the second signal transmission path of the first signal transmission path or the second signal transmission path, and the input rendering When the drawing data of the image is for the movable liquid crystal display devices 1925a to 1925d as the display means included in the second system, the movable liquid crystal display device using the input rendering data of the effect image as the display means included in the second system. Since the image can be divided so as to correspond to the effect images displayed on 1925a to 1925d, the effect images corresponding to the movable liquid crystal display devices 1925a to 1925d are respectively displayed as display means included in the second system. can do.

  In a conventional pachinko machine, a large number of material image data is prepared in advance in a non-volatile memory (so-called character ROM), and a video according to the progress of the game based on the material image read out as necessary. Is displayed on the liquid crystal display device to attract the player's interest (see Japanese Patent Application Laid-Open No. 2010-279799). By the way, in recent years, more diverse images have been desired, and it is gradually becoming difficult to prepare all necessary material image data in advance. Therefore, in the present embodiment, the following configuration is adopted for the purpose of realizing a variety of images while suppressing the amount of data to be prepared in advance in the nonvolatile memory.

  First, in the pachinko gaming machine 1 according to the present embodiment, for example, when a game ball is received at a start port formed in the game area of the game board (when a predetermined start condition is satisfied), then, It is determined whether or not the jackpot random number value acquired when accepted at the start port matches a predetermined jackpot random number value (whether or not a predetermined winning condition is satisfied), and then the winning condition Is established, the main control board 4100 (game control means) on which the main control MPU 4100a for executing the control for shifting from the normal game state to the special game state advantageous to the player is mounted, and its start condition is established Then, the peripheral control board on which the peripheral control MPU 4150a for controlling the effect operation according to the establishment condition of the winning condition is then controlled by the control of the main control board 4100. In addition to 140 (production control means) and the payout control board 4110 (payout control means) for executing the game medium payout operation using the payout device according to the established winning condition, the following configuration is provided. Prepare. That is, the pachinko gaming machine 1 controls the game board side liquid crystal display device 1900 of FIG. 10 as the first display means for displaying the first effect image by the control of the peripheral control board 4140, and the second by the control of the peripheral control board 4140. 10 as the second display means for displaying the effect image of FIG. 10, and a plurality of display devices including the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d. I have. The game board side liquid crystal display device 1900 can display effect images. The movable liquid crystal display devices 1925a to 1925d are provided separately from the game board side liquid crystal display device 1900 and can display effect images.

  As described above, the peripheral control board 4140 has a plurality of sprite data (displayed on the liquid crystal and sound control ROM 4160b (production control storage means) as a so-called character ROM used for displaying a plurality of sprites (material images) constituting the video. A plurality of material image data) is stored in advance.

  The pachinko gaming machine 1 according to the present embodiment further includes the built-in sound source VDP 4160a shown in FIG. The sound source built-in VDP 4160a generates drawing data from necessary sprite data among a plurality of sprite data, stores the drawing data in a built-in VRAM (storage means) as a frame buffer, and outputs the stored drawing data by a dual link method. It is something that can be done.

  The sound source built-in VDP 4160a stores at least the drawing data of the first effect image displayed on the game board side liquid crystal display device 1900 in each of the above-described even strip areas that can be designated by the even address of the built-in VRAM, and the movable liquid crystal. The drawing data of the second effect image displayed on the display devices 1925a to 1925d is stored in each of the above-described even strip areas that can be specified by the odd address of the built-in VRAM, for example.

  The sound source built-in VDP 4160a is a first image obtained by extending the first effect image as shown in FIG. 32B based on the drawing data of the first effect image stored in the even strip area. As shown in FIG. 32 (e), the first distraction drawing data corresponding to the distraction effect image is generated, and the second effect image drawing data stored in the odd strip area described above is used as shown in FIG. The second extended drawing data corresponding to the second extended effect image, which is an image obtained by extending the effect image, is generated (effect image extending means).

  The sound source built-in VDP 4160a extends a predetermined even-numbered dot row mask pattern prepared in advance in the liquid crystal and sound control ROM 4160b to generate a predetermined slit-shaped even-numbered row mask pattern (even-numbered row mask pattern generating means), as well as liquid crystal and sound. A predetermined odd-numbered dot row mask pattern prepared in advance in the control ROM 4160b is extended to generate a predetermined slit-like odd-numbered row mask pattern (odd-numbered row mask pattern generating means).

  As shown in FIG. 32C, the built-in sound source VDP 4160a has an even-numbered column remaining by masking a predetermined slit-shaped odd-numbered mask pattern on the first distraction effect image showing a state where two characters are playing. The first decompressed drawing data for each minute is stored in each even strip area of the built-in VRAM (frame buffer MVD), while a second rendered effect image imitating a ladybird as shown in FIG. The second decompressed drawing data for the odd number columns remaining after masking by overlapping the slit-shaped even number mask patterns is stored in each odd strip area of the built-in VRAM (frame buffer MVD (or frame buffer MVD ′)) ( Mask processing control means).

  After that, the built-in tone generator VDP 4160a has the first even number of columns stored in each even strip area that can be specified by the even address of the built-in VRAM (frame buffer MVD (or frame buffer MVD ′)) for the game board side liquid crystal display device 1900. Output of drawing data (first decompression drawing data) of effect image and each odd strip area that can be specified by an odd address of a built-in VRAM (frame buffer MVD (or frame buffer MVD ′)) for the movable liquid crystal display devices 1925a to 1925d. The drawing data (second decompression drawing data) of the second effect image for the odd-numbered columns stored in can be simultaneously output (simultaneous output control means).

  Specifically, drawing data for the game board-side liquid crystal display device 1900 transmitted from the even channel to the liquid crystal output substrate 3420 and drawing for the four movable liquid crystal display devices 1925a to 1925d transmitted from the odd channel to the liquid crystal output substrate 3420. The data is created in the frame buffer MVD (or frame buffer MVD ′) on the built-in VRAM of the liquid crystal and sound source built-in VDP 4160a of the sound control unit 4160 in the peripheral control board 4140, respectively.

  As described above, the channel CH1 in the sound source built-in VDP 4160a employs the dual link method as the LVDS. The built-in tone generator VDP 4160a uses the first signal transmission path as an even channel and the second signal transmission path as an odd channel, and transmits drawing data for the game board side liquid crystal display device 1900 from the even channel to the liquid crystal output board 3420. The drawing data for the four movable liquid crystal display devices 1925a to 1925d is transmitted to the liquid crystal output substrate 3420 from the odd-numbered channels. This sound source built-in VDP 4160a simultaneously transmits drawing data of even addresses and odd addresses by a dual link method. When the drawing data for the game board side liquid crystal display device 1900 created in the frame buffer MVD is transmitted to the liquid crystal output board 3420 from the even channel of the channel CH1 in the built-in sound source VDP 4160a, the liquid crystal display on the game board side is displayed via the liquid crystal output board 3420. The large original image MVD0 is output to the device 1900 and drawn on the display area of the game board side liquid crystal display device 1900, and transmitted to the liquid crystal output substrate 3420 created in the frame buffer MVD (or frame buffer MVD ′). When the drawing data for the display devices 1925a to 1925d is transmitted to the liquid crystal output board 3420 from the odd channel of the channel CH1 in the sound source built-in VDP 4160a, the drawing data is decomposed and enlarged on the liquid crystal output board 3420. Location 1925A～1925d to be outputted by Omoto image SVDA0~SVDD0 is drawn respectively in the display area of the movable liquid crystal display device 1925A～1925d.

  As described above, the built-in sound source VDP 4160a outputs the rendering data of the effect image stored at the even address of the built-in VRAM for the game board side liquid crystal display device 1900 and the built-in VRAM for the movable liquid crystal display devices 1925a to 1925d by the dual link method. Since it is possible to simultaneously output rendering data of rendering images stored at odd addresses, the dual link method conventionally used for displaying one display device is displayed on a plurality of display devices. Therefore, the present invention can be applied to the pachinko gaming machine 1 as an unprecedented novel method. Therefore, by displaying a plurality of display devices of the game board side liquid crystal display device 1900 and the movable liquid crystal display devices 1925a to 1925d with respect to one output by the dual link method, an effect image is displayed on each of the plurality of display devices. Can do.

  Further, as shown in FIG. 33A, from the even basic dot row mask pattern (basic dot row mask pattern) having the minimum dot configuration prepared in advance in the liquid crystal and sound control ROM 4160b to the odd basic dot row. If not only the mask pattern but also the predetermined grid-like even-numbered row mask pattern and the default odd-numbered-row mask pattern are generated, the liquid crystal and sound control ROM 4160b has a predetermined grid-like odd-numbered row mask pattern and a predetermined There is no need to prepare even grid-like even-row mask patterns, and the default odd-row mask pattern can be changed from an even-numbered basic dot-row mask pattern (basic dot-row mask pattern) with a minimum dot configuration as necessary. In addition, the predetermined even column mask pattern may be generated by being extended. Accordingly, the amount of data to be prepared in advance in the liquid crystal and sound control ROM 4160b, which is a non-volatile memory, can be extremely suppressed, and accordingly other material image data such as sprite data is stored in the liquid crystal and sound control ROM 4160b. It will be possible to prepare more, and it will be possible to realize even more diverse images.

[19. Another example]
It should be noted that the present invention is not limited to the above-described embodiment, and it goes without saying that the present invention can be implemented in various modes as long as it belongs to the technical scope of the present invention.

  For example, in the above-described embodiment, a plurality of game board side liquid crystal display devices 1900 as the first display means and movable liquid crystal display devices 1925a to 1925d as the second display means for one dual link type output. The display images can be displayed on a plurality of display devices by associating the display devices with each other. However, a game board side liquid crystal display device 1900 as a first display means for one dual link type output and One game board side sub liquid crystal display device as a second display means provided separately from the game board side liquid crystal display device 1900 (this game board side sub liquid crystal display device is, for example, the game board shown in FIG. 4 character units 3400 are associated with a plurality of display devices, which are provided separately from the game board side liquid crystal display device 1900. Thus, it is possible to display the effect images on a plurality of display devices, respectively, and separately from the game board side liquid crystal display device 1900 as the first display means for one dual link type output. One door frame side sub liquid crystal display device as the second display means provided on the door frame (this door frame side sub liquid crystal display device is attached to, for example, the upper outer periphery of the gaming window 101 of the door frame 5 shown in FIG. In the upper decoration unit 280, it is provided separately from the game board-side liquid crystal display device 1900.) By associating a plurality of display devices with each other, the effect images are respectively displayed on the plurality of display devices. You can also. In this case, the drawing data for the game board side sub liquid crystal display device or the door frame side sub liquid crystal display device created in the frame buffer MVD shown in FIGS. 32 (d) to (g) is shown in FIGS. The game board side sub-liquid crystal display device or the door frame side sub-liquid crystal display device is smaller in image size due to structural restrictions than the game board-side liquid crystal display device 1900. Therefore, the image size of the original image for drawing in the display area of the game board side sub liquid crystal display device or the door frame side sub liquid crystal display device is also larger than the image size 800 × 600 dots shown in FIG. Get smaller.

  In the embodiment described above, drawing data for the game board side liquid crystal display device 1900 is transmitted from the even channel to the liquid crystal output substrate 3420, while drawing data for the four movable liquid crystal display devices 1925a to 1925d is transmitted from the odd channel to the liquid crystal output substrate. Although the drawing data for the four movable liquid crystal display devices 1925a to 1925d is transmitted from the even channel to the liquid crystal output substrate 3420, the drawing data for the game board side liquid crystal display device 1900 is transmitted from the odd channel. May be transmitted to the liquid crystal output substrate 3420. In this case, drawing data for the game board side liquid crystal display device 1900 from the odd-numbered channel is created in the frame buffer MVD according to the procedure shown in FIGS. Drawing data for the movable liquid crystal display devices 1925a to 1925d is created in the frame buffer MVD according to the procedure shown in FIGS. The RGB conversion circuit 3420x shown in FIG. 31 receives drawing data (serial signals) for the four movable liquid crystal display devices 1925a to 1925d from the even channels. The drawing data for the game board side liquid crystal display device 1900 from the odd-numbered channel is output to the game board side liquid crystal display device 1900 via the liquid crystal output substrate 3420.

  Further, in the above-described embodiment, drawing data for one game board side liquid crystal display device 1900 is transmitted from the even channel to the liquid crystal output substrate 3420, while drawing data for the four movable liquid crystal display devices 1925a to 1925d is liquid crystal from the odd channel. Although it was comprised so that it might transmit to the output board 3420, the game board side liquid crystal display device 1900 is comprised as four movable liquid crystal display devices 1900A-1900D, and it draws with respect to four movable liquid crystal display devices 1900A-1900D from an even-numbered channel. While the data is transmitted to the liquid crystal output substrate 3420, the drawing data for the four movable liquid crystal display devices 1925a to 1925d may be transmitted from the odd-numbered channel to the liquid crystal output substrate 3420. This configuration will be described with reference to FIG. FIG. 99 is a block diagram showing a circuit configuration of a liquid crystal output substrate when eight movable liquid crystal display devices are provided on the game board. Note that the drawing data (serial signal) for the movable liquid crystal display devices 1925a to 1925d from the odd-numbered channels has already been described with reference to FIG. The movable liquid crystal display devices 1900A to 1900D will be described below assuming that they have the same specifications (4.3 inches) as the movable liquid crystal display devices 1925a to 1925d.

  The drawing data for the movable liquid crystal display devices 1900A to 1900D created in the frame buffer MVD is created in the frame buffer MVD according to the procedure shown in FIGS. 32 (d) to (g). Frame buffers MVDA to MVDD corresponding to the frame buffers SVDA to SVDD (regions for creating large original images MVDA0 to MVDD0 for drawing in the display regions of the movable liquid crystal display devices 1900A to 1900D) are provided, and the region RGNA described above is provided. , RGNB, RGNC, RGND areas RGNAA, RGNBA, GRNCA, RGNDA are partitioned into frame buffers MVD.

  As shown in FIG. 99, the liquid crystal output substrate 3420 can be decomposed (divided) and expanded when drawing data (serial signals) from the odd-numbered channels to the movable liquid crystal display devices 1925a to 1925d is input. In addition to the RGB conversion circuit 3420x and the signal division circuits 3420y and 3420z shown in FIG. 5, when drawing data (serial signals) for the movable liquid crystal display devices 1900A to 1900D from the even-numbered channels is input, they are decomposed (divided) and enlarged. The RGB conversion circuit 3420u and the signal division circuits 3420v and 3420w are mainly configured.

  When drawing data for the movable liquid crystal display devices 1900A to 1900D created in the frame buffer MVD is transmitted to the liquid crystal output board 3420 from the even channel of the channel CH1 in the sound source built-in VDP 4160a, the RGB conversion circuit 3420u in the liquid crystal output board 3420 The received drawing data is converted into a parallel signal composed of three video signals, a red video signal, a green video signal, and a blue video signal, and three synchronization signals, a horizontal synchronization signal, a vertical synchronization signal, and a clock signal. Convert. The parallel signals converted by the RGB conversion circuit 3420u are input to the signal division circuits 3420v and 3420w.

  The signal dividing circuit 3420v takes in the drawing data when the control signal from the built-in sound source VDP 4160a informs that the drawing data for the movable liquid crystal display devices 1900A and 1900B should be taken in. Since the image size of the drawn drawing data is the image size 360 × 204 dot of the large original images MVDA0 and MVDB0, it is compared with the image size (4.3 inches) 480 × 272 dots of the movable liquid crystal display devices 1900A and 1900B. Small in both vertical and horizontal directions. Therefore, the signal dividing circuit 3420v performs size adjustment for drawing in the display area of the movable liquid crystal display devices 1900A and 1900B and outputs the result to the movable liquid crystal display devices 1900A and 1900B. That is, images obtained by enlarging the large original images MVDA0 and MVDB0 are drawn in the display areas of the movable liquid crystal display devices 1900A and 1900B, respectively.

  The signal dividing circuit 3420w takes in the drawing data when the control signal from the built-in sound source VDP 4160a informs that the drawing data for the movable liquid crystal display devices 1900C and 1900D should be received and taken in. Since the image size of the drawn drawing data is the image size 360 × 204 dot of the large original images MVDC0 and MVDD0, it is compared with the image size (4.3 inches) 480 × 272 dots of the movable liquid crystal display devices 1900C and 1900D. Small in both vertical and horizontal directions. Therefore, the signal dividing circuit 3420w performs size adjustment for drawing in the display area of the movable liquid crystal display devices 1900C and 1900D and outputs the result to the movable liquid crystal display devices 1900C and 1900D. That is, images obtained by enlarging the large original images MVDC0 and MVDD0 are drawn in the display areas of the movable liquid crystal display devices 1925c and 1925d, respectively.

  When the drawing data for the movable liquid crystal display devices 1900A to 1900D transmitted to the liquid crystal output substrate 3420 created in the frame buffer MVD is transmitted to the liquid crystal output substrate 3420 from the even channel of the channel CH1 in the built-in sound source VDP 4160a, the liquid crystal output substrate 3420. In FIG. 5, the separated (divided) and enlarged images are output to the movable liquid crystal display devices 1900A to 1900D, and the large original images MVDA0 to MVDD0 are drawn in the display areas of the movable liquid crystal display devices 1900A to 1900D, respectively.

  Each of the original positions of the movable liquid crystal display devices 1900A to 1900D is a combined position as one display device, and is the same position as the position where the game board side liquid crystal display device 1900 shown in FIG. 10 is arranged. ing. When the movable liquid crystal display devices 1900A to 1900D are in their original positions, for example, the movable liquid crystal display devices 1925a to 1925d are display areas of one display device in which the movable liquid crystal display devices 1900A to 1900D are merged from the respective original positions described above. 10 (that is, each of the original positions of the movable liquid crystal display devices 1900A to 1900D is a combined position as one display device, and is a position where the game board side liquid crystal display device 1900 shown in FIG. 10 is disposed. Is moved to the center of the display area of the game board side liquid crystal display device 1900 shown in FIG. 10 (a), so that the movable liquid crystal display united as one display device. Appears in front of devices 1900A-1900D and merges as one display device, merges as one display device. The manner to cover the entire display area of the movable liquid crystal display device 1900A～1900D (i.e., FIG. 10 (b), the the embodiment shown in (c)).

  Although the detailed illustration of the back unit 3000 described above is omitted, movable liquid crystal display devices 1925a to 1925d are arranged in the vertical and horizontal directions on the upper left side of the back box 3001, the lower left side on the rear side, the lower right side on the rear side, and the upper right side on the rear side. In addition to the movable devices 1925aa, 1925ba, 1925ca, and 1925da, the movable liquid crystal display devices 1900A to 1900D are also provided with movable devices 1900Aa, 1900Ba, 1900Ca, and 1900Da that can move in the vertical and horizontal directions, respectively. Yes. Each of these movable devices 1900Aa to 1900Da includes two stepping motors and a conversion mechanism that converts the rotational motions of the output shafts of the two stepping motors into linear motions, and each of the movable devices 1900Aa to 1900Da includes. When the two stepping motors are driven, the movable liquid crystal display devices 1900A to 1900D can be independently moved in the vertical and horizontal directions. Further, the movable devices 1900Aa to 1900Da are each provided with a photosensor (not shown) for detecting the state in which the movable liquid crystal display devices 1900A to 1900D are in their original positions, and the detection signals from these photosensors are used for peripheral control. Each input to the MPU 4150a, the peripheral control MPU 4150a determines whether or not the movable liquid crystal display devices 1900A to 1900D are in the standby state based on the detection signal from the photosensor. Peripheral control MPU4150a outputs a drive signal (drive pulse) from the state which movable liquid crystal display device 1900A-1900D waited in the original position to the stepping motor with which movable device 1900Aa-1900Da is equipped based on the detection signal from a photosensor. Thus, the rotation angle per step of the rotation axis of the stepping motor is determined, so that the movable positions of the movable liquid crystal display devices 1900A to 1900D are estimated and moved based on the output drive signal (drive pulse). .

  The built-in sound source VDP 4160a displays at least the movable liquid crystal display devices 1900A to 1900D as a plurality of display means and the movable liquid crystal display devices 1900A to 1900D as display means included in the first system among the movable liquid crystal display devices 1925a to 1925d. Image drawing data is stored in even addresses of the built-in VRAM, and movable liquid crystal display devices 1900A to 1900D as a plurality of display means and movable liquid crystal as display means included in the first system among the movable liquid crystal display devices 1925a to 1925d. The rendering data displayed on the movable liquid crystal display devices 1925a to 1925d as display means included in the remaining second system excluding the display devices 1900A to 1900D is stored in odd addresses of the built-in VRAM, and then the even number of the built-in VRAM. Mark in address The output of the rendered image drawing data to the first signal transmission path and the output of the rendered image rendering data stored in the odd address of the built-in VRAM to the second signal transmission path can be performed simultaneously. It has become.

  The signal division circuits 3420v and 3420w receive drawing data of the effect image transmitted from the first signal transmission path of the first signal transmission path or the second signal transmission path, and the input effect image When the drawing data is for the movable liquid crystal display devices 1900A to 1900D as the display means included in the first system, the input rendering image drawing data is used as the display means included in the first system for the movable liquid crystal display devices 1900A to 1900A. Each of the images is divided so as to correspond to the effect image displayed on 1900D and can be output to movable liquid crystal display devices 1900A to 1900D as display means included in the first system.

  The signal dividing circuits 3420y and 3420z receive drawing data of the effect image transmitted from the second signal transmission path of the first signal transmission path or the second signal transmission path, and the input effect image When the drawing data is for the movable liquid crystal display devices 1925a to 1925d as the display means included in the second system, the input rendering image drawing data is used as the display means included in the second system for the movable liquid crystal display devices 1925a to 1925a. Each of the images is divided so as to correspond to the effect image displayed on 1925d, and can be output to the movable liquid crystal display devices 1925a to 1925d as display means included in the second system.

  In this way, the game board side liquid crystal display device 1900 is configured as four movable liquid crystal display devices 1900A to 1900D, and drawing data for the four movable liquid crystal display devices 1900A to 1900D is transmitted to the liquid crystal output substrate 3420 from the even channel. In the configuration in which drawing data for the four movable liquid crystal display devices 1925a to 1925d is transmitted from the odd-numbered channels to the liquid crystal output substrate 3420, the built-in sound source VDP 4160a is a movable liquid crystal display device 1900A to 1900D as a plurality of display means. In addition, drawing data of effect images to be displayed on the movable liquid crystal display devices 1900A to 1900D as display means included in the first system among the movable liquid crystal display devices 1925a to 1925d can be stored in even-numbered addresses of the built-in VRAM. ing Among the movable liquid crystal display devices 1900A to 1900D as a plurality of display means and the liquid crystal display devices 1925a to 1925d, the display means included in the first system is included in the remaining second system except for the movable liquid crystal display devices 1900A to 1900D. The rendering data of the effect image displayed on the movable liquid crystal display devices 1925a to 1925d as the display means can be stored in odd addresses of the built-in VRAM. The sound source built-in VDP 4160a outputs the rendering data of the rendering image stored in the even address of the built-in VRAM to the first signal transmission path and the rendering data of the rendering image stored in the odd address of the built-in VRAM by the dual link method. Since output to the second signal transmission path can be performed simultaneously, the movable liquid crystal display devices 1900A to 1900D as display means included in the first system, and display means included in the second system As a result, the synchronism of the progress of the effect image is not disturbed by the plurality of display means by the movable liquid crystal display devices 1925a to 1925d, and the dual link method that has been used for displaying one display means conventionally. Is suitable for the pachinko gaming machine 1 as an unprecedented novel method for displaying effect images on a plurality of display means. It can be. Therefore, a plurality of display means for output by one dual link method without breaking the synchronism of the progression of effect images by the movable liquid crystal display devices 1900A to 1900D and the movable liquid crystal display devices 1925a to 1925d as a plurality of display means. As the movable liquid crystal display devices 1900A to 1900D and the movable liquid crystal display devices 1925a to 1925d are associated with each other, the effect images can be displayed on the plurality of display means, respectively.

  Further, the game board side liquid crystal display device 1900 is configured as four movable liquid crystal display devices 1900A to 1900D, and drawing data for the four movable liquid crystal display devices 1900A to 1900D is transmitted from the even channel to the liquid crystal output substrate 3420, while the odd number In the configuration in which drawing data for the four movable liquid crystal display devices 1925a to 1925d is transmitted from the channel to the liquid crystal output substrate 3420, the signal dividing circuits 3420v and 3420w are the first signal transmission path or the second signal transmission. The drawing data of the effect image transmitted from the first signal transmission line is input to the movable liquid crystal display devices 1900A to 1900D as display means included in the first system. If it is, the drawing of the input effect image As the display means included in the first system, the data can be divided so as to correspond to the effect images displayed on the movable liquid crystal display devices 1900A to 1900D as the display means included in the first system. The effect images corresponding to the movable liquid crystal display devices 1900A to 1900D can be respectively displayed, and the signal dividing circuits 3420y and 3420z can transmit the second signal among the first signal transmission path or the second signal transmission path. When rendering data of the effect image transmitted from the road is input and the input rendering data of the effect image is for the movable liquid crystal display devices 1925a to 1925d as display means included in the second system, the input is performed. Movable liquid crystal display devices 1925a to 1925a as display means included in the second system for rendering data of effect images Since the image can be divided so as to correspond to the effect image displayed on 925d, the effect images corresponding to the movable liquid crystal display devices 1925a to 1925d are respectively displayed as display means included in the second system. Can do.

  In the above description, drawing data for the movable liquid crystal display devices 1900A to 1900D is transmitted from the even channel to the liquid crystal output substrate 3420, while drawing data for the four movable liquid crystal display devices 1925a to 1925d is transmitted from the odd channel to the liquid crystal output substrate. Although the drawing data for the four movable liquid crystal display devices 1925a to 1925d is transmitted from the even channel to the liquid crystal output substrate 3420, the drawing data for the movable liquid crystal display devices 1900A to 1900D is transmitted from the odd channel. May be transmitted to the liquid crystal output substrate 3420. In this case, the wiring for electrically connecting the even channel and the RGB conversion circuit 20u and the wiring for electrically connecting the odd channel and the RGB conversion circuit 20x are interchanged so that the even channel and the RGB conversion circuit 20x are electrically connected. It is necessary to connect the odd-numbered channel and the RGB conversion circuit 20u electrically. The built-in sound source VDP 4160a displays at least the movable liquid crystal display devices 1900A to 1900D as a plurality of display means and the movable liquid crystal display devices 1900A to 1900D as display means included in the first system among the movable liquid crystal display devices 1925a to 1925d. Image drawing data is stored in odd addresses of the built-in VRAM, and movable liquid crystal display devices 1900A to 1900D as a plurality of display means and movable liquid crystal as display means included in the first system among the movable liquid crystal display devices 1925a to 1925d. The drawing data of the effect image displayed on the movable liquid crystal display devices 1925a to 1925d as display means included in the remaining second system excluding the display devices 1900A to 1900D is stored in the even-numbered address of the built-in VRAM, and then the odd number of the built-in VRAM. Mark in address And output to the first run of the signal transmission path of the drawing data of the effect image, the output of the two second signal transmission path of the drawing data of the effect image stored in an even address of the internal VRAM, can be performed simultaneously. The signal dividing circuits 3420v and 3420w receive rendering data of the rendering image transmitted from the first signal transmission path of the first signal transmission path or the second signal transmission path. When the drawing data of the image is for the movable liquid crystal display devices 1900A to 1900D as the display means included in the first system, the movable liquid crystal display device using the input rendering data of the effect image as the display means included in the first system. It is possible to divide the images so as to correspond to the effect images displayed on 1900A to 1900D, respectively, and to output them to the movable liquid crystal display devices 1900A to 1900D as display means included in the first system.

  The signal dividing circuits 3420y and 3420z receive drawing data of the effect image transmitted from the second signal transmission path of the first signal transmission path or the second signal transmission path, and the input effect image When the drawing data is for the movable liquid crystal display devices 1925a to 1925d as the display means included in the second system, the input rendering image drawing data is used as the display means included in the second system for the movable liquid crystal display devices 1925a to 1925a. Each of the images is divided so as to correspond to the effect image displayed on 1925d, and can be output to the movable liquid crystal display devices 1925a to 1925d as display means included in the second system.

  Furthermore, in the embodiment described above, the pachinko gaming machine 1 has been described as an example. However, a gaming machine to which the present invention can be applied is not limited to a pachinko gaming machine, and a gaming machine other than a pachinko gaming machine, for example, a slot machine. The present invention can also be applied to a (revolving game machine) or a fusion game machine in which a pachinko game machine and a slot machine are fused (one that uses a game ball to play a slot game). In either case, the same operational effects as those described above can be obtained.

  As a basic configuration of such a rotating type gaming machine or a gaming machine formed by combining the rotating type gaming machine, for example, a rotating display body (rotating display means) including a plurality of reels (rotating bodies) with a plurality of types of symbols, A housing provided with the rotating display, an operating lever (first operating means) provided outside the housing, and a plurality of devices provided outside the housing corresponding to the plurality of reels, respectively. And a stop button (second operation means), wherein the plurality of reels are rotated by the operation of the operation lever (corresponding to the establishment of the start condition) as a trigger. Rotating body control means for stopping the rotation of each corresponding reel according to the operation sequence of the buttons, and an internal lottery for determining whether or not a predetermined winning condition is satisfied when the start lever is operated Run Game control means (main control board described above) having lottery means and game state control means for shifting from the normal game state to the special game state advantageous to the player after the predetermined winning condition is satisfied 4100) and production control means for controlling the production operation according to the establishment condition of the predetermined winning condition by the control of the game control means (substantially equivalent to the function of the peripheral control board 4140 described above) The display control means performs display operation as a part of the effect operation (substantially equivalent to the function of the liquid crystal display device 1900 described above), and is attached to the plurality of reels under the control of the game control means. A payout device (payout hand) for performing a game medium payout operation according to a combination mode of a plurality of symbols stopped in a symbol display area in which a variation mode of the plurality of symbols is visually recognized ) And it includes a.

  More specifically, a slot machine as an example of a swivel game machine will be described with reference to FIG. FIG. 100 is a schematic perspective view of the slot machine. As shown in FIG. 100, the slot machine 6000 includes a front door 6002 and a main body portion 6004. Front door 6002 and main body portion 6004 are connected to each other via a hinge (not shown). With this hinge as the center of rotation, the front door 6002 can be opened from the main body portion 6004 by inserting a key into a key hole 6005 provided at the right end of the front door 6002 and turning it clockwise.

  The upper half of the front door 6002 is provided with a game panel 6006, and the lower half of the front door 6002 is formed with a protruding portion protruding forward from the game panel 6006. In the protruding portion, a medal slot 6008, bet buttons 6010 and 6012, a start lever 6014, a left stop button 6016, a middle stop button 6018, a right stop button 6020, and the like are arranged along the lower edge of the game panel 6006. In addition, a storage and settlement button 6022 and a decorative plate 6024 are disposed in the lower half of the front door 6002, and a tray 6026 is provided below the decorative plate 6024. These bet buttons 6010 and 6012, a start lever 6014, a left stop button 6016, a middle stop button 6018, a right stop button 6020, a storage settlement button 6022, and the like are a main control board (main control MPU) that controls the progress of a game (not shown). ) Is electrically connected.

  A rectangular display window (not shown) is formed at a substantially central position of the game panel 6006. Three variable rotators (not shown) installed in the slot machine 6000 through the display window, a plurality of liquid crystal display devices, and the like Can be seen through. On these variable rotators, translucent symbol bands on which a plurality of types of symbols (for example, bell, watermelon, cherry, 7, V, etc.) are printed as symbol information are affixed to the respective cylindrical frameworks. ing. Such a cylindrical variable rotating body is called a reel or a drum in a gaming machine such as a slot machine, and an output shaft of a stepping motor (not shown) and each variable rotating body are connected to each other. These stepping motors are driven and controlled by a main control board (main control MPU), and by rotating the output shaft of the stepping motor, a plurality of types of symbols are continuously displayed from above to the bottom from the display window. It seems to change to. The plurality of liquid crystal display devices are display-controlled by an effect control board (one VDP with a built-in sound source) that controls the progress of the effect (not shown), and these display controls are performed based on various commands from the main control board. ing. The main control board and the effect control board are installed in the slot machine 6000.

  On the main control board (main control MPU), a predetermined number of medals are inserted as medal into the medal slot 6008, and the symbol information fluctuation display is started based on the operation of the start lever 6014. The change display of the symbol information is stopped based on the operation of the button 6018 and the right stop button 6020 or the elapse of a predetermined time. The main control board (main control MPU) generates a profit granting state (big hit gaming state) on the condition that the symbol information is in a predetermined specific display mode, and receives a large amount of medals as game media in the tray 6026. Pay out.

  In the fusion gaming machine, the medal slot 6008 becomes the ball slot 6008 ′, and the main control board (main control MPU) has a predetermined number of game balls thrown in the ball slot 6008 ′ as a game medium, and the start lever The symbol information variation display is started based on the operation 6014, and the symbol information variation display is stopped based on the operation of the left stop button 6016, the middle stop button 6018, the right stop button 6020, or the elapse of a predetermined time. Then, the main control board (main control MPU) generates a profit-giving state (big hit game state) on the condition that the symbol information is in a predetermined specific display mode, and receives a large amount of game balls as a game medium in the receiving tray 6026. Pay out.

  DESCRIPTION OF SYMBOLS 1 ... Pachinko machine (game machine), 2 ... Outer frame, 3 ... Main body frame, 4 ... Game board, 5 ... Door frame, 192 ... Handle relay terminal board, 300 ... Plate unit, 450 ... Touch panel drive substrate, 450V ... Liquid crystal module circuit, 450W ... touch panel circuit, 470 ... upper plate side liquid crystal display device, 480 ... touch panel, 650 ... hitting ball launching device, 740 ... prize ball device, 744 ... payout motor, 751 ... counting switch, 784 ... external terminal board, 851 ... Power supply board, 855 ... Power supply control unit, 855d ... Power supply creation circuit, 855da ... Power consumption monitoring circuit, 855daa ... Power measurement circuit, 855dab ... Power consumption suppression stage determination circuit, 860a ... Operation switch, 860b ... Error LED indicator 1100: Game area, 1900: Game board side liquid crystal display device (display means), 1925a to 1925d. Liquid crystal display device (display means), 2100 ... Attacker unit, 2105 ... Starter solenoid, 2108 ... Attacker solenoid, 3420 ... Liquid crystal output board, 3420x ... RGB conversion circuit, 3420y, 3420z ... Signal division circuit, 4100 ... Main control board, 4100a ... main control MPU, 4110 ... payout control board, 4120 ... payout control unit, 4120a ... payout control MPU, 4120ag ... fired ball feed control circuit, 4120ah ... fired ball feed fault monitoring circuit, 4140 ... peripheral control board, 4150 ... peripheral Control unit, 4150a ... peripheral control MPU, 4150f ... power consumption status history RAM, 4150g ... battery, 4150k ... power saving mode transition notification LED, 4160 ... liquid crystal and sound control unit, 4160a ... sound source built-in VDP (image generation means), 4165 ... RTC control unit 4165 ... RTC, 4165B ... battery, 4170 ... lamp driving substrate, 4180 ... motor drive board, BC0 ... capacitors, MC2 ... electrolytic capacitor.

Claims (1)

A gaming machine comprising a plurality of display means capable of displaying an image,
The gaming machine is
An image generation means capable of generating an image and storing the image in a storage means and outputting the stored image by a dual link method;
The image generating means includes
Among the plurality of display means, first extension drawing data corresponding to a first extended image obtained by extending an image to be displayed on one display means is generated, and other display means excluding the one display means are used. Image distraction means for generating second distraction drawing data corresponding to the second distraction image obtained by extending the image to be displayed ;
The odd-numbered odd-numbered mask pattern used to generate the first stretched drawing data for the even-numbered columns that remain masked over the first stretched image and the odd-numbers that remain masked over the second stretched image A mask pattern generating means for generating a slit-shaped even-numbered mask pattern used for generating second distraction drawing data for columns;
Image storage means for storing the first extended drawing data for the even number columns at the even address of the storage means, and storing the second extended drawing data for the odd number columns at the odd address of the storage means;
The output of the first distraction drawing data of the even row content stored in an even address before term memory unit, an output of the second distraction drawing data of the odd column fraction stored in the odd address before term memory unit, and line cormorant simultaneous output means at the same time,
Have
The mask pattern generating means generates the slit odd-numbered mask pattern by extending a predetermined odd-numbered dot mask pattern, and generates the slit-shaped even-numbered mask pattern by extending a predetermined even-numbered dot mask pattern. And
The one display means is fixedly arranged at a predetermined position,
The other display means is arranged to be movable by an electric drive means.
A gaming machine characterized by that.