JP2016045482A - Scanning signal generation circuit - Google Patents
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- 101001124937 Homo sapiens Pre-mRNA-splicing factor 38B Proteins 0.000 description 7
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- 238000010586 diagram Methods 0.000 description 6
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- 238000012827 research and development Methods 0.000 description 2
- 102100021942 C-C motif chemokine 28 Human genes 0.000 description 1
- 101000897477 Homo sapiens C-C motif chemokine 28 Proteins 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
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- G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
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- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
Description
本発明は走査信号発生回路に関し、特に走査信号を交互に出力する２つのトランジスタを有する走査信号発生回路に関する。 The present invention relates to a scanning signal generation circuit, and more particularly to a scanning signal generation circuit having two transistors that alternately output scanning signals.
現在、表示技術の発展に伴って、モニタの設計動向は、より大きなサイズ、より高い解像度、より狭額縁化及び３Ｄ表示などの方向に向かって発展している。 Currently, with the development of display technology, monitor design trends are evolving toward larger sizes, higher resolutions, narrower frames and 3D display.
そのうち、狭額縁の設計方向について、モニタの元のフレームは主としてチップと回路を収納するための領域であるため、フレーム内の走査信号発生回路を簡素化に設計すると、フレームの幅を大幅に減少することができ、しかしながら、如何に当該走査信号発生回路を簡素化する上で、同時に出力走査信号を安定させる機能を持たせることは本発明の最も重要な研究開発の動機である。 Of these, the original frame of the monitor is mainly an area for housing the chip and circuit in the design direction of the narrow frame, so if the scanning signal generation circuit in the frame is designed to be simplified, the frame width will be greatly reduced. However, it is the most important motivation for research and development of the present invention to have the function of stabilizing the output scanning signal at the same time in order to simplify the scanning signal generation circuit.
図１に示すように、従来の走査信号発生回路の回路図が示され、主にトランジスタＭ１〜トランジスタＭ８、及びコンデンサーＣ１、Ｃ２からなり、トランジスタＭ１〜トランジスタＭ８は電界効果トランジスタであり、より好ましくは薄膜トランジスタ（Thin−Film Transistor、TFTと略称する）であり、当該走査信号発生回路は実際の使用場合に以下のような欠陥を有する。 As shown in FIG. 1, a circuit diagram of a conventional scanning signal generation circuit is shown. The circuit mainly includes transistors M1 to M8 and capacitors C1 and C2. The transistors M1 to M8 are field effect transistors, and more preferably. Is a thin film transistor (abbreviated as Thin-Film Transistor, TFT), and the scanning signal generation circuit has the following defects in actual use.
一、当該走査信号発生回路が発生する走査信号を出力するか否かは主にトランジスタＭ１によって制御され、一つの当該トランジスタＭ１のみが走査信号を出力するためのものであり、しかも常に導通状態にあるため、当該トランジスタＭ１の機能が衰退し、当該トランジスタＭ１の機能が異常になれば、回路全体の異常を引き起こし、さらに、モニタの表示が異常になる。 First, whether or not to output the scanning signal generated by the scanning signal generation circuit is mainly controlled by the transistor M1, and only one transistor M1 outputs the scanning signal, and is always in a conductive state. Therefore, if the function of the transistor M1 declines and the function of the transistor M1 becomes abnormal, the entire circuit is abnormal and the monitor display becomes abnormal.
二、当該従来の走査信号発生回路は、８つのトランジスタに２つのコンデンサーＣ１、Ｃ２を組み合わせて構成しなければならないため、トランジスタの数が多すぎることにより、当該走査信号発生回路の所要の空間が大きくなり、モニタの狭額縁設計の要求を満たせず、また、生産歩留まりも低下させてしまう。 2. Since the conventional scanning signal generation circuit must be configured by combining two capacitors C1 and C2 with eight transistors, the required number of the scanning signal generation circuit is reduced due to the excessive number of transistors. This increases the size of the monitor, which does not meet the requirements for designing a narrow frame of the monitor, and also reduces the production yield.
このため、上記の欠陥を同時に解決できる走査信号発生回路を如何に設計するかは本発明の研究開発の動機である。 For this reason, how to design a scanning signal generation circuit that can simultaneously solve the above defects is the motivation for the research and development of the present invention.
本発明は、安定性を向上させるように、走査信号を交互に出力する２つのトランジスタを主に有する走査信号発生回路を提供することを目的とする。 An object of the present invention is to provide a scanning signal generation circuit mainly including two transistors that alternately output scanning signals so as to improve stability.
本発明は、設置空間を削減し、モニタの狭額縁設計の要求を達成するように、主に５つのトランジスタに２つのコンデンサーを組み合わせることによって設計してなる走査信号発生回路を提供することを他の目的とする。 It is another object of the present invention to provide a scanning signal generation circuit which is designed mainly by combining two capacitors with five transistors so as to reduce the installation space and achieve the requirements of the narrow frame design of the monitor. The purpose.
上記の目的を達成するために、本発明は、モニタ走査信号を提供するための走査信号発生回路であって、データ信号を受信するための第１端と、第２周波数信号を受信するための第１制御端と、第１ノードに電気的に接続される第２端と、を有する第１トランジスタと、第２ノードに電気的に接続される第１端と、当該第１ノードに電気的に接続される第２制御端と、電源電圧を受信するための第２端と、を有する第２トランジスタと、走査信号出力端に電気的に接続される第１端と、当該第１ノードに電気的に接続される第２端と、を有する第１コンデンサーと、第１周波数信号を受信するための第１端と、当該第１ノードに電気的に接続される第３制御端と、当該第１コンデンサーの第１正極端に電気的に接続される第２端と、を有する第３トランジスタと、当該走査信号出力端に電気的に接続される第１端と、当該第２ノードに電気的に接続される第４制御端と、当該第２トランジスタの第２端に電気的に接続される第２端と、を有する第４トランジスタと、当該第４トランジスタの第１端に電気的に接続される第１端と、当該第２周波数信号を受信するための第５制御端と、当該第４トランジスタの第２端に電気的に接続される第２端と、を有する第５トランジスタと、当該第２ノードに電気的に接続される第１端と、当該第１周波数信号に電気的に接続される第２端と、を有する第２コンデンサーと、を備えることを特徴とする走査信号発生回路を開示する。 In order to achieve the above object, the present invention provides a scanning signal generation circuit for providing a monitor scanning signal, a first end for receiving a data signal, and a second frequency signal for receiving a second frequency signal. A first transistor having a first control end and a second end electrically connected to the first node; a first end electrically connected to the second node; and electrically connected to the first node A second transistor having a second control terminal connected to the second transistor, a second terminal for receiving a power supply voltage, a first terminal electrically connected to the scanning signal output terminal, and a first node A first capacitor having a second end electrically connected; a first end for receiving a first frequency signal; a third control end electrically connected to the first node; And a second end electrically connected to the first positive electrode end of the first capacitor. 3 transistors, a first end electrically connected to the scanning signal output end, a fourth control end electrically connected to the second node, and a second end of the second transistor electrically A fourth transistor having a second end connected; a first end electrically connected to the first end of the fourth transistor; a fifth control end for receiving the second frequency signal; A fifth transistor having a second terminal electrically connected to the second terminal of the fourth transistor, a first terminal electrically connected to the second node, and the first frequency signal. Disclosed is a scanning signal generating circuit comprising a second capacitor having a second end electrically connected.
本発明の更なる改良は、前記第１トランジスタ〜第５トランジスタはいずれもＰ型薄膜トランジスタ（Thin−Film Transistor、TFTと略称する）であることにある。 A further improvement of the present invention is that each of the first to fifth transistors is a P-type thin film transistor (abbreviated as Thin-Film Transistor, TFT).
本発明の更なる改良は、前記第１制御端〜第５制御端はいずれもゲート端であることにある。 A further improvement of the present invention is that the first control end to the fifth control end are all gate ends.
本発明の更なる改良は、前記第１トランジスタ〜第５トランジスタの第１端はいずれもソース端又はドレイン端であり、当該第１トランジスタ〜第５トランジスタの第２端はいずれもドレイン端又はソース端であり、且つ当該第２端が第１端と異なることにある。 In a further improvement of the present invention, the first ends of the first to fifth transistors are all source ends or drain ends, and the second ends of the first to fifth transistors are all drain ends or sources. And the second end is different from the first end.
本発明の更なる改良は、当該第１トランジスタ〜第５トランジスタの第１端はいずれもソース端であり、当該第１トランジスタ〜第５トランジスタの第２端はいずれもドレイン端であることにある。 A further improvement of the present invention is that the first ends of the first to fifth transistors are all source ends, and the second ends of the first to fifth transistors are all drain ends. .
本発明の更なる改良は、当該第１トランジスタ〜第５トランジスタの第１端はいずれもドレイン端であり、当該第１トランジスタ〜第５トランジスタの第２端はいずれもソース端であることにある。 A further improvement of the present invention is that the first ends of the first to fifth transistors are all drain ends, and the second ends of the first to fifth transistors are all source ends. .
本発明の更なる改良は、第１段階において、低レベルのデータ信号を当該第１トランジスタの第１端に提供し、高レベルの第１周波数信号を当該第２コンデンサー、第２ノードを介して当該第４トランジスタの第４制御端に提供し、低レベルの第２周波数信号をそれぞれ当該第１トランジスタの第１制御端及び当該第５トランジスタの第５制御端に提供し、このとき、当該第１トランジスタが導通状態であり、データ信号の低レベルを当該第１ノードに入力し、当該第３トランジスタを同様に導通状態にし、さらに、当該第１周波数信号が高レベルにあり、当該第２周波数信号が低レベルにあり、当該第４トランジスタを遮断状態にし、当該第５トランジスタを導通状態にし、このように、当該走査信号出力端の電圧が当該電源電圧と等しくなり、当該第５トランジスタを、走査信号を出力するトランジスタとすることにある。 A further improvement of the present invention is that in the first stage, a low level data signal is provided to the first end of the first transistor and a high level first frequency signal is provided via the second capacitor, the second node. And providing a low-level second frequency signal to the first control terminal of the first transistor and the fifth control terminal of the fifth transistor, respectively. One transistor is conductive, the low level of the data signal is input to the first node, the third transistor is similarly conductive, the first frequency signal is high, and the second frequency The signal is at a low level, the fourth transistor is turned off, the fifth transistor is turned on, and thus the voltage at the scanning signal output terminal is equal to the power supply voltage. Ri is the fifth transistor, to a transistor that outputs a scan signal.
本発明の更なる改良は、第２段階において、高レベルのデータ信号を当該第１トランジスタの第１端に提供し、高レベルの第２周波数信号をそれぞれ当該第１トランジスタの第１制御端及び当該第５トランジスタの第５制御端に提供し、このとき、当該第１トランジスタ及び第５トランジスタが遮断状態であり、当該第１ノードが低レベルを維持し、当該第３トランジスタを導通状態にし、このように、当該第１周波数信号の低レベルを当該走査信号出力端に入力し、且つ当該第４トランジスタが遮断状態であることにある。 According to a further improvement of the invention, in the second stage, a high level data signal is provided to the first end of the first transistor, and a high level second frequency signal is provided to the first control end of the first transistor, respectively. Provided to the fifth control terminal of the fifth transistor, wherein the first transistor and the fifth transistor are in a cut-off state, the first node is maintained at a low level, and the third transistor is turned on; Thus, the low level of the first frequency signal is input to the scanning signal output terminal, and the fourth transistor is in the cut-off state.
本発明の更なる改良は、第３段階において、高レベルの第１周波数信号を当該第２コンデンサー、第２ノードを介して当該第４トランジスタの第４制御端に提供し、低レベルの第２周波数信号をそれぞれ当該第１トランジスタの第１制御端及び当該第５トランジスタの第５制御端に提供し、このとき、当該第１トランジスタ及び第５トランジスタが同様に導通状態であり、当該第２トランジスタ及び第３トランジスタが同様に遮断状態であり、第１ノード及び第２ノードが高レベルにあり、当該第４トランジスタを遮断状態にすることにある。 According to a further improvement of the present invention, in the third stage, a high-level first frequency signal is provided to the fourth control terminal of the fourth transistor via the second capacitor and the second node. A frequency signal is provided to the first control terminal of the first transistor and the fifth control terminal of the fifth transistor, respectively. At this time, the first transistor and the fifth transistor are similarly in a conductive state, and the second transistor Similarly, the third transistor is in a cutoff state, the first node and the second node are at a high level, and the fourth transistor is in a cutoff state.
本発明の更なる改良は、その後のタイミング作動過程において、第２ノードは第２コンデンサーによって、第１周波数信号の変化に伴って変化し、そのタイミングが第１周波数信号と同様であり、第１周波数信号と第２周波数信号のタイミングがちょうど逆であり、当該第４トランジスタと第５トランジスタを交互に導通させることにある。 In a further improvement of the present invention, in the subsequent timing operation process, the second node is changed by the second capacitor according to the change of the first frequency signal, and the timing is the same as the first frequency signal. The timing of the frequency signal and the second frequency signal is exactly opposite, and the fourth transistor and the fifth transistor are alternately made conductive.
以下、図面及び具体的な実施形態を参照しながら、本発明をさらに詳しく説明する。 Hereinafter, the present invention will be described in more detail with reference to the drawings and specific embodiments.
図２に示すように、本発明実施例が提供する走査信号発生回路であり、主に第１トランジスタＭ１と、第２トランジスタＭ２と、第１コンデンサーＣ１と、第３トランジスタＭ３と、第４トランジスタＭ４と、第５トランジスタＭ５と、第２コンデンサーＣ２とからなり、当該第１トランジスタＭ１〜第５トランジスタＭ５がいずれもＰ型薄膜トランジスタ（Thin−Film Transistor、TFTと略称する）である。 As shown in FIG. 2, the scanning signal generating circuit provided by the embodiment of the present invention is mainly a first transistor M1, a second transistor M2, a first capacitor C1, a third transistor M3, and a fourth transistor. M4, a fifth transistor M5, and a second capacitor C2, each of the first transistor M1 to the fifth transistor M5 is a P-type thin film transistor (abbreviated as Thin-Film Transistor, TFT).
当該第１トランジスタＭ１は、データ信号ＳＴＶを受信するための第１端１１と、第２周波数信号ＣＫ２を受信するための第１制御端１２と、第１ノードＮＥＴ１に電気的に接続される第２端１３とを有する。本実施例において、当該第１トランジスタＭ１の第１制御端１２はゲート端であり、当該第１端１１と第２端１３との間の導通を制御し、当該第１トランジスタＭ１を導通状態又は遮断状態にするためのものであり、当該第１端１１はソース端又はドレイン端であり、当該第２端１３はドレイン端又はソース端であり、且つ当該第２端１３と第１端１１とが異なり、即ち、第１端１１がソース端であると、第２端１３がドレイン端であり、第１端１１がドレイン端であると、第２端１３がソース端である。同様に、以下の第２トランジスタＭ２、第３トランジスタＭ３、第４トランジスタＭ４及び第５トランジスタＭ５がそれぞれ対応する第２制御端２２、第３制御端３２、第４制御端４２及び第５制御端５２はいずれもゲート端であり、それぞれは、対応する当該第１端２１、３１、４１、５１と第２端２３、３３、４３、５３との間の導通を制御するためのものであり、当該第１端２１、３１、４１、５１のそれぞれはソース端又はドレイン端であり、当該第２端２３、３３、４３、５３のそれぞれはドレイン端又はソース端であり、且つ当該第２端２３、３３、４３、５３と第１端２１、３１、４１、５１とが異なる。
The first transistor M1 is electrically connected to a first terminal 11 for receiving the data signal STV, a
当該第２トランジスタＭ２は、第２ノードＮＥＴ２に電気的に接続される第１端２１と、当該第１ノードＮＥＴ１に電気的に接続される第２制御端２２と、電源電圧ＶＤＤを受信するための第２端２３と、を有する。
The second transistor M2 receives a power supply voltage VDD, a first terminal 21 electrically connected to the second node NET2, a
当該第１コンデンサーＣ１は、走査信号出力端Ｓｎに電気的に接続される第１端６１と、当該第１ノードＮＥＴ１に電気的に接続される第２端６２と、を有する。本実施例において、第１端６１は、例えば正極端であり、第２端６２は、例えば負極端である。
The first capacitor C1 has a
当該第３トランジスタＭ３は、第１周波数信号ＣＫ１を受信するための第１端３１と、当該第１ノードＮＥＴ１に電気的に接続される第３制御端３２と、当該第１コンデンサーＣ１の第１正極端６１に電気的に接続される第２端３３と、を有する。
The third transistor M3 includes a first end 31 for receiving the first frequency signal CK1, a third control end 32 electrically connected to the first node NET1, and a first end of the first capacitor C1. And a
当該第４トランジスタＭ４は、当該走査信号出力端Ｓｎに電気的に接続される第１端４１と、当該第２ノードＮＥＴ２に電気的に接続される第４制御端４２と、当該第２トランジスタＭ２の第２端２３に電気的に接続される第２端４３と、を有する。
The fourth transistor M4 includes a first end 41 electrically connected to the scanning signal output terminal Sn, a fourth control terminal 42 electrically connected to the second node NET2, and the second transistor M2. And a
当該第５トランジスタＭ５は、当該第４トランジスタＭ４の第１端４１に電気的に接続される第１端５１と、当該第２周波数信号ＣＫ２を受信するための第５制御端５２と、当該第４トランジスタＭ４の第２端４３に電気的に接続される第２端５３と、を有する。
The fifth transistor M5 includes a
当該第２コンデンサーＣ２は、当該第２ノードＮＥＴ２に電気的に接続される第１端７１と、当該第１周波数信号ＣＫ１に電気的に接続される第２端７２と、を有する。
The second capacitor C2 has a first end 71 that is electrically connected to the second node NET2, and a
以上のように本発明実施例の各主要部品の構成説明である。本発明の作動方式及びその効果については以下に説明する。 As described above, the configuration of each main part of the embodiment of the present invention is described. The operation method and effects of the present invention will be described below.
図２、３に示すように、図３は本発明実施例の制御タイミング模式図であり、水平軸は時間を示し、ＳＴＶ＿Ｈはデータ信号ＳＴＶの高レベルであり、ＳＴＶ＿Ｌはデータ信号ＳＴＶの低レベルであり、ＣＫ１＿Ｈは第１周波数信号ＣＫ１の高レベルであり、ＣＫ１＿Ｌは第１周波数信号ＣＫ１の低レベルであり、ＣＫ２＿Ｈは第２周波数信号ＣＫ２の高レベルであり、ＣＫ２＿Ｌは第２周波数信号ＣＫ２の低レベルである。 As shown in FIGS. 2 and 3, FIG. 3 is a schematic diagram of the control timing of the embodiment of the present invention, the horizontal axis indicates time, STV_H is the high level of the data signal STV, and STV_L is the low level of the data signal STV. CK1_H is a high level of the first frequency signal CK1, CK1_L is a low level of the first frequency signal CK1, CK2_H is a high level of the second frequency signal CK2, and CK2_L is a level of the second frequency signal CK2. Low level.
第１段階Ｔ１において、低レベルのデータ信号ＳＴＶを当該第１トランジスタＭ１の第１端１１に提供し、高レベルの第１周波数信号ＣＫ１を当該第２コンデンサーＣ２、第２ノードＮＥＴ２を介して当該第４トランジスタＭ４の第４制御端４２に提供し、低レベルの第２周波数信号ＣＫ２をそれぞれ当該第１トランジスタＭ１の第１制御端１２及び当該第５トランジスタＭ５の第５制御端５２に提供し、このとき、当該第１トランジスタＭ１は導通状態であり、データ信号ＳＴＶの低れべるを当該第１ノードＮＥＴ１に入力し、当該第３トランジスタＭ３を同様に導通状態にし、さらに、当該第１周波数信号ＣＫ１が高レベルにあり、出力が高レベルであり、また、Ｍ２が導通状態であり、高電位の電源電圧ＶＤＤを第４トランジスタＭ４の第４制御端４２に入力し、当該第４トランジスタＭ４を遮断状態にし、当該第２周波数信号ＣＫ２が低レベルにあり、当該第５トランジスタＭ５が導通状態であり、このように、当該走査信号出力端Ｓｎの電圧が当該電源電圧ＶＤＤと等しくなり、当該第５トランジスタＭ５を、走査信号を出力するトランジスタとする。
In the first stage T1, the low level data signal STV is provided to the first terminal 11 of the first transistor M1, and the high level first frequency signal CK1 is supplied to the first terminal 11 through the second capacitor C2 and the second node NET2. Provided to the fourth control terminal 42 of the fourth transistor M4, and provides the low-level second frequency signal CK2 to the
第２段階Ｔ２において、高レベルのデータ信号ＳＴＶを当該第１トランジスタＭ１の第１端１１に提供し、高レベルの第２周波数信号ＣＫ２をそれぞれ当該第１トランジスタＭ１の第１制御端１２及び当該第５トランジスタＭ５の第５制御端５２に提供し、このとき、当該第１トランジスタＭ１及び第５トランジスタＭ５が遮断状態であり、当該第１ノードＮＥＴ１が低レベルを維持し、当該第３トランジスタＭ３を導通状態にし、このように、当該第１周波数信号ＣＫ１の低レベルを当該走査信号出力端Ｓｎに入力し、このとき第２トランジスタＭ２の導通によって、電源電圧ＶＤＤを高電位で第４トランジスタＭ４の第４制御端４２に入力し、当該第４トランジスタＭ４を遮断状態にする。
In the second stage T2, the high level data signal STV is provided to the first end 11 of the first transistor M1, and the high level second frequency signal CK2 is supplied to the
第３段階Ｔ３において、高レベルの第１周波数信号ＣＫ１を当該第２コンデンサーＣ２、第２ノードＮＥＴ２を介して当該第４トランジスタＭ４の第４制御端４２に提供し、低れべるの第２周波数信号ＣＫ２をそれぞれ当該第１トランジスタＭ１の第１制御端１２及び当該第５とらんじすたＭ５の第５制御端５２に提供し、このとき、当該第１トランジスタＭ１及び第５トランジスタＭ５が同様に導通状態であり、当該第２トランジスタＭ２及び第３トランジスタＭ３が同様に遮断状態であり、第１ノードＮＥＴ１及び第２ノードＮＥＴ２が高レベルにあり、当該第４トランジスタＭ４を遮断状態にする。
In the third stage T3, the high-level first frequency signal CK1 is provided to the fourth control terminal 42 of the fourth transistor M4 through the second capacitor C2 and the second node NET2, and the second level of the second signal CCK1 is decreased. The frequency signal CK2 is provided to the
その後のタイミング作動過程において、第２ノードＮＥＴ２が第２コンデンサーＣ２によって、第１周波数信号ＣＫ１の変化に伴って変化し、そのタイミングが第１周波数信号ＣＫ１と同様であり、第１周波数信号ＣＫ１と第２周波数信号ＣＫ２のタイミングがちょうど逆であり、当該第４トランジスタＭ４と第５トランジスタＭ５を交互に導通させ、これによって、本発明は、当該走査信号発生回路の安定性を向上させるための、走査信号を交互に出力する２つのトランジスタ（即ち、第４トランジスタＭ４と第５トランジスタＭ５）を主に有する。 In the subsequent timing operation process, the second node NET2 is changed by the second capacitor C2 in accordance with the change of the first frequency signal CK1, and the timing is the same as the first frequency signal CK1, and the first frequency signal CK1 The timing of the second frequency signal CK2 is exactly opposite, and the fourth transistor M4 and the fifth transistor M5 are alternately turned on, whereby the present invention improves the stability of the scanning signal generation circuit. It mainly includes two transistors (that is, a fourth transistor M4 and a fifth transistor M5) that alternately output scanning signals.
また、本発明は、当該走査信号発生回路の設置空間を削減し、モニタの狭額縁設計の要求を達成するために、主に５つのトランジスタに２つのコンデンサーを組み合わせることによって設計してなる。 Further, the present invention is designed mainly by combining two capacitors with five transistors in order to reduce the installation space of the scanning signal generation circuit and achieve the requirement for designing a narrow frame of the monitor.
図４は４つの本発明の回路により構成された回路である。図４は上記基本回路を４つのユニットとして組み合わせて、Ｓｔｖからの入力から第４段階の出力までを完成し、この回路はモニタ製品に適用し、タイミングの制御を完成することができる。 FIG. 4 shows a circuit constituted by four circuits of the present invention. FIG. 4 combines the above basic circuit as four units to complete the input from Stv to the fourth stage output, and this circuit can be applied to a monitor product to complete the timing control.
以上、図面と実施例を参照しながら本発明を詳しく説明したが、当業者は、上記の説明に基づいて本発明に対して種々の変形例を施すことができる。このため、実施例におけるいくつかの細部は本発明を限定すべきではなく、本発明は、添付の特許請求の範囲で定義された範囲を本発明の保護範囲とする。 Although the present invention has been described in detail with reference to the drawings and embodiments, those skilled in the art can make various modifications to the present invention based on the above description. For this reason, some details in the examples should not limit the present invention, and the scope of the present invention shall be defined by the appended claims.
Claims (10)
データ信号を受信するための第１端と、第２周波数信号を受信するための第１制御端と、第１ノードに電気的に接続される第２端と、を有する第１トランジスタと、
第２ノードに電気的に接続される第１端と、当該第１ノードに電気的に接続される第２制御端と、電源電圧を受信するための第２端と、を有する第２トランジスタと、
走査信号出力端に電気的に接続される第１端と、当該第１ノードに電気的に接続される第２端と、を有する第１コンデンサーと、
第１周波数信号を受信するための第１端と、当該第１ノードに電気的に接続される第３制御端と、当該第１コンデンサーの第１端に電気的に接続される第２端と、を有する第３トランジスタと、
当該走査信号出力端に電気的に接続される第１端と、当該第２ノードに電気的に接続される第４制御端と、当該第２トランジスタの第２端に電気的に接続される第２端と、を有する第４トランジスタと、
当該第４トランジスタの第１端に電気的に接続される第１端と、当該第２周波数信号を受信するための第５制御端と、当該第４トランジスタの第２端に電気的に接続される第２端と、を有する第５トランジスタと、
当該第２ノードに電気的に接続される第１端と、当該第１周波数信号に電気的に接続される第２端と、を有する第２コンデンサーと、
を備えることを特徴とする走査信号発生回路。 A scanning signal generation circuit for providing a monitor scanning signal,
A first transistor having a first end for receiving a data signal, a first control end for receiving a second frequency signal, and a second end electrically connected to the first node;
A second transistor having a first end electrically connected to the second node, a second control end electrically connected to the first node, and a second end for receiving a power supply voltage; ,
A first capacitor having a first end electrically connected to the scanning signal output end and a second end electrically connected to the first node;
A first end for receiving the first frequency signal; a third control end electrically connected to the first node; a second end electrically connected to the first end of the first capacitor; A third transistor having
A first end electrically connected to the scanning signal output end, a fourth control end electrically connected to the second node, and a second end electrically connected to the second end of the second transistor. A fourth transistor having two ends;
A first end electrically connected to the first end of the fourth transistor, a fifth control end for receiving the second frequency signal, and a second end of the fourth transistor are electrically connected. A fifth transistor having a second end;
A second capacitor having a first end electrically connected to the second node and a second end electrically connected to the first frequency signal;
A scanning signal generation circuit comprising:
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006024350A (en) * | 2004-06-30 | 2006-01-26 | Samsung Electronics Co Ltd | Shift register, display device having the same and method of driving the same |
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| CN102629459A (en) * | 2011-10-26 | 2012-08-08 | 北京京东方光电科技有限公司 | Gate line driving method, shift register and gate line driving device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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