CN106981263A - A kind of array scanning control circuit of flat-panel monitor - Google Patents
A kind of array scanning control circuit of flat-panel monitor Download PDFInfo
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- CN106981263A CN106981263A CN201710381545.5A CN201710381545A CN106981263A CN 106981263 A CN106981263 A CN 106981263A CN 201710381545 A CN201710381545 A CN 201710381545A CN 106981263 A CN106981263 A CN 106981263A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
A kind of array scanning control circuit of flat-panel monitor, array scanning control circuit includes multiple stage array scan control unit, and the array scanning control unit is feedback signal using the output signal of the array scanning control unit.The array scanning control circuit of the present invention reduces transistor size, reduces the area of array scanning control unit, and stable output signal.
Description
Technical field
The present invention relates to display device technology field, more particularly to a kind of array scanning control circuit.This case is
The division of 2015103640894 (a kind of array scanning control circuits of flat-panel monitor).
Background technology
Flat-panel monitor is the main product of current display device, and array scanning control circuit is widely used in flat board and shown
Show in the drive circuit of device.Array scanning control circuit has storage and shift function, and scanning letter is sequentially generated by scan line
Number and be output to the grid of image element circuit, realize the function of gating line by line.
The circuit of array scanning control circuit in a kind of conventional driver circuits of prior art is as shown in figure 1, the array
Scan control circuit is using every four array scanning control units as one group, and every group of structure is identical, in order to simplify structure, and the figure is only drawn
Gone out first group of the circuit diagram that the array scanning controls circuit, i.e., the circuit diagram of preceding level Four array scanning control unit, including：
First order array scanning control unit 11, second level array scanning control unit 12, the and of third level array scanning control unit 13
Fourth stage array scanning control unit 14.It can be seen that array scanning control circuit has 4 input clock signals
(except supply voltage VDD and input initial pulse signal Start), makes sequential more complicated.First clock signal clk 1 and
Three clock signal clks 3 are connected to first order array scanning control unit 11 and the control of the 3rd array scanning in the way of the method for reporting to the leadship after accomplishing a task
Unit 13, and second clock signal CLK2 and the 4th clock signal clk 4 are connected to second level array scanning in the way of the method for reporting to the leadship after accomplishing a task
The array scanning control unit 14 of control unit 12 and the 4th, so makes structure more complicated, can increase circuit in placement-and-routing
Difficulty.In order to increase the driving force of array scanning control unit output end, transistor T5 and transistor T6 have to bear
Larger electric current, and PMOS (Positivechannel Metal Oxide Semiconductor, P-channel metal oxide half
Conductor field-effect transistor) hole mobility it is lower than electron mobility, so T5 and T6 conducting channel width is larger, its
Width is typically about several millimeters, and each array scanning control unit is made up of 6 PMOSs, and this can make circuit area
Increase.Generally speaking, array scanning control circuit can increase cost, and yield rate is low.
In addition, by analysis, the array scanning control circuit of the figure goes wrong in 4M+1 and 4M+2 units, and (M is just
Integer).By taking the 5th array scanning control unit as an example, the first time of the first clock signal clk 1 be low level when, the unit it is defeated
Go out to hold OUT5 to should be high level, but be actually not.Because at this moment T5 and the T6 cut-off of Unit the 5th, equivalent to two resistance pair
The partial pressure of VDD and CLK1 electrical potential difference, causes output voltage to be pulled low, and the row is gated in advance, causes data corruption.
The content of the invention
The problem to be solved in the present invention is to provide a kind of array scanning control circuit, with overcome in the prior art cost it is high,
Yield rate is low, easily cause the defect of data corruption.
To reach above-mentioned purpose, technical scheme provides a kind of array scanning control circuit, and the circuit includes
Multiple stage array scan control unit, described multiple stage array scan control unit includes：
One the first transistor, with grid level, one first source/drain and one second source/drain level, wherein, the first order
The output signal of the array scanning control unit of the first source/drain level connection previous stage of transistor；
One second transistor, with grid level, one first source/drain and one second source/drain level, wherein, second crystalline substance
The grid level of body pipe and grid level connection a period of time clock signal of the first transistor, the first source/drain level connection one of the second transistor
Low level voltage；
One third transistor, with grid level, one first source/drain and one second source/drain level, wherein, the 3rd is brilliant
The first source/drain level of body pipe connects the second source/drain level of the second transistor；
One the 4th transistor, with grid level, one first source/drain and one second source/drain level, wherein, the 4th is brilliant
The grid level of body pipe connects the second source/drain level of the first transistor, another clock of the first source/drain level connection of the 4th transistor
Signal；And
One the 5th transistor, with grid level, one first source/drain and one second source/drain level, wherein, the 5th is brilliant
The grid level of body pipe connects the second source/drain level of the second transistor and the first source/drain level of third transistor, the 5th transistor
The first source/drain level, the second source/drain of the 4th transistor level and third transistor grid level connection this grade of array scanning control it is single
The output end of member, the second source/drain level of the 5th transistor and the second source/drain level connection one high level electricity of the third transistor
Pressure.
Wherein, in an odd level array scanning control unit of the multiple stage array scan control unit, this second
The grid level of transistor and grid level the first clock signal of connection of the first transistor, the first source/drain cascade of the 4th transistor
Connect second clock signal.
Wherein, when the array scanning control unit is first order array scanning control unit, the first transistor of this grade
The first source/drain connection one input initial pulse signal.
Wherein, in an even level array scanning control unit of the multiple stage array scan control unit, this second
The grid level of transistor and the grid level connection second clock signal of the first transistor, the first source/drain cascade of the 4th transistor
Connect the first clock signal.
Wherein, the first transistor, second transistor, third transistor, the 4th transistor and the 5th transistor are
PMOS transistor.
Wherein, every grade of array scanning control unit of the circuit is made up of 5 PMOS transistors.
Wherein, the first transistor, second transistor, third transistor, the 4th transistor and the 5th transistor are TFT
(Thin Film Transistor, TFT).
Wherein, the circuit production is on a glass substrate.
Wherein, the output of the circuit is extended to the output of multiple array scanning control units.
Compared with prior art, technical scheme has the following advantages that：
The array scanning control circuit of the present invention has multiple stage array scan control unit, every grade of array scanning control unit
Only five input signals, five transistors and an output signal, the present invention are feedback signal, output letter using output signal
Scanning signal is provided for image element circuit number by scan line.The array scanning control circuit area of the present invention is small, simple in construction, defeated
Go out signal stabilization, yield rate can be significantly increased, cost is reduced.
Brief description of the drawings
Fig. 1 controls the circuit diagram of circuit for the array scanning in a kind of conventional driver circuits of prior art；
Fig. 2 is a kind of circuit diagram of array scanning control unit of the embodiment of the present invention；
Fig. 3 is the circuit diagram of Fig. 2 odd level array scanning control unit；
Fig. 4 is the circuit diagram of Fig. 2 even level array scanning control unit；
Fig. 5 controls the structure chart of circuit for a kind of array scanning of the embodiment of the present invention；
Fig. 6 controls the circuit diagram of the preceding level Four array scanning control unit of circuit for the array scanning according to Fig. 5；
Fig. 7 is the timing diagram of the circuit according to Fig. 6.
Reference in above-mentioned accompanying drawing is as follows：
11st, 61 first order array scanning control unit
12nd, 62 second level array scanning control unit
13rd, 63 third level array scanning control unit
14th, 64 fourth stage array scanning control unit
21st, 22,23, G (2n) input signal
24th, G (2n+1), G (2n+2) output signal
Start, SIN input initial pulse signal
The clock signals of CLK1 first
CLK2 second clock signals
The clock signals of CLK3 the 3rd
The clock signals of CLK4 the 4th
VDD high level voltages
VSS low level voltages
The output signal of OUT1, G1 first order array scanning control unit
The output signal of OUT2, G2 second level array scanning control unit
The output signal of OUT3, G3 third level array scanning control unit
The output signal of OUT4, G4 fourth stage array scanning control unit
The output signal of N grades of array scanning control units of Gn
T1 the first transistors
T2 second transistors
T3 third transistor
The transistors of T4 the 4th
The transistors of T5 the 5th
The transistors of T6 the 6th
T1, t2, t3, t4, t5 period
Embodiment
With reference to the accompanying drawings and examples, the embodiment to the present invention is described in further detail.Implement below
Example is used to illustrate the present invention, but is not limited to the scope of the present invention.
A kind of circuit of array scanning control unit of the embodiment of the present invention is as shown in Fig. 2 be N grades of battle arrays in the present embodiment
The circuit of column scan control unit.The circuit is made up of 5 transistors, including transistor T1, transistor T2, transistor T3, crystalline substance
Transistor T1, transistor T2, transistor T3, transistor T4 and transistor T5 are in body pipe T4 and transistor T5, the present embodiment
PMOS；The circuit has 5 input ports, including input port 21, input port 22, input port 23, input port VSS and
Input port VDD, an output port 24.Wherein, the control of the connection of input port 21 previous stage ((N-1) level) array scanning is single
The output signal of first output end, input port 22 and input port 23 connect the clock signal of two opposite in phase respectively.Crystal
Pipe T1 grid level and transistor T2 grid level connection input port 22, transistor T1 the first source/drain connection input port
21.Transistor T2 the first source/drain connects a low level voltage VSS, transistor T2 the second source/drain and transistor
T3 the first source/drain connection transistor T5 grid.Transistor T3 the second source/drain and the second of transistor T5
Source/drain connects a high level voltage VDD.Transistor T4 grid connection transistor T1 the second source/drain, transistor T4
The first source/drain connection input port 23, transistor T4 the second source/drain and transistor T5 the first source/drain
Connect output port 24.The feedback link transistor of output port 24 T3 grid.
The present invention is in order to realize that function takes connection method of reporting to the leadship after accomplishing a task between odd even several levels array scanning control unit.Below will
It is discussed in detail, refer to Fig. 3 and Fig. 4, Fig. 3 is the circuit diagram of Fig. 2 odd level array scanning control unit, and Fig. 4 is Fig. 2's
The circuit diagram of even level array scanning control unit, wherein n are positive integer.In figure 3, odd number (2n+1) level array scanning
Transistor T1 and transistor T2 grid connect a clock signal CLK1 in control unit, and transistor T4 the first source/drain connects
Meet a clock signal CLK2, the output letter of transistor T1 the first source/drain connection previous stage (G (2n) level) output port
Number, i.e. the output signal of even level output port.As n=0, G (2n)=G0, then input port G0 is an input starting arteries and veins
Rush signal.In Fig. 4, transistor T1 and transistor T2 grid connection should in even number (2n+2) level array scanning control unit
Clock signal clk 2, transistor T4 the first source/drain connects the clock signal clk 1, and transistor T1 the first source/drain connects
Connect the output signal of the output signal, i.e. odd level output port of previous stage (G (2n+1) level) output port.
Odd level and even level array scanning control unit are sequentially connected as requested and just obtained with many
The array scanning control circuit of level array scanning control unit, in order to simplify structure and readily appreciate, this array scanning control electricity
Road is represented with structured flowchart, as shown in figure 5, the Fig. 5, which is the array scanning with N grades of array scanning control units, controls circuit
Structured flowchart, wherein N ＞ 0.
In order to be even further appreciated that refer to Fig. 6, the figure lists array and swept to the array scanning of present invention control circuit
The circuit of the preceding level Four array scanning control unit of control circuit is retouched, including：First order array scanning control unit 61, the second level
Array scanning control unit 62, third level array scanning control unit 63 and fourth stage array scanning control unit 64.First
In level array scanning control unit 61, transistor T1 first order source/drain connection one inputs initial pulse signal SIN, crystal
Pipe T1 grid and transistor T2 grid connect the first clock signal clk 1, transistor T4 first order source/drain connection the
Two clock signal clks 2.In second level array scanning control unit 62, the transistor T1 first order source/drain connection first order
The output end G1 of array scanning control unit 61, transistor T1 grid and transistor T2 grid connection second clock signal
CLK2, transistor T4 first order source/drain connect the first clock signal clk 1.In third level array scanning control unit 63
In, transistor T1 first order source/drain connects the output end G2 of second level array scanning control unit 62, transistor T1 grid
Pole and transistor T2 grid connect the first clock signal clk 1, transistor T4 first order source/drain connection second clock letter
Number CLK2.In level Four array scanning control unit 64, transistor T1 first order source/drain connection third level array scanning control
The output end G3 of unit 63 processed, transistor T1 grid and transistor T2 grid connection second clock signal CLK2, transistor
T4 first order source/drain connects the first clock signal clk 1.
In order to illustrate Fig. 6 circuit operation, Fig. 7 is refer to, the Fig. 7 is a timing diagram of the circuit according to Fig. 6.
Analysis first order array scanning control unit 61, in time t1, inputs initial pulse signal SIN for low level first, and first
Clock signal clk 1 is low level, and second clock signal CLK2 is high level.In first order array scanning control unit 61, the
One transistor T1 pipes are turned on, and initial pulse signal SIN low level is transferred to the 4th transistor T4 grid, then the 4th transistor
T4 is turned on, and second clock signal CLK2 high level is transferred to output end G1, then output end G1 is high level；Meanwhile, second is brilliant
Body pipe T2 is turned on, and low level voltage VSS is transferred to the 5th transistor T5 grid, then the 5th transistor T5 is turned on, high level electricity
Pressure VDD is transferred to output end G1, then output end G1 is still high level；Output end G1 high level feedback transmission is to third transistor
T3 grid, third transistor T3 cut-offs.Therefore, during time t1, output end G1 remains high level.In time t2,
Input initial pulse signal SIN is changed into high level, and the first clock signal clk 1 is changed into high level, and second clock signal CLK2 is changed into
Low level.In first order array scanning control unit 61, the first transistor T1 pipes cut-off, but the 4th transistor T4 grid still
Low level so is maintained at, so the 4th transistor T4 is still turned on, second clock signal CLK2 low level is transferred to output end
G1, then output end G1 be pulled down to low level；Meanwhile, second transistor T2 cut-offs, low level voltage VSS can not be transferred to the 5th
Transistor T5 grid, and output end G1 low level feedback transmission is to third transistor T3 grid, then third transistor T3
Conducting, high level voltage VDD is transferred to the 5th transistor T5 grid, then the 5th transistor T5 ends；Therefore, in phase time t2
Between, output end G1 is pulled down and remains low level.In time t3, input initial pulse signal SIN is high level, when first
Clock signal CLK1 is low level, and second clock signal CLK2 is high level.In first order array scanning control unit 61, first
Transistor T1 pipes are turned on, and initial pulse signal SIN high level is transferred to the 4th transistor T4 grid, then the 4th transistor T4
Cut-off；Meanwhile, second transistor T2 conductings, low level voltage VSS is transferred to the 5th transistor T5 grid, then the 5th transistor
T5 is turned on, and high level voltage VDD is transferred to output end G1, then output end G1 is pulled up as high level；Output end G1 high level
Feedback transmission to third transistor T3 grid, third transistor T3 cut-off.Therefore, during time t3, output end G1 is kept
For high level.Hereafter, output end G1 is that high level is always until inputting initial pulse signal SIN low level next time and arriving
Only.Similarly, when analyzing second level array scanning control unit 62, by the output end G1 of first order array scanning control unit 61
It is used as the input initial pulse signal of the second array scanning control unit.In time t2, first order array scanning control unit
61 output end G1 is low level, and the first clock signal clk 1 is changed into high level, and second clock signal CLK2 is changed into low level.
In second level array scanning control unit 62, the first transistor T1 pipes conducting, output end G1 low level is transferred to the 4th crystal
Pipe T4 grid, then the 4th transistor T4 conductings, the high level of the first clock signal clk 1 is transferred to output end G2, then output end
G2 is high level；Meanwhile, second transistor T2 conductings, low level voltage VSS is transferred to the 5th transistor T5 grid, then and the 5th
Transistor T5 is turned on, and high level voltage VDD is transferred to output end G2, then output end G2 is still high level；Output end G2 height electricity
Feedback of redressing is transferred to third transistor T3 grid, then third transistor T3 ends.Therefore, during time t2, output end G2
Remain high level.In time t3, the output end G1 of first order array scanning control unit 61 is high level, the first clock letter
Number CLK1 is changed into low level, and second clock signal CLK2 is changed into high level.In second level array scanning control unit 62, first
Transistor T1 pipes end, but the 4th transistor T4 grid remains in that low level, so the 4th transistor T4 is still turned on, the
One clock signal CLK1 low level is transferred to output end G2, then output end G2 is pulled down to low level；Meanwhile, second transistor
T2 ends, and low level voltage VSS can not be transferred to the 5th transistor T5 grid, and output end G2 low level feedback transmission is arrived
Third transistor T3 grid, then third transistor T3 conductings, high level voltage VDD is transferred to the 5th transistor T5 grid,
Then the 5th transistor T5 ends；Therefore, during time t3, output end G2 is pulled down and remains low level.In time t4,
The output end G1 of first order array scanning control unit 61 is high level, and the first clock signal clk 1 is high level, second clock
Signal CLK2 is low level.In second level array scanning control unit 62, the conducting of the first transistor T1 pipes, output end G1 height
Level is transferred to the 4th transistor T4 grid, then the 4th transistor T4 ends；Meanwhile, second transistor T2 conductings, low level
Voltage VSS is transferred to the 5th transistor T5 grid, then the 5th transistor T5 is turned on, and high level voltage VDD is transferred to output end
G2, then output end G2 be pulled up as high level；Output end G2 high level feedback transmission to third transistor T3 grid, then
Three transistor T3 end.Therefore, during time t3, output end G2 remains high level.Hereafter, output end G2 is always high electricity
Untill the straight low level next time to output end G1 arrives.When analyzing third level array scanning control unit 63, by second
The output end G2 of level array scanning control unit 62 is used as the input initial pulse signal of the 3rd array scanning control unit, work
Principle is as first order array scanning control unit 61 or second level array scanning control unit 62, by that analogy.
The array scanning control circuit of the present invention has multiple stage array scan control unit, every grade of array scanning control unit
Only five input signals, five transistors and an output signal, the present invention utilize output signal for feedback signal, and defeated
Go out signal and provide scanning signal by scan line for image element circuit.Relatively conventional array scanning control circuit (refer to Fig. 1), this
Invention reduces input clock signal number, although add low level voltage VSS, but total input signal is also the reduction of,
And input clock signal reduces half, the annoyance level between clock signal is just reduced.In addition, utilizing the output of output end
Signal not only reduces the transistor size of array scanning control unit as the method for feedback signal, and makes output signal steady
It is fixed.Thus the array scanning control circuit area of the present invention is small, simple in construction, so as to reduce production cost, improves yield rate.
In addition, the array scanning of the present invention controls circuit except the gate driving circuit applied to display device drive circuit
In, it can also be applied in source electrode drive circuit.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, some improvements and modifications can also be made, these improvements and modifications
Also it should be regarded as protection scope of the present invention.
Claims (3)
1. a kind of array scanning with N grades of array scanning control units controls circuit, including：The control of first order array scanning is single
First (61), second level array scanning control unit (62), third level array scanning control unit (63) and fourth stage array scanning
Control unit (64), it is characterised in that in first order array scanning control unit (61), transistor T1 first order source/drain
Pole connection one inputs initial pulse signal SIN, and transistor T1 grid and transistor T2 grid connect the first clock signal
CLK1, transistor T4 first order source/drain connection second clock signal CLK2, in second level array scanning control unit (62)
In, the output end G1 of transistor T1 first order source/drain connection first order array scanning control unit (61), transistor T1's
Grid and transistor T2 grid connection second clock signal CLK2, transistor T4 first order source/drain connect the first clock
Signal CLK1, in third level array scanning control unit (63), transistor T1 first order source/drain connection second level array
The output end G2 of scan control unit (62), transistor T1 grid and transistor T2 grid connect the first clock signal
CLK1, transistor T4 first order source/drain connection second clock signal CLK2, in fourth stage array scanning control unit (64)
In, the output end G3 of transistor T1 first order source/drain connection third level array scanning control unit (63), transistor T1's
Grid and transistor T2 grid connection second clock signal CLK2, transistor T4 first order source/drain connect the first clock
Signal CLK1.
2. array scanning as claimed in claim 1 controls circuit, it is characterised in that first order array scanning control unit
(61), in time t1, input initial pulse signal SIN is low level, and the first clock signal clk 1 is low level, second clock
Signal CLK2 is high level, in first order array scanning control unit (61), the conducting of the first transistor T1 pipes, initial pulse letter
Number SIN low level is transferred to the 4th transistor T4 grid, then the 4th transistor T4 is turned on, second clock signal CLK2 height
Level is transferred to output end G1, then output end G1 is high level；Meanwhile, second transistor T2 conductings, low level voltage VSS transmission
To the 5th transistor T5 grid, then the 5th transistor T5 conductings, high level voltage VDD is transferred to output end G1, then output end
G1 is still high level；Output end G1 high level feedback transmission to third transistor T3 grid, third transistor T3 cut-off.
3. array scanning as claimed in claim 2 controls circuit, it is characterised in that in time t2, input initial pulse letter
Number SIN is changed into high level, and the first clock signal clk 1 is changed into high level, and second clock signal CLK2 is changed into low level, first
In level array scanning control unit (61), the cut-off of the first transistor T1 pipes, but the 4th transistor T4 grid still remain in it is low
Level, so the 4th transistor T4 is still turned on, second clock signal CLK2 low level is transferred to output end G1, then output end
G1 is pulled down to low level；Meanwhile, second transistor T2 cut-offs, low level voltage VSS can not be transferred to the 5th transistor T5's
Grid, and output end G1 low level feedback transmission is to third transistor T3 grid, then third transistor T3 is turned on, high level
Voltage VDD is transferred to the 5th transistor T5 grid, then the 5th transistor T5 ends.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710381545.5A CN106981263A (en) | 2015-06-29 | 2015-06-29 | A kind of array scanning control circuit of flat-panel monitor |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510364089.4A CN104900179B (en) | 2015-06-29 | 2015-06-29 | A kind of array scanning control circuit of flat-panel monitor |
| CN201710381545.5A CN106981263A (en) | 2015-06-29 | 2015-06-29 | A kind of array scanning control circuit of flat-panel monitor |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510364089.4A Division CN104900179B (en) | 2015-06-29 | 2015-06-29 | A kind of array scanning control circuit of flat-panel monitor |
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| CN106981263A true CN106981263A (en) | 2017-07-25 |
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| CN201510364089.4A Expired - Fee Related CN104900179B (en) | 2015-06-29 | 2015-06-29 | A kind of array scanning control circuit of flat-panel monitor |
| CN201710381545.5A Pending CN106981263A (en) | 2015-06-29 | 2015-06-29 | A kind of array scanning control circuit of flat-panel monitor |
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| KR100796137B1 (en) * | 2006-09-12 | 2008-01-21 | 삼성에스디아이 주식회사 | Shift register and organic light emitting display device using the same |
| CN101145398A (en) * | 2006-09-12 | 2008-03-19 | 三星Sdi株式会社 | Shift register and organic light emitting display using the same |
| CN102598144A (en) * | 2009-11-04 | 2012-07-18 | 夏普株式会社 | Shift register and the scan signal line driving circuit provided there with, and display device |
| CN102867475A (en) * | 2012-09-13 | 2013-01-09 | 京东方科技集团股份有限公司 | Shifting register unit, grid driving circuit and display device |
| CN203849978U (en) * | 2013-12-25 | 2014-09-24 | 昆山工研院新型平板显示技术中心有限公司 | Scanning driver and organic light-emitting display employing same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104900179A (en) | 2015-09-09 |
| CN104900179B (en) | 2017-08-18 |
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Application publication date: 20170725 |