JP2016040995A - Drive circuit board, power unit, and power conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit board provided with a drive circuit of a power semiconductor element suitable for miniaturization, a power unit having the drive circuit board, and a power conversion device including the power unit.SOLUTION: A drive circuit board is provided with a drive circuit having: a primary circuit 41 which is inputted with a pulse train signal supplied from a higher level control circuit; a secondary circuit 42 which converts the pulse train signal supplied from the primary circuit into a gate drive signal of a power semiconductor element, and drives on/off the power semiconductor element in response to the gate drive signal; a feedback circuit for feeding the gate drive signal from the secondary circuit back to the primary circuit; and a detection circuit which is provided on the primary circuit, and detects that a state in which a feedback signal by the feedback circuit does not match the pulse train signal on the primary circuit side continues for at least a fixed period.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a drive circuit board, a power unit, and a power conversion device.

  There is a power conversion device having a function of converting DC power into AC power or a function of converting AC power into DC power. In recent years, there has been a demand for higher output density of this type of power converter, and accordingly, power converters have been reduced in size and weight. Then, in the power conversion device, as the power unit integrated with components such as a power semiconductor module, a capacitor, and a bus bar on which the power semiconductor element is mounted is miniaturized, a driving circuit for driving the power semiconductor element (the power semiconductor element of the power semiconductor element) There is a growing need for miniaturization of drive circuit boards on which drive circuits are mounted.

  By the way, in addition to a circuit for controlling the turn-on and turn-off of the power semiconductor element, a circuit for detecting an abnormality in the power semiconductor element and the drive circuit is mounted on the power semiconductor element drive circuit. As a conventional technique for detecting an abnormality in a power semiconductor element or a drive circuit, there are a technique described in Patent Document 1 and a technique described in Patent Document 2.

  In Patent Document 1, a secondary side (high voltage side) circuit for driving a power semiconductor element is provided with a comparator, and it is determined whether the gate voltage of the power semiconductor element is higher than the reference voltage of the comparator. A technique for feeding back to a primary side (low voltage side) circuit by a photocoupler transistor is described. In Patent Document 2, a gate voltage discriminating unit and a gate current discriminating unit are provided in a gate driving circuit which is a high-voltage side circuit, and the gate voltage feedback pulse and the gate current feedback pulse output from these discriminating units are used as the basis. Describes a technique for generating a gate feedback pulse.

JP-A-8-298786 JP 2009-165348 A

  As described above, each of the conventional techniques described in Patent Documents 1 and 2 adopts a circuit configuration that detects an abnormality of the power semiconductor element and the gate drive circuit in the secondary side circuit that is the high-voltage side circuit. For this reason, the circuit scale of the secondary circuit is increased, and a high-breakdown-voltage circuit element is required. Therefore, the drive circuit of the power semiconductor element according to the prior art is not suitable for miniaturization of the drive circuit board on which the drive circuit is mounted because the circuit area occupied by the circuit element increases.

  Therefore, an object of the present invention is to provide a drive circuit board on which a drive circuit for a power semiconductor element suitable for miniaturization is mounted, a power unit having the drive circuit board, and a power conversion device including the power unit.

In order to solve the above problems, for example, the configuration described in the claims is adopted.
The present application includes a plurality of means for solving the above problems.
A primary circuit that receives a pulse train signal supplied from an upper control circuit;
A secondary side circuit that uses the pulse train signal supplied from the primary side circuit as a gate drive signal of a power semiconductor element, and drives the power semiconductor element on and off based on the gate drive signal;
A feedback circuit for feeding back the gate drive signal from the secondary circuit to the primary circuit;
A detection circuit provided in the primary side circuit for detecting that a state in which a feedback signal from the feedback circuit is inconsistent with a pulse train signal on the primary side circuit side continues for a certain period;
A drive circuit having the above is mounted.

According to the present invention, the circuit configuration of the secondary side circuit can be simplified and the board occupation area of the circuit element can be reduced as a whole, so that the drive circuit board and the power unit having the drive circuit board can be reduced in size. Can do. Moreover, size reduction of the power converter device which has a power unit can be achieved by using the said power unit.
Problems, configurations, and effects other than those described above will become apparent from the following description of embodiments.

It is an example of a block diagram which shows the basic composition of the drive circuit of a power semiconductor element. It is an example of the perspective view which shows the outline of a structure of a power unit and a power converter device. It is an example of the circuit diagram which shows the circuit structure of the drive circuit of the power semiconductor element which concerns on a reference example. It is an example of the timing chart which shows the operation timing of the drive circuit of the power semiconductor element which concerns on a reference example. It is an example of the schematic plan view which shows the image of arrangement | positioning of the primary side circuit and secondary side circuit on a control board at the time of mounting the drive circuit of a power semiconductor element on a control board. 1 is an example of a circuit diagram illustrating a circuit configuration of a drive circuit for a power semiconductor element according to Embodiment 1. FIG. 3 is an example of a timing chart showing the operation timing of the drive circuit for the power semiconductor element according to the first embodiment. FIG. 8A is an example of a component board mounting image diagram for explaining the effect of reducing the component board mounting area. FIG. 8A shows a case of a reference example, and FIG. 8B shows a case of Example 1. FIG. 6 is an example of a circuit diagram illustrating a circuit configuration of a drive circuit for a power semiconductor element according to Embodiment 2. FIG. FIG. 9 is an example of a circuit diagram illustrating a circuit configuration of a drive circuit for a power semiconductor element according to a third embodiment. FIG. 10 is an example of a circuit diagram illustrating a circuit configuration of a drive circuit for a power semiconductor element according to a fourth embodiment.

  Hereinafter, modes for carrying out the present invention (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The present invention is not limited to the embodiment. In the present specification and drawings, the same components or components having substantially the same function are denoted by the same reference numerals, and redundant description is omitted.

<Power conversion device>
The power converter has a function of an inverter that converts DC power into AC power or a function of a converter that converts AC power into DC power. This type of power conversion device is, for example, an uninterruptible power system that aims to supply AC power to a load such as a server without interruption using energy stored in a storage battery. : UPS). However, the use illustrated here is an example and is not limited to the use for an uninterruptible power supply.

[Basic configuration of power semiconductor element drive circuit]
First, the basic configuration of the drive circuit for the power semiconductor element of the main circuit in the power conversion device will be described. FIG. 1 is an example of a block diagram showing a basic configuration of a drive circuit for a power semiconductor element.

  In FIG. 1, a power semiconductor element drive circuit 1 includes an upper arm drive circuit 4 that drives an upper arm power semiconductor element 2, a lower arm drive circuit 5 that drives a lower arm power semiconductor element 3, and an upper control circuit 6. It has composition which has. Hereinafter, the drive circuit 1 of the power semiconductor element may be simply referred to as the drive circuit 1.

  The upper arm power semiconductor element 2 and the lower arm power semiconductor element 3 are switching elements that switch a high power supply voltage according to a gate voltage. As the power semiconductor elements 2 and 3, an insulated gate bipolar transistor (IGBT), which is an example of a voltage-driven element, can be used.

  The upper arm power semiconductor element 2 and the lower arm power semiconductor element 3 are main circuits in the power converter, and are connected in series between the high potential side power source and the low potential side power source. That is, the drain of the upper arm power semiconductor element 2 is connected to the high potential side power source, the source of the lower arm power semiconductor element 3 is connected to the low potential side power source, and the source of the upper arm power semiconductor element 2 and the lower arm power semiconductor element 3 is connected in common to the output terminal OUT. Then, a voltage (output voltage) derived to the output terminal OUT is supplied to a load (not shown).

  The upper arm drive circuit 4 includes a primary side circuit 41 that is a low voltage side circuit and a secondary side circuit 42 that is a high voltage side circuit. Similarly, the lower arm drive circuit 5 includes a primary side circuit 51 and a secondary side circuit 52. Between the primary side circuits 41 and 51 and the secondary side circuits 42 and 52, transmission means 43 and 53 for transmitting signals while being electrically insulated between the two are provided.

  As the transmission means 43 and 53, for example, a well-known photocoupler composed of a combination of a light emitting diode and a phototransistor can be used. The photocoupler protects a circuit from high voltage and noise, and can ensure safety by electrical insulation and accuracy of a signal to be transmitted. However, the photocoupler is an example of means for transmitting signals while being electrically insulated, and the transmission means 43 and 53 are not limited to photocouplers.

  The upper control circuit 6 supplies a pulse train signal for controlling these to the upper arm drive circuit 4 and the lower arm drive circuit 5. The pulse train signal is, for example, a pulse width modulation (PWM) signal (hereinafter referred to as “PWM signal”) using a carrier wave that changes at a constant frequency. When the pulse train signal is a PWM signal, the accuracy of control can be increased by increasing the frequency of the carrier wave.

  In the upper arm drive circuit 4 and the lower arm drive circuit 5, the primary side circuits 41 and 51 receive the PWM signal supplied from the host control circuit 6 as an input. The PWM signal is electrically insulated by the transmission means 43 and 53 and transmitted from the primary side circuits 41 and 51 to the secondary side circuits 42 and 52. The secondary side circuits 42 and 52 use the PWM signals supplied from the primary side circuits 41 and 51 as gate drive signals for the power semiconductor elements 2 and 3, and turn on the power semiconductor elements 2 and 3 based on the gate drive signals. • Drive off.

  The gate drive signals of the power semiconductor elements 2 and 3 are pulse train signals corresponding to the PWM signals supplied from the primary side circuits 41 and 51. Here, when there is an abnormality in the circuit elements (for example, resistance elements) and the power semiconductor elements 2 and 3 constituting the secondary side circuits 42 and 52, a missing pulse (missing) occurs in the gate drive signal which is a pulse train signal. There is a case. Hereinafter, the phenomenon in which the pulse of the gate drive signal is missing (missed) is referred to as “pulse missing phase”.

  The occurrence of a pulse phase loss in the gate drive signal means that the waveform of the gate drive signal does not match the waveform of the PWM signal in a certain section in the time axis direction, that is, does not match. When the power semiconductor elements 2 and 3 are driven by a gate drive signal whose waveform does not match that of the PWM signal supplied from the host control circuit 6, normal driving corresponding to the PWM signal cannot be performed.

  Therefore, the upper arm drive circuit 4 and the lower arm drive circuit 5 include a detection circuit (not shown) (hereinafter referred to as “pulse phase loss detection circuit”) that detects a pulse phase loss of the gate drive signal. This pulse phase loss detection circuit detects that a pulse phase loss has occurred in the gate drive signal when the state in which the gate drive signal and the PWM signal do not match continues for a certain period or longer. The pulse phase loss detection circuit supplies the pulse phase loss detection signal to the control circuit 6 when detecting the pulse phase loss of the gate drive signal.

  By the way, the PWM signal is not always supplied from the control circuit 6 to the upper arm drive circuit 4 and the lower arm drive circuit 5, and the PWM signal may not be supplied. As described above, even when the PWM signal is not supplied from the control circuit 6, the pulse phase loss detection circuit determines that the state in which the gate drive signal and the PWM signal do not match continues for a certain period or more, and the pulse phase loss detection signal Will be output. However, the pulse phase loss detection signal at this time is a detection signal when the PWM signal is not supplied from the control circuit 6 and is an abnormality of the circuit elements constituting the secondary side circuits 42 and 52 and the power semiconductor elements 2 and 3. It is not a detection signal caused by

  Therefore, when a pulse phase loss detection signal is supplied from the pulse phase loss detection circuit of the upper arm drive circuit 4 or the lower arm drive circuit 5, the control circuit 6 starts with the upper arm drive circuit 4 and the lower arm drive circuit 5. It is determined from the supply state of the PWM signal supplied to the primary side circuits 41 and 51 whether the pulse phase loss detection signal is valid. Here, the “PWM signal supply state” refers to supplying a PWM signal (pulse train signal) to the upper arm drive circuit 4 (primary side circuit 41) and the lower arm drive circuit 5 (primary side circuit 51). Whether the state is a state or a state where a PWM signal is not supplied.

  When the supply state of the PWM signal when the pulse phase loss detection signal is supplied is a state in which the PWM signal is not supplied, the control circuit 6 configures the secondary side circuits 42 and 52. Since the detection signal is not caused by an abnormality of the circuit element or the power semiconductor elements 2 and 3, the pulse phase loss detection signal is determined to be invalid. Further, when the supply state of the PWM signal when the pulse phase loss detection signal is supplied is a state in which the PWM signal is supplied, the control circuit 6 outputs the pulse phase loss detection signal to the secondary side circuits 42 and 52. Because the detection signal is caused by an abnormality in the circuit elements and power semiconductor elements 2 and 3, the pulse phase loss detection signal is determined to be valid. In this case, the control circuit 6 stops supplying the PWM signal to the primary side circuits 41 and 51.

[Configuration of power unit and power converter]
Next, the structure of a power unit and a power converter device is demonstrated. FIG. 2 is an example of a perspective view showing an outline of the configuration of the power unit and the power conversion device.

  In FIG. 2, the power unit 10 includes components such as the power semiconductor elements 2 and 3, the smoothing capacitor 11, the heat receiving block 12, the heat pipe 13, the heat radiating fins 14, the bus bar 15, and the fuses 16n and 16p. It is a unit unit configured integrally. The heat receiving block 12 is provided so as to sandwich the power semiconductor module 17 on which the power semiconductor elements 2 and 3 are mounted from both sides. The heat pipe 13 is built in the heat receiving block 12. The heat radiating fins 14 function to release heat from the heat pipe 13. The bus bar 15 is a member for connecting the power semiconductor elements 2 and 3 and the smoothing capacitor 11. The fuses 16n and 16p are connected to the bus bar 15.

  A control board 20 is further attached to the power unit 10. The control board 20 is a drive circuit board on which the power semiconductor element drive circuit 1 described above is mounted. The width (size in the X direction in the figure) of the power unit 10 is determined by the width (size in the X direction in the figure) of the control board 20. Therefore, if the control board 20 can be reduced in size, particularly narrowed, the power unit 10 can be narrowed.

  The power conversion device 30 is configured by combining a fan unit 31 for discharging cooling air, a passive component 32 of the power conversion device 30, and the like using a plurality of power units 10 having the above-described configuration. In the case of this example, six power units 10 are arranged in the middle part of the power conversion device 30. The six power units 10 include, for example, three power units for three phases of inverters and three power units for three phases of converters. However, the number of power units 10 arranged in the power converter 30 is not limited to six, and the number is arbitrary. The fan unit 31 is disposed on the upper portion of the power conversion device 30, and the passive component 32 is disposed on the lower portion of the power conversion device 30.

  If the width of the control board 20 and the accompanying reduction in the width of the power unit 10 can be achieved, when the power unit 10 is incorporated in the power conversion device 30, the accessibility from the front of the device to the control board 20 at the time of signal check is easy. In addition, the installation area of the power conversion device 30 can be reduced and the power conversion device 30 can be reduced in size.

  As described above, the drive circuit 1 of the power semiconductor element mounted on the control board (drive circuit board) 20 has a state in which the gate drive signal and the PWM signal do not coincide with each other for a certain period or longer. A pulse phase loss detection circuit for detecting the pulse phase loss is provided. Hereinafter, the pulse phase loss detection circuit will be described more specifically.

<Drive circuit of power semiconductor element according to reference example>
First, the power semiconductor element drive circuit 1 adopting the configuration in which the pulse phase loss detection circuit described above is provided in the secondary side circuits 42 and 52 of FIG. 1 will be described as a power semiconductor element drive circuit according to a reference example.

  The upper arm drive circuit 4 that drives the upper arm power semiconductor element 2 and the lower arm drive circuit 5 that drives the lower arm power semiconductor element 3 basically adopt the same circuit configuration. Therefore, in the following description, the upper arm drive circuit 4 that drives the upper arm power semiconductor element 2 will be described as an example of the drive circuit 1 for the power semiconductor element.

  FIG. 3 is an example of a circuit diagram illustrating a circuit configuration of a drive circuit for a power semiconductor element according to a reference example. FIG. 4 is an example of a timing chart showing the operation timing of the drive circuit for the power semiconductor element according to the reference example.

  In the upper arm drive circuit 4 that drives the upper arm power semiconductor element 2, the PWM signal is input from the upper control circuit 6 (see FIG. 1) to the primary side circuit 41 that is the low voltage side circuit. The PWM signal input to the primary side circuit 41 is transmitted to the secondary side circuit 42 by a photocoupler 43A which is an example of the transmission means 43. The photocoupler 43A transmits the PWM signal from the primary side circuit 41 to the secondary side circuit 42 while being electrically insulated.

  The secondary side circuit 42 includes a positive bias power supply 61 and a negative bias power supply 62 as drive power supplies. The PWM signal transmitted from the primary side circuit 41 to the secondary side circuit 42 is supplied to the gate of the upper arm power semiconductor element 2 through the buffer circuit 63 and the resistance element 64 as a gate drive signal of the upper arm power semiconductor element 2. Applied.

  A resistance element 65 is connected between the output node N1 of the buffer circuit 63 and the low potential side power supply line L1. A diode 66 and a resistance element 67 are connected in series between a node N2 which is one end of the resistance element 65 and the low potential side power supply line L1. That is, a series connection circuit of the diode 66 and the resistance element 67 is connected in parallel to the resistance element 65. The node N2 is also an output node N1 of the buffer circuit 63. A capacitive element 68 is connected between the positive node of the positive bias power supply 61 and the low potential power supply line L1.

  Between the secondary circuit 42 and the primary circuit 41, a photocoupler 43B is provided as an example of means for transmitting a signal from the secondary circuit 42 to the primary circuit 41. The anode of the light emitting diode 431 of the photocoupler 43B is connected to the node N3 which is one end of the capacitive element 68. The node N3 is also a positive side node of the positive bias power supply 61. A Zener diode 69 and a resistance element 70 are connected in series between the cathode of the light emitting diode 431 and the low potential side power supply line L1. In addition, a resistance element 71 is connected in parallel to the light emitting diode 431, and a capacitive element 72 is connected in parallel to the Zener diode 69.

  Then, the above-described pulse phase loss detection circuit, that is, the pulse phase loss of the gate drive signal is obtained by the resistor element 65, the diode 66, the resistor element 67, the capacitor element 68, the Zener diode 69, the resistor elements 70 and 71, and the capacitor element 72. A pulse phase loss detection circuit for detection is configured. The circuit operation of the pulse phase loss detection circuit according to this reference example will be described with reference to the timing chart of FIG. FIG. 4 shows waveforms of the voltage across the capacitor 68, the gate drive signal, and the pulse phase loss detection signal.

  When the gate drive signal output from the buffer circuit 63 is in an inactive (low level / low) state, a potential difference occurs between both ends of the capacitive element 68, so that the capacitive element 68 is charged via the resistive element 65. Is done. Further, when the gate drive signal output from the buffer circuit 63 is in an active (high level / high) state, the potentials of the node N2 and the node N3 become the same potential, and the nodes N2 and N3 are simulated. Are short-circuited, so that the charge charged in the capacitor element 68 is discharged through the diode 66 and the resistance element 67. If the resistance value of the resistance element 65 as the charging resistance is larger than the resistance value of the resistance element 67 as the discharging resistance, the discharging time becomes shorter than the charging time.

  As shown in the timing chart of FIG. 4, since the capacitive element 68 is charged when the gate drive signal output from the buffer circuit 63 is in an inactive state, the voltage across the capacitive element 68 gradually increases. Further, since the capacitive element 68 is discharged when the gate drive signal output from the buffer circuit 63 is in the active state, the voltage across the capacitive element 68 rapidly decreases. The maximum voltage Vmax applied to the capacitive element 68 is a total voltage of the power supply voltages of the positive bias power supply 61 and the negative bias power supply 62 of the drive power supply of the secondary side circuit 42.

  Here, when the inactive state continues for a predetermined period T or more in the gate drive signal, the voltage across the capacitive element 68 reaches the detection threshold voltage Vth of the pulse phase loss detection circuit. This detection threshold voltage Vth is determined by the Zener voltage of the Zener diode 69, the voltage across the resistance element 70, which is a current limiting resistor, and the ON voltage of the photocoupler 43B. When the voltage across the capacitor 68 reaches the detection threshold voltage Vth, the photocoupler 43B becomes conductive. Thereby, the pulse phase loss detection circuit detects that the state in which the gate drive signal and the PWM signal do not match continues for a certain period T or more, that is, the pulse phase loss occurs in the gate drive signal. A pulse phase loss detection signal by this detection is transmitted from the secondary side circuit 42 to the primary side circuit 41 by the photocoupler 43B, and further supplied from the primary side circuit 41 to the upper control circuit 6 (see FIG. 1). Is done.

  Note that the resistance element 71 and the capacitance element 72 in FIG. 3 do not directly contribute to the detection of the pulse phase loss and the voltage detection, but absorb noise generated by the switching operation of the upper arm power semiconductor element 2 and the like. Acts as a filter.

  In the upper arm drive circuit 4 according to the reference example shown in FIG. 3, the secondary circuit 42 is generally a circuit that handles a high voltage, and thus is configured using high-breakdown-voltage circuit elements. Therefore, the resistance element 65 and the capacitive element 68 that are charging resistors are increased in size to increase the breakdown voltage. As for the capacitive element 68, an electrolytic capacitor having a large unit capacity is used in order to achieve a high breakdown voltage and a large capacity. However, electrolytic capacitors have low reliability with respect to ripple and life. Further, regarding the resistance element 65, it is necessary to consider the usage rate and make it a specification corresponding to a large power, resulting in an increase in the size of the element.

  For the reason described above, in the upper arm drive circuit 4 according to the reference example in which the pulse phase loss detection circuit is provided in the secondary side circuit 42, the circuit scale of the secondary side circuit 42 is increased, and the resistance element 65 and A high breakdown voltage circuit element is required as the capacitor element 68. The same applies to the lower arm drive circuit 5. Therefore, the power semiconductor element drive circuit including the upper arm drive circuit 4 and the lower arm drive circuit 5 according to the reference example has a large area occupied by the circuit elements, and thus the control board 20 on which the drive circuit is mounted can be downsized. Not suitable.

<Drive Circuit for Power Semiconductor Device According to this Embodiment>
The power semiconductor element driving circuit according to the present embodiment employs a configuration in which a pulse phase loss detection circuit is provided in the primary side circuits 41 and 51. As a result, the drive circuit for the power semiconductor element according to this embodiment has a pulse missing phase detection circuit as compared with the drive circuit for the power semiconductor element according to the comparative example in which the pulse missing phase detection circuit is provided in the secondary side circuits 42 and 52. The circuit configurations of the secondary side circuits 42 and 52 can be simplified by the absence of the phase detection circuit.

  Furthermore, in the power semiconductor element drive circuit according to the present embodiment, the element breakdown voltage and the element power consumption of the circuit elements constituting the pulse phase loss detection circuit can be reduced. Thereby, since the circuit scale of the pulse phase loss detection circuit can be reduced as compared with the case where it is provided in the secondary side circuits 42 and 52, coupled with the fact that the circuit configuration of the secondary side circuits 42 and 52 can be simplified, The board occupation area of the circuit element can be reduced as a whole. As a result, the control board 20 on which the drive circuit for the power semiconductor element is mounted and the power unit 10 (see FIG. 2) having the control board 20 can be reduced in size, in particular, the width can be reduced, and a plurality of power units 10 can be used. The power conversion device 30 (see FIG. 2) configured as described above can be reduced in size, and the installation area can be reduced accordingly.

  By the way, when mounting the drive circuit 1 of the power semiconductor element shown in FIG. 1 on the control board 20, it is possible to reduce the cost of the control board 20 by sharing the components (circuit elements) constituting the drive circuit 1 as much as possible. This is preferable. At this time, since the primary side circuits 41 and 51 are low voltage side circuits, it is possible to share components between the primary side circuits 41 and 51. However, as for the secondary side circuits 42 and 52, since elements having different powers are usually used as the upper arm power semiconductor element 2 and the lower arm power semiconductor element 3, components are shared between the secondary side circuits 42 and 52. Is difficult to

  FIG. 5 is a schematic plan view showing an image of the arrangement of the primary side circuits 41 and 51 and the secondary side circuits 42 and 52 on the control board 20 when the power semiconductor element drive circuit 1 is mounted on the control board 20. It is an example. 5 shows a state in which only the primary side circuits 41 and 51 and the secondary side circuits 42 and 52 are mounted on the control board 20 for easy understanding. Other circuits will be installed.

  As shown in FIG. 5, the primary side circuits 41 and 51 capable of sharing components are mounted on the control board 20 as a common circuit, and the secondary circuits 42 and 52 that are difficult to share components are used. It is mounted on the control board 20 as an individual circuit. At that time, regarding the secondary side circuits 42 and 52 mounted on the control board 20 as individual circuits, it is important to reduce the circuit scale in order to reduce the size of the control board 20, in particular, to reduce the width. Become.

  On the other hand, according to the drive circuit for the power semiconductor element according to the present embodiment, the circuit configuration of the secondary side circuits 42 and 52 can be simplified, and the area occupied by the substrate of the circuit element can be reduced as a whole. Therefore, since the circuit scale of the secondary side circuits 42 and 52 can be reduced, the effect is great in reducing the size, particularly the width, of the control board 20 and the power unit 10 having the control board 20.

  A specific example of the drive circuit for the power semiconductor element according to the present embodiment in which the pulse phase loss detection circuit is provided in the primary side circuits 41 and 51 will be described below.

[Example 1]
FIG. 6 is an example of a circuit diagram illustrating the circuit configuration of the drive circuit for the power semiconductor element according to the first embodiment. FIG. 7 is an example of a timing chart showing the operation timing of the drive circuit for the power semiconductor element according to the first embodiment. In the first embodiment, as the power semiconductor element drive circuit 1, an upper arm drive circuit 4 that drives the upper arm power semiconductor element 2 will be described as an example. The same applies to the examples described later.

  In FIG. 6, the PWM signal transmitted from the primary side circuit 41 to the secondary side circuit 42 by the photocoupler 43A passes through the input resistance element 73 as the gate drive signal of the upper arm power semiconductor element 2, and then is buffered. The voltage is applied to the gate of the upper arm power semiconductor element 2 through the circuit 63 and the resistance element 64. The gate drive signal output from the buffer circuit 63 is transmitted from the secondary circuit 42 to the primary circuit 41 by the photocoupler 43B after passing through the current limiting resistor 74. Here, the current limiting resistor element 74 and the photocoupler 43B constitute a feedback circuit that feeds back a gate drive signal from the secondary side circuit 42 to the primary side circuit 41.

  The primary side circuit 41 includes a charge / discharge circuit 81 that performs a charge / discharge operation in accordance with a feedback signal (gate drive signal) fed back from the secondary side circuit 42, and a comparator 82 that is an example of a comparison circuit. Yes. The charge / discharge circuit 81 includes a resistance element 84 and a capacitor element 85 connected in series between a primary power supply 83 that is a first power supply and a power supply line L2 of a low potential power supply that is a second power supply. The charge / discharge circuit 81 charges the capacitive element 85 from the primary side power supply 83 via the resistance element 84 when the feedback signal is in an inactive state (low level state).

  The charge / discharge circuit 81 discharges the charge accumulated in the capacitor element 85 when the feedback signal is in an active state (high level state). More specifically, the phototransistor 432 of the photocoupler 43B is connected in parallel to the capacitor element 85. Then, the phototransistor 432 becomes conductive when the feedback signal is in the active state, and discharges the charge accumulated in the capacitor 85. That is, the charging / discharging circuit 81 includes a resistance element 84, a capacitive element 85, and a phototransistor 432 of the photocoupler 43B.

  In the charging / discharging circuit 81, a common connection node N <b> 11 between the resistance element 84 and the capacitive element 85 is an output terminal of the charging / discharging circuit 81. The output voltage of the charge / discharge circuit 81 led to this output terminal becomes the non-inverted (+) input of the comparator 82. A resistive element 86 and a resistive element 87 are connected in series between the primary power supply 83 and the power supply line L2, and a voltage dividing circuit that divides the voltage between the primary power supply 83 and the power supply line L2. Is configured. Then, the divided voltage derived to the common connection node N <b> 12 between the resistance element 86 and the resistance element 87 becomes an inverting (−) input of the comparator 82.

  The comparator 82 uses the divided voltage as an inverting input as a reference voltage, and compares the output voltage of the charge / discharge circuit 81 with the reference voltage, so that the feedback signal does not match the PWM signal on the primary circuit 41 side. It is determined whether or not the state has continued for a certain period T or more. Therefore, the divided voltage serving as the reference voltage is set so as to correspond to a certain period T according to the resistance values of the resistance element 86 and the resistance element 87. When the output voltage of the charge / discharge circuit 81 exceeds the reference voltage, the comparator 82 determines that the state in which the feedback signal does not match the PWM signal has continued for a certain period T or more, and the output voltage is changed from a low level to a high level. Invert.

  The output voltage of the comparator 82 is applied to the base of the output transistor 89 via the resistance element 88. A resistance element 90 is connected between the base and emitter of the output transistor 89. The output transistor 89 becomes conductive in response to the polarity inversion from the low level to the high level of the output voltage of the comparator 82, and indicates that the state where the feedback signal does not match the PWM signal has continued for a certain period T or more. Outputs a pulse phase loss detection signal. This pulse phase loss detection signal is supplied from the primary side circuit 41 to the upper control circuit 6 (see FIG. 1).

  The charge / discharge circuit 81, the comparator 82, the resistance elements 86 and 87, which are voltage dividing resistors, the output transistor 89, and the resistance elements 88 and 90 constitute a pulse phase loss detection circuit. The circuit operation of the pulse phase loss detection circuit according to the first embodiment will be described with reference to the timing chart of FIG. FIG. 7 shows waveforms of the voltage across the capacitor 68, the feedback signal (gate drive signal), the output of the photocoupler 43B, and the pulse phase loss detection signal.

  When the feedback signal (gate drive signal) fed back from the secondary circuit 42 is in an inactive (low level / low) state, the phototransistor 432 of the photocoupler 43B is in a non-conduction (off) state. . As a result, the capacitive element 85 is charged from the primary power supply 83 via the resistive element 84, and thus the voltage across the capacitive element 85 monotonously increases.

  On the other hand, when the feedback signal (gate drive signal) is in an active (high level / high) state, the phototransistor 432 of the photocoupler 43B is in a conductive (on) state. As a result, the charge accumulated in the capacitive element 85 is discharged through the phototransistor 432, so that the voltage across the capacitive element 85 rapidly decreases. The maximum voltage Vmax applied to the capacitive element 85 is determined by the power supply voltage of the primary side power supply 83.

  Here, when the feedback signal (gate drive signal) continues inactive for a certain period T or more, the voltage across the capacitive element 85 reaches the detection threshold voltage Vth of the pulse phase loss detection circuit. This detection threshold voltage Vth is set as a reference voltage for the comparator 82 by a resistance element 86 and a resistance element 87, which are voltage dividing resistors, provided on the input side of the comparator 82. When the voltage across the capacitive element 85 exceeds the detection threshold voltage Vth, that is, when the output voltage of the charge / discharge circuit 81 exceeds the reference voltage of the comparator 82, the polarity of the output of the comparator 82 is reversed, so that the output transistor 89 becomes conductive ( ON) state. Thereby, the pulse phase loss detection circuit detects that the state in which the feedback signal (gate drive signal) and the PWM signal do not match continues for a certain period T or more. A pulse phase loss detection signal based on this detection is supplied from the primary side circuit 41 to the upper control circuit 6 (see FIG. 1).

  Here, when the resistance value of the resistance element 84 provided in the primary side circuit 41 is R, the capacitance value of the capacitance element 85 is C, and the power supply voltage of the primary side power supply 83 is V0, the voltage across the capacitance element 85 Vc can be expressed as (Equation 1).

  When the value of the detection time T (the fixed period T in FIG. 7) is Ts, the voltage value Vs of the detection threshold voltage Vth can be expressed by (Expression 2).

  The detection threshold voltage Vth can be set as a reference voltage of the comparator 82 by the resistance elements 86 and 87 provided on the input side of the comparator 82. The resistance value of the resistance element 86 is R1, and the resistance value of the resistance element 87 is Is R2, the voltage value Vs of the detection threshold voltage Vth is set as shown in (Expression 3).

  When the voltage Vc across the capacitor 85 is larger than the voltage value Vs of the detection threshold voltage Vth, the output of the comparator 82 is inverted in polarity. Then, the inverted output of the comparator 82 is output as a phase loss detection signal via the pulse output transistor 89.

  As described above, in the upper arm drive circuit 4 according to the first embodiment, since the pulse phase loss detection circuit is configured by the resistor element 84, the capacitor element 85, and the like provided in the primary side circuit 41, the secondary side Compared with the case where the pulse phase loss detection circuit is configured in the circuit 42, the circuit configuration of the secondary side circuit 42 can be simplified by the absence of the pulse phase loss detection circuit.

  Further, by providing the pulse phase loss detection circuit in the primary side circuit 41, it is possible to set the detection threshold voltage Vth when the same detection time T as that provided in the secondary side circuit 42 is set to a lower voltage. Therefore, it is possible to use components (elements) having a low breakdown voltage as the resistance element 84 and the capacitor element 85. Thereby, as the capacitive element 85, for example, a ceramic capacitor having higher reliability with respect to ripple and life compared to the electrolytic capacitor can be used, so that the reliability of the circuit can be improved.

  In addition, since the low breakdown voltage component can be easily downsized, the board mounting area of the component (circuit element) can be reduced. Thereby, coupled with the fact that the circuit configuration of the secondary circuit 42 can be simplified, the board area occupied by the components can be reduced as a whole, so that the size of the control board 20 on which the drive circuit 1 for power semiconductor elements is mounted can be reduced. Especially, it can contribute to narrowing.

  Here, with reference to FIG. 8, the effect of reducing the board mounting area of the component by providing the primary phase circuit 41 with the pulse phase loss detection circuit will be specifically described. FIG. 8 is an example of a component board mounting image diagram for explaining the effect of reducing the substrate mounting area of the component. Here, FIG. 8A is a substrate mounting image diagram of components of the secondary circuit 42 in the power semiconductor element drive circuit 1 according to the reference example shown in FIG. 3, and FIG. 8B is a drive of the power semiconductor element according to the first embodiment. FIG. 3 is a board mounting image diagram of components of a primary side circuit 41 and a secondary side circuit 42 in the circuit 1.

  As shown in FIG. 8A, in the power semiconductor element drive circuit 1 according to the reference example, the secondary side circuit 42 which is a high-voltage side circuit is connected to a resistance element 65 for charging, a capacitive element 68, a diode 66, and a resistance for discharging An element 67 is provided. Accordingly, since the size of these four components is increased, the secondary circuit 42 occupies a large board mounting area.

  In the power semiconductor element drive circuit 1 according to the first embodiment, the above four components occupying a large board mounting area are deleted from the secondary side circuit 42. Instead, the primary side circuit 41 includes a resistance element 84 and a capacitor. An element 85, resistance elements 86 and 87 for setting a reference voltage, an output transistor 89, and the like are provided. As a result, since any low-breakdown-voltage element can be used as a part newly added to the primary side circuit 41, as is apparent from FIG. 8B, the part size is small, and the board mounting area of the total circuit parts is reduced. Significant reduction is possible.

[Example 2]
FIG. 9 is an example of a circuit diagram illustrating a circuit configuration of a power semiconductor element drive circuit according to the second embodiment. The second embodiment is a modification of the first embodiment.

  The circuit configuration of the second embodiment shown in FIG. 9 is different from the circuit configuration of the first embodiment shown in FIG. 6 in that the noise filter resistance element 71, the capacitive element 72, and the Zener diode 69 are omitted. The three components, the resistive element 71, the capacitive element 72, and the Zener diode 69, are components that do not participate in the pulse phase loss detection operation. Therefore, even if these three parts are deleted, the pulse phase loss detection signal is derived in the same manner as in the circuit configuration of the first embodiment shown in FIG. be able to. However, noise resistance is inferior to that of the circuit configuration of the first embodiment shown in FIG.

  In the circuit configuration of the second embodiment, since the three components of the resistance element 71, the capacitance element 72, and the Zener diode 69 are deleted, the components involved in the detection of the pulse phase loss in the secondary side circuit 42 include a feedback circuit. Only the current limiting resistor element 74 and the photocoupler 43B are included. Thereby, compared with the circuit configuration of the first embodiment, the circuit configuration of the secondary circuit 42 can be further simplified. The power semiconductor element drive circuit according to the second embodiment is particularly applicable to a drive circuit having a slow switching operation.

[Example 3]
FIG. 10 is an example of a circuit diagram illustrating a circuit configuration of a power semiconductor element drive circuit according to the third embodiment. The third embodiment is a modification of the second embodiment.

  The circuit configuration of the third embodiment shown in FIG. 10 is different from the circuit configuration of the second embodiment shown in FIG. 9 in that the detection point A of the gate drive signal for detecting the pulse phase loss includes the input resistance element 73 and the buffer circuit 63. It differs in the point set between. According to the power semiconductor element drive circuit 1 according to the third embodiment, by setting the detection point A of the gate drive signal in front of the buffer circuit 63, without being affected by the switching noise from the power semiconductor element 2, There is an advantage that a pulse phase loss detection operation can be performed. The simplification of the circuit configuration of the secondary circuit 42 is the same as that in the second embodiment.

[Example 4]
FIG. 11 is an example of a circuit diagram illustrating a circuit configuration of a power semiconductor element drive circuit according to the fourth embodiment. The fourth embodiment is a modification of the first embodiment.

  The circuit configuration of the fourth embodiment shown in FIG. 11 is different from the circuit configuration of the first embodiment shown in FIG. 6 in that the detection point B of the gate drive signal for detecting the pulse phase loss is set between the resistance element 64 and the power semiconductor element 2. It differs in the point set between. As described above, even when the detection point B of the gate drive signal is set between the resistance element 64 and the power semiconductor element 2, basically, as in the circuit configuration of the first embodiment of FIG. A detection operation can be performed.

  This is because when the buffer circuit 69 performs the charging / discharging operation of the gate of the power semiconductor element 2 through the resistance element 64, no current flows through the resistance element 64 when charging / discharging is completed. Is the same. Further, even when the gate of the power semiconductor element 2 cannot be charged / discharged when the resistance element 64 is abnormal, it is possible to perform a pulse phase loss detection operation.

  In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations. Further, a part of the configuration of a certain embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of a certain embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

DESCRIPTION OF SYMBOLS 1 Drive circuit of power semiconductor element 2 Upper arm power semiconductor element 3 Lower arm power semiconductor element 4 Upper arm drive circuit 5 Lower arm drive circuit 6 Higher control circuit 10 Power unit 11 Smoothing capacitor 12 Heat receiving block 13 Heat pipe 14 Heat radiation fin 15 Bus bar 16n, 16p fuse 17 power semiconductor module 20 control board (drive circuit board)
30 Power converter 41, 51 Primary side circuit (low voltage side circuit)
42,52 Secondary circuit (high voltage circuit)
43, 53 Transmission means 43A, 43B Photocoupler 61 Positive bias power source 62 Negative bias power source 73 Resistance element 74 for input Current resistance element 81 Charge / discharge circuit 82 Comparator 86, 87 Resistance element for voltage division

In order to solve the above problems, for example, the configuration described in the claims is adopted.
The present application includes a plurality of means for solving the above problems.
A primary circuit that receives a pulse train signal supplied from an upper control circuit;
A secondary side circuit that uses the pulse train signal supplied from the primary side circuit as a gate drive signal of a power semiconductor element, and drives the power semiconductor element on and off based on the gate drive signal;
A feedback circuit for feeding back the gate drive signal from the secondary circuit to the primary circuit;
A detection circuit provided in the primary side circuit for detecting that a state in which a feedback signal from the feedback circuit is inconsistent with a pulse train signal on the primary side circuit side continues for a certain period;
Mounting a drive circuit having,
The detection circuit includes a charge / discharge circuit that performs a charge / discharge operation in response to the feedback signal, and a comparison circuit that compares an output voltage of the charge / discharge circuit with a reference voltage set to correspond to the predetermined period. It is characterized by having .

Claims (8)

A primary circuit that receives a pulse train signal supplied from an upper control circuit;
A secondary side circuit that uses the pulse train signal supplied from the primary side circuit as a gate drive signal of a power semiconductor element, and drives the power semiconductor element on and off based on the gate drive signal;
A feedback circuit for feeding back the gate drive signal from the secondary circuit to the primary circuit;
A detection circuit provided in the primary side circuit for detecting that a state in which a feedback signal from the feedback circuit is inconsistent with a pulse train signal on the primary side circuit side continues for a certain period;
A drive circuit board comprising a drive circuit having The detection circuit includes:
A charge / discharge circuit that performs a charge / discharge operation in response to the feedback signal;
The drive circuit board according to claim 1, further comprising: a comparison circuit that compares an output voltage of the charge / discharge circuit with a reference voltage set so as to correspond to the predetermined period. The charge / discharge circuit includes a resistance element and a capacitance element connected in series between a first power source and a second power source,
The charge element is charged through the resistance element when the feedback signal is in an inactive state, and the charge accumulated in the capacitor element is discharged when the feedback signal is in an active state. 2. The drive circuit board according to 2. The feedback circuit includes a photocoupler including a light emitting diode provided on the secondary circuit side and a phototransistor provided on the primary circuit side,
The said phototransistor is connected in parallel with respect to the said capacitive element, becomes a conduction | electrical_connection state when the said feedback signal is an active state, and discharges the electric charge accumulate | stored in the said capacitive element. The drive circuit board described. The detection signal of the detection circuit is supplied to the control circuit,
The control circuit determines whether or not the detection signal of the detection circuit is valid from the supply state of the pulse train signal from the control circuit to the primary side circuit. The drive circuit board according to claim 1, wherein supply of the pulse train signal to the secondary circuit is stopped. The drive circuit board according to claim 1, wherein the pulse train signal is a pulse width modulation signal using a carrier wave that changes at a constant frequency. A power semiconductor module equipped with a power semiconductor element;
And a drive circuit board on which a drive circuit for driving the power semiconductor element is mounted,
The drive circuit is
A primary circuit that receives a pulse train signal supplied from an upper control circuit;
A secondary side circuit that uses the pulse train signal supplied from the primary side circuit as a gate drive signal of a power semiconductor element, and drives the power semiconductor element on and off based on the gate drive signal;
A feedback circuit for feeding back the gate drive signal from the secondary circuit to the primary circuit;
A detection circuit that is provided in the primary side circuit and detects that a state in which a feedback signal from the feedback circuit is inconsistent with a pulse train signal on the primary side circuit side continues for a certain period or more. Power unit to do. A power semiconductor module equipped with a power semiconductor element;
A drive circuit board mounted with a drive circuit for driving the power semiconductor element, and a power unit,
The drive circuit is
A primary circuit that receives a pulse train signal supplied from an upper control circuit;
A secondary side circuit that uses the pulse train signal supplied from the primary side circuit as a gate drive signal of a power semiconductor element, and drives the power semiconductor element on and off based on the gate drive signal;
A feedback circuit for feeding back the gate drive signal from the secondary circuit to the primary circuit;
A detection circuit that is provided in the primary side circuit and detects that a state in which a feedback signal from the feedback circuit is inconsistent with a pulse train signal on the primary side circuit side continues for a certain period or more. Power converter.

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