JP2016039530A - Clock data recovery circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock data recovery circuit which allows for normal holding of data with no malfunction of a CDR circuit, even if the frequency offset of reference frequency signal sources on the data transmission side and reception side is large.SOLUTION: An even phase ring oscillator has a delay circuit outputting a plurality of data holding clocks in a delay circuit connected in ring-shape, selects one delay circuit not causing steep circuit operation leading to malfunction, on the basis of the oscillation output signal of even phase, and synchronizes only the delay time measurement start timing, until the delay circuit outputs the data holding clock, with the data change, thereby preventing malfunction of the circuit.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a clock data recovery circuit.

  For example, CDR (Clock Data Recovery) technology is a technology that communicates only with a data line without using a clock line. For example, the number of wirings in the vehicle can be reduced by using it in a vehicle. There are several circuit systems for the CDR technology. For example, in vehicle communication, an optimal circuit system that satisfies the following two characteristics may be selected.

  First, it is desirable to perform communication processing capable of high-speed locking. For example, in an electronic control system of an automobile, there is a case where safety cannot be secured unless processing is completed within a certain period when a certain special event occurs.

  An example is a collision safety control system. In this system, at the timing when the ECU (Electrical Control Unit) detects an abnormal signal by the acceleration sensor, the processing until the airbag deployment processing and the seat belt winding processing are completed must be completed in a short period of time. Therefore, it is desired that the vehicle communication process has low latency and can be locked at high speed.

  Second, it is desirable to use an inexpensive built-in oscillator. Some CDR circuit systems are based on the premise that an expensive external crystal oscillator is used as a local reference frequency signal source. For example, in an existing IC (Integrated Circuit) to reduce the number of parts in vehicle communication, It is desirable that the CDR operates by using the built-in oscillator in FIG.

  The problem here is the CDR frequency offset tolerance. An expensive crystal oscillator has a frequency error of, for example, about ± 100 ppm, but an oscillator built in the vehicle has, for example, about ± 5%. For this reason, the CDR circuit must operate correctly even when there is a frequency offset of about 10% between the reference frequency signal source on the data transmission side and the data reception side. As a CDR circuit system that satisfies such requirements for vehicle communication, there is a system called Gated Oscillator-Based CDR (see, for example, Non-Patent Document 1).

Armin Tajalli, and et al, "A Low-Power, Multichannel Gated Oscillator-Base CDR for Short-Haul Applications" Low Power Electronics and Design, 2005. ISLPED '05. Proceedings of the 2005 International Symposium on

  An object of the present invention is to provide a clock data recovery circuit capable of holding normal data without malfunction of the CDR circuit even when the frequency offset of the reference frequency signal source on the data transmission side and the data reception side is large. It is in.

  According to the first aspect of the present invention, the even-phase ring oscillator is configured by cascading a plurality of pairs of two or more first delay circuits and second delay circuits alternately, and oscillating by feedback connection in a ring shape. Operates and outputs clock signals of 4 phases or more. The delay time from the input change of the first and second delay circuits to the output of the clock signal is one data time of the data signal determined by the communication protocol by the frequency control unit using the local reference frequency signal source. The delay time is controlled to be a predetermined delay time (0.5 T) which is half of the delay time. Hereinafter, a time that is twice a predetermined delay time (0.5T) is referred to as one basic time T. When the number of phases of the oscillating unit is 2n (n ≧ 2), the oscillation frequency f is expressed by f = 1 / n / T, and the delay time (0.5 T) can be controlled by controlling the frequency. The holding unit holds the value of the data signal using the outputs of two or more second delay circuits of the even-phase ring oscillator as clock signals. The edge detection unit outputs an edge signal at a timing when the data signal changes. The timing control unit determines the phase state of the oscillation unit from the even-numbered multiphase oscillation waveform, and within one basic time T from the generation timing of the edge detected by the edge detection unit among the two or more second delay circuits. Only the second delay circuit that outputs the clock, that is, outputs the clock before one basic time T or more is selected, and the delay time measurement start timing until the clock is output is synchronized with the edge generation timing.

  Then, after a predetermined delay time (0.5 T) has elapsed from the generation timing of this edge, a clock signal is output from the oscillator to the holding unit. As a result, the holding unit can receive normal data because the clock is input at the timing of the center of one data time when the data signal is most stable. However, the edge cannot be detected in a continuous section of data where no change in the data signal occurs. Therefore, during that interval, the oscillator cannot be synchronized by edge detection.

  When there is a frequency offset in the reference frequency signal source on the data transmission side and the data reception side, the clock to the holding unit starts to deviate from the center of one data time in this interval, and the deviation is accumulated. Thereafter, when the data changes, it may be necessary to detect the edge immediately after the oscillation unit outputs the clock signal and output the synchronized clock again. Even in a general gated oscillator-based CDR, an edge is detected in the same manner as in the present invention, and the clock output from the delay circuit in the oscillation unit is synchronized so as to be the center of one data time, but the delay circuit outputs a clock signal. Since there is one, there is a case where the delay circuit outputs two clocks that are close in time. In this case, a steep circuit operation is required, leading to a malfunction of the circuit. The even-phase ring oscillator of the present invention has a plurality of delay circuits that output a clock in a delay circuit connected in a ring shape, and selects one delay circuit that does not cause a steep circuit operation as described above. Only the delay time measurement start timing until the delay circuit outputs a clock is synchronized with the edge to prevent circuit malfunction.

Electrical configuration diagram schematically showing a clock data recovery circuit in the first embodiment Electrical configuration diagram schematically showing a configuration example of a NOR gate with a hysteresis delay function Electrical configuration diagram schematically showing a configuration example of a reset signal generation circuit Explanatory drawing schematically showing the operation of NOR gate with hysteresis delay function Operation explanatory diagram schematically showing the oscillation operation of the even-phase ring oscillator Explanatory drawing schematically showing phase compensation operation at the time of phase advance Explanatory drawing schematically showing the phase compensation operation at the time of phase delay Electrical configuration diagram schematically showing a clock data recovery circuit in the second embodiment (corresponding to FIG. 1) Electrical configuration diagram schematically showing a configuration example of a NAND gate with a hysteresis delay function (corresponding to FIG. 2) Electrical configuration diagram schematically showing a configuration example of the reset signal generation circuit (corresponding to FIG. 3) Explanatory diagram schematically showing the operation of a NAND gate with a hysteresis delay function (corresponding to FIG. 4) Operation explanatory diagram schematically showing the oscillation operation of the even-phase ring oscillator (corresponding to FIG. 5) Electrical configuration diagram schematically showing the clock data recovery circuit of the third embodiment (corresponding to FIG. 1) Timing chart schematically showing signal changes at each node when no frequency offset occurs Timing chart schematically showing signal changes at each node when a frequency offset occurs Electrical configuration diagram schematically showing a clock data recovery circuit in a fourth embodiment Electrical configuration diagram schematically showing a comparative example of a clock data recovery circuit Timing chart schematically showing signal changes at each node when no frequency offset occurs in the comparison target example Timing chart schematically showing signal changes at each node when a frequency offset occurs in the comparison target example

  Hereinafter, some embodiments of the present invention will be described with reference to the drawings. In the embodiments, the same or similar components are denoted by the same or similar reference numerals, only the main parts are described, and the description of the same parts is omitted as necessary. The clock data recovery circuit of each embodiment is used to regenerate a clock signal for defining the sampling timing of the data signal when the data signal is received on the slave side, for example, in communication processing between the master and the slave .

(First embodiment)
1 to 7 show a first embodiment. As shown in FIG. 1, a clock data recovery (CDR) circuit 1 is configured on the slave side, for example, and includes an even-phase ring oscillator 2, an edge detector 3, and timing control. A reset signal generation circuit 4 as a unit, an OR gate 5, and a latch circuit 100 as a holding unit. The CDR circuit 1 inputs a data signal from a master transmitter 200 to a digital input terminal (hereinafter abbreviated as an input terminal) 1a.

  The edge detection unit 3 is configured by connecting to the illustrated form using, for example, an EXOR gate 3a and a delay circuit (corresponding to a third delay circuit) 3b. The edge detection unit 3 detects an edge when the value of the data input signal DIN input to the input terminal 1a from the master transmission unit 200 changes, and is normally “L”, and instantaneously becomes “H” when the edge is detected. The edge detection signal EDET is output to the reset signal generation circuit 4. The reset signal generation circuit 4 is configured to reset the phase of the clock output of the even-phase ring oscillator 2 in accordance with the generation timing of the edge detection signal EDET. The delay time until the input signal of the NOR gates X1 to X4 constituting the even-phase ring oscillator changes and the clock signal is output can be varied by a control signal (corresponding to a bias signal) Tbias. The reset signal generation circuit 4 is a delay of the NOR gate X2 or X4 that outputs a clock at a timing within 1T (one basic time) from the edge detection signal EDET among the NOR gates X2 and X4 that output a data sampling clock. This circuit performs an operation of synchronizing the time measurement start timing with the generation timing of the edge detection signal EDET, and the detailed operation will be described later.

  On the other hand, the frequency control unit 6 includes, for example, a PLL circuit 7 and a reference frequency signal source 8. The CDR circuit 1 and the frequency control unit 6 are configured, for example, as an IC (Integrated Circuit: not shown). The reference frequency signal source 8 is configured by using, for example, an inexpensive oscillator (for example, CR oscillator: not shown) included in the IC in order to reduce the number of parts.

  The reference frequency signal source 8 includes a frequency error corresponding to the error of the constituent elements, and includes a frequency error of ± 5%, for example. The PLL circuit 7 includes, as a replica of the even-phase ring oscillator 2, an even-phase ring oscillator 9c having the same configuration as the even-phase ring oscillator 2, a control circuit 9b that outputs a control signal Tbias for controlling the frequency, and an even-phase ring oscillator It comprises a frequency divider 9d that divides the output of 9c and a phase comparator 9a that compares the phase of this frequency-divided signal with the reference frequency signal. The PLL circuit 7 performs phase lock processing (synchronous control of the oscillation phase) on the output of the even-phase ring oscillator 9 c after frequency division with respect to the reference frequency signal source 8.

  The fact that the oscillation phase is constantly synchronized means that the output frequency of the oscillator 11 is accurately controlled to the frequency division ratio times the reference frequency signal of the reference frequency signal source 8. The control signal Tbias of the even-phase ring oscillator 2 is connected to the same output as that of the control circuit 9b connected to the even-phase ring oscillator 9c. Thereby, the frequencies of the outputs of the even-phase ring oscillators 9c and 2 are the same, and the delay time (0.5T) can be accurately controlled by the reference frequency signal.

  In general, it is difficult to directly measure the delay time of the delay circuit, but in this embodiment, the delay time is controlled by measuring and controlling the oscillation frequency determined by the delay time. The frequency control unit 6 using the PLL circuit 7 is an example of delay time (0.5T) control, and may be configured to directly measure and dynamically adjust the output of the even-phase ring oscillator 2 or trim the first time. You may adjust and fix by processing.

  The even-phase ring oscillator 2 is configured by using an even number (2n) of NOR gates X1 to X4, and outputs a clock in a state in which the frequency is controlled by the frequency control unit 6. In the present embodiment, description will be made assuming that the even-phase ring oscillator 2 has a four-stage configuration (n = 2). In these NOR gates X1 to X4, the even-numbered NOR gates X2 and X4 are configured as 4-input 1-output gate circuits as the second delay circuit, and the odd-numbered NOR gates X1 and X3 are configured as the first delay circuit. It consists of a gate circuit with two inputs and one output. The NOR gates X1 to X4 have the same configuration, and the odd-numbered NOR gates X1 and X3 have a configuration in which two unnecessary inputs among four inputs are fixed to “L” = 0V. (See FIG. 2 described later).

  The even-phase ring oscillator 2 is configured by alternately connecting a plurality of pairs of NOR gates X1 to X4 of odd-numbered stages and even-numbered stages, and feedback-connecting delay gates of the NOR gates X1 to X4 in a ring shape. The NOR gates X1 to X4 constituting the even-phase ring oscillator 2 are the first stage on the most output side, the second stage from the output side, the third stage from the output side, the third stage, and the fourth stage on the most input side. Will be described. Outputs from the NOR gates X1 to X4 in the first to fourth stages to the reset signal generation circuit 4 are output signals PH1 to PH4 (corresponding to even multiphase clock signals), respectively.

  The output of the first-stage NOR gate X1 is input to the reset signal generation circuit 4 as an output signal PH1, and is provided as an input signal to the fourth-stage NOR gate X4. The input of the first stage NOR gate X1 is supplied with the output of the second stage NOR gate X2 and the output of the third stage NOR gate X3.

  The input of the NOR gate X2 at the second stage is supplied with the output of the NOR gate X3 at the third stage and the output of the NOR gate X4 at the fourth stage, and the input of the NOR gate X2 is reset. Reset signals RS11 and RS22 from the signal generation circuit 4 are also provided. The output of the NOR gate X2 at the second stage is output to the reset signal generation circuit 4 as an output signal PH2 and is given to the OR gate 5.

  The input of the third-stage NOR gate X3 is supplied with the output of the fourth-stage NOR gate X4 and the output of the first-stage NOR gate X1. The output of the third-stage NOR gate X3 is output to the reset signal generation circuit 4 as the output signal PH3.

  The output of the NOR gate X1 of the first stage and the output of the NOR gate X2 of the second stage are given to the input of the fourth stage NOR gate X4, and the reset signal RS12 by the reset signal generation circuit 4 is provided. RS21 is also given. The output of the fourth-stage NOR gate X4 is output to the reset signal generation circuit 4 as an output signal PH4 and is given to the OR gate 5. The second-stage NOR gate X2 and the fourth-stage NOR gate X4 start measuring the delay time from when the input signal changes to when the clock signal is output by the reset signal (RS11, RS12, RS21, RS22). A function to reset the timing is provided. The OR gate 5 receives the outputs of the NOR gates X2 and X4 of the second and fourth stages, ORs the input data, and outputs the logical sum as a clock signal RCLK to the latch circuit 100 as a holding unit. The latch circuit 100 is constituted by, for example, a D flip-flop, holds the value of the data input signal DIN at the timing of the up edge of the clock signal RCLK (change from “L” to “H”), and outputs the value as the output DOUT. It will be. As a result, the latch circuit 100 holds data using the output of the OR gate 5 as a clock for sampling the data input signal DIN.

  Next, a configuration example of the NOR gates (X1, X2, X3, X4) is shown in FIG. As shown in FIG. 2, the NOR gate includes a delay circuit 12a and a comparator circuit 12b. The delay circuit 12a is connected to a power supply voltage supply terminal 13 to which a power supply voltage Vcc is supplied, and a current source 15 capable of adjusting and controlling the amount of current by a control signal Tbias; a current supply terminal node N1 of the current source 15; And four N-channel type MOS transistors 16 to 19 connected in parallel. Each of the N-channel MOS transistors 16 to 19 sets the voltage of the input node of the comparator circuit 12b to a voltage that becomes the ground level (“L”) when the input signals of the input terminals IN1 to IN4 become “H”.

  The comparator circuit 12b compares the voltage of the current supply terminal node N1 of the current source 15 with a certain threshold value and converts it into a digital level. For example, the comparator circuit 12b is configured by connecting two inverters 20 in cascade. In this case, the threshold value is the logical threshold value of the inverter 20 (generally, half of the power supply voltage). The MOS transistors 16 to 19 have drain-source capacitances and drain-gate capacitances when turned off, and the inverter 20 has input parasitic capacitances, and a predetermined delay time (in accordance with a time constant when charging these capacitors) A rise delay of 0.5T) is realized.

  Also, each of the MOS transistors 16 to 19 is set to have a low on-resistance when the input terminals IN1 to IN4 are turned on by being given "H", so that any of the MOS transistors 16 to 19 is turned on. The time constant at the time of discharging is set lower (for example, approximately 0 seconds) than the time constant at the time of charging the capacity. Thereby, the NOR gate (X1, X2, X3, X4) has a predetermined delay time (0.5T) when the input signal changes and outputs a clock signal rising from “L” to “H”. It is configured as a gate that has the function of setting the output that has become “H” by the next timing to raise the output from “L” to “H” to “L” again (this delay time is approximately 0 seconds, for example). ing. When the four-input NOR gate shown in FIG. 2 is used as the two-input NOR gates X1 and X3, unused input terminals may be fixed at “L” = 0V in advance.

  FIG. 3 shows a configuration example of the reset signal generation circuit 4. The reset signal generation circuit 4 includes a plurality (four pieces) of AND gates 21 to 24 to which the edge detection signal EDET of the edge detection unit 3 is input. These AND gates 21 to 24 receive the output signals PH1 to PH4 of the NOR gates X1 to X4 in the first to fourth stages, respectively, and output the logical product calculation results.

  In particular, the AND gate 21 outputs a logical product operation result of the output signal PH1 of the first-stage NOR gate X1 and the edge detection signal EDET as the reset signal RS11. The AND gate 22 outputs a logical product operation result of the output signal PH2 of the second-stage NOR gate X2 and the edge detection signal EDET as the reset signal RS22. The AND gate 23 outputs a logical product operation result of the output signal PH3 of the third-stage NOR gate X3 and the edge detection signal EDET as the reset signal RS21. The AND gate 24 outputs a logical product operation result of the output signal PH4 of the fourth-stage NOR gate X4 and the edge detection signal EDET as the reset signal RS12.

  The operation of the above-described configuration will be described with reference to FIGS. First, an input / output operation of each NOR gate X1 to X4 will be described with reference to FIG. Since the operations of the NOR gates X1 to X4 are almost the same, the operation of the NOR gate X2 will be described as a representative.

  The NOR gate X2 is configured so that the current source 15 gradually charges the capacitor of the node N1 at a predetermined speed from the time when all the input terminals IN1 to IN4 change from “H” to “L”, so that the input node N1 gradually The voltage is increased, and “H” is output at the timing when the voltage of the node N1 reaches a predetermined threshold voltage (the logical threshold of the inverter 20) (timing t2 in FIG. 4). The delay time (0.5 T) determined from the charging time can be controlled by a control signal Tbias that determines the current value of the current source 15. The NOR gate X2 has a timing when the charge voltage of the capacity of the node N1 is discharged and falls below the threshold voltage when any one of the input terminals IN1 to IN4 changes from “L” to “H”. “L” is output rapidly (approximately 0 second) (timing t3 in FIG. 4). As described above, the NOR gate X2 has a characteristic that the time constant at the time of rising and the time of falling are different from each other, and the time constant at the time of rising can be controlled by the control signal Tbias.

  The NOR gate X4 performs the same operation as the NOR gate X2, and the NOR gates X1 and X3 receive unused inputs although there is a difference between the NOR gates X2 and X4 having two inputs or four inputs. Since the MOS switch is fixed to “L” in the OFF state, these NOR gates X1 to X4 operate in the same manner. These NOR gates X1 to X4 are configured by a current source 15 that can be adjusted by a control signal Tbias and MOS transistors (corresponding to switches) 16 to 19 that can switch charging by the current source 15. For this reason, the rise time of the voltage can be easily adjusted by adjusting the constant current amount of the current source 15 by the control signal Tbias.

  Next, the basic operation of ring oscillation will be described with reference to FIG. Here, it is assumed that the initial values of the reset signals RS11, RS12, RS21, and RS22 of the reset signal generation circuit 4 are all “L”. In consideration of the steady state of the clock oscillation operation, the output signals PH1 to PH4 of the NOR gates X1 to X4 are sequentially changed to “H” and changed. For example, consider the timing when the output signal PH1 of the NOR gate X1 becomes “H”.

  At this time, since “H” is input to the NOR gates X3 and X4 at the timing when the output signal PH1 of the NOR gate X1 changes to “H”, “L” of the output signals PH3 and PH4 is determined, and the NOR gate X2 All inputs are fixed at “L” (t11 in FIG. 5). The NOR gate X2 starts the charging operation shown in FIG. 4 from this timing t11. Then, after a predetermined delay time (0.5T) has elapsed, the output signal PH2 of the NOR gate X2 changes from “L” to “H”. Since “H” is input to the input of the NOR gate X1 at the timing when the output signal PH2 of the NOR gate X2 changes to “H”, the output signal PH1 of the NOR gate X1 is instantaneously reset to “L” ( T12 in FIG.

  On the other hand, at timing t12 when the output signal PH2 of the NOR gate X2 becomes “H”, “H” is input to the NOR gates X1 and X4, so that “L” of the output signals PH1 and PH4 is determined and the NOR gate X3 All inputs are fixed to “L”. The NOR gate X3 starts the charging operation shown in FIG. 4 from this timing t12. Then, after a lapse of a predetermined delay time (0.5T) from this timing t12, the output signal PH3 of the NOR gate X3 changes from “L” to “H”. Since “H” is input to the input of the NOR gate X2, the output signal PH2 of the NOR gate X2 is instantaneously reset to “L” (t13 in FIG. 5).

  At the timing when the output signal PH3 of the NOR gate X3 changes to “H”, “H” is input to the NOR gates X1 and X2, so that “L” of the output signals PH1 and PH2 is determined, and the input of the NOR gate X4 is All are fixed to “L”. The NOR gate X4 starts the charging operation shown in FIG. 4 from this timing t13. Then, after a delay of a predetermined delay time (0.5T), the output signal PH4 of the NOR gate X4 changes from “L” to “H”. Since “H” is input to the input of the NOR gate X2, the output signal PH3 of the NOR gate X3 is instantaneously reset to “L” (t14 in FIG. 5).

  At the timing when the output signal PH4 of the NOR gate X4 changes to “H”, “H” is input to the inputs of the NOR gates X2 and X3, so that “L” of the output signals PH2 and PH3 is determined, and the NOR gate X1 All inputs are fixed to “L”. The NOR gate X1 starts the charging operation shown in FIG. 4 from this timing t14. Then, after a predetermined delay time (0.5T) has elapsed, the output signal PH1 of the NOR gate X1 changes from “L” to “H”. Since “H” is input to the input of the NOR gate X4, the output signal PH4 of the NOR gate X4 is instantaneously reset to “L” (t15 in FIG. 5). Such an operation repeatedly occurs with the output signals PH1 to PH4. Therefore, a clock signal changing from “L” to “H” propagates through each delay circuit X1 to X4 while being delayed by a predetermined delay time (0.5T) and becomes “H”. A four-phase clock signal set to “L” can be obtained. This is because the even-phase ring oscillator 2 resets the output to the state before the clock output after each delay circuit outputs the clock signal and the feedback loop in which the clock signal propagates through each delay circuit with a predetermined delay time. This is because it has a food back loop. The even-phase ring oscillator 2 outputs only the even-phase (two-phase) output clock signal of the four-phase ring oscillator to the OR gate 5.

  The delay time (0.5T) of the delay NOR gates X1 to X4 constituting the even-phase ring oscillator 2 can be adjusted by the control signal Tbias. Since the oscillation frequency f of the even-phase ring oscillator 2 is determined by f = 1 / (0.5T × 4), the delay time (0.5T) is also accurate by adjusting the control signal Tbias and accurately controlling the frequency f. Can be controlled. The frequency control unit 6 accurately controls the frequency by, for example, phase-locking the oscillation of the replica even-phase ring oscillator 11 that oscillates at the same oscillation frequency as the even-phase ring oscillator 2 with respect to the reference frequency signal. However, since an error also exists in the reference frequency, the error remains in the oscillation frequency f and the delay time (0.5 T) of the even-phase ring oscillator 2. The detailed operation of the PLL circuit 7 is general (Non-Patent Document 1) and will not be described.

  The basic operation of the even-phase ring oscillator 2 has been described above. Next, details of the reset control operation by the reset signal generation circuit 4 according to the edge detection signal EDET will be described. The edge detection signal EDET is a signal generated in a short pulse shape at the timing when the data input signal DIN changes. The data value changes near the timing when the edge detection signal EDET is generated and near one data time after the edge, and the voltage level of the data input signal DIN is unstable near these two timings. Therefore, it is desirable to hold the data input signal DIN at a timing delayed by a predetermined delay time (0.5 T) from the generation of the edge that is the center of one data time from the timing at which the edge detection signal EDET is generated.

  However, as will be described later as Comparative Example X, if control is performed to generate a clock again in the delay gate circuit immediately after outputting the clock, it will lead to malfunction of the circuit and it will be difficult to generate a normal sampling clock. There is. Therefore, in the present embodiment, by selectively adjusting the clock generation timing of either the output signal PH2 or PH4 at which the clock signal appears within one basic time T from the edge generation timing of the edge detection signal EDET, as much as possible. The sampling clock of the output signal PH2 or PH4 is generated with good timing.

  FIGS. 6A and 6B schematically show signal changes when, for example, the oscillation phase of the even-phase ring oscillator 2 is advanced with respect to the edge detection signal EDET. As shown in FIG. 6A, it is assumed that the even-phase ring oscillator 2 sequentially outputs clock signals as output signals PH1 to PH4 (t31 in FIG. 6A). At this time, it is assumed that the level of the data input signal DIN is switched from “L” → “H” or “H” → “L” and the edge detection signal EDET is generated (t32 in FIG. 6A).

  In the example shown in FIG. 6A, the output signal PH2 is switched from “L” to “H” within one basic time T after generation of the edge detection signal EDET among the output signals PH2 and PH4 (FIG. 6A). (See A in)). In this case, the output signal PH2 changes in a time less than 0.5T from this switching timing. Then, since the data input signal DIN is sampled immediately after the change, there is a possibility that the data input signal DIN cannot be sampled accurately. For this reason, it is desirable to delay the sampling timing of the data input signal DIN by a predetermined delay time (0.5 T) from the generation timing of the edge detection signal EDET (see the portion A of PH2 in FIG. 6A).

  In the reset signal generation circuit 4 of the present embodiment, the AND gates 21 to 24 output the logical sum operation result of the edge detection signal EDET and the output signals PH1 to PH4. For this reason, as shown in FIG. 6B, the reset signal generation circuit 4 outputs a signal that instantaneously becomes “H” to the reset signal RS11 that is the logical sum of the edge detection signal EDET and the output signal PH1.

  The NOR gate X2 to which the reset signal RS11 is input starts charging the node N1 at the timing t33 when the output signal PH1 changes from “L” to “H” (see the above description). When the edge detection signal EDET is generated within the delay time (0.5T), the MOS transistor (any one of 16 to 19) in the NOR gate X2 is switched on for a moment, and the charging voltage of the input capacitance of the NOR gate X2 is discharged again. It is reset (see timing t32 in FIG. 6B). Thereby, the delay time measurement start timing from the clock output (up edge change from “L” to “H” of the NOR gate X2 output) is synchronized with the edge detection signal EDET.

  Since the charging voltage of the capacity of the node N1 of the NOR gate X2 reaches the threshold value after the elapse of a predetermined delay time (0.5T) from the timing t32 when the discharge is reset again, the output signal PH2 of the NOR gate X2 is Changes to “H”. The output signal PH2 passes through the OR gate 5 and is input to the clock terminal of the latch circuit 100 as the clock signal RCLK. Therefore, the latch circuit 100 holds the data input signal DIN at this timing. As a result, the data input signal DIN can be held at the elapse of a predetermined delay time (0.5 T) from the generation timing of the edge detection signal EDET, and accurate data can be held. At the moment when the edge detection signal EDET is generated (see timing t32 in FIG. 6B), the output signals PH2, PH3, and PH4 are “L”, and the outputs of the AND gates 22, 23, and 24 are “L”. Remains. Therefore, the delay time measurement start timing until the clock output of the NOR gates X1, X3, and X4 is not reset. Thereafter, if the edge detection signal EDET is not generated, the output signals PH3 and PH4 are sequentially set to “H” with a predetermined delay time (0.5T) because the output signal PH2 is changed to “H” as described above. The oscillation continues after changing to.

  FIGS. 7A and 7B schematically show signal changes when, for example, the oscillation phase of the even-phase ring oscillator 2 is delayed with respect to the edge detection signal EDET. As shown in FIG. 7A, it is assumed that the even-phase ring oscillator 2 sequentially outputs clock signals PH1 to PH4 (see t41 in FIG. 7A). At this time, it is assumed that the level of the data input signal DIN is switched from “L” → “H” or “H” → “L” and the edge detection signal EDET is generated (t42 in FIG. 7A).

  In the example shown in FIG. 7A, the output signal PH2 is switched from “L” to “H” within one basic time T after the generation of the edge detection signal EDET (part A2 in FIG. 7A). reference). In this case, the output signal PH2 has changed in a time exceeding 0.5T from the generation timing t42 of the edge detection signal EDET. As a result, sampling takes place after a time exceeding 0.5T has elapsed from the timing at which the level of the data input signal DIN has changed, so the data input signal DIN may start to change to the next data and may not be sampled accurately. There is. For this reason, it is desirable to delay the sampling timing of the data input signal DIN by 0.5T from the generation timing of the edge detection signal EDET, that is, to set the output signal PH2 to “H” faster than the expected timing (FIG. 7 ( (Refer to A2 portion of PH2 in a)).

  In the reset signal generation circuit 4 of the present embodiment, the AND gates 21 to 24 output the logical sum operation results of the edge detection signal EDET and the output signals PH1 to PH4. For this reason, as shown in FIG. 6B, the reset signal generation circuit 4 outputs a signal that instantaneously becomes “H” to the reset signal RS12 that is the logical sum of the edge detection signal EDET and the output signal PH4.

  The NOR gate X4, to which the reset signal RS12 is input, has its output terminal set to “L” because the reset signal RS12 is given as “H” (t42 in FIG. 7A). In addition, since the node N1 of the NOR gate X4 is discharged even after the reset signal RS12 returns to “L”, the output remains “L” for a certain period (0.5T). Since the output signals PH1, PH2 and PH3 at this moment are “L”, the inputs of the NOR gate X2 are all determined to be “L”, and the NOR gate X2 starts the charging operation shown in FIG. 4 from this timing t42. In this manner, the delay time measurement start timing from the clock output (up edge change from “L” to “H” of the output of the NOR gate X2) is synchronized with the edge signal. Then, after a delay of 0.5T, the output signal PH2 of the NOR gate X2 changes from “L” to “H”. In this case, the output signal PH2 can be set to “H” faster than expected timing. At the moment when the edge detection signal EDET is generated (see timing t42 in FIG. 7B), the output signals PH1, PH2, and PH3 are “L”, and the outputs of the AND gates 21, 22, and 23 are “L”. Remains. Therefore, the delay time measurement start timing until the clock output of the NOR gates X1, X3, and X4 is not reset. Thereafter, if the edge detection signal EDET is not generated, the output signals PH3 and PH4 are sequentially set to “H” with a predetermined delay time (0.5T) because the output signal PH2 is changed to “H” as described above. The oscillation continues after changing to.

  Since the output signal PH2 passes through the OR gate 5 and is input to the clock terminal of the latch circuit 100, the latch circuit 100 holds the data input signal DIN at this timing t43. As a result, the data input signal DIN can be held at the elapse of a predetermined delay time (0.5 T) from the generation timing t42 of the edge detection signal EDET, and normal data can be held.

  As described above, according to the present embodiment, the reset signal generation circuit 4 selects and resets one NOR gate X2 or X4 that outputs a clock within one basic time T from the generation timing of the edge detection signal EDET. By outputting the reset signals RS11, RS12, RS21, and RS22, the delay time measurement start timing of the NOR gate X2 or X4 is synchronized with the generation timings t32 and t42 of the edge detection signal EDET. Then, the clock output signals PH2 and PH4 can be adjusted and controlled at a timing after a predetermined delay time (0.5T) has elapsed from the generation timing of the edge. Therefore, when the data input signal DIN changes, the edge is detected and the data input signal is detected. DIN can be maintained normally.

  When there is a frequency error between the reference frequency signal source on the data transmission side and the reception side, the clock to the holding unit 100 starts to deviate from the center of one data time and the deviation is accumulated in a period in which data continues. Thereafter, when an edge of data change is detected, the reset signal generation circuit 4 outputs a clock within one basic time T of the NOR gates X2 and X4 that output the clock signal from the edge detection timing. A gate whose clock output is earlier than one basic time T is selected, and the delay time measurement start timing until the clock output is synchronized. Thereby, since the clock outputs of all the NOR gates X1 to X4 are not continuous within one basic time T, the steep circuit operation of the NOR gates X1 to X4 can be prevented, and the malfunction of the circuit can be prevented. A specific example of the circuit malfunction will be described later as a comparison target X.

  Further, the edge detection unit 3 inputs a data signal using the EXOR gate 3a and the delay circuit 3b, and outputs an edge signal that instantaneously becomes “H” in response to a change in the data input signal DIN, thereby generating a reset signal. Since the circuit 4 only outputs the reset signals RS11, RS12, and RS21 through the AND gates (logic gates) 21 to 24 with respect to the edge signal, the edge signal propagates as the reset signal while being configured with the simplest circuit. Propagation delay can be minimized. Further, the timing signal shift due to the delay of each gate of the edge detection unit 3 and the reset signal generation circuit 4 may be adjusted using a dummy gate (not shown).

(Second Embodiment)
8 to 12 show a second embodiment. In the first embodiment, an example in the case of operating with positive logic is shown, but in the second embodiment, an example in the case of operating with negative logic is shown.

  FIG. 8 shows a configuration example corresponding to FIG. The configuration shown in FIG. 8 is different from that shown in FIG. 1 in the configuration of the even-phase ring oscillator 2, and the NAND gates X11 to X14 are provided instead of the NOR gates X1 to X4 to configure the even-phase ring oscillator 32. . In the configuration shown in FIG. 8, the holding unit 100 shown in FIG. 1 is changed to a latch circuit 100 that samples an input at a down edge (change from “H” to “L”). Here, the connection relationship between the NAND gates X11 to X14 in the even-phase ring oscillator 32 is the same as the connection relationship between the NOR gates X1 to X4 in the even-phase ring oscillator 2. Therefore, the configuration of the NAND gates X11 to X14 will be described, and the other configuration descriptions will be omitted.

A configuration example of the NAND gates X11 to X14 is shown in FIG. As shown in FIG. 9, NAND gates X11 to X14 include a delay circuit 40a and a comparator circuit 40b.
The delay circuit 40a is connected between the input node N2 and the ground, the current source 35 capable of adjusting and controlling the amount of current by the control signal Tbias, the current of the power source voltage supply terminal 13 and the current source 35 to which the power source voltage Vcc is applied. And four P-channel type MOS transistors (corresponding to switches) 36 to 39 connected in parallel with the source terminal node N2.

  The comparator circuit 40b compares the voltage of the common connection node N2 of the current source 35 and the switches 36 to 39 with a certain threshold value and converts it to a digital level. For example, the comparator circuit 40b is constituted by connecting two inverters 30 in cascade. Has been. In this case, the threshold value is the logical threshold value of the inverter 30 (generally, half of the power supply voltage). The MOS transistors 36 to 39 have a source-drain capacitance and a drain-gate capacitance when they are turned off, and the inverter 30 has an input parasitic capacitance. The current source 25 subtracts a current from the voltage accumulated in these capacitance components. A falling delay of a predetermined delay time (0.5 T) is realized according to the time constant when discharging.

  Each of the MOS transistors 36 to 39 is set to have a low on-resistance when the input terminals IN11 to IN14 are turned on with “L” applied thereto, and any of the MOS transistors 36 to 39 is turned on. The time constant at the time of charging is set lower (for example, approximately 0 T) than the time constant at the time of the capacity discharge. Thereby, the NAND gate (X11, X12, X13, X14) has a predetermined delay time (0.5T) when the input signal changes and outputs a clock signal falling from “H” to “L”. It is configured as a gate with the function of setting the output that became “L” by the next timing when the output falls from “H” to “L” to “H” again (this delay time is approximately 0 seconds, for example). ing. When the 4-input NAND gate shown in FIG. 9 is used as the 2-input NAND gates X11 and X13, the unused input terminal is preferably fixed to “H” (for example, = 5 V) in advance.

  FIG. 10 shows a configuration example of a reset signal generation circuit 34 that replaces the reset signal generation circuit 4. Where the reset signal generation circuit 34 is different from the reset signal generation circuit 4, OR gates 41 to 44 are used instead of the AND gates 21 to 24, and the output of the edge detection unit 3 is inverted by the NOT gate 45 and the OR gate 41. To 44. That is, the reset signal generation circuit 34 normally inputs “H” from the edge detection unit 3 through the NOT gate 45, and outputs a signal that becomes “L” for a moment at the timing when the edge detection unit 3 detects the edge. To 44. At this time, when the output signals PH1 to PH4 of the NAND gates X11 to X14 are “L”, the reset signals RS11, RS12, RS21, and RS22 are output as “L” for a moment.

  FIG. 11 shows the operation of the NAND gate. Since the operations of the NAND gates X11 to X14 are almost the same, the operation of the NAND gate X12 will be described as a representative. In the NAND gate X12, the accumulated voltage (Vcc) of the capacitance of the node N2 of the delay circuit 40a from the time point when all the input terminals IN11 to IN14 are changed from “L” to “H” (t51 in FIG. 11) by the current source 35. Reduce. The current source 35 gradually reduces the voltage by discharging the current from the accumulated voltage of the capacitor at the node N2, and at the timing when the input voltage at the node N2 reaches a predetermined threshold voltage (the logical threshold of the inverter 30). “L” is output (t52 in FIG. 11). The delay time (0.5 T) determined from the charging time can be controlled by a control signal Tbias that determines the current value of the current source 35. In addition, when one of the input terminals IN11 to IN14 changes from “H” to “L”, the NAND gate X12 rapidly (at the timing when the capacity of the node N2 is charged and exceeds the threshold voltage ( “H” is output in approximately 0 seconds (t53 in FIG. 11). As described above, the NAND gate X12 has a characteristic that the time constant at the time of falling and the time constant at the time of rising are different from each other, and the time constant at the time of falling can be controlled by the control signal Tbias.

  The NAND gate X14 performs the same operation as the NAND gate X12, and the NAND gates X11 and X13 are different from the NAND gates N12 and X14 in that they have two inputs or four inputs, but unused inputs. Since the MOS switch is fixed to OFF by setting “H” to “H”, these NAND gates X11 to X14 perform the same operation. These NAND gates X11 to X14 are configured by a current source 35 that can be adjusted by a control signal Tbias, and MOS transistors (corresponding to switches) 36 to 39 that can switch discharge by the current source 35. For this reason, the fall time of the voltage can be easily adjusted by adjusting the constant current amount of the current source 35 by the control signal Tbias.

  Next, the basic operation of ring oscillation will be described with reference to FIG. Here, it is assumed that the initial values of the reset signals RS11, RS12, RS21, and RS22 of the reset signal generation circuit 34 are all “H”. In consideration of the steady state of the oscillation operation, the output signals PH11 to PH14 of the NAND gates X11 to X14 are sequentially changed to “L” and changed. For example, consider the timing when the output signal PH1 of the NAND gate X11 becomes “L”.

  At this time, since “L” is input to the NAND gates X13 and X14 at the timing when the output signal PH1 of the NAND gate X11 changes to “L”, “H” of the output signals PH3 and PH4 is determined, and the NAND gate X12 Are all set to “H” (t61 in FIG. 12). The NAND gate X12 starts the discharge operation shown in FIG. 11 from this timing t61. The output signal PH2 of the NAND gate X12 changes from “H” to “L” after a predetermined delay time (0.5T) has elapsed. Since “L” is input to the input of the NAND gate X11 at the timing when the output signal PH2 of the NAND gate X12 changes to “L”, the output signal PH11 of the NAND gate X11 is instantaneously reset to “H” ( T62 in FIG.

  On the other hand, at the timing t62 when the output signal PH2 of the NAND gate X12 becomes “L”, “L” is input to the NAND gates X11 and X14, so that “H” of the output signals PH1 and PH4 is determined. All inputs of the NAND gate X13 are fixed to “H”. The NAND gate X13 starts the discharging operation shown in FIG. 11 from this timing t62. Then, the output signal PH3 of the NAND gate X13 changes from “H” to “L” after elapse of a predetermined delay time (0.5T) from the timing t62 (t63 in FIG. 12). Since “L” is input to the NAND gate X12, the output signal PH12 of the NAND gate X12 is instantaneously reset to “H” (t63 in FIG. 12).

  At the timing when the output signal PH3 of the NAND gate X13 changes to “L”, “L” is input to the NAND gates X11 and X12, so that “H” of the output signals PH1 and PH2 is determined and the input of the NAND gate X14 is All are fixed to “H” (t63 in FIG. 12). The NAND gate X14 starts the discharging operation shown in FIG. 11 from this timing t63. Then, after a delay of 0.5T, the output signal PH4 of the NAND gate X14 changes from “H” to “L”. Since “L” is input to the input of the NAND gate X13, the output signal PH13 of the NAND gate X13 is instantaneously reset to “H” (t64 in FIG. 12).

  At the timing when the output signal PH4 of the NAND gate X14 changes to "L", "L" is input to the inputs of the NAND gates N12 and X13, so that "H" of the output signals PH2 and PH3 is determined and the NAND gate X11 All inputs are fixed at “H”. The NAND gate X11 starts the discharge operation shown in FIG. 11 from this timing t64. Then, after a predetermined delay time (0.5T) has elapsed, the output signal PH11 of the NAND gate X11 changes from “H” to “L”. Since “L” is input to the input of the NAND gate N14, the output signal PH14 of the NAND gate X14 is instantaneously reset to “H” (t65 in FIG. 12). Such an operation repeatedly occurs with the output signals PH1 to PH4. For this reason, the clock signal changing from “H” to “L” propagates through each delay circuit X11 to X14 while being delayed by a predetermined delay time (0.5T), and after becoming “L”, again. , A four-phase clock signal set to “H” can be obtained. This is because the even-phase ring oscillator 32 resets the output to the state before the clock output after the feedback loop in which the clock signal propagates through each delay circuit with a predetermined delay time and each delay circuit outputs the clock signal. This is because it has a feedback loop.

  The delay time (0.5T) of the delay NAND gates X11 to X14 constituting the even-phase ring oscillator 32 can be adjusted by the control signal Tbias. Since the oscillation frequency f of the even-phase ring oscillator 32 is determined by f = 1 / (0.5T × 4), the delay time (0.5T) is also accurate by adjusting the control signal Tbias and accurately controlling the frequency f. Can be controlled. Since the operation of the frequency control unit 6 (PLL circuit 7) is the same as that of the above-described embodiment, the description thereof is omitted. The basic operation of the even-phase ring oscillator 32 has been described above.

  Also, the reset signal generation circuit 34 outputs reset signals RS11, RS12, RS21, and RS22 that reset the delay time measurement start timing with negative logic “L” with OR as the OR, as compared with the first embodiment. Therefore, as in the first embodiment, the sampling clock (down edge in this embodiment) of the output signal PH2 or PH4 can be generated with the best possible timing.

As described above, the same effects can be obtained even with negative logic as in this embodiment.
(Third embodiment)
13 to 15 show a third embodiment. In the third embodiment, the even-phase ring oscillators 2 and 32 in the above-described embodiment are shown in a more general form. As shown in FIG. 13, the even-phase ring oscillator 52 includes delay circuits X <b> 21 to X <b> 24 connected in cascade (even numbers) (four) and feedback connected in a ring shape. The delay circuits X21 to X24 have a function of adjusting the delay time from the change of the input signal to the output of the clock signal changing from “L” to “H” by the control signal Tbias. Further, it has a function of setting the output that has become “H” until the next timing of outputting the clock signal to “L” again. The delay circuit X21 at the second stage and the delay circuit X24 at the fourth stage reset control the measurement start timing of the delay time from when the input signal changes until the clock signal is output by the reset signal (RS21, RS22). It has a function.

  Each of the delay circuits X21 to X24 is configured by using the NOR gates X1 to X4, NAND gates X11 to X14, or other delay circuits shown in the above-described embodiment, and has the same configuration. Is used. The delay gates are not limited to those shown in the first and second embodiments, and a plurality of delay gates may be combined, for example. Further, the function of resetting to “L” again after the output voltage becomes “H” is to feed back the outputs of the delay circuits X21 to X24 to the inputs of the respective delay circuits as in the first and second embodiments. Can be realized. In this embodiment, when the output of the delay circuit X22 changes from “L” to “H”, the output of the delay circuit X21 is set to “L”, and when the output of the delay circuit X23 changes from “L” to “H”. When the output of the delay circuit X22 is set to “L” and the output of the delay circuit X24 changes from “L” to “H”, the output of the delay circuit X23 is set to “L”, and the output of the delay circuit X21 is set to “L”. In the following description, it is assumed that the feedback circuit is configured so that the output of the delay circuit X24 is set to “L” when it changes from “” to “H”. This feedback loop is not shown in FIG. 13 because it can be realized for each delay circuit configuration as shown in the first and second embodiments and does not affect the CDR operation described below. The timing at which the outputs of the delay circuits X21 to X24 are set from “H” to “L” is not limited to the next timing when the output changes from “L” to “H”. Further, as in the second embodiment, a clock signal that changes from “H” to “L” may be used. In these delay circuits X21 to X24, the rise of the voltage is delay-controlled by a predetermined delay time (0.5T) by a control signal Tbias connected to the frequency control unit 6 using the reference frequency signal source 8 respectively. In this embodiment, the frequency control unit 6 includes a frequency divider 55 to which the local reference frequency signal source 8 and the output of the even-phase ring oscillator 52 are connected, a frequency measurement unit 56, and a control circuit 57 that outputs a bias signal. It is comprised by. The reset signal generation circuit 54 has a function of resetting the phase of the even-phase ring oscillator 52 from the edge detection signal EDET, and adds a function capable of reset control of the delay time measurement start timing only to the delay circuits X22 and X24. Configured. The outputs of the delay circuits X22 and X24 are input to the clock input terminal of the latch circuit 100 through the OR gate 5, and the output signals PH22 and PH24 of the delay circuits X22 and X24 are changed from “L” to “H”. A change (up edge) signal is used as a two-phase sampling clock of the data input signal DIN.

  In the free-running oscillation state of the even-phase ring oscillator 52, the reset signal generation circuit 54 outputs the next clock at a delay circuit X22 having a phase relationship within one basic time T from the generation timing of the edge detection signal EDET or The delay time measurement start timing of any one of X24 is selectively reset based on the output signals PH21 to PH24 of each phase. Then, one basic time T or more can be secured in the interval between the rising timings of the output signals PH22 and PH24.

  A configuration in the frequency control unit 6 shown in the present embodiment will be described. At a time when it is not necessary to receive data from the data input signal DIN (for example, when the system is started up), the frequency divider 55 divides the output signal of the even-phase ring oscillator 52, and the frequency measurement unit 56 performs the reference frequency signal source 8 The oscillation frequency of the even-phase ring oscillator 52 is measured using the reference frequency signal. The control circuit 57 adjusts the control signal Tbias so that the frequency becomes predetermined, and performs feedback that adjusts the delay time of the delay circuits X21 to X24 constituting the even-phase ring oscillator 52. As described above, the frequency controller 6 can employ various configurations.

  The effect | action of this embodiment is demonstrated with reference to FIGS. Between one data time of the data input signal DIN determined from the reference frequency source on the transmission unit 200 side and one basic time T determined from the delay time (0.5T) of the delay circuits X21 to X24 controlled by the frequency control unit 6 FIG. 14 shows a case where no offset is generated in FIG. The delay circuits X21 to X24 feed back the clock signal while delaying by a predetermined delay time (0.5T) and output a four-phase oscillation signal. From the above-described feedback loop setting for resetting the output of the delay circuit to the state before the clock output, the oscillation waveforms of the output signals PH1 to PH4 become “H” only in the 0.5T section, and the other sections (1.5T (Section) is “L”. When the edge detection unit 3 detects an edge of the data input signal DIN, the reset signal generation circuit 54 outputs an output that changes the edge from “L” to “H” within one basic time T from the edge of the data input signal DIN. The signal PH22 or PH24 is determined from the phase state of the current oscillation output signals PH21 to PH24.

  For example, when the output signal PH22 is the target signal, the reset signal generation circuit 54 outputs the reset signal RS1 for synchronizing the delay time measurement start timing to the edge detection timing to the delay circuit X22 (FIG. 14). T71, t73). Then, the delay circuit X22 outputs a clock signal that changes from “L” to “H” at a timing delayed by a predetermined delay time (0.5T) from the timing (t71a and t73a in FIG. 14).

  On the contrary, the reset signal generation circuit 54 outputs, to the delay circuit X24, a reset signal RS2 for synchronizing the delay time measurement start timing with the edge detection timing, for example, when the output signal PH4 is the target signal. (T72, t74 in FIG. 14). Then, the delay circuit X24 outputs a clock signal that changes from “L” to “H” at a timing delayed by a predetermined delay time (0.5T) from that timing (t72a and t74a in FIG. 14). In this way, the delay time measurement start timing of the delay circuit X22 or X24 is selectively reset in synchronization with the change of the data input signal DIN.

  If there is no offset between one data time of the data input signal DIN determined from the reference frequency source on the transmission side and one local basic time T determined from the reference frequency source on the reception side, the data input signal DIN in FIG. As shown by the circle of the sampling timing in the signal waveform of, the center of one data time of the data input signal DIN can be accurately sampled, including the case where the data input signal DIN has three consecutive identical states. .

  Next, when the frequency error of the reference frequency signal source on the data transmission side is -5% and the frequency error on the reception side is + 5%, that is, one data time of the data input signal DIN is one local basic time T. An example in which an offset of −10% is generated will be described with reference to FIG. Similarly to the above, when the output signal PH22 is the target signal, the reset signal generation circuit 54 outputs the reset signal RS1 for synchronizing the delay time measurement start timing to the edge detection timing to the delay circuit X22. (T81 and t83 in FIG. 15). Then, the delay circuit X22 outputs a clock signal that changes from “L” to “H” at a timing delayed by a predetermined delay time (0.5T) from that timing (t81a and t83a in FIG. 15).

  Further, when the output signal PH4 is the target signal, the reset signal generation circuit 54 outputs a reset signal RS2 for synchronizing the delay time measurement start timing with the edge detection timing to the delay circuit X24 (FIG. 15 t82, t84). Then, the delay circuit X24 outputs a clock signal that changes from “L” to “H” at a timing delayed by a predetermined delay time (0.5T) from the timing (t82a and t84a in FIG. 15).

  Even if one data time of the data input signal DIN is offset by -10% with respect to one local basic time T, the sampling timing is circled in the signal waveform of the data input signal DIN in FIG. As shown, accurate data can be held by performing the phase compensation process. The above effect can be obtained in the first to second embodiments as well.

<Description of Comparative Example X (Technique described in Non-Patent Document 1)>
For example, as another example of the gated oscillator-based CDR circuit 51, there is a CDR circuit 61 shown in FIG. In FIG. 17, the same components as those shown in FIG.

  As shown in FIG. 4, the CDR circuit 61 includes a delay line 62 that delays the data input signal DIN, and an XNOR gate 63 that performs XOR processing on the data input signal DIN and the output signal of the delay line 62 and inputs the result to the gate oscillator 64. And a gate oscillator 64 that oscillates and outputs in accordance with the output of the XNOR gate 63.

  The CDR circuit 61 outputs the output of the delay line 62 to the data input terminal of the latch circuit 100 and outputs the output of the gate oscillator 64 to the clock input terminal CK of the latch circuit 100. However, unlike the embodiment of FIG. 1, the latch circuit samples data at the down edge.

  The gate oscillator 64 is replica-biased by the PLL circuit 7. The delay line 62 delays the data input signal DIN and generates a delayed digital input signal DDIN. Here, the delay amount of the delay line 62 is set to half the local basic time T (0.5T). The frequency f of the oscillator 64 is controlled by the PLL circuit 7 so that f = 1 / T.

  When the XOR gate 63 outputs the exclusive OR of the data input signal DIN and the delayed digital input signal DDIN to the node N10, the gate oscillator 64 uses the obtained output of the node N10 as the gate input signal. The gate oscillator 64 stops oscillating when the output of the XNOR gate 63 is “L”, and oscillates when the output is “H” level. Then, the gate oscillator 64 performs phase alignment (retiming) at the timing when the change occurs in the node N10, and can generate the clock signal RCLK.

For example, FIG. 18 shows the clock signal RCLK when the offset of one data time of the data input signal DIN and one local basic time T is 0%. Due to the change in DIN, the output N10 of XNOR changes from “H” to “L”, and changes from “L” to “H” after 0.5T. When N10 changes to “L” when RCLK is “H”, N11 becomes “H” and the signal propagates while delaying the gates G11 to G14, and after 0.5T, RCLK becomes “H”. On the other hand, when N10 changes to “H” when RCLK is “H”, N11 becomes “L” and the signal propagates while delaying the gates G11 to G14, and after 0.5T elapses, RCLK becomes “L”. . When there is no change in DIN and N10 is “H” and constant, the oscillator 64 self-runs and outputs RCLK. From the above operation, an RCLK signal having a frequency f = 1 / T synchronized with a change in DIN can be obtained. Since the latch circuit 100 samples DDIN at the down edge timing of RCLK, it can hold accurate data.
FIG. 19 shows the clock signal RCLK when the offset is −10%. At this time, for example, when the CDR circuit 51 receives continuous bits, there is a problem that it is difficult to generate a final sampling edge of the continuous bits.

  That is, as shown in FIG. 19, the free-running oscillation frequency of the oscillator 64 is low with respect to the continuous bit interval 2.7T of DIN, the falling timing of the output node N11 of the NAND gate G11, and the output node N10 of the XOR gate 63 For example, it is possible to ensure only an interval of about 0.075 T with respect to the falling timing of. At this time, since only a narrow pulse is generated at the output node N11 of the NAND gate G11 in the first stage of the gate oscillator 64, this pulse disappears while propagating through the gate oscillator 64 (see C portion in FIG. 19). At this time, the latch circuit 100 cannot hold data accurately. For this reason, the configuration shown in FIG. 17 cannot be used for communication using a reference frequency signal source (for example, an IC built-in oscillator) 8 having a large frequency offset.

  On the other hand, according to the configuration of the third embodiment, as shown in FIG. 15, among the delay circuits X22 and X24 of the even-phase ring oscillator 52, the clock of the delay circuit that does not become a steep circuit operation as shown in FIG. In order to selectively synchronize the outputs, the interval between the oscillation pulses of the even-phase ring oscillator 52 can be as small as 1.2T. This eliminates the possibility of circuit malfunction due to the disappearance of the oscillation waveform.

  In addition, it becomes difficult for the delay line 62 as a comparative example to generate an accurate 0.5T. In the third embodiment, the delay by the delay circuit of the even-phase ring oscillator 52 is controlled so that the oscillation frequency f of the even-phase ring oscillator 52 is directly measured and becomes a predetermined frequency. it can.

(Fourth embodiment)
FIG. 16 shows a fourth embodiment. The fourth embodiment shows a form in which a plurality of latch circuits are provided. In the third embodiment, for example, when a frequency offset of −10% is generated, a short pulse as shown in a part D of FIG. 15 is generated because the logical sum of the output signals PH2 and PH4 is acquired. Such a latch circuit that operates with a continuous clock for a short time needs to operate at high speed. In this embodiment, latch circuits 100a and 100b are provided corresponding to the output signals PH2 and PH4, respectively, in order not to generate a short pulse as shown in part D of FIG. Then, sampling can be performed individually by the latch circuits 100a and 100b corresponding to the output signals PH2 and PH4, and the short pulse shown in the portion D of FIG. 15 is not generated, so that the operation speed necessary for the latch circuit can be reduced.

  In addition, the code | symbol with the parenthesis attached | subjected to the claim attaches | subjects the code | symbol corresponding to the component of this-application specification, and gives an example of the component. Therefore, the invention according to the present application is not limited to the content of the reference numerals of the constituent elements of the claims, and various extensions can be made within the terms of the claims or their equivalents.

  In the drawing, 2, 32 and 52 are even-phase ring oscillators, 3 is an edge detection unit, 3a is an EXOR gate, 3b is a delay circuit (third delay circuit), 4, 34 and 54 are reset signal generation circuits (timing control unit) ), 16 to 19 are N-channel MOS transistors (switches), 36 to 39 are P-channel MOS transistors (switches), 100, 100a and 100b are latch circuits (holding units), and X1 and X3 are input signals. NOR gate (gate circuit, first delay circuit) having a predetermined time delay from the change until the clock signal is output, X2 and X4 have a predetermined time delay, and the delay time measurement start timing can be set NOR gate (gate circuit, second delay circuit), X11, X13 are NAND gates (gate circuit, first delay circuit) having a predetermined time delay, 12, X14 have a delay of a predetermined time and a delay time measurement start timing can be set NAND gate (gate circuit, second delay circuit), X21, X23 are a delay circuit (first delay) having a predetermined time delay Circuit), X22, and X24 indicate a delay circuit (second delay circuit) having a delay of a predetermined time and capable of setting a delay time measurement start timing.

Claims (6)

An edge detector (3) that outputs an edge signal at a timing when the value of the data signal changes;
An even number of first delay circuits (X1, X3, X11, X13, X21, X23) that output a clock signal delayed by a predetermined time from the change of the input signal, and a clock delayed by the predetermined time from the change of the input signal An even number of second delay circuits (X2, X4, X12, X14, X22) capable of setting a measurement start timing (referred to as a delay time measurement start timing) until the clock signal is output while outputting a signal. , X24) are alternately connected in cascade with each other and are connected in a feedback manner in a ring shape to oscillate and output the outputs of the first delay circuit and the second delay circuit as even-numbered multiphase clock signal outputs ( 2, 32, 52),
A holding unit (100, 100a, 100b) for holding the value of the data signal according to a clock signal output from the second delay circuit of the even-phase ring oscillator;
A timing control unit (4, 34, 54) for controlling the delay time measurement start timing of the second delay circuit,
The timing control unit (4, 34, 54) is configured to detect the edge generation timing detected by the edge detection unit among the plurality of second delay circuits of the even-phase ring oscillator from the even-numbered multiphase clock signal. By determining one of the second delay circuits whose clock is output within twice the predetermined time, and setting the delay time measurement start timing of only the second delay circuit as the generation timing of the edge, A clock data recovery circuit that controls the clock output of the delay circuit from the edge generation timing to a timing after the predetermined time has elapsed. The clock data recovery circuit according to claim 1, wherein
The even-phase ring oscillator includes a feedback loop in which the clock signal propagates through the first and second delay circuits with a delay of the predetermined time, and an output of the delay circuit after the first and second delay circuits output a clock. A clock data recovery circuit comprising a feedback loop for resetting to a state before clock output. The clock data recovery circuit according to claim 2,
The even-phase ring oscillator is configured to be able to vary the predetermined time of the first and second delay circuits based on a bias signal,
A clock data recovery circuit comprising a frequency control unit (6) for adjusting the bias signal and controlling the oscillation frequency of the even-numbered multiphase ring oscillator. The clock data recovery circuit according to claim 3,
The first and second delay circuits include a current source (15, 35) that can vary a current amount by the bias signal, and a switch (16-19, 36-39) that performs charge switching or discharge switching by the current source. And a clock data recovery circuit comprising: In the clock data recovery circuit according to any one of claims 1 to 4,
The clock data recovery circuit, wherein the gate circuit is configured using NOR gates (X1, X2, X3, X4) or NAND gates (X11, X12, X13, X14). In the clock data recovery circuit according to any one of claims 1 to 5,
The edge detection unit (3) includes one EXOR gate (3a) and a third delay circuit (3b). A data signal is input using the EXOR gate and the third delay circuit, and the data signal changes. Output a pulse signal in response to
The clock data recovery circuit, wherein the timing control unit outputs a timing received through a logic gate of the pulse signal and the even multiphase clock signal as the delay time measurement start timing.

Images