JP2016033702A - Electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a new connection configuration connecting a main board and a sub board.SOLUTION: A sub board is provided with a first circuit and a second circuit. When the first circuit or the second circuit executes its function, first, an interruption signal is output from each circuit toward a control circuit. An integrated circuit integrates the interruption signal output from the first circuit or second circuit and generates an integrated signal. The integrated signal output from the integrated circuit is supplied to the control circuit via an interruption signal line. The control circuit detects an interruption request occurring inside the sub board when receiving the integrated signal. The control circuit transmits communication with the first circuit or the second circuit by a communication signal line when receiving the interruption signal from the integrated signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic device having a main board and a sub board.

  Some electronic devices have a main board on which a control circuit for controlling driving is mounted, and a sub board connected to the main board. A plurality of devices are mounted on the sub-board, and each device is connected to the control unit of the main board through a communication signal line and an interrupt signal wiring.

  Since all devices on the sub-board side are connected to the control circuit on a one-to-one basis, the following problems occur. The number of signal lines connecting the main board and the sub board increases. When the number of wirings on the sub board is changed due to the correspondence to the destination, not only the sub board but also the hardware of the main board needs to be changed.

  In Patent Document 1, an image forming apparatus including a controller for controlling driving and an operation unit including a touch panel and a liquid crystal screen is connected to the controller and the touch panel via a USB standard wiring (USB bus). An invention in which the number of wirings is reduced is disclosed (for example, see Patent Document 1).

JP 2010-135886 A

  When the main board and the sub board are connected using the USB standard wiring, the control circuit mounted on the main board needs to always keep the USB communication active in preparation for the input of the interrupt signal through the USB bus. . In order to keep the USB communication active at all times, it is necessary to continuously supply power to the control circuit, and it is not possible to shift to a mode in which the power consumption of the apparatus is reduced, such as a sleep mode.

  The present invention has been made in view of the above problems, and an object thereof is to provide a new connection configuration for connecting a main board and a sub board.

One embodiment of the present invention relates to an electronic device including a main board on which a control circuit is mounted and a sub board connected to the main board. The control circuit mounted on the main board may be any circuit such as a CPU, microcomputer, ASIC such as an ASIC, LSI, or the like as long as it controls the driving of the electronic device. The sub-board may be composed of two or more boards in addition to one board.
The sub board includes a first circuit and a second circuit. When the first circuit or the second circuit performs the function, first, an interrupt signal is output from each circuit to the control circuit. The integrated circuit integrates the interrupt signals output from the first circuit or the second circuit to generate an integrated signal. The integrated signal generated by the integrated circuit may be of any format as long as it is a signal that informs the control circuit that an interrupt signal has been generated from the circuit mounted on the sub-board.
The integrated signal output from the integrated circuit is supplied to the control circuit via the interrupt signal line. Upon receiving this integrated signal, the control circuit detects that an interrupt request has occurred in the sub-board. When the control circuit receives the interrupt signal from the integrated signal, it communicates communication with the first circuit or the second circuit through the communication signal line.
Any method can be used for the control circuit to determine the transmission source of the interrupt signal based on the integrated signal. The first circuit or the second circuit is accessed by communication using the communication signal line, and the state of each circuit ( (Interrupt request) may be determined, or the integrated circuit is provided with a recording unit that records the state of each circuit, and the control circuit accesses the recording unit using the communication signal line, thereby changing the state of each circuit. It may be determined.

  In the invention configured as described above, the integrated circuit communicates the interrupt signal from the first circuit or the second circuit as an integrated signal to the control circuit of the main board through the interrupt signal line. The number of signal lines can be reduced. In addition, by connecting the main board and the sub board using the interrupt signal of the conventional configuration, the control circuit can shift to the sleep mode with reduced power consumption during the period when the integrated signal is not input. The power consumption of the device can be reduced.

FIG. 11 is a block diagram illustrating a configuration of an electronic device. The block diagram which shows the structure of the integrated circuit as an example. As an example, a timing chart illustrating control using an interrupt signal performed by the electronic device 100. The block diagram which shows the structure of the electronic device 100 concerning 2nd Embodiment. The figure which shows the internal structure of the integrated circuit 101 as an example in 2nd Embodiment. As an example according to the second embodiment, a timing chart illustrating control using an interrupt signal performed by the electronic device 100. The block diagram which shows the structure of the electronic device 100 concerning 3rd Embodiment. The block block diagram which shows the structure of the electronic device as an example concerning 4th Embodiment.

Hereinafter, embodiments of the present invention will be described in the following order.
1. First embodiment:
(1) Configuration of electronic device (2) Interrupt processing Second embodiment:
3. Third embodiment:
4). Fourth embodiment:
5. Other embodiments:

1. First embodiment:
(1) Configuration of electronic equipment

FIG. 1 is a block configuration diagram illustrating a configuration of an electronic apparatus 100 as an example.
In FIG. 1, the electronic device 100 will be described by taking a printer as an example. In the electronic device 100 functioning as a printer, a transport mechanism 51 that transports paper, a head module 50 that records a color material such as ink on the paper, and a main board that controls driving of the head module 50 and the transport mechanism 51. 40. In addition, the panel substrate 30 is connected to the main substrate 40. In FIG. 1, the main board 40 functions as the main board of the present invention, and the panel board 30 functions as the sub board of the present invention.

A host CPU 41 that functions as a control circuit is mounted on the main board 40. A host CPU (Central Processing Unit) 41 controls driving of the electronic device 100. The host CPU 41 is connected to the panel substrate 30, the head module 50, and the transport mechanism 51. The main board 40 is connected to a ROM (not shown) in which data referred to by the host CPU 41 is recorded, and a RAM (not shown) for expanding the data recorded in the ROM.
The host CPU 41 shifts to the sleep mode when a predetermined condition is satisfied. In this sleep mode, power consumption is reduced by reducing the voltage supplied from a power supply circuit (not shown). The sleep mode is continued until an interrupt signal is input to the host CPU 41.

In FIG. 1, the host CPU 41 is connected to the panel substrate 30 via the video signal line 21, the serial signal line 22, and the interrupt signal line 23. The video signal line 21 supplies a video signal from the host CPU 41 to the panel substrate 30. The video signal is a signal for displaying characters and images on the display panel 52 connected to the panel substrate 30.
The serial signal line 22 functions as a communication signal line of the present invention and transmits serial communication performed between the host CPU 41 and the panel substrate 30. As the serial communication performed between the host CPU 41 and the panel substrate 30, known communication such as I2C, SPI, and I2S can be applied. Hereinafter, I2C will be described as an example of serial communication.
The interrupt signal line 23 transmits an interrupt signal IN for transmitting an interrupt request generated inside the panel substrate 30 to the main substrate 40.

  The panel substrate 30 includes an LCDC (liquid crystal display controller) 31, a TPC (touch panel controller) 32, a microcomputer 33, an authentication device 34, and an integrated circuit 10 that integrates interrupt signals output from each circuit. Yes. Here, devices other than the LCDC 31 (TPC 32, microcomputer 33, authentication device 34) need to output the interrupt signal IN and set the occupation of the serial communication line 22 in order to perform serial communication with the host CPU 41. . Therefore, the LCDC 31, TPC 32, and microcomputer 33 function as the first circuit or the second circuit of the present invention.

  The LCDC 31 is connected to the display panel 52 and controls the display panel 52 to display characters and screens. The LCDC 31 is connected to the host CPU 41 via the video signal line 21 and the serial signal line 22. When a video signal is input from the host CPU 41 via the video signal line 21, the LCDC 31 drives the display panel 52 based on the video signal.

  A TPC (touch panel controller) 32 is connected to the touch panel 53 and outputs an input from the touch panel 53 to the host CPU 41 via the serial communication line 22.

  The microcomputer 33 is connected to an operation key 54 and outputs a signal generated in response to the operation of the operation key 54 to the host CPU 41 via the serial communication line 22.

  The authentication device 34 analyzes the authentication information input by the user, and inputs a signal corresponding to the analysis result to the host CPU 41 via the serial communication line 22. The authentication information is information created based on the characteristics of the user's human body such as fingerprint authentication and iris authentication, or a password uniquely determined by the user.

  The TPC 32, the microcomputer 33, and the authentication device 34 are connected to the integrated circuit 10 via internal interrupt signal lines 24a, 24b, and 24c. When the integrated circuit 10 receives the interrupt signal IN transmitted from any of the TPC 32, the microcomputer 33, and the authentication device 34 via the internal interrupt lines 24a to 24c, the integrated circuit 10 generates an integrated signal UN that integrates the interrupt signal IN. To do. The integrated circuit 10 is connected to the host CPU 41 via the serial signal line 22 and the interrupt signal line 23. Therefore, even if the interrupt signal IN flowing through the interrupt signal line 23 is based on the interrupt signal IN input from any of the TPC 32, the microcomputer 33, and the authentication device 34, the interrupt signal IN is integrated by the integrated circuit 10 and the same signal. (Integrated signal UN) is input to the host CPU 41.

FIG. 2 is a diagram illustrating an internal configuration of the integrated circuit 10 as an example.
2 is an OR circuit 11 that integrates interrupt signals IN1 to IN3 flowing through internal interrupt signal lines 24a to 24c, and an interrupt register 12 that records interrupt information for identifying an interrupt signal input to the OR circuit 11. And. In FIG. 2, the interrupt signal IN1 is an interrupt signal from the TPC 32, the interrupt signal IN2 is an interrupt signal from the microcomputer 33, and the interrupt signal IN3 is an interrupt signal from the authentication device 34.

  Internal interrupt signal lines 24a to 24c are connected to the OR circuit 11, and an interrupt signal line 23 is connected to the output side. Internal interrupt signal lines 24 a to 24 c connected to the input side of the OR circuit 11 are branched and connected to the interrupt register 12. Therefore, the interrupt signals IN1 to IN3 flowing through the internal interrupt signal lines 24a to 24c are input to the OR circuit 11 and the interrupt register 12, respectively. A serial communication line 22 is connected to the output side of the interrupt register 12 so that interrupt information recorded in the interrupt register 12 can be output to the host CPU 14 via the serial communication line 22. The interrupt information is information for uniquely identifying the interrupt signals IN1 to IN3.

  In the integrated circuit 10 having the above configuration, when an interrupt signal flows through any of the internal interrupt signal lines 24 a to 24 c, the interrupt signal IN is input to the OR circuit 11 and the interrupt register 12. The OR circuit 11 integrates the input interrupt signal IN and outputs an integrated signal UN to the interrupt signal line 23. The interrupt register 12 records interrupt information indicating the original interrupt signal IN in accordance with the input interrupt signal IN.

(2) Interrupt Processing FIG. 3 is a timing chart for explaining control using an interrupt signal performed by the electronic device 100 as an example. FIG. 3A shows a change in the signal flowing through the internal interrupt signal line 24a. FIG. 3B shows a change in the signal flowing through the internal interrupt signal line 24b. FIG. 3C shows a change in the signal flowing through the internal interrupt signal line 24c. FIG. 3D shows a change in the signal flowing through the interrupt signal line 23. FIG. 3E shows changes in the signal flowing through the serial signal line 22.

  The control using the interrupt signal IN performed between the main board 40 and the panel board 30 will be described with reference to FIG. In FIG. 3, each control will be described by taking an example of interrupt processing executed by the interrupt signal IN <b> 2 transmitted from the microcomputer 33, but the same applies to the interrupt signal IN from the TPC 32 and the authentication device 33. be able to.

  When an operation signal is input to the microcomputer 33 by the user operating the operation key 54, the microcomputer 33 sends an interrupt signal IN2 to the internal interrupt signal line 24b (FIG. 3B).

  When the interrupt signal IN2 flows through the internal interrupt signal line 24b, the integrated circuit 10 receives the interrupt signal IN2, and the OR circuit 11 generates the integrated signal UN. The integrated signal UN generated by the integrated circuit 10 flows to the interrupt signal line 23 (FIG. 3 (d)). In the integrated circuit 10, interrupt information is recorded in the interrupt register 12 by the interrupt signal IN2 flowing through the internal interrupt signal line 24b.

When the integrated signal UN flowing through the interrupt signal line 23 is input to the host CPU 41, the host CPU 41 accesses the integrated circuit 10 (interrupt register 12) via the serial communication line 22. At this time, if the host CPU is in the hibernation mode, it returns from the hibernation mode by the input of the integrated signal UN.
As an example, the host CPU 41 outputs a read signal for reading interrupt information via the serial communication line 22 (FIG. 3 (e)). The integrated circuit 10 (interrupt register 12) that has received the read signal through the serial signal line 22 outputs interrupt information to the host CPU 41 through the serial communication line 22 (FIG. 3 (e)).

  The host CPU 41 that has received the return of the interrupt information through the serial signal line 22 confirms the interrupt content through the serial signal line 22 with respect to the device (the microcomputer 33 in this example) specified by the interrupt information. When the host CPU 41 can confirm the interrupt content, the host CPU 41 performs serial communication with the corresponding device based on the interrupt information via the serial communication line 22.

As described above, the first embodiment has the following effects.
The panel substrate 30 on which the first circuit and the second circuit are mounted is equipped with an integrated circuit 10 that integrates the interrupt signal IN output in response to an interrupt request from the first circuit or the second circuit to generate an integrated signal UN. ing. The integrated signal UN generated by the integrated circuit 10 is transmitted to the host CPU 41 mounted on the main board 40 through one interrupt signal line 23 connecting the panel board 30 and the main board 40. Therefore, even when the panel substrate 30 includes a plurality of devices, an interrupt request from each device can be transmitted to the host CPU 41 on the main substrate 40 side through one interrupt signal line 23, and the main substrate 40 and the panel substrate 30 are connected to each other. The number of wires to be connected can be reduced.
Regardless of the number of devices mounted on the panel substrate 30, an interrupt request is made through one interrupt signal line 23, so even if the number of devices mounted on the panel substrate 30 is changed, only the panel substrate 30 needs to be changed. The main board 40 can be used. That is, versatility when changing the design of a product can be improved.
Since the interrupt request from the first circuit or the second circuit mounted on the panel substrate 30 is made using the integrated signal UN flowing through the interrupt signal line 23 having the conventional configuration, the host CPU 41 is in a period when there is no interrupt request. It is possible to shift to the sleep mode. As a result, power consumption of the electronic device can be reduced.

  The integrated circuit 10 includes a recording unit (interrupt register 12) that records information on the circuit that generated the interrupt signal IN, and the host CPU 41 records using a communication signal line (serial communication line 22) connected to the integrated circuit 10. Get part information. Since the host CPU 41 can confirm the interrupt source circuit (device) based on the interrupt information recorded in the interrupt register 12, serial communication after the integrated signal UN is input can be performed more appropriately. .

  The integrated circuit 10 can implement the integrated circuit of the present invention with a simple configuration by integrating the interrupt signal IN from each circuit (device) to the host CPU 41 with an OR circuit.

2. Second embodiment:
As a serial communication format, in order to select a device with which the host CPU 41 communicates, a chip select signal CS and a reset signal RESET are transmitted to the device. When signal lines for transmitting the chip select signal CS and the reset signal RESET are wired for each device, the number of wirings connecting the main board 40 and the panel board 30 is increased. Therefore, in the second embodiment, the number of wires connecting the main board 40 and the panel board 30 is reduced by providing the integrated circuit with a function of distributing the chip select signal and the reset signal.

FIG. 4 is a block diagram illustrating a configuration of the electronic device 100 according to the second embodiment. In addition, what attached | subjected the same code | symbol in the figure has the same function as 1st Embodiment, The description is not repeated.
In the electronic device 100 shown in FIG. 4, as in the first embodiment, each device 31, 32, 34 mounted on the panel substrate 30 is connected to the host CPU 41 via the serial communication line 22 to perform serial communication. it can. The panel substrate 30 includes an integrated circuit 101, and integrates interrupt signals from the TPC 32 and the authentication device 34 among the devices mounted on the panel substrate 30. Further, the TPC 32 and the authentication device 34 are connected to the integrated circuit 101 through interrupt signal lines (24a, 24b), chip select signal lines (25a, 25b), and reset signal lines (26a, 26b).

FIG. 5 is a diagram illustrating an internal configuration of the integrated circuit 101 as an example in the second embodiment. In addition to the OR circuit 11 and the interrupt register 12, the integrated circuit 101 shown in FIG. 5 includes a GPIO register 13 that distributes the chip select signal CS and the reset signal RESET to each device.
The OR circuit 11 and the interrupt register 12 have the same functions as those in the first embodiment. The interrupt signal IN11 is an interrupt signal output from the TPC 32, and the interrupt signal IN12 is an interrupt signal from the authentication device 34.
The GPIO register 13 is connected to the serial communication line 22 and can communicate with the host CPU 41. The GPIO register 13 is connected to the TPC 32 and the authentication device 34 by the chip select signal line (25a, 25b) and the reset signal line (26a, 26b), respectively. The signal RESET is output.

Next, control using an interrupt signal in the second embodiment will be described.
FIG. 6 is a timing chart illustrating control using an interrupt signal performed by the electronic device 100 as an example according to the second embodiment. FIG. 6A shows a change in the signal flowing through the internal interrupt signal line 24a. FIG. 6B shows a change in the signal flowing through the internal interrupt signal line 24b. FIG. 6C shows a change in the signal flowing through the interrupt signal line 23. FIG. 6D shows changes in the signal flowing through the serial signal line 22. FIG. 6E shows a change in the signal flowing through the chip select signal line 25a. FIG. 6F shows changes in the signal flowing through the chip select signal line 25b.
In FIG. 6, a description will be given by taking as an example the process until the chip select signal CS is input to the TPC 32 by the interrupt process executed by the interrupt signal IN11 transmitted from the TPC 32. Of course, the present invention can be applied in the same manner to the processing for the interrupt signal IN12 from the authentication device 34 and the processing for outputting the reset signal RESET.

  When the user operates the touch panel 53 and the TPC 32 causes the interrupt signal IN11 to flow through the internal interrupt line 24a (FIG. 6A), the interrupt signal IN11 is input to the OR circuit 11 and the interrupt register 12 in the integrated circuit 101. The OR circuit 11 integrates the input interrupt signal IN11 and outputs the integrated signal UN to the interrupt signal line 23 (FIG. 6C), and the interrupt register 12 generates the original signal according to the input interrupt signal IN11. Interrupt information indicating the interrupt signal IN is recorded.

  When the integrated signal UN is input to the host CPU 41, the host CPU 41 accesses the interrupt register 12 of the integrated circuit 101 via the serial communication line 22 (FIG. 6 (d)). For example, the host CPU 41 sends a read signal for requesting interrupt information to the serial signal line 22. In response to access from the host CPU 41, the integrated circuit 101 (interrupt register 12) outputs interrupt information to the host CPU 41 through the serial communication line 22 (FIG. 6 (d)).

  The host CPU 41 that has received the return of the interrupt information through the serial signal line 22 accesses the GPIO register 13 through the serial signal line 22 (FIG. 6D). When the host CPU 41 accesses the GPIO register 13, a device to which the GPIO register 13 transmits a chip select signal CS is set. The GPIO register 13 transmits a chip select signal CS to the device (TPC 32) set by the host CPU 41 through the chip select signal line 25a (FIG. 6 (e)). The device that has received the chip select signal CS signal is ensured to occupy the serial communication line 22 and starts serial communication with the host CPU 41.

  As described above, the second embodiment has the following effects in addition to the effects of the first embodiment. The present invention can also be applied to a serial communication system using the chip select signal CS and the reset signal RESET, and the number of wirings between the main board 40 and the panel board 30 can be reduced.

3. Third embodiment:
FIG. 7 is a block diagram illustrating a configuration of the electronic device 100 according to the third embodiment.
In the electronic device 100 shown in FIG. 7, the integrated circuit 10 is different from the first embodiment in the configuration that is a part of the LCDC 31 that functions as a third circuit. In addition, since the location which attached | subjected the same code | symbol is the same as that of 1st Embodiment, description is not repeated.

  In the third embodiment, the main board is composed of a first panel board 35 and a second panel board 36. The first panel substrate 35 has the LCDC 31 mounted thereon. The LCDC 31 functions as a third circuit that controls the display function of the display panel 52 and does not perform the interrupt of the present invention. An integrated circuit 10 that integrates interrupt signals from the respective devices is mounted inside the LCDC 31. The integrated circuit 10 mounted on the LCDC 31 is connected to the TPC 32, the microcomputer 33, and the authentication device 34 via internal interrupt signal lines 24a to 24c.

  On the second panel substrate 36, the TPC 32, the microcomputer 33, and the authentication device 34 are mounted. Interrupt signals IN from the TPC 32, the microcomputer 33, and the authentication device 34 are integrated by the integrated circuit 10 mounted on the LCDC 31.

As described above, in the third embodiment, by forming the integrated circuit 10 inside the LCDC 31, two devices can be made into one device, and the substrate size of the sub-board (panel board) can be reduced. can do. The circuit (device) forming the integrated circuit 10 is not limited to the LCDC 31 and may be another circuit.
Further, by dividing the sub-board, the board layout can be set more flexibly, and the degree of freedom in designing the electronic device can be increased.

4). Fourth embodiment:
The substrate functioning as the sub-substrate is not limited to the panel substrate, and may be another substrate. FIG. 8 is a block configuration diagram illustrating a configuration of an electronic apparatus as an example according to the fourth embodiment.
In FIG. 8, a description will be given taking a printer as an example of the electronic device. In the electronic device 110 shown in FIG. 8, the main board 40 is the main board 40 of the present invention, and the sensor board 60 is the sub board of the present invention. A panel substrate 30 is connected to the main substrate 40, and the panel substrate 30 has the same functions as those in the first to third embodiments.

  The sensor board 60 is connected to the sensors 70, 71, internally converts signals corresponding to the detection of the sensors 70, 71, and outputs them to the host CPU 41 of the main board 40 via the serial communication line 122. The sensors 70 and 71 are a line sensor, a potentiometer, an acceleration sensor, and the like.

  The sensor board 60 is mounted with A / D conversion circuits 61 and 62 that are connected to the sensors 70 and 71, respectively, and perform analog / digital conversion on the inputs from the sensors 70 and 71. The A / D conversion circuits 61 and 62 are respectively connected to the host CPU 41 through the serial communication line 122, and output A / D converted signals to the host CPU 41 through the serial communication line 122.

  The A / D conversion circuits 61 and 62 are connected to the integrated circuit 102 through internal interrupt signal lines 124a and 124b. As in the other embodiments, the integrated circuit 102 outputs an integrated signal UN obtained by integrating the interrupt signals from the A / D conversion circuits 61 and 62 to the host CPU 41 through the interrupt signal line 123.

  In the sensor substrate 60, when the detection signal from the sensor 70 is input to the A / D conversion circuit 61, the A / D conversion circuit 61 sends the interrupt signal IN to the internal interrupt signal line 124a. The integrated circuit 102 integrates the interrupt signal IN and flows the integrated signal UN to the interrupt signal line 123. In the main board 40, when the host CPU 41 receives the integrated signal UN, the host CPU 41 accesses the interrupt register of the integrated circuit 102 through the serial communication line 122. The host CPU 41 starts serial communication with the A / D conversion circuit 61 specified by the interrupt information recorded in the interrupt register. Although description is omitted, the serial communication operates in the same manner even when a detection signal from the sensor 71 is input.

  As described above, in the fourth embodiment, the present invention can also be applied to a substrate (sensor substrate 60) that integrates sensor inputs.

5. Other embodiments:
The description of the electronic device as an example is just an example.
The electronic device may be a multifunction device in which a reading device such as a scanner is mounted on a printer, a display device such as a PC, or a wearable device.

  The first circuit or the second circuit mounted on the sub-board is not limited to the one shown in the specification, and any circuit (device) that outputs an interrupt signal when communicating with the main board. ) May be used.

Needless to say, the present invention is not limited to the above embodiments. It goes without saying for those skilled in the art,
・ Applying mutually interchangeable members and configurations disclosed in the above embodiments by appropriately changing the combination thereof.− Although not disclosed in the above embodiments, it is a publicly known technique and the above embodiments. The members and configurations that can be mutually replaced with the members and configurations disclosed in the above are appropriately replaced, and the combination is changed and applied. It is an embodiment of the present invention that a person skilled in the art can appropriately replace the members and configurations that can be assumed as substitutes for the members and configurations disclosed in the above-described embodiments, and change the combinations and apply them. It is disclosed as.

DESCRIPTION OF SYMBOLS 10 ... Integrated circuit, 21 ... Video signal line, 22 ... Serial signal line, 23 ... Interrupt signal line, 30 ... Panel board, 31 ... LCDC, 32 ... TPC, 33 ... Microcomputer, 34 ... Authentication device, 40 ... Main board 41 ... Host CPU, 50 ... Head module, 51 ... Transport mechanism, 52 ... Display panel, 53 ... Touch panel, 54 ... Operation key

Claims (6)

A main board with a control circuit,
A first circuit for controlling the first function, a second circuit for controlling the second function, and an interrupt signal transmitted from the first circuit or the second circuit to the control circuit are integrated into an integrated signal. An integrated circuit to generate, a sub-board comprising:
An interrupt signal line for connecting the control circuit and the integrated circuit and transmitting the integrated signal;
An electronic apparatus comprising: the control circuit; and a communication signal line for communicating with the first circuit and the second circuit. The integrated circuit includes a recording unit that records information of a circuit that has generated the interrupt signal.
The electronic apparatus according to claim 1, wherein the control circuit acquires the information of the recording unit using the communication signal line connected to the integrated circuit.   The electronic apparatus according to claim 1, wherein the integrated circuit is a part of the first circuit. The sub-board further includes a third circuit that controls the display function and does not interrupt,
The electronic device according to claim 1, wherein the integrated circuit is a part of the third circuit.   The electronic device according to any one of claims 1 to 4, wherein the sub-board includes a plurality of boards.   The electronic circuit according to any one of claims 1 to 5, wherein the integrated circuit integrates the interrupt signals from the first circuit and the second circuit to the control circuit by an OR circuit. machine.

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