JP2016025157A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which the device characteristics, when a fuse is not cut by first time cutting, can be reproduced by second time cutting of other fuse.SOLUTION: A semiconductor device includes a fuse circuit 11 having N(N≥2) fuses, and outputting a first logical value of N bits depending on the cutting and non-cutting each of the N fuses, and a decoder 12 generating a second logical value of M(M≥2) bits, by converting the first logical value. When J(1≤J<N) fuses, out of the N fuses, and other fuse are cut, a decoder generates a logical value same as the second logical value when K(0≤K<J) fuses, out of J fuses, are cut but different from that when only J fuses are cut.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a fuse logic circuit.

  Generally, a semiconductor device such as a DRAM (Dynamic Random Access Memory) is manufactured through a wafer manufacturing process, a wafer test process, an assembly process, and an assembly test process. In some cases, a semiconductor device is provided with a fuse for various purposes. In the semiconductor device having this fuse, the wafer test process includes, for example, a first wafer test process, a fuse blow process, and a second wafer test process. Specifically, after the first wafer test process, for example, a memory cell determined to be defective is replaced with another redundant memory cell in the fuse blow process, and the test is performed again in the second wafer test process. Is called. In the fuse blow process, circuit characteristics such as adjustment of the cycle of the built-in oscillation circuit and switching of circuit specifications such as switching of the input / output bus and switching of the load drive capacity of the output buffer are performed by cutting the fuse. May be.

  For example, Patent Document 1 discloses a semiconductor integrated circuit including a bandgap reference voltage generation circuit having a variable resistor for correcting temperature characteristics and a plurality of trimming circuits to which first and second fuses are connected. The temperature characteristic correcting variable resistor is variable according to the output voltage of the trimming circuit, and the output voltage of the trimming circuit is set by cutting one of the first and second fuses.

JP 2010-177612 A

  In the semiconductor manufacturing process, the number of wafers to be produced is determined according to the quantity requested by the user, but in reality, more wafers are produced than the quantity requested by the user. In manufacturing, the wafer test process is performed for all the wafers. However, as many wafers as required by the user are put into the assembly process of the subsequent process. Therefore, the wafers exceeding the user's required quantity are put on hold with the wafer test process completed.

  This held wafer is a wafer that has already undergone a fuse blow process. Therefore, the held wafer is a wafer in which specification change or characteristic adjustment is performed by cutting a fuse. Therefore, for example, when a request for a chip having the same specification is newly generated, a semiconductor device can be manufactured using the held wafer. However, if a request for a chip having another specification is generated, it is different. This wafer is manufactured from the beginning.

  The present invention has been made in view of the above points, and a semiconductor device capable of reproducing device characteristics when the fuse is not cut after the fuse is cut by cutting the other fuse for the second time. The purpose is to provide.

  A semiconductor device according to the present invention has N (N ≧ 2) fuses, and outputs a first logic value of N bits according to the cutting and non-cutting of each of the N fuses, A decoder that converts a logical value of 1 to generate a second logical value of M bits (M ≧ 2), and the decoder includes J (1 ≦ J <N) of N fuses And the other fuses are cut, the second logic value is different from the case where only J fuses are cut, and K of the J fuses (0 ≦ K). <J) The same logical value as the second logical value when the fuse is cut is generated.

  According to the semiconductor device according to the embodiment of the present invention, it is possible to reproduce the circuit specification when the fuse is not cut for the first time by cutting the fuse for the first time by cutting the other fuse for the second time. Become. Therefore, it is possible to set specifications and characteristics with the same degree of freedom before and after the wafer test.

(A) is a block diagram showing the configuration of the semiconductor device 10 of the first embodiment, and (b) is a diagram showing the input / output logic of the decoder 12. 2 is a circuit diagram of a fuse circuit 11. FIG. 2 is a flowchart showing a method for manufacturing the semiconductor device 10. FIG. FIG. 6 is a block diagram illustrating a configuration of a semiconductor device 30 according to a second embodiment. It is a logic circuit diagram of the output buffer circuit 33A. 3 is a logic circuit diagram of a decoder 32. FIG. FIG. 10 is a block diagram illustrating a configuration of a semiconductor device 50 according to a third embodiment. 4 is a diagram illustrating input / output logic of a decoder 52. FIG. 3 is a logic circuit diagram of a decoder 52. FIG.

  Examples of the present invention will be described in detail below.

  FIG. 1A is a block diagram illustrating a configuration of the semiconductor device 10 according to the first embodiment. The semiconductor device 10 has N (N ≧ 2) fuses (three fuses F1, F2, and F3 in this embodiment), and N bits corresponding to the cutting and non-cutting of each of the N fuses. The fuse circuit 11 outputs a pre-conversion logical value (first logical value, which is a 3-bit logical value “FV1, FV2, FV3” in this embodiment). The fuse circuit 11 is a logic circuit using a fuse.

  The semiconductor device 10 converts a 3-bit pre-conversion logical value “FV1, FV2, FV3” to an M-bit (M ≧ 2) post-conversion logical value (second logical value, in this embodiment, 2-bit logical value). And a decoder 12 for generating logical values “CV1, CV2”). The semiconductor device 10 is connected to the decoder 12 and is configured such that the circuit characteristics can be changed by the converted logical values “CV1, CV2”. For example, the functional circuit 13 is a period adjustment circuit of a built-in oscillation circuit, an input / output bus switching circuit, and a circuit connected thereto, but is not limited thereto. In the present embodiment, a case where the functional circuit 13 has three types of characteristics A, B, and C will be described. In the following description, the pre-conversion logical value may be simply referred to as FV, and the post-conversion logical value may be simply referred to as CV.

  FIG. 1B is a truth table of inputs / outputs in the decoder 12, that is, logical values FV and CV before and after conversion. First, among the three fuses F1 to F3, the decoder 12 has J (1 ≦ J <N) fuses and other fuses cut, and only the J fuses are cut. Generates different transformed logical values CV.

  Specifically, for example, when the fuse F1 is cut (that is, when J = 1), the decoder 12 receives a 3-bit logical value “001” as the pre-conversion logical value FV, and the decoder 12 A 2-bit logical value “10” is generated as the subsequent logical value CV. In response to this, the circuit characteristic of the functional circuit 13 is set to the circuit characteristic B. On the other hand, when the fuse F2, which is another fuse, is cut in addition to the fuse F1, the logical value “011” is input to the decoder 12 as the pre-conversion logical value FV, and the decoder 12 receives the logical value CV after conversion. A logical value “01” is generated. In response to this, the circuit characteristic of the functional circuit 13 is set to the circuit characteristic A. In this way, the decoder 12 generates a converted logical value CV that differs between when the fuse F1 is cut and when the fuses F1 and F2 are cut.

  In addition, when J fuses (1 ≦ J <N) and other fuses are cut, the decoder 12 has K fuses (0 ≦ K <J) among the J fuses cut. In this case, the same logical value as the converted logical value CV is generated.

  Specifically, the fuse F1 is cut (that is, J = 1), and in addition to the fuse F1, the fuse F2, which is another fuse, is cut. If the fuse F1 is not cut, for example, all the fuses are cut. If not (ie, when K = 0), the same logical value (ie, logical value “01”) as the converted logical value CV is generated. When the fuse F3 is cut as another fuse in addition to the fuse F1, the logical value “11” is different from the logical value “00”, which is the converted logical value CV, which is different from the case where only the fuse F1 is cut. Is generated. Further, this logical value “11” is obtained when K (K = 0) fuses smaller than J among the fuses F1 (J = 1) are cut (that is, the fuse F1 is not cut). For example, it is the same logical value as the converted logical value “11” when the fuse F2 is cut instead of the fuse F1.

  The decoder 12 is configured to include logic for generating the same post-conversion logical value CV even when different pre-conversion logical values FV are input. For this reason, for example, even after an arbitrary fuse is cut at the first time, by cutting another fuse at the second time, the converted logical value CV is the same as when the fuse cut at the first time is not cut. Can be obtained. The truth table shown in FIG. 1B is only an example.

  In this embodiment, for example, when performing fuse blow twice, one of the fuses F1 and F2 is logically configured assuming the first blow. Although a plurality of fuses may be cut at the first time, the number of uncut fuses is reduced, and the degree of freedom of characteristic change in the second fuse blow is reduced. Therefore, it is preferable to configure the logic of the decoder 12 on the assumption that the minimum fuse (that is, any one fuse) is cut (when J = 1) in the first fuse blow.

  Moreover, it is desirable that the fuse to be cut after the second time (that is, the “other fuse” in the above) is any one fuse other than the fuse cut at the first time. This is because it is desirable to minimize the number of fuses to be cut at the second time so that the third and subsequent cuts, that is, the characteristic change at least three times can be dealt with as much as possible. In other words, it is desirable to cut only one uncut fuse at the time of the fuse blow process performed a plurality of times.

  Further, as in this embodiment, when N and M satisfy the relationship of N> M, that is, when the number of bits N of the pre-conversion logical value FV is larger than the number of bits M of the post-conversion logical value CV, it is more than twice. Even if the fuse is cut a large number of times, the same converted logical value CV can be reproduced. Specifically, when N = 3 and M = 2, a maximum of eight types of pre-conversion logical values FV can be assigned to a maximum of four types of post-conversion logical values CV. Therefore, after the second blow of the fuse, even if another fuse is cut, the circuit characteristics can be changed (reproduced) again and again. Therefore, when N> M, the degree of freedom in changing characteristics increases.

  FIG. 2 is a diagram illustrating a circuit configuration of the fuse circuit 11. A configuration example of the fuse circuit 11 will be described with reference to FIG. The fuse circuit 11 includes a logic circuit as shown in FIG. The output of the pre-conversion logical value FV is controlled by the signal RS. When the signal RS becomes H level, the pre-conversion logical value FV is output. When the fuse F1 is not cut, the H level signal RS is at the L level at the node N11 and at the H level at the node N12, and the logic value signal FV1 at the logic level 0 is output. On the other hand, when the fuse F1 is blown, the H level signal RS becomes H level at the node N11 and L level at the node N12, and the logic value signal FV1 of the logic level 1 is output.

  Also for the fuses F2 and F3, when the signal RS is at the H level, the levels of the nodes N21, N22, N31 and N32 change according to the cutting and non-cutting of the fuses, and the logical value signals FV2 and FV3 are output. The In this manner, the fuse circuit 11 outputs the pre-conversion logical value FV corresponding to the cutting and non-cutting of the fuses F1 to F3.

  FIG. 3 is a flowchart showing manufacturing steps of the semiconductor device 10. First, in step S1, wafer manufacturing is performed. Specifically, transistors and wirings are formed on a semiconductor wafer. Next, a first wafer test is performed in step S2. Subsequently, in step S3, a first fuse blow is performed. Specifically, in this embodiment, one of the fuses F1 and F2 is cut, and the circuit characteristics of the functional circuit 13 are determined (selected). Next, in step S4, a second wafer test is performed. Specifically, the characteristic of the functional circuit 13 determined by cutting the fuse is tested.

  After the second wafer test in step S4, most of the wafer is packed and shipped through the assembly process in step S5 and the assembly test process in step S6. On the other hand, some wafers are put on hold after completion of step S4. Here, if there is a product request having a circuit characteristic different from the circuit characteristic of the functional circuit 13 determined in the first fuse blow process by the user, the held wafer proceeds to the second fuse blow process in step S7.

  In the second fuse blowing process in step S7, any of the fuses that were not cut in the first fuse blowing process is additionally cut. That is, in the second fuse blow process, in addition to the fuses (J fuses) cut in the first fuse blow process, other fuses are cut to change the circuit characteristics of the functional circuit 13. Subsequently, a third wafer test is performed in step S8. Thereafter, assembly is performed in step S9, and an assembly test is performed in step S10. Thus, the semiconductor device 10 whose characteristics are changed is manufactured. Therefore, for example, when an order with a short delivery date for a product with different characteristics is entered, the wafer after the first fuse blow can be allocated to enable rapid delivery. Note that the second and third wafer test steps may be omitted depending on the circuit characteristics of the functional circuit 13 and the like.

  FIG. 4 is a block diagram illustrating a configuration of the semiconductor device 30 according to the second embodiment. The semiconductor device 30 includes four fuses F1 to F4 and outputs a 4-bit pre-conversion logical value “FV1, FV2, FV3, FV4”, and a 4-bit by converting the pre-conversion logical value. The decoder 32 generates the logical values “CV1, CV2, CV3, CV4” after conversion. That is, in this embodiment, the bit number N of the pre-conversion logical value FV is the same as the bit number M of the post-conversion logical value CV (that is, N = M = 4). The fuse circuit 31 has the same configuration as the fuse 11 except that the number of fuses is changed from three to four.

  The semiconductor device 30 includes a memory circuit 33 that outputs memory data RD, a data buffer circuit 34 that adjusts the memory data RD to generate output data DO, and an output that adjusts the output intensity (load driving capability) of the output data DO. And a buffer circuit group 35. The output buffer circuit group 35 includes four output buffer circuits 35A, 35B, 35C, and 35D. The data buffer circuit 34 includes, for example, a latch circuit and a level shift circuit. In this embodiment, the output buffer circuits 35 </ b> A to 35 </ b> D are functional circuits to be controlled by the decoder 32.

  The output data DO is input to each of the output buffer circuits 35A to 35D of the output buffer circuit group 35, and is output to the outside as adjusted output data DT whose output intensity is adjusted. In addition, the converted logic value CV from the decoder 32 is input in parallel to each of the output buffer circuits 35A to 35D as logic value signals CV1 to CV4. The logical value signals CV1 to CV4 function as output control signals for the output buffer circuit group 35. That is, the converted logical value CV is supplied to the output buffer circuit group 35 as an output control signal (enable signal) of each of the output buffer circuits 35A to 35D. Each of the output buffer circuits 35A to 35B is configured to output output data DO having different output intensities based on the pre-conversion logical value.

  FIG. 5A shows a logic circuit of the output buffer circuit 35A. The output buffer circuit 35A is composed of, for example, a tristate buffer. Specifically, when the logic value signal CV1 is at L level (logic level is 0), the output buffer circuit 35A is in a high impedance (HiZ) state, and the output data DO is not output from the output buffer circuit 35A. On the other hand, when the logical value signal CV1 is at the H level (the logical level is 1), the output data DO is output. Although not shown, the other output buffer circuits 35B to 35D have the same configuration as the output buffer circuit 35A.

  For example, when all of the logic value signals CV1 to CV4 are at the H level, that is, when the converted logic value CV of the decoder 32 is “1111”, the output data DO input to each of all the output buffer circuits 35A to 35D. Is output. Therefore, the output buffer circuit group 35 outputs adjusted output data DT having a strength of 100% with respect to the strength of the output data DO. On the other hand, for example, when the logical value signal CV1 is at the L level, the output data DO is output from the output buffer circuits 35B to 35D. Therefore, the output buffer circuit group 35 outputs adjusted output data DT having 75% strength of the output data DT.

  In this embodiment, each of the output buffer circuits 35A to 35D of the output buffer circuit group 35 has the same structure. Therefore, the output intensity can be adjusted by 25% per output buffer circuit. That is, the output buffer circuit group 35 can adjust the intensity of the output data DO in units of 25%.

  FIG. 5B is an input / output truth table in the decoder 32 of the semiconductor device 30. Similarly to the decoder 12, the decoder 32, when the J fuses (1 ≦ J <N) and the other fuses among the four fuses F1 to F4 are cut, only the J fuses are cut. A post-conversion logical value CV that is different from the above case is generated.

  Specifically, for example, when the fuse F1 is blown (that is, when J = 1), the decoder 32 receives the logical value “0001” as the pre-conversion logical value FV, and the decoder 32 displays the post-conversion logical value. A logical value “0111” is generated as CV. In response to this, the output data DO is output from the output buffer circuits 35A to 35C, and adjusted output data DT having 75% strength is output.

  On the other hand, when the fuse F2, which is another fuse, is cut in addition to the fuse F1, the logical value “0011” is input to the decoder 32 as the pre-conversion logical value FV, and the decoder 32 displays the post-conversion logical value CV. A logical value “1111” is generated. In response to this, the output buffer circuit group 35 outputs adjusted output data DT having 100% strength. Therefore, the decoder 32 generates a converted logical value CV that is different between when the fuse F1 is cut and when the fuses F1 and F2 are cut.

  In addition, when J fuses (1 ≦ J <N) and other fuses are cut, the decoder 12 has K fuses (0 ≦ K <J) among the J fuses cut. In this case, the same logical value as the converted logical value CV is generated.

  Specifically, the fuse F1 is cut, and in addition to the fuse F1, the fuse F2, which is another fuse, is cut, the fuse F1 is not cut, for example, all the fuses are not cut (that is, K The same logical value as the converted logical value CV (that is, the logical value “1111”) in the case of = 0) is generated.

  In the present embodiment, the load driving capability in the semiconductor device 30 functioning as a semiconductor memory can be adjusted by cutting the fuse. Since electronic parts are specified in various places in general life, countermeasures against electromagnetic noise are important. For example, in the case of a semiconductor memory, it is possible to reduce electromagnetic noise by setting the output intensity according to the size and quantity of loads connected to the memory. Therefore, considering that different loads for each user are connected to the memory, it is highly likely that the output intensity specification is changed frequently. Therefore, as in this embodiment, the semiconductor device 30 whose specifications can be re-changed (re-set) at the manufacturing stage is very effective for use as a semiconductor memory.

  FIG. 6 is a diagram illustrating a logic circuit of the decoder 32. As shown in FIG. 6, the decoder 32 can be configured using an AND circuit, a NOT circuit, and an OR circuit. The illustrated circuit configuration is merely an example.

  In the present embodiment, the case where the output buffer circuit group 35 includes four output buffer circuits 35A to 35D has been described. For example, only the output buffer circuit 35A (one output buffer circuit) has the drive capability of the output data DO. You may adjust. Although the case where the data buffer circuit 34 adjusts the memory data RD from the memory circuit 33 to generate the output data DO has been described, the memory data RD may be output as it is as the output data DO. Therefore, each of the output buffer circuits 35A to 35D can adjust the output intensity of the memory data RD.

  FIG. 7 is a block diagram illustrating a configuration of the semiconductor device 50 according to the third embodiment. Similar to the semiconductor device 30, the semiconductor device 50 functions as a semiconductor memory. The semiconductor device 50 includes a fuse circuit 51, a memory circuit 53, and a data buffer circuit 54 having the same configuration as the fuse circuit 31, the memory circuit 33, and the data buffer circuit 34, respectively.

  The decoder 52 of the semiconductor device 50 is different from the decoder 32 in that the number of bits of the converted logical value CV is six. That is, in this embodiment, N = 4 and M = 6. The output buffer circuit group 53 of the semiconductor device 50 includes output buffer circuits 53B to 53D having the same configuration as the output buffer circuits 33B to 33D. In addition, the output buffer circuit group 53 divides the output buffer circuit 33A into a portion that outputs a signal with a strength of 20% and a portion that outputs a signal with a strength of 5%, and is independent by logical value signals CV11 and CV12, respectively. The output buffer circuit 53A1 is configured to output the output data DO, and the output buffer circuit 53A2 is configured to output a signal having an intensity of 5%. Each output buffer circuit is connected in parallel by a signal line for output data DO.

  FIG. 8 is a diagram showing an input / output truth table of the decoder 52. In this embodiment, the output intensity can be finely adjusted by controlling the logic value signals CV12 and CV13, that is, by switching whether or not data is output from the output buffer circuits 53A1 and 53A2. Specifically, by setting the logical value signal CV13 of the converted logical value CV to the H level, it is possible to output output data having an output intensity obtained by adding 5% to the output intensity set by the data of other bits. It becomes. Further, by setting the logical value signal CV12 to the L level, output data having an intensity obtained by subtracting 5% from the output intensity set by data of other bits can be output. This adjustment can be performed by the logical value signals FV3 and FV4 of the pre-conversion logical value FV. That is, adjustment can be performed by cutting and non-cutting the fuses F3 and F4. The decoder 52 is configured to have such logic.

  FIG. 9 is a diagram illustrating a logic circuit of the decoder 52. As shown in FIG. 9, like the decoder 32, the decoder 52 can be configured by combining an AND circuit, an OR circuit, and a NOT circuit. The illustrated circuit configuration is merely an example.

  In this modification, the fuses F1 and F2 are configured as output strength selection (coarse adjustment) fuses, and the fuses F3 and F4 are configured as output strength fine adjustment fuses. The output buffer circuits 55A1 and 55A2 function as output buffer circuits that finely adjust the output intensity of the output data DO (or memory data RD) in an expanded manner.

  In other words, in the present modification, the output buffer circuit group 55 performs coarse adjustment output buffer circuits 55B, 55C and 55D for coarse adjustment of the output intensity of the memory data RD, and fine adjustment for fine adjustment of the memory data RD. Output buffer circuits 55A1 and 55A2 are provided. Therefore, for example, when the output buffer circuit group 55 is combined with the output buffer circuit group 35 of the second embodiment, both rough adjustment and fine adjustment of the output intensity of the memory data RD can be performed by cutting the fuse multiple times. Specifically, various characteristics can be changed and reproduced (rough adjustment of output intensity) by cutting a plurality of fuses, and finally the characteristics can be finely adjusted. Therefore, not only can the characteristics be changed with a high degree of freedom, but also the changed characteristics can be finely adjusted. Therefore, it becomes possible to meet the detailed needs of customers.

  This modification can be combined with the first and second embodiments. Specifically, like the fuse circuit 51, the fuse circuit 31 has a fuse prepared only for adjusting the output intensity of the output data DO by the second and subsequent cutting (for example, final fine adjustment). You may do it. Further, the output buffer circuit according to the second embodiment can be configured like the output buffer circuit according to the modified example, or another functional circuit can be added.

  In the above, the decoder is different from the case where only J fuses are cut when J (1 ≦ J <N) fuses and other fuses are cut out of N fuses. A second logical value that is the same as the second logical value when K (0 ≦ K <J) fuses among the J fuses are cut is generated. Therefore, by cutting the fuse after the second time, it is possible to return to the characteristics of the device when the fuse cut first time is not cut.

10, 30, 50 Semiconductor devices 11, 31, 51 Fuse circuit FV Logical value before conversion (first logical value)
12, 32, 52 Decoder CV Logical value after conversion (second logical value)
33, 53 Memory circuit 34, 54 Data buffer circuit 35, 55 Output buffer circuit group

Claims (7)

A fuse circuit having N (N ≧ 2) fuses, and outputting an N-bit first logic value corresponding to cutting and non-cutting of each of the N fuses;
A decoder that converts the first logic value to generate a second logic value of M bits (M ≧ 2);
The decoder
Of the N fuses, when the J fuses (1 ≦ J <N) and other fuses are cut, the second logic is different from the case where only the J fuses are cut. And the same logical value as the second logical value when K (0 ≦ K <J) fuses among the J fuses are cut is generated. Semiconductor device.   The semiconductor device according to claim 1, further comprising: a functional circuit connected to the decoder and configured to change circuit characteristics according to the second logic value.   The semiconductor device according to claim 1, wherein the J fuses are any one of the N fuses.   4. The semiconductor device according to claim 1, wherein the other fuse is any one of the N fuses other than the J fuses. 5.   The semiconductor device according to claim 3, wherein the N and the M satisfy a relationship of N> M. A memory circuit for outputting memory data;
An output buffer circuit for adjusting the output intensity of the memory data,
6. The semiconductor according to claim 1, wherein the output buffer circuit is configured to output output data having different output intensities based on the second logical value. apparatus.   The output buffer circuit includes: a coarse adjustment output buffer circuit that performs coarse adjustment of the output intensity of the memory data; and a fine adjustment output buffer circuit that performs fine adjustment of the output intensity of the memory data. The semiconductor device according to claim 6.

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