JP2016019147A - Semiconductor device, display system and display method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, a display system and a display method which achieve less visibility of deterioration in display characteristics even when a semiconductor device having homeostatic abnormality is used.SOLUTION: A semiconductor device (60) is constituted to include: a storage part (36) having a storage region for storing data; a writing part (32A) for sequentially writing a data group of a predetermined unit from an initial address indicating a starting position of the storage region; a reading part (32B) for sequentially reading the data group written in the storage region from the initial address; and a creation part (50) for creating initial addresses different form each other every one or a plurality of predetermined units.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, a display system, and a display method.

  In recent years, the use of a display system that displays an image captured by a camera on a display device such as a display in real time has expanded. As such a display system, for example, a display system that displays an image showing an area around a vehicle on a display in a vehicle interior based on a captured image obtained by a camera mounted on a vehicle such as an automobile is known. ing.

  The video signal used for display on the display device includes an image (frame) corresponding to the screen of the display device at a predetermined cycle. An image processing apparatus that processes such a video signal may use a frame memory as a buffer memory that stores an image in order to adjust the synchronization timing of the video signal.

  In this case, the image processing apparatus periodically writes an image included in the video signal in the frame memory. The image processing apparatus can adjust the synchronization timing of the video signal by periodically reading out images from the frame memory at a predetermined timing.

  Conventionally, there is a method using ECC (Error Correction Code) as a countermeasure when, for example, a 1-bit error (failure) occurs in this frame memory. According to the method using ECC, the memory can be protected from a 1-bit error by adding an error correction code to the data when writing to or reading from the memory.

  Another example of a countermeasure when a bit error occurs in the frame memory is disclosed in Patent Document 1. According to the countermeasure disclosed in Patent Document 1, when a bit error is detected, it is possible to prevent the display screen from being disturbed by stopping and skipping the processing for the frame in which the bit error is detected.

JP 2012-233965 A

  However, when a method of adding a code such as ECC is adopted, the circuit scale of the circuit for controlling the frame memory is increased, resulting in an increase in cost. In addition, since the amount of calculation increases by performing error correction or the like, there is a concern about a decrease in processing speed.

  The countermeasure disclosed in Patent Document 1 is effective in the case of a temporary error such as a soft error, but functions sufficiently for a permanent error such as a memory bit (memory cell) failure. There is no concern.

  On the other hand, in the inspection process at the time of shipment, various methods can be considered to detect failures of individual memory bits. However, this method is not practical because the test time is enormous and it is not realistic. It cannot deal with the failure of

  The present invention has been made to solve the above-described problem, and provides a semiconductor device, a display system, and a display method in which deterioration of display characteristics is hardly visually recognized even when a semiconductor device having a constant abnormality is used. The purpose is to do.

  The semiconductor device according to the present invention includes a storage unit having a storage area for storing data, a writing unit for sequentially writing a data group of a predetermined unit from a head address indicating a write start position of the storage area, and the storage area A reading unit that sequentially reads the data group written to the first address from the first address, and a generation unit that generates the first address different for each of the predetermined units.

  In addition, a display system according to the present invention includes the semiconductor device, an imaging unit that acquires an image of an object, and a display unit that displays an image based on image data, and the writing unit includes the imaging The image data based on the video acquired by the unit is the data group, and the predetermined unit is one frame, and is periodically written in units of one frame from the start address of the storage area. The image data written in the storage area is periodically read out in units of one frame from the start address and sent to the display unit, and the generation unit generates a different start address for each one or a plurality of frames. Is.

  On the other hand, the display method according to the present invention includes a step of generating image data in units of frames based on video acquired by the imaging unit, and a storage unit having a storage area for storing the image data for one frame. A first address indicating a write start position of the storage area is different for each of the one or more frames, and the image data is periodically generated in units of one frame in order from the first address. A step of writing in the storage area; a step of periodically reading out the image data written in the storage area in units of one frame in order from the head address; and a period of reading out of the storage area in units of one frame And displaying a video based on the image data on a display unit.

  According to the present invention, it is possible to provide a semiconductor device, a display system, and a display method in which deterioration of display characteristics is hardly visible even when a semiconductor device having a constant abnormality is used.

It is a functional block diagram which shows an example of a structure of the display system which concerns on embodiment. It is a block diagram which shows an example of a structure of the memory control part which concerns on 1st Embodiment. It is a conceptual diagram which shows the memory | storage form of the frame memory which concerns on embodiment. FIG. 5 is a block diagram of a memory control unit according to a comparative example, and a diagram for explaining a relationship between a memory address space of a frame memory and screen display. It is a figure for demonstrating the relationship between failure of the memory bit which concerns on a comparative example, and the display of a screen. It is a time chart for demonstrating the relationship between the memory | storage surface of the frame memory which concerns on 1st Embodiment, and write-in control and read-out control. It is a figure for demonstrating the relationship between the failure of the memory bit which concerns on 1st Embodiment, and the display of a screen. It is a block diagram which shows an example of a structure of the memory control part which concerns on 2nd Embodiment. It is a conceptual diagram which shows the memory | storage form of the image data which concerns on 2nd Embodiment. It is a figure for demonstrating the relationship between the failure of the memory bit which concerns on 2nd Embodiment, and the display of a screen.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[First Embodiment]
A display system 10 according to the present embodiment will be described with reference to FIGS.
In this embodiment, an example in which the display system according to the present invention is applied to a display system mounted on an automobile will be described. The display system 10 is mounted on a vehicle such as an automobile, and has a function of displaying an image showing a state around the vehicle in a vehicle interior.

  As shown in FIG. 1, the display system 10 includes an in-vehicle camera 12, an image processing device 14, a display device 16, and a control unit 18.

  The in-vehicle camera 12 is a camera for taking an image of the rear of the vehicle provided behind the vehicle, for example. The image processing device 14 is a device that performs processing for converting video captured by the in-vehicle camera 12 into image data suitable for display on the display device 16. The display device 16 is a display using, for example, a liquid crystal, and is provided in the vehicle as an example. The display device 16 displays an image showing the rear of the vehicle photographed by the in-vehicle camera 12 in real time.

  The control unit 18 includes a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), an NVM (Non-Volatile Memory), and the like (not shown), and controls the display system 10 in an integrated manner. The display system 10 functions as a back monitor system that monitors the rear of the vehicle as a whole.

  The image processing apparatus 14 includes an image acquisition unit 30, a memory control unit 32, an image output unit 34, and a frame memory 36.

  The image acquisition unit 30 acquires an analog image from the in-vehicle camera 12 at a predetermined cycle, and converts the analog image into a digital image (A / D conversion). Accordingly, the image acquisition unit 30 outputs a video signal (image data) including a digital image at a predetermined cycle together with the synchronization signal.

  The memory control unit 32 adjusts the synchronization timing of the image data so as to match the synchronization timing of the display device 16. As a result, the memory control unit 32 outputs the image data including the progressive image (frame) having all the horizontal lines at a predetermined cycle and the synchronization timing adjusted to suit the display.

  The image output unit 34 outputs the image data output from the memory control unit 32 to the display device 16. Thereby, an image showing a state behind the vehicle is displayed on the display device 16.

  The frame memory 36 is a buffer memory that writes and reads image data in units of frames. As an example, the frame memory 36 is configured by using an SDRAM (Synchronous Dynamic Random Access Memory).

  Details of the memory control unit 32 according to the present embodiment will be described with reference to FIG. As shown in FIG. 2, the memory control unit 32 includes a write-side memory control circuit 32A, a read-side memory control circuit 32B, and a head address generation circuit 50.

  The write-side memory control circuit 32A is a circuit that writes image data to the frame memory 36 in units of frames while sending the write data and the write-side address to the frame memory 36 based on the image data and the synchronization signal received from the image acquisition unit 30. is there.

  Based on the synchronization signal received from the image output unit 34, the read-side memory control circuit 32B reads image data in units of frames from the frame memory 36 while sending the read-side address to the frame memory 36, and sends the image data to the image output unit 34. It is.

  Here, the semiconductor device 60 according to the present embodiment includes a memory control unit 32 and a frame memory 36. Of course, the present invention is not limited to this. For example, the entire image processing apparatus 14 may be a semiconductor device.

  The start address generation circuit 50 is a circuit that generates the start address of the frame memory 36 that is designated in the write process and the read process in the frame memory control method according to the present embodiment to be described later. The start address generation circuit 50 may be a circuit that randomly generates a start address using a pseudo-random pattern generation circuit, or a circuit that generates an adder at a predetermined interval (a constant interval or a variable interval). It is good. In this embodiment, a circuit that randomly generates a head address is employed. The generated head address may be stored in storage means such as a RAM (not shown).

FIG. 3 shows a storage form of image data in the frame memory 36 according to the present embodiment. The frame memory 36 has a storage area specified by the address A ₁ to A _n, FIG. 3 shows a state where the image data D ₁ to D _n to each of the storage areas is stored.

Although the format of the image data D _{1 to} D _n is not particularly limited, in the present embodiment, 8 bits each of red (R), green (G), and blue (B) for the gradation value of each pixel of the display device 16. The image data is a total of 24 bits represented by (256 gradations). In the present embodiment, a mode using image data expressed in the RGB color space is described as an example. However, the present invention is not limited to this. For example, a mode using image data expressed in the YCbCr color space may be used. Good.

  Next, with reference to FIGS. 4 and 5, the display on the display device 16 when a part of the memory bits of the frame memory according to the comparative example has a failure will be described. FIG. 4 is a block diagram showing a memory control unit according to a comparative example, and FIG. 5 is a diagram for explaining the relationship between the memory address space of the frame memory and the screen display.

  As shown in FIG. 4A, the memory control unit 70 according to the comparative example includes a write side memory control circuit 70A and a read side memory control circuit 70B, and the memory control unit 32 according to the present embodiment. Thus, the head address generation circuit 50 is not provided.

  FIG. 4B shows a memory address space of the frame memory 72, an input display screen 100 conceptually showing a screen when image data in units of frames written in the frame memory 72 is displayed on the display device 16, and the frame memory 7 shows an output display screen 102 when image data in units of frames read from 72 is displayed on the display device 16.

  The write-side memory control circuit 70A in the comparative example sets the head position DHI (the upper left corner of the input display screen 100) of the input display screen 100 to the head address Ah that is the fixed head address of the memory address space of the frame memory 72. The image data is written correspondingly.

  Further, the read-side memory control circuit 70B sequentially reads out the image data stored at the start address Ah of the frame memory 72 in correspondence with the start position DHO of the output display screen 102.

  With reference to FIG. 5, in the frame memory control method according to the comparative example as described above, a display on the display device 16 when a specific memory bit of the frame memory 72 has a failure will be described. FIG. 5B shows a memory address space in which the frame memory 72 includes a failed memory bit M that has failed and cannot be stored.

  As described above, the write-side memory control circuit 70A writes image data from the start address Ah of the frame memory 72 in correspondence with the start position DHI of the input display screen 100 shown in FIG. Further, the read-side memory control circuit 70B reads the image data from the frame memory 72 with the start address Ah corresponding to the start position DHO of the output display screen 102 shown in FIG. At this time, no image is displayed at the position corresponding to the failure memory bit M on the output display screen 102 (the position indicated by the symbol N in FIG. 5C). Hereinafter, the fact that an image is not displayed on the output display screen 102 due to the faulty memory bit M may be referred to as “screen noise N”.

  In the frame memory control method according to the comparative example, the position of the noise N on the screen corresponds to the address of the failure memory bit M of the frame memory 72, so the position of the noise N on the output display screen is always the same position. is there. In this case, since a portion that is not always displayed is generated on a part of the output display screen 102, it is easily recognized by the viewer of the display device 16, and the defect of the display device 16 is conspicuous. Therefore, in the present embodiment, the head address generation circuit 50 generates a head address for each frame, and the head address Ah is changed for each frame.

  Next, a frame memory control method according to the present embodiment will be described with reference to FIGS.

  FIG. 6 shows the time when the write frame Fw (corresponding to the write data shown in FIG. 2) is written to the frame memory 36 as image data, and the written image data is read as the read frame Fr (corresponding to the read data shown in FIG. 2). A chart is shown. In FIG. 6, a case where the frame memory 36 according to the present embodiment is composed of two frame memories 36A and 36B will be described as an example.

In FIG. 6, as indicated by the timing t1, the write frame Fw1 is first started from a state in which it is written to the frame memory 36A. At this time, it is assumed that the head address generation circuit 50 generates an address A _i as the head address. That is, at timing t1, the image data D _{1 to} D _n are written with the leading position DHI of the input display screen 100 shown in FIG. 7A corresponding to the address A _i . At timing t1, image data has not yet been written in the frame memory 36B.

If the write side memory control circuit 32A, is provided with a counter for counting the number of image data to be written, the start address generation circuit 50 generates the start address A _i is, (n-i + 1) pieces of image data after writing the frame memory 36A, and writes the image data _{D n-i + 2} to return to the address _{a 1.} Therefore, the last image data D _n is stored at the address A _i−1 .

In the next timing t2, the read side memory control circuit 32B has the address _{A i} of the frame memory 36A in correspondence to the leading position DHO output display screen 102 of FIG. 7 (c), the image data _D 1 ~ from the frame memory 36A it reads the D _n as a read frame Fr1. And counter for counting the number of image data is also provided on the read side memory control circuit 32B, the (n-i + 1) pieces of image data after reading from the frame memory 36A, the D _{n-i + 2} to return to the address A ₁ Read out.

In the present embodiment, by counting the number of image data, the designation of addresses in writing to and reading from the frame memory 36 when the head address is changed is controlled (address _An). While the address to control the return to a ₁₎ will be exemplified in the form of after reaching, not limited to this, for example, be in the form of controlling the designation of addresses by onboard software to the control unit 18 Good.

On the other hand, at the timing t2, the write frame Fw2 is written in the frame memory 36B as the image data D ₁ ′ to D _n ′. At this time, it is assumed that the head address generation circuit 50 generates an address A _j as the head address. The writing of the image data when the address _Aj is the head address is the same as that at the timing t1.

In the next timing t3, the read side memory control circuit 32B is an address _{A j} of the frame memory 36B in correspondence to the leading position DHO output display screen 102 shown in FIG. 7 (c), the image data _{D 1} from the frame memory 36B “˜D _n ” is read as a read frame Fr2.

On the other hand, at the timing t3, the write frame Fw3 is written to the frame memory 36A as the image data D ₁ ″ to D _n ″. In this case, the start address generation circuit 50 is assumed to generate the address A _k as the start address.

  Similarly, image data is written to the frame memory 36 and image data is read from the frame memory 36.

  With reference to FIG. 7, in the frame memory control method according to the present embodiment, display on display device 16 when a specific memory bit in frame memory 36 has a failure will be described. FIG. 7 corresponds to the frame memory control method shown in FIG.

In FIG. 7B, the head address of the frame memory 36 corresponding to the head position DHI of the input display screen 100 is changed from A _i to A _j . As described above, when the head address changes, the relative address of the image data corresponding to the failed memory bit M changes, so that the screen noise also changes from N _i to N _j as shown in FIG. Change.

  In this embodiment, since the head address is randomly generated, the position of the noise on the screen also changes randomly. Then, since there is a limit to the human visual response speed, it is difficult for the viewer to see.

  As described in detail above, according to the present embodiment, it is possible to provide a semiconductor device, a display system, and a display method in which deterioration of display characteristics is hardly visually recognized even when a semiconductor device having a constant abnormality is used. It becomes possible.

  In addition, according to the semiconductor device, the display system, and the display method according to the present embodiment, the above-described effect can be achieved only by adding a start address generation circuit having a small circuit scale, and therefore, it is possible to suppress an increase in cost. .

[Second Embodiment]
The display system 10 according to the present embodiment will be described with reference to FIGS. As shown in FIG. 8, the memory control unit 40 of the display system 10 according to the present embodiment has a configuration in which a bit position generation circuit 52 is added to the memory control unit 32 shown in FIG.

  Here, the semiconductor device 80 according to the present embodiment includes the memory control unit 40 and the frame memory 36. Of course, the present invention is not limited to this, and the entire image processing apparatus 14 may be a semiconductor device.

As described above, in the present embodiment, the image data to be stored in the frame memory 36 is
The gradation value of each pixel of the display device 16 is image data of a total of 24 bits represented by 8 bits (256 gradations) for each of red (R), green (G), and blue (B). The bit position generation circuit 52 according to the present embodiment changes the bit position in at least one of the R, G, and B 8-bit frame memories 36 for each frame. Note that the bit position generation circuit 52 according to the present embodiment can be configured using a pseudo-random pattern generation circuit or an adder, similarly to the head address generation circuit 50. The generated bit position is
You may memorize | store in memory | storage means, such as RAM which is not shown in figure.

9, as an example, the storage area of image data of R (i.e., corresponding to the respective addresses _A 1 to A _n of the frame memory 36 shown in FIG. 3, part of the area for storing the image data _D 1 to D _n ), R0 to R7 (8 bits). Normally, the image data of R is stored in order from R0 to R7 in order from the MSB (Most Significant Bit) to the LSB (Least Significant Bit). In the present embodiment, the bit position generation circuit 52 changes the MSB position of the image data in the storage areas R0 to R7 for each frame.

Next, the reason why the position of the MSB in the storage areas R0 to R7 is changed for each frame will be described with reference to FIG. FIG. 10 corresponds to the frame memory control method shown in FIG. As described above, when the head address for writing to and reading from the frame memory 36 is changed from Ai to Aj (see FIG. 10B), the position on the output display screen 102 corresponding to the position of the failure memory bit M ( In other words, the noise position on the screen was changed from N _i to N _j (see FIG. 10C).

However, if there is a failure in one of the storage areas R0 to R7, for example, if there is a failure in R0, the position of the 8-bit R image data is not changed and stored in order from the MSB to the LSB. As a result, an abnormality always occurs in the MSB of the R image data. In this case, depending on the mode of abnormality, the MSB is always valid (always becomes data “1”), and the gradation value of the R portion of the image data always takes a large value (128 or more). As a result, even if the screen noise changes from N _i to N _j , since the gradation of N _i or N _j itself is large (since N _i or N _j is bright red), it is easily recognized by the viewer.

On the other hand, in the display system according to the present embodiment, the head address is changed from A _i to A _j and the MSB bit position of the R image data is changed from MSB _i to MSB _j as shown in FIG. It has changed. By doing so, since the gradation value of the R image data changes for each frame, the gradations of the screen noises N _i and N _j are also randomized. As a result, the screen noise is not easily recognized by the viewer. Become.

  Note that the MSB bit position change of the image data according to the present embodiment may be applied when the position of the faulty memory bit in the frame memory 36 is specified in advance by inspection or the like. In this case, the address of the failed memory bit may be stored in storage means such as NVM (not shown).

  As described above, according to this embodiment as well, it is possible to provide a semiconductor device, a display system, and a display method in which deterioration of display characteristics is hardly visually recognized even when a semiconductor device having a constant abnormality is used. .

  In addition, according to the semiconductor device, the display system, and the display method according to the present embodiment, the above-described effect can be obtained only by adding a start address generation circuit and a bit position generation circuit with a small circuit scale, which causes an increase in cost. It is suppressed.

  Here, in the above-described embodiment, an example in which the MSB bit position is changed for the 8 bits of the R image data of the image data has been described, but considering the case where there are a plurality of failure memory bits, etc. For other colors (G, B), the bit position of the MSB may be changed at the same time.

  In the above embodiment, an example has been described in which the MSB bit position of the image data is changed to make the screen noise less visible. However, the present invention is not limited to this. For example, it is 8 bits (or 24 bits). You may make it change the arrangement | sequence of image data at random.

  In the above-described embodiment, an example in which the MSB bit position is changed in addition to the change of the start address has been described. However, the present invention is not limited to this, and the MSB bit position is changed without changing the start address. It is good also as a form to do.

Further, in each of the above-described embodiments, a mode in which the head address is generated by the head address generation circuit 50 for each frame, or a mode in which the bit position of the MSB is generated by the bit position generation circuit 52 for each frame will be described. However, the present invention is not limited to this, and depending on the allowable screen noise or the like, the start address every several frames, for example, every five frames,
Alternatively, the MSB bit position may be generated.

  In each of the above embodiments, the frame memory 36 is described as an example in which the frame memory 36 is composed of two frame memories 36A and 36B. However, the present invention is not limited to this. It is good also as a form comprised from the frame memory.

  In each of the above embodiments, a description has been given of an example in which a start address generation circuit or a bit position generation circuit is provided. However, the present invention is not limited to this, and a start address or a bit position is generated by a CPU (not shown). May be.

DESCRIPTION OF SYMBOLS 10 Display system 12 Car-mounted camera 14 Image processing apparatus 16 Display apparatus 18 Control part 30 Image acquisition part 32, 40, 70 Memory control part 32A, 70A Write side memory control circuit 32B, 70B Read side memory control circuit 34 Image output part 36, 36A, 36B, 72 Frame memory 50 First address generation circuit 52 Bit position generation circuit 60, 80 Semiconductor device 100 Input display screen 102 Output display screen M Fault memory bit N Screen noise

Claims (9)

A storage unit having a storage area for storing data;
A writing unit that writes a data group of a predetermined unit in order from a top address indicating a write start position of the storage area;
A reading unit that sequentially reads the data group written in the storage area from the head address;
A generating unit that generates the different start address for each of the predetermined units or a plurality of the predetermined units;
Including semiconductor devices. The semiconductor device according to claim 1, wherein the generation unit generates the head address by making the head address different at random or different at predetermined intervals. A semiconductor device according to claim 1 or 2,
An imaging unit for acquiring an image of the object;
A display unit for displaying video based on image data,
The writing unit sets image data based on the video acquired by the imaging unit as the data group,
And the predetermined unit is one frame, and is periodically written in units of one frame in order from the head address of the storage area,
The reading unit periodically reads the image data written in the storage area in units of one frame in order from the top address and sends the data to the display unit,
The generation unit generates a different start address for each one or a plurality of frames. Each of the image data is represented by a gradation value of a predetermined number of bits,
The display system according to claim 3, wherein the semiconductor device further includes a replacement unit that replaces an arrangement of bits indicating the gradation value of the image data to be stored in at least one specific storage area. The replacement unit generates the position of the MSB of the bit array indicating the gradation value of the image data to be stored in the specific storage area for each one or more frames, and generates the image data The display system according to claim 4, wherein an arrangement of bits indicating the gradation value is exchanged. The display system according to claim 4, wherein the specific storage area is a storage area that cannot be normally stored. When the writing unit reaches the last address of the storage unit while writing the image data for one frame, the writing unit reads the remaining image data from the storage area corresponding to the first address of the storage unit. writing,
The reading unit reads the remaining image data from the storage area corresponding to the first address of the storage unit when the last address of the storage unit is reached in the middle of reading the image data for one frame. The display system according to any one of claims 3 to 6. Generating image data in units of frames based on video acquired by the imaging unit;
When writing the image data for one frame in a storage unit having a storage area for storing data, the head address indicating the write start position of the storage area is generated differently for each of the one or more frames. Steps,
Writing the image data into the storage area periodically in units of one frame in order from the head address;
Periodically reading out the image data written in the storage area in units of one frame in order from the head address;
Displaying a video based on the image data periodically read from the storage area in units of one frame on a display unit;
Display method including. A storage unit having a storage area for storing data;
A writing unit that sets image data based on video acquired by the imaging unit as a data group in units of one frame, and periodically writes the data group in units of one frame in order from a head address indicating a writing start position of the storage area;
A reading unit that periodically reads the data group written in the storage area in units of one frame in order from the top address, and sends the data group to a display unit that displays video based on image data;
A generating unit that generates the different start address for each of the one or more frames;
Including semiconductor devices.

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