JP2016015406A - Package for high definition imaging element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a package capable of reducing noise produced in a signal in a high definition imaging element.SOLUTION: A package for a high definition imaging element has a pin arrangement structure where a pin group including an output pin of a high speed digital I/F and a pin group including input pins for a pixel drive signal and an A/D conversion circuit drive signal are spatially arranged with a space therebetween without arranging pins at a central part and four corners of a package board. Accordingly, an imaging element can be reduced in noise and improved in thermal durability.

Description

  The present invention relates to a solid-state image sensor package, and more particularly to a high-definition image sensor package having an output pin of a high-speed digital interface.

  High-definition images such as Super Hi-Vision are being researched and developed as a next-generation ultra-high-sense broadcast system. Super Hi-Vision images have 33 million pixels, 16 times that of Hi-Vision. In addition to improving image quality through higher definition, attempts have also been made to improve the frame rate in order to reproduce the motion of moving images more smoothly. Equipment that can capture images is also being developed.

  With such high-definition images and improved frame rates, the image sensors used to achieve them are becoming more highly integrated and faster, and the amount of input / output data has become extremely large. The number of pins of the image sensor package is increasing. Here, the “pin” means an external input / output terminal of the package, and includes not only a needle-like package pin but also terminals of various shapes such as a ball (hemisphere) shape and a land (pad) shape. Including.

  For example, an imaging device with 33 million pixels and 120 fps has various signals such as high-speed digital output, digital input, and clock as input / output, and includes several hundreds of power supply and reference voltage in total, and the total number of pins is 800 More than a book. In order to arrange a large number of pins in a small area, using a technology such as BGA (Ball Grid Array) or LGA (Land Grid Array), pins are arranged in an array on the back of the package, and printed circuit board ( A method of connecting to a printed circuit board (PCB) is used.

  On the other hand, digital signal processing and analog signal processing often coexist, such as recent high-definition image sensors, which include an A / D (analog / digital) conversion circuit. In particular, high-speed digital I / F (interface) such as LVDS (Low Voltage Differential Signaling) and SLVS (Scalable Low Voltage Signaling) is used for video signal output. If the noise generated by this digital signal wraps around a power supply pin for an analog circuit (pixel or A / D conversion circuit) or a pin for supplying a reference voltage, the video signal is deteriorated.

  In particular, when pins are arranged in an array using BGA or LGA, the analog and digital wirings are spatially close to each other in the package or on the printed circuit board, and the ratio of noise mixing increases.

  In the present invention, an “analog signal” does not mean only an analog signal, but an input / output signal of a circuit used for processing / control of an image signal (analog signal). That is, in addition to the drive signal used in the pixel area or A / D conversion circuit which is an analog circuit, the power supply / reference voltage of the analog circuit can also be included. In particular, the power supply / reference voltage is often noticed from the viewpoint of noise wraparound. As an analog circuit, a correlated double sampling circuit for noise removal may be included. In the present invention, “digital signal” means an input / output related to a high-speed digital I / F. In addition to a digital output signal of a high-speed digital I / F circuit (multi-parallel signal output circuit), a high-speed digital Control signals used in the I / F circuit, power supply / reference voltage can also be included.

  FIG. 3 schematically shows a package structure of a conventional image sensor (image sensor). 3A is a view as seen from the front side (light incident surface side) of the package, and FIG. 3B is a view as seen from the back side (pin arrangement side) of the package.

  Referring to FIG. 3A, a chip 10 of a high-definition image sensor (image sensor) is disposed at the center of a substrate 20 of the package, and the package side PAD (input side) is located near the left and right sides (short sides). (For signal) 21 and 22 are arranged, and package side PAD (for output signal) 23 and 24 are arranged in the vicinity of the upper and lower sides (long sides). Various control signals for the image sensor are input from the package side PAD (for input signals) 21 and 22 to the chip 10.

  The image sensor chip 10 is provided with a pixel region (light receiving region) 11 in the center thereof, which is, for example, an effective pixel of 7680 (H) × 4320 (V), an optical black pixel that serves as a black reference signal, and the like. The total number of pixels is 7808 (H) × 4336 (V). Each pixel can be composed of a photodiode and a CMOS circuit.

  A video signal (analog signal) generated in each pixel is obtained by causing a vertical scanning circuit (not shown) to place half of the pixels (for example, odd columns of pixels) on the upper side in the drawing and the other half of pixels (for example, even columns). Are read out downward in the drawing. A signal processing circuit 12 including an A / D conversion circuit is provided on the upper side and the lower side of the pixel region 11, and converts a video signal (analog signal) of each pixel column into, for example, a 12-bit digital signal. The signal processing circuit 12 can include a correlated double sampling circuit for removing noise.

  Thereafter, the digital signal is processed by a high-speed digital I / F circuit (multiple parallel signal output circuit) 13 arranged outside the signal processing circuit 12 and output as, for example, 96 channels (up and down 48 channels) of LVDS. . The output data rate of the image sensor for Super Hi-Vision is 48 Gbps or more (number of pixels (7808 × 4336) × frame rate (120) × gradation (12)). This is 6 533 Mbps LVDS drivers per block. Is output using 16 blocks (upper and lower 8 blocks each).

  The high-speed digital output signal composed of LVDS is connected to the package-side PAD (for output signal) 23 and 24 and output externally (Non-Patent Document 1).

  FIG. 3B shows an example of a conventional pin arrangement on the back side of the package substrate 20. A heat radiating plate 30 made of a metal having high thermal conductivity is disposed at the center of the substrate, and external input / output pins 31 are disposed around the heat radiating plate 30. Although the pin shape can be selected as appropriate, an example in which ball-shaped pins are arranged in an array by BGA is shown here. The figure conceptually shows the pin arrangement, and the number of pins is not always accurate.

  Here, the pins are arranged vertically and horizontally at regular intervals, and the intervals between adjacent pins are the same. Since it is desirable in terms of layout design to arrange pins of the same type collectively, for example, in FIG. 3B, input pins for pixels and A / D conversion circuits are provided in the left and right regions of the heat sink 30. The high-speed digital I / F pin groups 34 and 35 are arranged along the upper and lower sides.

  At this time, in the portion where the high-speed digital I / F pin groups 34 and 35 are in contact with the input pin groups 32 and 33 for the pixel and A / D conversion circuit, an analog system (for pixel and A / D conversion) is used. The wiring of the digital system (for high-speed digital I / F) is in a spatially close position, and the ratio of noise mixing increases.

  In order to avoid this noise, there is a method of arranging a capacitor in a package (Patent Document 1). That is, a component arrangement region for arranging electronic components connected to bonding pads connected to the terminals of the image sensor chip can be formed on the package, and an electronic component (capacitor) as a noise removing component can be arranged near the image sensor chip. Thus, it is possible to effectively remove the noise component in the output signal that has been caused by the instability of the power supply and the DC bias.

Japanese Patent No. 3786866

Kazuya Kitamura, et al., “Development of 120Hz Super Hi-Vision Image Sensor”, NHK R & D No. 141, (September 2013), issued by Japan Broadcasting Corporation, Broadcasting Technology Research Institute, p. 15-22

  However, although the package structure described in Patent Document 1 has a certain effect in reducing noise, there is a drawback in that one step of arranging a capacitor in the package is increased. In addition, if the power consumption increases due to the higher resolution and higher frame rate of the image sensor, the heat generation associated with it increases, so the size of the package increases as a result of the placement of the capacitor. The mechanical pressure on the pin at the end due to the difference in thermal expansion coefficient is increased. In particular, since BGA and LGA are connected to a printed circuit board by solder reflow, there is a possibility that a crack may occur in the solder portion or the package may be peeled off.

  Accordingly, an object of the present invention made in view of the above problems is to provide a package capable of reducing noise generated in a signal of a high-definition image sensor.

  In order to solve the above problems, a package for a high-definition image pickup device according to the present invention includes a first pin group including a pixel of an image pickup device and an input pin for an A / D conversion circuit, and a high-speed digital I / O of the image pickup device. The second pin group including the F output pins is separated, and the first pin group and the second pin group are arranged with a space therebetween.

  In the package for the high-definition image pickup device, the first pin group is disposed along a pair of opposing sides of the package substrate, and the second pin group is disposed on the other one of the package substrates facing each other. It is desirable to provide a region where pins are not arranged at the center and four corners of the package substrate, which are arranged along a pair of sides.

  In the package for the high-definition image pickup device, it is desirable that a heat sink is provided in at least one of a region where the central portion of the package substrate and the pins at the four corners are not arranged.

  In the package for the high-definition image pickup device, the closest distance between the pins of the first pin group and the pins of the second pin group is the average pin interval in the first pin group and the second pin group. It is desirable to be larger than any of the average pin intervals in the pin group.

  In the high-definition image pickup device package, it is desirable that a pin closest to the first pin group among the pins of the second pin group is a power supply pin.

  According to the high-definition image pickup device package of the present invention, noise generated in the image pickup device signal can be reduced, and the thermal durability of the package can be improved.

It is a figure which shows the structure of the package for image sensors of Example 1 of this invention. It is a figure which shows the structure of the package for image sensors of Example 2 of this invention. It is a figure which shows the structure of the conventional package for image sensors.

  Embodiments of the present invention will be described below.

Example 1
FIG. 1 shows the structure of an image pickup device package according to Embodiment 1 of the present invention. 1A is a diagram viewed from the front side (light incident surface side) of the package, and FIG. 1B is a diagram viewed from the back side (pin arrangement side) of the package. The same members as those in the prior art (FIG. 3) are denoted by the same reference numerals, and the description will be simplified.

  In FIG. 1A, a chip 10 of a high-definition image sensor (image sensor) is arranged at the center of a substrate 20 of a package, and a package side PAD (input signal signal) is located near the left and right sides (short sides). ) 21 and 22 are disposed, and package side PADs (for output signals) 23 and 24 are disposed in the vicinity of the upper and lower sides (long sides). The package side PADs 21 to 24 are pad electrodes formed inside the package, and are electrically connected to the input / output pins 31 provided outside the package through through holes and via holes. The imaging element chip 10 and the package side PADs 21 to 24 are connected by appropriate means such as wire bonding. The package substrate 20 can be made of an appropriate material such as ceramic or glass epoxy plastic in consideration of heat resistance, air tightness, and the like. The imaging element chip 10 may be configured to be covered with a light-transmitting sealing glass and covered with resin sealing or the like other than the light receiving region (not shown).

  Various control signals for the image sensor are input to the chip 10 from the left and right package side PADs (for input signals) 21 and 22. The image sensor chip 10 is provided with a pixel region (light receiving region) 11 in the center thereof, and can be an image sensor corresponding to Super Hi-Vision having, for example, 7680 (H) × 4320 (V) effective pixels. .

  Adjacent to the pixel region 11, signal processing circuits 12 including an A / D conversion circuit are provided on the upper and lower sides in the drawing, respectively, and convert a video signal (analog signal) into, for example, a 12-bit digital signal. Note that the signal processing circuit 12 can include a correlated double sampling circuit, if necessary, and A / D conversion may be performed after noise removal.

  Thereafter, the digitized video signal is converted into a high-speed digital output signal such as LVDS or SLVS by an upper and lower high-speed digital I / F circuit (multi-parallel signal output circuit) 13, and the output signal is a package side PAD (output (For signal) 23 and 24. The configuration of the imaging element chip 10 is an example, and an imaging element chip having an arbitrary configuration can be applied to the structure of the package of the present invention.

  In this embodiment, as shown in FIG. 1A, various control signals are supplied to the image sensor chip 10 from the left and right, and high-speed digital I / F signals are output vertically. It can be changed as appropriate. However, as will be described later, when analog signal wiring and digital signal wiring are placed close to each other, analog signals are easily affected by noise, and therefore it is desirable to arrange the signal wirings as separated as possible.

  FIG. 1B shows the structure of the back surface of the package in the first embodiment. On the back surface of the package, for example, BGAs are arranged on the top and bottom and part of the left and right of the package substrate 20 as shown in the figure, and regions (spaces) in which pins are not arranged are provided at the center and four corners. The package size is sufficient to take this pin arrangement.

  The left and right pin groups 32 and 33 arranged along the short side of the package are used for analog signals, that is, input pins of the signal processing circuit 12 such as the pixel region 11 and the A / D conversion circuit. Analog signals include drive signals for analog circuits, power supplies, and reference voltages.

  On the other hand, the upper and lower pin groups 34 and 35 arranged along the long side of the package are used as input / output pins related to digital signals, that is, high-speed digital I / F. In addition to the digital output signal of the high-speed digital I / F circuit (multiple parallel signal output circuit) 13, the input / output related to the high-speed digital I / F includes control signals and power supplies used in the high-speed digital I / F circuit 13.・ Includes reference voltage.

  In this embodiment, the left and right pin groups 32 and 33 are analog, and the upper and lower pin groups 34 and 35 are digital. However, which pin group is arranged on which side according to the required number of pins. Can be designed as appropriate. The pin arrangement is also an example, and the number of vertical and horizontal pins may be freely adjusted.

  It is desirable that the upper, lower, left and right pin groups 32 to 35 are arranged in an array and are arranged at a fixed pin interval. Further, the pin groups are arranged so as to have a distance larger than the average pin interval of adjacent pins in each pin group. That is, in FIG. 1B, the distance between the pin at the lower right end of the analog pin group 32 and the pin at the upper left end of the high speed digital I / F pin group 35 is as follows. It is desirable that the distance be larger than any of the average pin interval in the pin group 35 and the average pin interval in the pin group 35.

  For example, a heat radiating plate 30 made of a metal having high thermal conductivity may be disposed in the space at the center of the package, and this portion may be used for heat dissipation. Thermal durability can be improved by providing the heat sink 30 larger than before.

  Furthermore, a shield power supply pin or the like may be arranged in an adjacent portion of each pin group. In other words, the pin closest to the analog pin group among the pins of the digital pin group is preferably a power supply pin. As a result, the influence of noise on the analog system is further reduced.

  By adopting such a pin arrangement, it is possible to spatially separate digital and analog in-package wirings and pins, so that mixing of noise into the analog system can be reduced. Furthermore, thermal durability can be improved by not arranging pins at the four corners that are most affected by the difference in thermal expansion coefficient between the printed circuit board and the package.

(Example 2)
FIG. 2 shows the structure of an image sensor package according to the second embodiment of the present invention. FIG. 2 is a view as seen from the back side (pin arrangement side) of the package. The structure on the front side (light incident surface side) of the package is the same as that in FIG.

  The difference between the package structure of Example 2 and Example 1 is that the four corner spaces on the back side of the package are also used for heat dissipation.

  The left and right pin groups 32 and 33 on the back of the package are used as analog signal input pins, the upper and lower pin groups 34 and 35 are used for high-speed digital I / F, and the heat sink 30 is arranged in the central space. This is the same as in the first embodiment.

  In the second embodiment, a heat radiating plate 36 made of a metal having high thermal conductivity is disposed in the four corner spaces between the left and right pin groups 32 and 33 and the upper and lower pin groups 34 and 35.

  With this structure, in addition to the heat radiating plate 30 at the center of the package, the heat radiating plate 36 also radiates heat from the four corners, so that the thermal durability can be improved. In addition, it is not necessary to arrange | position the heat sinks 30 and 36 in all the center parts and four corners like FIG. 2, and it can also install only in the required place of the space provided in the center part and four corners. .

  Although the present invention has been described based on the drawings and examples, it should be noted that those skilled in the art can easily make various modifications and corrections based on the present disclosure. Therefore, it should be noted that these variations and modifications are included in the scope of the present invention. For example, the functions and the like included in each means can be rearranged so as not to be logically contradictory, and a plurality of means and configurations can be combined into one or divided.

10 Image sensor chip 11 Pixel region 12 Signal processing circuit 13 High-speed digital I / F circuit 20 Package substrate 21 Package side PAD (for input signal)
22 Package side PAD (for input signal)
23 Package side PAD (for output signal)
24 Package side PAD (for output signal)
30 heat sink 31 pin 32 analog signal pin group 33 analog signal pin group 34 digital signal pin group 35 digital signal pin group 36 heat sink

Claims (5)

  A first pin group including pixels of the image sensor and an input pin for the A / D conversion circuit is separated from a second pin group including an output pin of the high-speed digital I / F of the image sensor, and the first pin group is separated. A package for a high-definition image pickup device, wherein the pin group and the second pin group are arranged with a space therebetween.   2. The package for a high-definition image pickup device according to claim 1, wherein the first pin group is disposed along a pair of opposing sides of the package substrate, and the second pin group is opposed to the package substrate. A package for a high-definition image pickup device, which is arranged along another pair of sides and provided with regions where pins are not arranged at the center and four corners of the package substrate.   The package for a high-definition image pickup device according to claim 2, wherein a heat sink is provided in at least one of a region where the central portion of the package substrate and the pins at the four corners are not arranged. package.   4. The package for a high-definition image pickup device according to claim 1, wherein the closest distance between the pin of the first pin group and the pin of the second pin group is the first pin. 5. A package for a high-definition image pickup device, which is larger than both of the average pin interval in the group and the average pin interval in the second pin group.   5. The package for a high-definition imaging device according to claim 1, wherein a pin closest to the first pin group among the pins of the second pin group is a power supply pin. 6. A package for a high-definition image sensor characterized by

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