JP2016014975A - Data calculation device, data calculation method, and defect inspection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a time required for performing calculation processing on a small number of pieces of run data as well as a large number of pieces of run data.SOLUTION: There is provided a data calculation device that performs calculation processing on a run data group comprising a plurality of pieces of run data obtained by run-lengthening binary image data, the data calculation device including: a plurality of first thread processing parts that perform calculation processing on single run data; and a processing control part that can execute first parallel calculation processing of causing first thread processing parts different from each other to perform calculations in parallel on each run data forming the run data group.

Description

  The present invention relates to a data calculation technique for performing calculation processing on run data and a defect inspection apparatus using the data calculation technique.

  In the field of manufacturing technology such as semiconductor substrates and printed circuit boards, in order to detect defects contained in products, and to analyze and evaluate the defects, the evaluation object is imaged with a microscope or the like. Extract the containing image. Then, the defect image is accurately obtained by executing a mask process using the mask image on the extracted image. In order to perform this masking process, for example, a logical operation described in Patent Document 1 is executed on the run data of the image.

JP-A-7-203178

  In the invention described in Patent Document 1, the logical product, logical sum, and exclusive logical sum of two images are obtained without converting the run data groups of the two images to be processed into bitmap data. More specifically, two run data groups to be processed are determined to be connected in order from one end of the run, and logical product, logical sum, and exclusive logical sum are determined according to overlapping portions. . Thus, the time required for the arithmetic processing can be shortened by performing the arithmetic processing with the run data without performing the conversion to the bitmap data.

  However, since the processing is performed in order from one end of the run, it takes time to determine the connection as the number of run data increases. Such a problem also occurs in other arithmetic processing using the run data performed by the defect inspection apparatus as it is, for example, labeling related processing (area calculation, circumscribed rectangle calculation, centroid calculation, etc.). This also occurs in arithmetic processing performed using run data as it is in an apparatus other than the defect inspection apparatus, for example, expansion / contraction processing, coordinate inversion processing, rotation processing, run inversion processing, and the like.

  The present invention has been made in view of the above problems, and can reduce the time required to perform arithmetic processing on run data as well as when the number of run data is small. It is an object of the present invention to provide a data inspection technique and a defect inspection apparatus capable of shortening the time required for defect inspection using the data calculation technique.

  A first aspect of the present invention is a data arithmetic device that performs arithmetic processing on a run data group composed of a plurality of run data obtained by converting binary image data into run lengths, and includes a single run data. A plurality of first thread processing units that perform arithmetic processing on the processing, and a processing control unit capable of executing a first parallel arithmetic processing that causes each run data constituting the run data group to perform parallel calculations in different first thread processing units It is characterized by comprising.

  According to a second aspect of the present invention, there is provided a data calculation method for performing arithmetic processing on a plurality of run data obtained by converting binary image data to run length, wherein the first thread performs arithmetic processing for each run data. It is characterized by comprising a first parallel operation step for performing processing in parallel.

  Furthermore, the third aspect of the present invention is a defect inspection apparatus, an image acquisition unit that acquires an inspection target image, an image extraction unit that inspects the inspection target image and extracts an extracted image including a defective part, Extraction is performed by performing a logical operation on an extracted run data group having a plurality of run data obtained by converting the extracted image to run length and a mask run data group having a plurality of run data obtained by converting the mask image to run length. A data operation unit that obtains defect image data by masking a part other than the defect part in the image with a mask image, and the data operation unit includes a plurality of first threads that perform a logical operation on a single run data. Process control capable of executing a first parallel operation process in which a processor and each run data constituting the extracted run data group are operated in parallel by different first thread processing units. It is characterized by having and.

  As described above, in the present invention, the arithmetic processing for the run data group composed of a plurality of run data obtained by converting the binary image data into run lengths is executed as follows. That is, the first thread processing for performing arithmetic processing (logical product processing, logical sum processing, labeling processing, etc.) for each run data is executed in parallel. For this reason, regardless of the number of elements of the run data constituting the run data group, it is possible to stably reduce the time required for performing arithmetic processing on the run data group.

It is a figure showing a 1st embodiment of a data operation device concerning the present invention. It is a flowchart which shows the data calculation operation | movement by the data calculation apparatus of FIG. It is a figure which shows typically the data calculation operation | movement by the data calculation apparatus of FIG. It is a graph which shows the change of the time required for the arithmetic processing with respect to the number of run elements in the data arithmetic device of FIG. It is a figure which shows typically the calculating operation in a comparative example. It is a graph which shows the change of the time required for the arithmetic processing with respect to the number of run elements in a comparative example. It is a figure which shows 2nd Embodiment of the data arithmetic unit concerning this invention. It is a flowchart which shows the data calculation operation | movement by the data calculation apparatus of FIG. It is a flowchart which shows the data calculation operation | movement by the data calculation apparatus of FIG. It is a figure which shows an example of the defect inspection apparatus equipped with the data arithmetic unit of FIG.1 and FIG.7. It is a block diagram which shows schematic structure of the image process part of the defect inspection apparatus shown in FIG.

A. First Embodiment FIG. 1 is a diagram showing a first embodiment of a data operation apparatus according to the present invention. FIG. 2 is a flowchart showing a data operation performed by the data operation device of FIG. Further, FIG. 3 is a diagram schematically showing a data operation by the data operation device of FIG. The data operation device 100 generates a run data group composed of a plurality of run data by converting binary image data supplied from an external device into a run length, and performs logical processing on a run data group composed of a plurality of run data. This is an apparatus that performs arithmetic processing such as product, logical sum, exclusive logical sum, labeling related processing (area calculation, circumscribed rectangle calculation, centroid calculation, etc.), expansion / contraction processing, coordinate inversion processing, rotation processing, run inversion processing, and the like.

  In the present embodiment, the data arithmetic device 100 is configured by a GPU (Graphics Processing Unit) having a plurality of processor cores 110, a storage unit 120, a run generation unit 130, a parallel processing control unit 140, and a data initial setting unit 150. . When the binary image data is given from the outside of the apparatus, the data arithmetic apparatus 100 stores the binary image data in the storage unit 120. In addition, the run generation unit 130 appropriately reads the binary image data stored in the storage unit 120, generates a run data group composed of a plurality of run data by performing run length, and then stores the run data group. Write to the storage unit 120. Note that many well-known techniques have been proposed for the run-length processing, and the general run-length processing is used as it is in this embodiment. Each run data obtained by the run length processing includes a column index (start coordinate) indicating the start pixel position of the run in binary image data, and a column index (end) indicating the end pixel position of the run in binary image data. Coordinate), and the row index of the run in the binary image data.

  Here, for example, as shown in the uppermost column of FIG. 3, binary image data Da and Db of pixels of p rows × q columns are given, and when the logical product and the logical sum of these are calculated, the data arithmetic device 100 performs these operations. Two binary image data Da and Db are temporarily stored in the storage unit 120, and each binary image data Da and Db is run-lengthed to generate two run data groups RDa and RDb. Remember. In order to facilitate understanding of the apparatus configuration and operation, the run data group RDa obtained by run-lengthing the binary image data Da is referred to as a “first run data group”, while the binary image data Db is run-length. The run data group RDb obtained by the conversion is referred to as a “second run data group”.

Each processor core 110 functions as a first thread processing unit 111 that performs arithmetic processing on a single run data. In this embodiment, each first thread processing unit 111 has an arithmetic function for obtaining a logical product and a logical sum with the second run data group RDb for each run data constituting the first run data group RDa. Further, the maximum number of run data in each row obtained by run lengthing the binary image data Da and Db shown in the uppermost column in FIG. 3 is (q / 2) when the value q is an even number. (q / 2) +1) when q is an odd number. Therefore, the maximum value M of the number of elements of run data obtained by the run length process is
When the value q is an even number, (q / 2) × p
When the value q is an odd number, ((q / 2) +1) × p,
It is.

  Therefore, in this embodiment, a GPU having M or more processor cores 110 is used as the data arithmetic device 100, and the arithmetic processing is performed in parallel for all run data constituting the first run data group RDa as described later. Can be done. Then, the calculation result (run data) in each processor core 110 is written in the storage unit 120. In FIG. 1, the first processor core (first processor core) 110 to the Mth processor core (Mth processor core) 110 are shown, and the other processor cores 110 are not shown. doing. Of course, it goes without saying that the number of processor cores 110 included in the data arithmetic device 100 may be set to exactly M.

  In addition, in order to operate a plurality of processor cores 110 in parallel, a parallel processing control unit 140 is provided in the present embodiment. The parallel processing control unit 140 has a function of executing thread processing executed in each processor core 110 in parallel while controlling the thread processing. Further, the data initial setting unit 150 clears the binary image data stored in the storage unit 120 and various types of information (start coordinate, end coordinate, and row index) included in each run data to zero. In the present embodiment, the binary image data Da and Db are received, and the binary image data Da and Db are run-lengthed to generate the first run data group RDa and the second run data group RDb. The run length process may be omitted by receiving at least one of the run data groups from the outside of the apparatus and storing it in the storage unit 120.

Next, a data operation performed by the data operation device 100 configured as described above will be described. When two binary image data Da and Db to be subjected to a logical operation are designated from the outside of the apparatus, the data arithmetic apparatus 100 acquires the binary image data Da and Db from the outside of the apparatus and stores the storage unit 120. (Step S1). Then, the run generation unit 130 reads the binary image data Da from the storage unit 120, performs run length processing on the binary image data Da, and acquires run data ra [1] to ra [m]. A first run data group RDa (see FIG. 3) including these run data ra [1] to ra [m] is stored in the storage unit 120 (step S2). As described above, the maximum number of elements of the run data ra when the binary image data of p rows × q columns is run-length is the value M, and the relationship between the value M and the value m is m ≦ M
It becomes.

  In addition, the run generation unit 130 reads the binary image data Db from the storage unit 120, performs run length processing on the binary image data Db, and acquires run data rb [1] to rb [n]. A second run data group RDb (see FIG. 3) including these run data rb [1] to rb [n] is stored in the storage unit 120 (step S3). The order of these steps S2 and S3 is not limited to the order in the present embodiment, and is arbitrary.

  When the acquisition of the two run data groups RDa and RDb to be calculated is completed, arithmetic processing by the processor core 110 (in this embodiment, logical product processing and logical sum processing) is performed for each run data ra constituting the first run data group RDa. ) Are executed in parallel (steps S4-1 to S4-m). More specifically, for the first run data ra [1], the first thread processing unit 111 of the first processor core 110 executes run data rb [1] to rb [that constitute the second run data group RDb. n] is performed (step S4-1). The same processing as that of the first thread is also executed by the first thread processing unit 111 of the second to m-th processor cores 110 (steps S4-2 to S4-m). When the (m + 1) th and subsequent run data ra do not exist, the first thread processing unit 111 of the (m + 1) th to Mth processor cores 110 does not perform arithmetic processing, and the first to mth processor cores 110 It waits until the parallel operation processing by the first thread processing unit 111 is completed.

  When the parallel operation processing (steps S4-1 to S4-m) is completed in this way, the data operation device 100 writes the operation result (run data) in the storage unit 120 and ends the series of processing (step S5).

  As described above, according to the first embodiment of the present invention, as shown in FIG. 2 and FIG. 3, the arithmetic processing by the processor core 110 is performed in parallel for each run data ra constituting the first run data group RDa. Since it is executed, the time required for the arithmetic processing for the run data group can be shortened. In particular, in this embodiment, since the processor core 110 having the maximum number M of the number of elements of run data obtained by converting the binary image data Da and Db into run length is provided in advance, the first run data group RDa The first thread processing for each of the run data ra [1] to ra [m] is performed in parallel even if the number m of the run data ra to be configured is relatively small, and even when the number m is equal to the maximum value M. For example, as shown in FIG. 4, the processing time required for the arithmetic processing of binary image data can be stably reduced.

FIG. 4 is a graph showing a change in time required for the arithmetic processing with respect to the number of run elements in the data arithmetic device of FIG. Here, two 256 gradation images (file size 32 MB) that are different from each other are created by random number generation, and the threshold value for binarizing the image for each image is changed in multiple stages to thereby obtain run data. Three types of binary image data having different numbers of elements were created. More specifically, binary image data having about 8 million (8M) points, about 5.6 million (5.6M) points, and about 50,000 (0.5M) points of run data,
Binary image data Da (8), Db (8),
Binary image data Da (5.6), Db (5.6),
Binary image data Da (0.5), Db (0.5),
It was created. For each number of elements of run data, the data arithmetic device 100 according to the first embodiment calculates the logical product and logical sum of the binary image data Da and Db, and measures the processing time required for the arithmetic processing. FIG. 4 summarizes the results. As apparent from FIG. 4, the logical product and logical sum of the binary image data Da and Db can be calculated in a short time almost independently of the number of elements of the run data. The effect of shortening the processing time in the first embodiment will be described with reference to the following comparative examples (FIGS. 5 and 6).

  FIG. 5 is a diagram schematically showing a calculation operation in the comparative example. FIG. 6 is a graph showing a change in time required for the arithmetic processing with respect to the number of run elements in the comparative example. The comparative example is greatly different from the first embodiment in the unit for performing the parallel operation. In this comparative example, the run data constituting the run data group is divided into row units or column units and assembled into a plurality of data areas. Divide and perform arithmetic processing on each data area. More specifically, the run data ra [1] to ra [m] constituting the run data group RDa are divided into rows and divided into p data areas, and the second run data group RDb is divided for each data area. Thread processing for obtaining the logical product and logical sum of these is performed in parallel. For example, when performing parallel operation processing of the run data groups RDa and RDb shown in FIG. 3, the run data group ra (ra [1], ra [2]) and the run data group rb (rb [1], rb [2]) and a logical product and a logical sum are calculated (first thread). For the second to p-th rows, the same arithmetic processing as that for the first row is executed in parallel with the first thread (second thread to p-th thread). Note that the threads on and after the (p + 1) -th line are on standby until the parallel calculation processing of the first to p-th threads is completed.

  As described above, in the comparative example, the run data is calculated in parallel, so that the time required for the calculation can be shortened as compared with the invention described in Patent Document 1. However, since the run data ra included in each thread is one or plural, the processing time becomes longer as the number of elements of the run data ra constituting the run data group RDa increases. Here, in the comparative example, as in the first embodiment, the logical product and the logical sum of the binary image data Da and Db are calculated, and the processing time required for the arithmetic processing is measured, as shown in FIG. Results were obtained. In addition, the dotted line in the figure has shown the processing time measured in 1st Embodiment.

  As is apparent from the figure, the first embodiment has a processing performance superior to that of the comparative example. That is, according to the first embodiment, it is possible to stably perform high-speed computation without being affected by the number of elements of run data, compared to the comparative example (performing thread processing in units of rows). Yes.

B. Second Embodiment By the way, FIG. 6 shows a reverse phenomenon of processing time. That is, when the number of run data elements is extremely reduced and the parallelism of the thread processing performed in the first embodiment is reduced, the processing time in the comparative example is shorter than the processing time in the first embodiment. . This means that when the index value indicating the parallelism of the thread processing exceeds the index value (hereinafter referred to as “boundary value”) at the time of occurrence of the reverse phenomenon, the parallel arithmetic processing performed in the first embodiment is performed. On the other hand, if the index value is less than or equal to the boundary value, it means that it is advantageous to perform the parallel operation processing performed in the comparative example. Therefore, in the second embodiment of the present invention, two types of parallel arithmetic processing can be executed, and high-speed arithmetic can be performed by properly using parallel arithmetic processing depending on whether or not the index value exceeds the boundary value. It expands the possible range. Hereinafter, a second embodiment of the present invention will be described with reference to FIGS.

  FIG. 7 is a diagram showing a second embodiment of the data arithmetic device according to the present invention. The second embodiment is greatly different from the first embodiment in the following three points. The first point is that each processor core 110 functions as a second thread processing unit 112 that performs arithmetic processing in units of rows in addition to the first thread processing unit 111 as in the comparative example. The second point is the occurrence frequency of calculating the occurrence frequency of run data obtained from the image size of the binary image data and the number of elements of run data generated by run lengthing the binary image data as the index value. The operation unit 160 is newly provided. Furthermore, the third point is that the parallel calculation processing is switched according to the occurrence frequency obtained by the occurrence frequency calculation unit 160. Since other configurations and operations are basically the same as those of the first embodiment, the same components are denoted by the same reference numerals and description thereof is omitted.

  8 and 9 are flow charts showing the data calculation operation by the data calculation device of FIG. Also in the second embodiment, when two binary image data Da and Db to be calculated are designated from the outside of the apparatus, the data calculation apparatus 100 stores the binary image data Da and Db in the storage unit 120. (Step S1), acquisition and storage of a first run data group RDa consisting of run data ra [1] to ra [m] (Step S2), second run data consisting of run data rb [1] to rb [n] The group RDb is acquired and stored (step S3).

  In the next step S6, the occurrence frequency calculation unit 160 of the data calculation device 100 divides the value m corresponding to the number of elements of the run data ra [1] to ra [m] by the image size of the binary image data Da. The frequency of occurrence of run data is calculated. For example, when the binary image data Da is data indicating a diagram image, the frequency of occurrence tends to be low, whereas when it is data indicating a photographic image, the frequency of occurrence tends to be high.

  After determining the occurrence frequency of the run data as the index value in this way, the data arithmetic device 100 determines whether or not the occurrence frequency exceeds the boundary value (step S7). Similar to the embodiment, arithmetic processing is performed in parallel for each run data ra (steps S4-1 to S4-m).

  On the other hand, when it is determined that the occurrence frequency is equal to or lower than the boundary value, the data arithmetic device 100 performs parallel arithmetic processing by the second thread processing unit 112 (steps S8-1 to S8-p). That is, the second thread processing unit 112 of the first processor core 110 has an arithmetic function for obtaining a logical product and a logical sum of the first run data group RDa and the second run data group RDb for the first row. Further, the second thread processing unit 112 of the second, third,..., M processor cores 110 thereafter is also similar to the second thread processing unit 112 of the first processor core 110. An arithmetic function for obtaining a logical product and a logical sum for the p-th row is provided. In steps S8-1 to S8-p, arithmetic processing (logical product processing and logical sum processing in the present embodiment) by the first to p-th processor cores 110 is executed in parallel in units of rows. Since the run data ra and rb do not exist after the (p + 1) th row, the second thread processing unit 112 of the (p + 1) th to Mth processor cores 110 does not perform arithmetic processing, and the first to pth processors. It waits until the parallel arithmetic processing by the second thread processing unit 112 of the core 110 is completed.

  When one of the two types of parallel arithmetic processing is completed in this way, the data arithmetic device 100 writes the arithmetic result (run data) in the storage unit 120 and ends the series of processing (step S5).

  As described above, in the second embodiment of the present invention, two types of parallel arithmetic processing are prepared in advance, and the occurrence frequency of run data is obtained as an index value indicating the parallelism of thread processing (step S6). Depending on whether or not exceeds the boundary value, the parallel arithmetic processing selection is switched. As described above, the parallel calculation processing corresponding to the frequency of generation of run data indicating the parallelism of the calculation by the first thread processing unit 111 is performed. In either case, high-speed calculation is possible, and the range in which high-speed calculation is possible is the first. More than the embodiment, high versatility can be obtained.

C. Defect Inspection Device FIG. 10 is a diagram illustrating an example of a defect inspection device equipped with a data operation device according to the second embodiment. The defect inspection apparatus 1 inspects for defects such as pinholes and foreign matters appearing on the appearance of a semiconductor substrate (hereinafter referred to as “substrate”) S to be inspected. The defect inspection apparatus 1 includes an imaging device 2 that images an inspection target region on the substrate S and a control device 3 that performs defect inspection based on image data from the imaging device 2.

  In the inspection system equipped with the defect inspection apparatus 1, when a defect is found in the substrate S in the substrate detection apparatus 200 provided in the production line of the substrate S separately from the defect inspection apparatus 1, the position coordinates of the defect are The defect inspection apparatus 1 is given. The substrate detection apparatus 200 incorporated in the production line inspects the entire substrate S by a predetermined processing algorithm, and acquires and outputs the position coordinates if there is a region on the substrate surface that satisfies the requirement as a defect. Therefore, the imaging unit included in the substrate detection apparatus 200 has a relatively low resolution, and the processing algorithm is fixed.

  On the other hand, the defect inspection apparatus 1 is connected to the substrate detection apparatus 200 via an interface (not shown), and an image pickup apparatus 2 having higher resolution captures an area in which position coordinates are reported as a defect from the substrate detection apparatus 200. At the same time, the control device 3 examines the image to determine in detail the presence or absence of the defect and the type thereof, and displays the image of the defective portion on the display unit.

  The imaging device 2 moves the stage 22 relative to the imaging unit 21 that acquires image data by imaging the inspection target region on the substrate S, the stage 22 that holds the substrate S, and the imaging unit 21. A stage driving unit 23 is provided. In addition, the imaging unit 21 includes an illumination unit 211 that emits illumination light, an optical system 212 that guides illumination light to the substrate S and receives light from the substrate S, and an image of the substrate S formed by the optical system 212. An imaging device 213 for converting the signal into an electrical signal. The stage drive unit 23 includes a ball screw, a guide rail, and a motor. The device control unit 4 provided in the control device 3 controls the stage drive unit 23 and the imaging unit 21, so that the inspection target region on the substrate S is changed. Imaged.

  The control device 3 has a device control unit 4. When the device control unit 4 executes a control program read in advance, each unit of the control device shown in FIG. 10 is operated as follows. The control device 3 includes an image acquisition unit 5 and an image processing unit 6 in addition to the device control unit 4 described above. The image acquisition unit 5 converts the electrical signal output from the imaging unit 21 into data, and acquires image data corresponding to the captured image. The image processing unit 6 performs appropriate image processing on the image data acquired by the image acquisition unit 5 to detect a defect included in the image and create an image of a defective portion (hereinafter referred to as “defect image”). Note that the image processing unit 6 includes a data calculation unit having the same configuration as that of the data calculation device 100 shown in FIG. 7, and for an image extracted from an image captured by the imaging device 2 (inspection target image). It is possible to derive information on a defective portion by performing mask processing. The configuration and operation of the image processing unit 6, particularly the data calculation unit will be described in detail later.

  Further, the control device 3 displays a storage unit 7 for storing various data, an input receiving unit 8 such as a keyboard and a mouse for receiving an operation input from the user, and a visual information for the user such as an operation procedure and a processing result. Part 9 and the like. Although not shown in the figure, the apparatus has a reader for reading information from a computer-readable recording medium such as an optical disk, a magnetic disk, a magneto-optical disk, etc. A communication unit that transmits and receives signals is appropriately connected through an interface (I / F) or the like.

  FIG. 11 is a block diagram showing a schematic configuration of the image processing unit of the defect inspection apparatus shown in FIG. The image processing unit 6 includes a filtering unit 61, a difference extraction unit 62, a binarization processing unit 63, and a data calculation unit 64. A captured image is sent from the image acquisition unit 5 to the filtering unit 61, and a reference image is sent from the storage unit 7. Of these two images, the picked-up image is an image of the substrate S picked up by the image pickup device 2 and corresponds to an inspection target image to be subjected to defect detection inspection. Further, the reference image is an image corresponding to an ideal substrate having no defect, and in this embodiment, as will be described below, defect detection is performed from the inspection target image by comparing the inspection target image with the reference image. . These defect images and reference images are stored in the storage unit 7 and referred to as necessary. However, image data stored in an external storage medium may be read as necessary.

  The filtering unit 61 performs a filtering process for removing minor image differences unrelated to image noise and defects for each of the inspection target image and the reference image, and sends each image to the difference extraction unit 62. The difference extraction unit 62 extracts areas having different image contents by obtaining a difference between the inspection target image and the reference image after the filtering process, and uses the difference image as an “extraction image” of the present invention. Send to 63. Then, the binarization processing unit 63 binarizes the difference image with an appropriate threshold value to generate binary image data Da, and sends it to the data calculation unit 64. As described above, the binary image data Db of the mask image is appropriately sent from the storage unit 7 to the data calculation unit 64 in addition to the binary image data Da of the difference image. Then, similarly to the second embodiment (FIGS. 8 and 9), the data calculation unit 64 converts the binary image data Da into run lengths and sets the first run data group RDa as the “extracted run data group” of the present invention. At the same time, the binary image data Db is run-lengthed to obtain the second run data group RDb as the “mask run data group” of the present invention. Then, the data calculation unit 64 calculates the logical product of both run data groups RDa and RDb. Thereby, parts other than the defective part are removed from the extracted image, and run data indicating good defect image data is obtained.

  As described above, in the defect inspection apparatus equipped with the second embodiment of the data operation apparatus, the operation for obtaining the defect run data can be performed at high speed, and the time required for defect inspection can be shortened. In addition, you may comprise the data calculating part 64 by having the same structure as the data calculating device concerning 1st Embodiment instead of 2nd Embodiment.

  Thus, the parallel arithmetic processing by the first thread processing unit 111 corresponds to an example of “first parallel arithmetic processing” and “first parallel arithmetic process” of the present invention, and the parallel arithmetic processing by the second thread processing unit 112 is performed. This corresponds to an example of the “second parallel calculation process” and the “second parallel calculation step” of the present invention. The parallel processing control unit 140 corresponds to an example of the “processing control unit” in the present invention. Further, the difference extraction unit 62 corresponds to an example of the “image extraction unit” of the present invention.

D. Others The present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit of the present invention. For example, in the above embodiment, each processor core 110 is configured to execute one thread, but each processor core 110 may be configured to execute a plurality of threads. In the above embodiment, a GPU having a plurality of processor cores 110 is used to perform arithmetic processing (logical product processing and logical sum processing). However, a plurality of CPUs are provided in place of the GPU, One or more threads may be configured to execute.

  In the above embodiment, the binary image data Da and Db sent from the external device are run-lengthed by the run generation unit 130 in the device to generate a plurality of run data. May be acquired in the form of a run data group that has already been run-length instead of binary image data.

  In the above-described embodiment, logical product processing and logical sum processing are performed as arithmetic processing. However, the present invention is applied to a data arithmetic device or method that performs only one of these processing or performs arithmetic processing other than these. Can be applied. Examples of “calculation processing other than these” include exclusive OR, labeling related processing (area calculation, circumscribed rectangle calculation, center of gravity calculation, etc.), expansion / contraction processing, coordinate inversion processing, rotation processing, run inversion processing, and the like. included.

  In the second embodiment, the area divided in units of rows is referred to as a “data area”. However, the “data area” is not limited to this. For example, the area divided in units of columns is referred to as a “data area”. May be used.

  Furthermore, in the above-described embodiment, the data calculation technique for logically calculating a plurality of run data groups is applied to the defect inspection apparatus, but the application target is not limited to this for the data calculation method and apparatus according to the present invention. However, the present invention can be applied to all devices using the above data calculation technique.

  The present invention can be suitably applied to a data calculation technique for performing calculation processing on run data.

1 ... Defect inspection device,
5 ... Image acquisition unit,
6 ... Image processing unit,
62 ... difference extraction unit (image extraction unit),
64 ... data operation unit (data operation device),
100: Data processing unit 110: Processor core,
111 ... 1st thread processing part,
112 ... the second thread processing unit,
130 ... run generation unit,
140 ... parallel processing control unit,
160... Occurrence frequency calculation unit,
Da, Db ... binary image data,
ra, rb ... run data,
RDa: first run data group,
RDb: second run data group,
S ... Board

Claims (9)

A data arithmetic device that performs arithmetic processing on a run data group composed of a plurality of run data obtained by converting the binary image data into run lengths,
A plurality of first thread processing units for performing the arithmetic processing on a single run data;
A data operation device comprising: a process control unit capable of executing a first parallel operation process for causing each run data constituting the run data group to perform an operation in parallel by the first thread processing units different from each other. The data operation device according to claim 1,
A plurality of second thread processing units for performing the arithmetic processing on each of the data areas composed by dividing the plurality of run data;
The processing control unit is capable of executing a second parallel calculation process that causes each set to be operated in parallel by the second thread processing unit different from each other, and relates to the parallelism of the calculation in the first parallel calculation process. A data arithmetic device that executes one of the first parallel arithmetic processing and the second parallel arithmetic processing according to an index value. The data operation device according to claim 2,
The data calculation device, wherein the index value is a frequency of occurrence of run data generated by converting the binary image data to run length. The data operation device according to claim 3,
A data operation device further comprising an occurrence frequency calculation unit that calculates the occurrence frequency based on the number of elements of the run data constituting the run data group and the image size of the binary image data. A data arithmetic device according to any one of claims 1 to 4,
The binary image data is image data of pixels of p rows × q columns,
The number of the first thread processing units is M. However, when q is an even number, M = (q / 2) × p,
When q is an odd number, M = ((q / 2) +1) × p
A data arithmetic device. The data operation device according to claim 5,
The data operation device, wherein the plurality of run data is divided into row units or column units and grouped into the plurality of data areas. A data calculation method for performing calculation processing on a plurality of run data obtained by converting binary image data to run length,
A data calculation method comprising: a first parallel calculation step of performing in parallel a first thread process for performing the calculation process for each run data. The data calculation method according to claim 7,
A second parallel operation step of dividing the plurality of run data into a plurality of groups and performing a second thread process for performing the operation process for each group in parallel;
A data operation method for executing one of the first parallel operation step and the second parallel operation step in accordance with an index value related to parallelism of operations in the first parallel operation step. An image acquisition unit for acquiring an image to be inspected;
An image extraction unit that inspects the inspection target image and extracts an extracted image including a defective portion;
By performing a logical operation between an extracted run data group having a plurality of run data obtained by run-lengthing the extracted image and a mask run data group having a plurality of run data obtained by run-lengthing the mask image, A data calculation unit that obtains defect image data by masking a portion other than the defective portion of the extracted image with the mask image;
The data calculation unit is
A plurality of first thread processing units for performing the logical operation on a single run data;
A defect inspection apparatus, comprising: a process control unit capable of executing a first parallel operation process in which each run data constituting the extracted run data group is operated in parallel by the first thread processing units different from each other.

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