JP2016001389A - Semiconductor device and clock transmission method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing power consumption by clock distribution.SOLUTION: Transition number detection unit detects the number of transitions of output clocks from a clock path A and a clock path B for respectively controlling the amplitudes of clocks transmitted by a bias voltage. A determination unit determines whether the detected transition number is greater than a set value or smaller the than the set value. A phase adjustment unit compares a phase of the output clock from the clock path A to a phase of the output clock from the clock path B, and outputs a phase adjustment instruction according to a phase difference. A bias generation unit generates a bias voltage according to the outputs of the determination unit and the phase adjustment unit and supplies it to a transmission path. Accordingly, clock transmission with a minimum amplitude is allowed and clock distribution with a small skew is realised.

Description

  The present invention relates to a semiconductor device and a clock transmission method.

  In a clock distribution of a circuit such as a high-speed IO (input / output) macro that handles a high-speed clock in a semiconductor device, it is required to reduce a phase difference (skew) between signals. In a high-speed IO receiver, the power consumed by clock distribution is particularly large. Some applications require multi-rate support that can operate over a wide frequency range.

  2. Description of the Related Art Conventionally, there is a semiconductor device that distributes a small skew clock with a small phase difference by mounting a circuit (De-skew circuit) that corrects a skew between signals. For example, a phase comparison circuit compares the phases of clocks transmitted through different paths in the clock tree, and controls the delay time of the clock driver according to the output of the phase comparison circuit to align the clock output phases. It has been proposed (see, for example, Patent Document 1).

  The operating environment etc. fluctuates by supplying a clock to the flip-flop that receives the data output from the logic circuit block that becomes the critical path via a delay buffer that uses a transistor formed by the same process as the logic circuit block. However, a technique for receiving data from the logic circuit block is disclosed (see Patent Document 2). There is disclosed a technique for adjusting a delay time by providing a feedback circuit that feeds back an output to an inverter and controlling a feedback amount (see Patent Document 3). Disclosed is a technique for compensating for a relative delay difference of a signal depending on a power supply voltage difference in a region generated in a plurality of regions using mutually independent power supplies in the same chip according to information indicating the power supply voltage difference. (See Patent Document 4).

JP 2005-44854 A JP 2004-38276 A JP 2008-67365 A JP 2009-301493 A

  Clock distribution in a semiconductor device generally uses a clock tree. However, in order to realize clock distribution with a small skew, the number of clock drivers increases as the clock speed increases, and large power is consumed. An object of the present invention is to provide a semiconductor device capable of reducing power consumed by clock distribution.

  In one embodiment of the semiconductor device, an output clock from a first transmission path that controls the amplitude of a clock that is transmitted by a first bias voltage, and a second transmission that controls the amplitude of a clock that is transmitted by a second bias voltage. A phase adjustment unit that compares the phase of the output clock from the path and outputs a phase adjustment instruction according to the phase difference, a transition number detection unit that detects the number of transitions of the output clock from the transmission path, and a transition number detection unit It is determined whether the number of transitions detected by is greater than the set value or smaller than the set value, a determination unit that outputs a determination result, and a bias voltage according to the output of the determination unit and the phase adjustment unit, A bias generation unit that supplies the transmission line.

  The disclosed semiconductor device can perform clock transmission with the minimum amplitude, realize clock distribution with a small skew, and reduce power consumed by clock distribution.

It is a figure which shows the structural example of the semiconductor device in embodiment of this invention. It is a figure which shows the structural example of the inverter which concerns on the clock transmission in this embodiment. It is a figure which shows the example of the current cell of the bias production | generation part in this embodiment. It is a figure which shows the structural example of the semiconductor device in this embodiment. 6 is a flowchart illustrating an operation example of the semiconductor device according to the present embodiment. It is a figure which shows the example of application of the semiconductor device in this embodiment. FIG. 7 is a diagram illustrating an example of a dummy circuit illustrated in FIG. 6.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram illustrating a configuration example of a semiconductor device according to an embodiment of the present invention. FIG. 1 shows a configuration related to clock transmission in the semiconductor device according to the present embodiment, and other portions are omitted.

  In FIG. 1, a clock transmission path (clock path A) in which inverters 11A as a plurality of clock drivers are connected in series transmits an input clock INA and outputs it as an output clock OUTA. A clock transmission path (clock path B) in which inverters 11B as a plurality of clock drivers are connected in series transmits an input clock INB and outputs it as an output clock OUTB. The clock INA and the clock INB are generated and distributed from one original clock. For example, one frequency of the clock INA and the clock INB is the same as or an integral multiple of the other frequency.

  Each of the inverters 11A and 11B includes two P-channel transistors 21 and 22 and two N-channel transistors 23 and 24, for example, as shown in FIG. Each of the inverters 11A and 11B has a driving capability (delay time) controlled by bias voltages BIASP and BIASN supplied from the corresponding bias generators 14A and 14B.

  The transistor 21 has a source connected to the node of the power supply voltage, a drain connected to the source of the transistor 22, and a bias voltage BIASP supplied to the gate. The transistor 22 has a drain connected to the output node OUT of the inverter 11 and a gate connected to the input node IN of the inverter 11. The transistor 23 has a source connected to the drain of the transistor 24, a drain connected to the output node OUT of the inverter 11, and a gate connected to the input node IN of the inverter 11. The source of the transistor 24 is connected to the node of the reference potential, and the bias voltage BIASN is supplied to the gate.

  That is, the inverter 11 inverts the signal input to the input node IN by the inverter composed of the transistors 22 and 23 and outputs the inverted signal from the output node OUT. In addition, the bias voltages BIASP and BIASN supplied to the respective gates of the transistors 21 and 24 control the current supplied from the power source or the like to the inverter formed of the transistors 22 and 23, and the drive capability ( Delay time) is controlled.

  Returning to FIG. 1, the transition number detection unit 12A has “0” (for example, low level (“L”)) and “1” (for example, high level) in the output clock OUTA from the clock path A in the specified detection period. The number of transitions between levels ("H") is detected. The determination unit 13A compares the number of transitions detected by the transition number detection unit 12A with the set value to determine whether the detected number of transitions is larger than the set value or smaller than the set value. The result is output to the bias generation unit 14A.

  Similarly, the transition number detection unit 12B detects the number of transitions between “0” and “1” in the output clock OUTB from the clock path B in the specified detection period. The determination unit 13B compares the number of transitions detected by the transition number detection unit 12B with the set value to determine whether the detected number of transitions is larger than the set value or smaller than the set value. The result is output to the bias generation unit 14B.

  The phase adjustment unit 15 performs determination and control related to phase adjustment for minimizing the skew between the output clock OUTA from the clock path A and the output clock OUTB from the clock path B. The phase adjustment unit 15 compares the phases of the output clock OUTA and the output clock OUTB, and determines the amplitude according to the phase difference with respect to one of the bias generation units 14A and 14B corresponding to the clock path of the clock whose phase is delayed. Outputs instructions for adjustment.

  The bias generation unit 14A generates bias voltages BIASP and BIASN corresponding to the outputs of the determination unit 13A and the phase adjustment unit 15, and supplies the bias voltages BIASP and BIASN to the inverter 11A of the clock path A. For example, when the determination unit 13A determines that the detected number of transitions is greater than the set value, the bias generation unit 14A reduces the clock amplitude, that is, the drive capability of the inverter 11A decreases. The bias voltages BIASP and BIASN are changed (to decrease the bias voltage BIASP and increase the bias voltage BIASN). On the other hand, when the determination unit 13A determines that the detected number of transitions is smaller than the set value, the bias generation unit 14A increases the clock amplitude, that is, the drive capability of the inverter 11A increases. The bias voltages BIASP and BIASN are changed (to increase the bias voltage BIASP and decrease the bias voltage BIASN). When the bias generation unit 14A receives an instruction to adjust the amplitude from the phase adjustment unit 15, the bias generation unit 14A increases the clock amplitude according to the phase difference, that is, the drive capability of the inverter 11A increases. The bias voltages BIASP and BIASN are changed (to shorten the delay time).

  Similarly, the bias generation unit 14B generates bias voltages BIASP and BIASN corresponding to the outputs of the determination unit 13B and the phase adjustment unit 15 and supplies them to the inverter 11B of the clock path B. For example, when the determination unit 13B determines that the detected number of transitions is greater than the set value, the bias generation unit 14B decreases the clock amplitude, that is, the drive capability of the inverter 11B decreases. The bias voltages BIASP and BIASN are changed (to increase the delay time). On the other hand, when the determination unit 13B determines that the detected number of transitions is smaller than the set value, the bias generation unit 14B increases the clock amplitude, that is, the drive capability of the inverter 11B increases. The bias voltages BIASP and BIASN are changed (to shorten the delay time). When the bias generator 14B receives an instruction to adjust the amplitude from the phase adjuster 15, the bias generator 14B increases the clock amplitude in accordance with the phase difference, that is, the drive capability of the inverter 11B increases. The bias voltages BIASP and BIASN are changed (to shorten the delay time).

  Here, the bias generators 14A and 14B have a plurality of current cells 31 as shown in FIG. 3, for example, and these current cells 31 are provided in parallel. FIG. 3 is a diagram illustrating an example of current cells included in the bias generation units 14A and 14B in the present embodiment. The current cell 31 shown in FIG. 3 has three N-channel transistors 32, 33, 34 and a current source 35.

  The transistor 32 has a source connected to the node of the reference potential, a drain connected to the current source 35 that flows the current Ir through the transistor 34, and a gate connected to the drain. The transistor 33 has a source connected to the node of the reference potential, a drain connected to the output current node Iout, and a gate connected to the gate of the transistor 32. That is, the transistors 32 and 33 are current mirror connected. The transistor 34 has a gate supplied with a control signal (control code) CD, and the other end of the current source 35 is connected to a node of the power supply voltage.

  The bias generators 14A and 14B are provided with a plurality of current cells 31 as shown in FIG. 3 in parallel to connect the output current node Iout in common, and control the number of turning on and off the transistor 34 as a switch. (Control code) Control by CD. Thereby, the bias generation units 14A and 14B control the total amount of output current from the plurality of current cells 31, and generate bias voltages BIASP and BIASN by converting the output current into current-voltage.

  Next, the operation of the semiconductor device in this embodiment shown in FIG. 1 will be described. The semiconductor device according to the present embodiment performs the amplitude adjustment operation and the phase adjustment operation, thereby optimizing the amplitude of the clock transmitted through the clock path A and the clock path B, minimizing the phase difference (skew), and distributing the clock. Reduces the power consumed by the clock and realizes clock distribution with a small skew.

  First, the minimum amplitude of the clock that can be transmitted through the clock path A and the clock path B is determined by the amplitude adjustment operation. Although the amplitude adjustment operation is performed for each clock path, the amplitude adjustment operations in the clock path A and the clock path B are the same, and therefore the clock path A will be described as an example. When the amplitude adjustment operation is started, the transition number detection unit 12A detects the number of transitions between “0” and “1” in the output clock OUTA from the clock path A during the specified detection period. Then, the determination unit 13A determines whether the number of transitions detected by the transition number detection unit 12A is larger than the set value or smaller than the set value.

  If the number of transitions detected is larger than the set value as a result of the determination, the bias generator 14A uses the bias voltages BIASP and BIASN supplied to the inverter 11A so as to reduce the amplitude of the output clock OUTA from the clock path A. Change. If the detected number of transitions is smaller than the set value, the bias generator 14A changes the bias voltages BIASP and BIASN supplied to the inverter 11A so as to increase the amplitude of the output clock OUTA from the clock path A. . When the operation described above is repeated and the relationship between the detected number of transitions and the set value becomes a steady state, the amplitude of the clock at that time is determined as the minimum amplitude of the clock that can be transmitted by the clock path A, and the amplitude adjustment operation is performed. finish.

  After the amplitude adjustment operation for the clock path A and the clock path B is completed, the phases of the clocks transmitted through the clock path A and the clock path B are aligned by the phase adjustment operation. When the phase adjustment operation is started, the phase adjustment unit 15 compares the phases of the output clock OUTA and the output clock OUTB. As a result of the comparison, the phase adjustment unit 15 instructs one of the bias generation units 14A and 14B corresponding to the clock path of the clock whose phase is delayed to increase the clock amplitude. Upon receiving an instruction from the phase adjustment unit 15, one of the bias generation units 14A and 14B changes the bias voltages BIASP and BIASN supplied to the inverters 11A and 11B so as to increase the amplitude of the clock. In this way, the phases of the clocks transmitted through the clock path A and the clock path B are adjusted to align the output phases. This phase adjustment operation is continuously performed even during normal operation.

  According to the semiconductor device of this embodiment, clock transmission with the minimum amplitude is possible, the phases of the clocks can be aligned, clock distribution with a small skew can be realized, and power consumption can be reduced. Can do. For example, when the operation speed (clock frequency) is slow, the minimum amplitude of the clock can be reduced, so that it is possible to determine the minimum amplitude according to the operation frequency and perform clock transmission. Even if changes, power can be optimized and clock distribution can be performed with minimum power.

  FIG. 4 is a diagram illustrating a specific configuration example of the semiconductor device according to the present embodiment. FIG. 4 also shows the configuration related to clock transmission in the semiconductor device according to the present embodiment, and other portions are omitted.

  In FIG. 4, a clock transmission path (clock path A) in which a plurality of inverters 101A are connected in series transmits an input clock INA and outputs it as an output clock OUTA. A clock transmission path (clock path B) in which a plurality of inverters 101B are connected in series transmits an input clock INB and outputs it as an output clock OUTB. The configuration of the inverters 101A and 101B is the same as that of the inverter 11 shown in FIG. 2, for example.

  The amplitude adjustment circuit 110A related to the output clock OUTA from the clock path A includes a dummy circuit 111A, a counter 112A, a comparison circuit 113A, an analog-digital conversion circuit (ADC circuit) 114A, an addition circuit 115A, and a bias circuit 116A. The dummy circuit 111A is a circuit having a load similar to a circuit (not shown) that receives the output clock OUTA from the clock path A and performs an actual operation, and outputs the clock CLKA corresponding to the output clock OUTA. The dummy circuit 111A is, for example, a frequency divider circuit.

  The counter 112A detects the number of transitions between “0” and “1” in the clock CLKA output from the dummy circuit 111A in the detection period (sampling period) defined by the supplied clock ExtXCLKA. For example, the counter 112A detects the number of transitions of the clock CLKA over a period of a specified number of cycles with the clock ExtXCLKA. The comparison circuit 113A compares the number of transitions detected by the counter 112A with the set value, and if the detected number of transitions is larger than the set value, the output (DC output) is reduced, and if it is smaller than the set value, the output is output. Increase

  The ADC circuit 114A converts the output (DC output) of the comparison circuit 113A from analog to digital, converts it to a digital code (amplitude adjustment code), and outputs it. The adder circuit 115A adds the digital code (amplitude adjustment code) obtained by the conversion in the ADC circuit 114A and the digital code supplied from the phase adjustment circuit 120 and outputs the result. The bias circuit 110A generates bias voltages BIASP and BIASN corresponding to the digital code output from the adder circuit 115A, and supplies the bias voltages BIASP and BIASN to the inverter 101A of the clock path A.

  The amplitude adjustment circuit 110B related to the output clock OUTB from the clock path B includes a dummy circuit 111B, a counter 112B, a comparison circuit 113B, an ADC circuit 114B, an addition circuit 115B, and a bias circuit 116B. The dummy circuit 111B is a circuit having a load similar to a circuit (not shown) that receives an output clock OUTB from the clock path B and performs an actual operation, and outputs a clock CLKB corresponding to the output clock OUTB. The dummy circuit 111B is, for example, a frequency divider circuit.

  The counter 112B detects the number of transitions between “0” and “1” in the clock CLKB output from the dummy circuit 111B in the detection period (sampling period) defined by the supplied clock ExtXCLKB. The comparison circuit 113B compares the number of transitions detected by the counter 112B with the set value, and reduces the output (DC output) if the detected number of transitions is larger than the set value, and outputs if it is smaller than the set value. Increase

  The ADC circuit 114B converts the output (DC output) of the comparison circuit 113B into a digital code (amplitude adjustment code) and outputs it. The adder circuit 115B adds the digital code (amplitude adjustment code) obtained by the conversion in the ADC circuit 114B and the digital code supplied from the phase adjustment circuit 120 and outputs the result. The bias circuit 110B generates bias voltages BIASP and BIASN corresponding to the digital code output from the adder circuit 115B, and supplies the bias voltages BIASP and BIASN to the inverter 101B in the clock path B.

  The phase adjustment circuit 120 includes a flip-flop 128, selection circuits 121, 122, and 127, a phase detection circuit 123, a charge pump circuit 124, a loop filter 125, and an ADC circuit 126. In the flip-flop 128, the output clock OUTA from the clock path A is input to the data input terminal, the output clock OUTB from the clock path B is input to the clock input terminal, and the output clock OUTA is captured in synchronization with the output clock OUTB. Output.

  In other words, the flip-flop 128 captures and outputs the output clock OUTA in synchronization with the output clock OUTB, so that the output indicates which phase of the output clock OUTA or the output clock OUTB is delayed. For example, the flip-flop 128 outputs “H” if the output clock OUTA is a signal that is delayed in phase, and outputs “L” if the output clock OUTB is a signal that is delayed in phase.

  The selection circuit 121 selects and outputs one of the output clock OUTA and the output clock OUTB, which is delayed in phase, as the target clock CKI according to the output of the flip-flop 128. The selection circuit 122 selects and outputs the other clock (clock different from the clock selected by the selection circuit 121) of the output clock OUTA and the output clock OUTB as the reference clock CKR according to the output of the flip-flop 128. To do.

  The phase detection circuit 123 detects the phase difference between the target clock CKI output from the selection circuit 121 and the reference clock CKR output from the selection circuit 122. The charge pump circuit 124 and the loop filter 125 generate an output voltage (DC output) according to the output of the phase detection circuit 123. The ADC circuit 126 converts the output voltage (DC output) from the charge pump circuit 124 and the loop filter 125 into a digital code and outputs the digital code.

  The selection circuit 121 outputs the digital code output from the ADC circuit 126 to the addition circuit 115A of the amplitude adjustment circuit 110A or the addition circuit 115B of the amplitude adjustment circuit 110B according to the output of the flip-flop 128. The selection circuit 121 supplies the digital code output from the ADC circuit 126 to one of the amplitude adjustment circuits 110 </ b> A and 110 </ b> B corresponding to the clock with a phase lag indicated by the output of the flip-flop 128.

  The sequencer 130 performs control related to the amplitude adjustment operation and the phase adjustment operation in the semiconductor device according to the present embodiment. For example, when an external signal CLK_ADJ_START is input (becomes “1”), the sequencer 130 starts the amplitude adjustment operation and the phase adjustment operation, and outputs the signal CLK_ADJ_END (set to “1”) when the operation ends. ).

  Next, the operation of the semiconductor device in this embodiment shown in FIG. 4 will be described. FIG. 5 is a flowchart showing an operation example of the semiconductor device in the present embodiment shown in FIG. As described above, the semiconductor device according to the present embodiment performs an amplitude adjustment operation and a phase adjustment operation.

  When the operation is started by inputting the signal CLK_ADJ_START (= “1”) to the sequencer 130 (S101), the amplitude adjustment operation by the amplitude adjustment circuit 110A and the amplitude adjustment circuit 110B is started according to an instruction from the sequencer 130. . The phase adjustment circuit 120 is stopped without operating. When the amplitude adjustment operation starts, the dummy circuit 111A of the amplitude adjustment circuit 110A starts generating the clock CLKA according to the output clock OUTA from the clock path A, and the dummy circuit 111B of the amplitude adjustment circuit 110B starts from the clock path B. The generation of the clock CLKB corresponding to the output clock OUTB is started (S102).

  When the clocks CLKA and CLKB are stabilized (S103), the amplitude adjustment circuits 110A and 110B confirm the number of transitions between “0” and “1” of the clocks CLKA and CLKB, and the number of transitions is larger than the set value. In this case, the digital code (amplitude adjustment code) is controlled to be small by reducing the clock amplitude. If the number of transitions is smaller than the set value, the digital code (amplitude adjustment code) is increased to increase the clock amplitude. Is controlled to increase (S104). The operations in steps S103 and S104 are repeated until the relationship between the number of transitions of the clocks CLKA and CLKB and the set value reaches a steady state (S105).

  When the relationship between the number of transitions of the clocks CLKA and CLKB and the set value becomes a steady state, the amplitude adjustment circuits 110A and 110B determine the clock amplitude at that time as the minimum transmittable amplitude. Then, the amplitude adjustment circuits 110A and 110B increase the digital code (amplitude adjustment code) corresponding to the determined minimum amplitude by a specified number (for example, 1) (S106). This is added in order to give a margin to the amplitude because the determined minimum amplitude is an amplitude as a limit of transmission. In this way, the amplitude adjustment operation by the amplitude adjustment circuit 110A and the amplitude adjustment circuit 110B is finished, the sequencer 130 outputs the signal CLK_ADJ_END (= “1”), and starts the phase adjustment operation (S107).

  Note that the amplitude adjustment operation by the amplitude adjustment circuit 110A and the amplitude adjustment circuit 110B does not have to be performed in parallel at the same time. After the amplitude adjustment operation by one of the amplitude adjustment circuit 110A and the amplitude adjustment circuit 110B is performed, the other is performed. An amplitude adjustment operation may be performed. Further, a part of the amplitude adjustment operation by the amplitude adjustment circuit 110A and a part of the amplitude adjustment operation by the amplitude adjustment circuit 110B may be executed in parallel.

  When the phase adjustment operation is started, the phase adjustment circuit 120 starts to operate in accordance with an instruction from the sequencer 130, and the operations of the amplitude adjustment circuit 110A and the amplitude adjustment circuit 110B are stopped, and the clocks CLKA, The generation of CLKB is stopped (S108). In the phase adjustment circuit 120, the phase detection circuit 123 starts operation, and performs phase comparison using one of the output clock OUTA and the output clock OUTB as the target clock CKI and the other as the reference clock CKR (S109). Then, the charge pump circuit 124 and the loop filter 125 convert the phase difference detected by the phase comparison in the phase detection circuit 123 into an output voltage (DC output) and output it (S110).

  Subsequently, the ADC circuit 126 converts the output voltage (DC output) from the charge pump circuit 124 and the loop filter 125 into a digital code. This digital code is input to the bias circuits 116A and 116B of the clock amplitude adjustment circuits 110A and 110B whose phases are delayed via the selection circuit 127 and the addition circuits 115A and 115B. As a result, the amplitude of the clock whose phase is delayed is increased and phase adjustment is performed so that the phases of the output clock OUTA and the output clock OUTB are aligned (S111), and the output phases of the output clock OUTA and the output clock OUTB are stabilized. (S112).

  The phase adjustment operation in steps S108 to S112 is continuously executed even during the actual operation of the semiconductor device. Therefore, even if the operating environment such as temperature changes, for example, phase adjustment is performed under the operating environment, and clock distribution with a small skew can be realized.

  As described above, in the semiconductor device according to the present embodiment, clock transmission with minimum amplitude is possible, clock distribution with a small skew can be realized, and power consumed by clock distribution can be reduced. In addition, it is possible to change the minimum amplitude according to the operating frequency and perform clock transmission. Even if the operating frequency changes, the power can be optimized and the clock can be distributed with the minimum power.

  FIG. 6 is a diagram illustrating an application example of the semiconductor device according to the present embodiment. In FIG. 6, components having the same functions as those shown in FIG. 4 are given the same reference numerals, and redundant descriptions are omitted. FIG. 6 shows an example used for clock distribution at each stage in the multiplexer circuit inside the transmitter of the high-speed IO circuit macro.

  In FIG. 6, the output clock OUTA from the clock path A is input to the 4: 2 multiplexer circuit 202 inside the transmitter of the high-speed IO circuit macro, and the output clock from the clock path B is input to the 2: 1 multiplexer circuit 203. OUTB is input. A clock obtained by dividing the clock CLK input by the frequency dividing circuit 201 by 2 by the frequency dividing circuit 201 is input to the clock path A as the input clock INA, and the clock CLK input to the clock path B is input. Is input as the input clock INB.

  FIG. 7 is a diagram illustrating an example of the dummy circuits 111A and 111B illustrated in FIG. The dummy circuit shown in FIG. 7 is a frequency dividing circuit including D latch circuits 301-1 and 301-2 and inverters 304 and 305. Each of the D latch circuits 301-1 and 301-2 includes a transfer gate 302 and an inverter 303. Each of the D latch circuits 301-1 and 301-2 has its input terminal connected to the input terminal of the inverter 303 via the transfer gate 302, and its output terminal connected to the input terminal of the inverter 303. Transfer gate 302 has an N-channel transistor controlled by input signal IN and a P-channel transistor controlled by input signal IN inverted by inverter 304. The output of the D latch circuit 301-2 is output as an output signal OUT and also input to the D latch circuit 301-1 via the inverter 305.

  As shown in FIG. 6, the present embodiment is applied to clock distribution to the multiplexer circuit inside the transmitter of the high-speed IO circuit macro, so that it is input to each of the 4: 2 multiplexer circuit 202 and the 2: 1 multiplexer circuit 203. The clock skew can be reduced and the clock can be transmitted with low power consumption.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

11A, 11B Inverter (clock driver)
12A, 12B Transition number detection unit 13A, 13B Determination unit 14A, 14B Bias generation unit 15 Phase adjustment unit 101A, 101B Inverter (clock driver)
110A, 110B Amplitude adjustment circuit 111A, 111B Dummy circuit 112A, 112B Counter 113A, 113B Comparison circuit 114A, 114B Analog to digital conversion circuit 115A, 115B Addition circuit 116A, 116B Bias circuit 120 Phase adjustment circuit 130 Sequencer

Claims (7)

A first transmission path for controlling the amplitude of the clock transmitted by the first bias voltage;
A second transmission path that is different from the first transmission path and controls the amplitude of the clock transmitted by the second bias voltage;
A phase adjustment unit that compares the phases of the output clock from the first transmission path and the output clock from the second transmission path and outputs a phase adjustment instruction according to the phase difference;
A transition number detector for detecting the number of transitions of the output clock from the transmission line in a specified detection period;
A determination unit that determines whether the number of transitions detected by the transition number detection unit is larger than a set value or smaller than a set value, and outputs a determination result;
A semiconductor device, comprising: a bias generation unit that generates the bias voltage corresponding to the output of the determination unit and the output of the phase adjustment unit and supplies the bias voltage to the transmission line.   The semiconductor device according to claim 1, further comprising: the transition number detection unit, the determination unit, and the bias generation unit for each of the first transmission path and the second transmission path. The bias generation unit includes:
When the determination unit determines that the number of transitions detected by the transition number detection unit is greater than a set value, generates the bias voltage that reduces the amplitude of the clock to be transmitted and supplies the bias voltage to the transmission line,
When the determination unit determines that the number of transitions detected by the transition number detection unit is smaller than a set value, the bias voltage for increasing the amplitude of the clock to be transmitted is generated and supplied to the transmission line. The semiconductor device according to claim 1 or 2. The bias generation unit includes:
According to the output of the phase adjustment unit, the amplitude of the output clock whose phase is delayed between the output clock from the first transmission path and the output clock from the second transmission path is determined according to the phase difference. The semiconductor device according to claim 1, wherein the bias voltage to be increased is generated and supplied to the transmission line. The bias generation unit includes:
After the bias voltage corresponding to the output of the determination unit is generated and supplied to the transmission line, the bias voltage supplied to the transmission line is changed according to the output of the phase adjustment unit. The semiconductor device according to claim 1, wherein the semiconductor device is characterized in that: The transition number detection unit includes a counter that detects the number of transitions related to the output clock from the transmission path,
The determination unit
A comparison circuit that increases the output if the number of transitions detected by the transition number detection unit is greater than a set value, and decreases the output if it is less than the set value;
The semiconductor device according to claim 1, further comprising an analog-to-digital conversion circuit that converts an output of the comparison circuit into a digital code. Detecting the number of transitions of the output clock from the transmission line in which the amplitude of the clock transmitted by the bias voltage is controlled over a specified detection period;
Determining whether the detected number of transitions is greater than a set value or less than a set value;
When it is determined that the detected number of transitions is larger than a set value, the bias voltage for reducing the amplitude of the clock to be transmitted is generated and supplied to the transmission line, and the detected number of transitions is smaller than the set value. If determined to be small, generate the bias voltage to increase the amplitude of the clock to be transmitted and supply it to the transmission path,
The phase of the output clock from the first transmission line to which the first bias voltage is supplied and the output clock from the second transmission line to which the second bias voltage is supplied are compared. One of the first bias voltage and the second bias voltage is changed in accordance with a phase difference. A clock transmission method for a semiconductor device, wherein:

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