JP2015515128A - Semiconductor structure and method for planarizing a plurality of conductive posts - Google Patents

Abstract

Some embodiments include a planarization method. The liner is formed along the post extending across the semiconductor substrate and upward from the substrate. The organic filler material is formed on the liner and between the posts. A planarized surface is formed that extends across the post and over one or both of the liner and filler material. Some embodiments include a semiconductor structure that includes a semiconductor die. The conductive post extends through the die. The post has a top surface on the back surface of the die and a sidewall surface extending between the back surface and the top surface. The liner extends over the backside surface of the die and along the sidewall surface of the post. The conductive cap is on the top surface of the post and has a rim along the liner adjacent to the side wall surface of the post. [Selection] Figure 7

Description

  A semiconductor structure and method for planarizing over a plurality of conductive posts.

  Commercial manufacture of integrated circuit devices such as memory dice may involve the creation of a number of identical circuit patterns on a single semiconductor wafer or other bulk semiconductor substrate. Increasing the density of semiconductor devices fabricated on any size semiconductor substrate is still a goal for semiconductor manufacturers to achieve improved semiconductor device manufacturing efficiency and improved semiconductor device performance. The

  One way to increase the density of semiconductor devices in a semiconductor assembly is to extend through the entire semiconductor die, ie vias that extend from the active surface of the die to the backside surface on the opposite side of the die. Is to create. The vias may be filled with a conductive material to form a through substrate interconnect that provides an electrical path from the active surface of the die to the backside surface of the die. The through-substrate interconnect may be electrically coupled to electrical contacts that extend along the back side of the die to circuit components outside the die. In some applications, the die may be incorporated into a three-dimensional multi-chip module (3-D MCM), and circuit components outside the die may be constituted by another semiconductor die and / or carrier substrate.

  Various methods have been disclosed for forming through-substrate interconnects in semiconductor substrates. For example, US Pat. Nos. 7,855,140, 7,626,269, and 6,943,106 describe exemplary methods that can be used to form through-substrate interconnects.

  Various problems may be encountered during the creation of through-substrate interconnects. For example, through-substrate interconnect conductive posts may be planarized to form a planarized surface that extends over the backside surface of the semiconductor die and extends across the post and die during the processing stage. May be desirable. However, the copper in the post may smear during planarization and / or the post may tilt or break during planarization. It is desirable to develop new methods of forming through-substrate interconnects that reduce, prevent, and / or overcome problems encountered with conventional processing. Furthermore, it is desirable to develop a new through-board interconnect architecture.

2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. It is a top view of the structure of FIG. The view of FIG. 1 is taken along line 1-1 of FIG. 1A. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. FIG. 8 is a top view of the structure of FIG. 7. The view of FIG. 7 is taken along line 7-7 of FIG. 7A. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. It is a top view of the structure of FIG. The view of FIG. 12 is taken along line 12-12 of FIG. 12A. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. FIG. 14 is a top view of the structure of FIG. 13. The view of FIG. 13 is taken along line 13-13 of FIG. 13A. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG. 2 is a cross-sectional view of a portion of a structure at various stages of processing of an example embodiment method. FIG.

  In some embodiments, the present invention includes a method for forming a planarized surface across a plurality of conductive posts. The post corresponds to a through-board interconnect and may include copper in some embodiments.

  Exemplary embodiments are described with reference to FIGS.

  With reference to FIGS. 1 and 1A, the semiconductor structure 10 is shown to include a plurality of conductive posts 20-22 that extend to a semiconductor base 12. In some embodiments, the base 12 may correspond to a semiconductor die. The die has a back side 14 and a front side 16. An integrated circuit (not shown) is associated with the front side, and a dashed line 17 is provided to illustrate the approximate boundaries of the circuit within the die. The integrated circuit may include a memory (eg, NAND, DRAM, etc.), logic, and the like. The integrated circuit may be primarily associated with the front side, but in some embodiments there may be an integrated circuit associated with the back side.

  The back side has a surface 15. Posts 20-22 have a top surface on backside surface 15 and a sidewall surface that extends from top surface to backside surface 15. For example, the conductive post 20 is shown to include an upper surface 25 and is shown to include a sidewall surface 23 that extends from the upper surface 25 to the backside surface 15 of the base 12.

  The base also has a front surface, and in some embodiments the posts 20-22 may pass through the entire die such that the post has a surface along the front surface of the die. The front surface is not shown in FIG. The front surface of the die may be bonded to a carrier wafer (not shown) during the processing steps of FIGS. 1 and 1A to assist in transport between processing devices through the die.

  The base 12 includes single crystal silicon and may be referred to as a semiconductor substrate or a part of the semiconductor substrate. The terms “semiconductive substrate”, “semiconductor structure” and “semiconductor substrate” refer to bulk semiconductive materials and semiconductive material layers (single layers) such as semiconductor wafers (either alone or assemblies containing other materials). Or any assembly that includes other materials) means any structure that includes a semiconductive material, including but not limited to any. The term “substrate” refers to any support structure, including but not limited to the semiconductive substrates described above.

  Conductive posts 20-22 may include any suitable conductive composition or combination of compositions. In some embodiments, the post may include one or more conductive compositions formed in a through substrate via (TSV). In some embodiments, the post may include copper.

  In the embodiment shown in FIGS. 1 and 1A, the posts are formed at different distances on the backside surface 15 of the base 12. Such non-uniformity of exposed post dimensions may result from the process used to make the post and / or the total thickness change (TTV) that occurs during or after polishing of the post surface. The change in exposed post size may be greater than 1 micrometer or greater than 10 micrometers in some embodiments.

  Referring to FIG. 2, the liner 26 is formed over the surface 15 and along the sidewalls of the upper surface of the posts 20-22. The liner 26 may include any suitable composition or combination of compositions. Although the liner is shown as being a single homogeneous composition, in some embodiments, the liner may include two or more individual materials. For example, the liner may include silicon dioxide on silicon nitride. In some embodiments, the liner 26 is composed of an inorganic material. In some embodiments, the liner includes a copper barrier material, such as a material comprising ruthenium or ruthenium oxide, substantially composed of ruthenium or ruthenium oxide, or a material composed of ruthenium or ruthenium oxide. The copper barrier material may be used in combination with a post containing copper, and may reduce or prevent copper diffusion that may result from a copper-containing post. The ruthenium-containing material may be used alone or in combination with one or both of silicon dioxide and silicon nitride. Accordingly, in some exemplary embodiments, liner 26 includes, is substantially comprised of, or consists of one or more of silicon dioxide, silicon nitride, and ruthenium.

  The liner 26 may be formed by any suitable method, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD).

  The liner is formed to any suitable thickness, and in some embodiments is formed to a thickness of 500 nanometers or less.

  In some embodiments, it may be desirable to form the liner 26 at a low temperature (ie, a temperature of about 200 ° C. or less) to avoid adversely affecting the circuitry associated with the base 12. . In such embodiments, the liner may comprise silicon deposited at a temperature of about 200 ° C. or less, consist essentially of silicon, or consist of silicon.

  With reference to FIG. 3, a filler material 28 is formed between the posts 20-22 on the liner 26. In the embodiment shown, the filler material is provided in the area between the posts but not on the posts. In other embodiments (such as the embodiment shown in FIG. 8), the filler material may be provided to a thickness that covers at least some of the posts.

  The filler material may comprise any suitable composition or combination of compositions. In some embodiments, one or more organic (ie, carbon-containing) compositions may be included. For example, in some embodiments, the fill material 28 may include, consist essentially of, or consist of photoresist.

  The filler material may be provided to any suitable thickness. In some embodiments, the filler material may be provided to a thickness in the range of about 500 nanometers to about 4 microns. In some embodiments, the combined thickness of the filler material and liner may be in the range of about 500 nanometers to about 5 microns.

  With reference to FIG. 4, the structure 10 is subjected to planarization to form a planarized surface 29. Planarization may be achieved utilizing any suitable method such as, for example, chemical mechanical polishing (CMP). In the illustrated embodiment, the planarization removes the filler material 28 (FIG. 3) and forms a planarization surface 29 that extends across the liner 26 and posts 20-22. In other embodiments (eg, the embodiment described below with reference to FIG. 9), the planarizing surface may extend across the filler material and post.

  Referring to FIG. 5, a conductive material 30 is formed over the planarized surface 29 and a patterned masking material 31 is formed on the conductive material. In some embodiments, the conductive material comprises copper and may be utilized as a seed material for subsequent copper electrolytic growth (eg, material 30 comprises a mixture of titanium and copper, or titanium and It may consist essentially of a mixture of copper or may consist of a mixture of titanium islands). In some embodiments, the patterned masking material 31 may comprise a photoresist patterned by photolithography.

  The patterned masking material has openings 32-34 extending therethrough, respectively, to expose areas on the posts 20-22.

  Referring to FIG. 6, conductive materials 36 and 38 are formed in openings 32-34. In some embodiments, material 36 includes, is substantially composed of, or may be composed of copper grown on conductive material 30, and material 38 may be nickel or palladium. May be included. In the illustrated embodiment, the two materials 36 and 38 are formed in the openings 32-34, but in other embodiments a single conductive material may be formed in the openings. Alternatively, two or more materials may be formed in the opening. In some embodiments, for example, both nickel and palladium may be formed on the copper-containing material 36. The materials 36 and 38 may eventually be incorporated under the bump metal (UBM), thereby in some embodiments including a conventional composition suitable for use in the UBM.

  Materials 36 and 38 form a stack 40-42 within openings 32-34, respectively. The stacks are spaced from each other by the intervening regions of the masking material 31 in the illustrated embodiment.

  Referring to FIGS. 7 and 7A, the masking material 31 (FIG. 6) is removed, after which the stack 40-42 is used as a hard mask during the etching of the material 30. FIG. The structure of FIGS. 7 and 7A may be considered to include a plurality of conductive caps 44-46 that include material 30 in combination with materials 36 and 38 of laminates 40-42. Caps 44-46 have a one-to-one correspondence with posts 20-22 and ultimately correspond to UBMs used for conductively bonded solder balls with posts or other wiring components (not shown). May be.

  The caps 44-46 have any suitable shape, and FIG. 7A shows one embodiment where the cap is circular.

  Another exemplary embodiment method for forming a planarized surface that extends across a plurality of conductive posts is described with reference to FIGS.

  Referring to FIG. 8, structure 10a is shown in a processing stage similar to the processing stage described above with reference to FIG. The structure of FIG. 8 is slightly different from the structure of FIG. 3 in that the filler material 28 is shown covering the post 21. The difference is provided to show that the depth of the filler material 28 can vary in various embodiments. In some embodiments, the filler material 28 may be provided to the depth shown in the processing stage of FIG. 3 and to the same depth in the processing stage of FIG. 8 or vice versa. Good.

  Referring to FIG. 9, a planarized surface 49 is formed over the structure 10a. The planarized surface may be formed using, for example, CMP. The planarized surface extends across the posts 20-22 and across the filler material 28. In the illustrated embodiment, the planarizing surface also extends over a portion of the liner 26 adjacent the sidewalls of the posts 20-22.

Referring to FIG. 10, filler material 28 (FIG. 9) is selectively removed relative to liner 26 and post 20-22. In some embodiments, the filling material an organic composition (e.g., photoresist) comprises, oxidation conditions (e.g., O ₂ of the presence of _plasma) by using, in the inorganic composition of the liner 26 and posts 20-22 Selectively removed. The upper region of post 20-22 includes a planarized surface 49.

  Referring to FIG. 11, conductive material 30 is formed over liner 26 and posts 20-22, patterned masking material 31 is formed on material 30, and conductive materials 36 and 38 are masking material 31. Formed in openings 32-34 extending therethrough.

  Referring to FIGS. 12 and 12A, structure 10a is shown in a processing stage similar to the processing stage of FIGS. 7 and 7A. Masking material 31 (FIG. 11) is removed and materials 30, 36 and 38 are incorporated into a plurality of conductive caps 44a-46a. In some embodiments, material 30 is formed facing the top surface of liner 26 and post (as shown), and material 36 corresponds to a copper-containing material that has been electrolytically grown on material 30. .

  In the illustrated embodiment of FIGS. 12 and 12A, the post 20-22 has a planarized top surface corresponding to the planarized surface 49 and is planarized to the backside surface 15 of the base 12. A sidewall surface extending from the upper surface. For example, post 20 has a sidewall surface 23 shown. In the illustrated embodiment, the conductive material 30 faces the top surface of the post so that the caps 44a-46a face the planarized top surface of the post. Caps 44a-46a have a region extending along the sidewall surface of the post. For example, the cap 44a is shown having a region 50 that extends along the sidewall surface 32 of the post 20. The area of the cap along the sidewall is referred to as the “rim” and is separated from the sidewall surface of the post by the liner 26 in the illustrated embodiment.

  The caps 44a-46a have any suitable shape, and FIG. 12A shows one embodiment where the cap is circular.

  Another exemplary embodiment method of a method for forming a planarized surface that extends across a plurality of conductive posts is described with reference to FIGS.

  Referring to FIGS. 13 and 13A, structure 10b is shown in a processing stage after the processing stage of FIG. A patterned electrically insulating material 60 is formed on the liner 26. The patterned electrically insulating material includes a thin region 63 and a thick region 65. The thin area may be considered to define an insertion area 62 that extends around the planarized upper surface 49 of the post.

  The material 60 includes any suitable composition or combination of compositions, and may include, for example, polyimide, substantially composed of polyimide, or composed of polyimide. In some embodiments, the liner 26 includes silicon nitride formed by a low temperature process. The silicon nitride may have pinholes extending therein or therethrough. In this embodiment, the conductive material of the subsequently formed cap (ie, caps 44b-46b described below with reference to FIG. 15) is not exposed to direct contact with the semiconductor material of the base 12. 60 may be used to close the pinhole.

  Material 60 may be patterned using any suitable method. In some embodiments, a photoresist mask (not shown) utilizes a photolithographic process that produces a stepped area in the mask (eg, a “leaky” reticle to pattern the mask). Formed on the spread of the material 60, and then the pattern may be transferred from the photoresist mask to the material 60 by one or more suitable etches. Thereby, a staircase region is formed in the material 60, the thin part of the staircase region corresponds to the region 63, and the thick part of the staircase region corresponds to the region 65. The photoresist mask may then be removed to leave the structure of FIGS. 13 and 13A.

  The top surface of post 20-22 is exposed through material 60. In some embodiments, the etching and / or planarization is performed after the formation of the material 60 spread and before the formation of the staircase region in the material 60 to expose the top surface of the post 20-22. May be implemented.

  Referring to FIG. 14, structure 10b is shown in a processing stage similar to the processing stage of FIG. Conductive material 30 is formed over material 60 and posts 20-22, patterned masking material 31 is formed on material 30, and conductive materials 36 and 38 are apertures extending through masking material 31. 32-34.

  Referring to FIGS. 15 and 15A, structure 10b is shown in a processing stage similar to the processing stage of FIGS. 12 and 12A. Masking material 31 (FIG. 14) is removed and materials 30, 36 and 38 are incorporated into a plurality of conductive caps 44b-46b. The cap has a rim that extends along the sidewall surface of the post 20 (eg, the rim 50 of the cap 44b extends along the sidewall surface 23 of the post 20), and the rim is in the illustrated embodiment. , Separated from the side wall surface of the post by liner 26.

  Some of the embodiments described herein include copper and silicon (eg, FIG. 1-FIG. 1) of through-substrate interconnects (eg, interconnects similar to posts 20-22 of FIGS. 1-15). Prior art problems associated with planarization across both of the 15 base 12 silicon-containing dies) may be advantageously avoided. That is, posts 20-22 are simultaneously planarized with an exposed surface that includes liner 26 (the embodiment of FIG. 4) and / or filler material 28 (the embodiment of FIG. 9). Thus, posts 20-22 include copper or another material that is smeared during planarization, and the smeared conductive material does not face the semiconductor material of base 12, but instead liner 26 and / or filling. Face material 28. The smeared conductive material may then be removed during removal of the underlying material (eg, in the embodiments of FIGS. 9 and 10, any conductive material smeared across the filler material 28 is May be removed during the removal of the filler material) or may be left on the underlying insulating material if it does not adversely affect the performance of the resulting structure.

  In some embodiments, the advantages of the processes described herein may include reduction or prevention of copper smear after polishing, problems associated with silicon dry etch chemistry (eg, sulfide formation, non-uniform etching). Performance and / or processing steps utilizing high-precision steppers to handle excessive post-polishing layer thickness changes without polishing to posts used for through-substrate interconnects May include exclusion.

  The liner 26 and / or filler material 28, in some embodiments, reduces or prevents tilting, bending, breakage, etc. that can occur in prior art processes where similar posts are not properly supported during planarization across the posts. To do so, support to posts 20-22 may be provided.

  In some embodiments, the structures described herein may be incorporated into a hybrid memory cubic (HMC) architecture, such as, for example, an architecture that includes DRAM circuits stacked on a logic circuit.

  The specific directions of the various embodiments in the drawings are for illustrative purposes only, and the embodiments may be rotated relative to the indicated directions in some applications. The description provided herein and the claims that follow provide a description between various features, regardless of whether the structure is in a particular direction in the drawing or whether it is rotated relative to that direction. Relates to any structure having a defined relationship.

  The cross-sectional views of the accompanying drawings show only the features in the cross-sectional plane, and the material behind the cross-sectional plane is not shown to simplify the drawing.

  When one structure is referred to above as being “on” or “against” another structure, it may be present directly on another structure or even if an intermediate structure is present Good. In contrast, when one structure is referred to as being “directly on” or “directly against” another structure, there is no intermediate structure. When one structure is referred to as being “connected” or “coupled” to another structure, is it directly connected or coupled to another structure; Or an intermediate structure may exist. In contrast, when one structure is referred to as being “directly connected” or “directly coupled” to another structure, there is no intermediate structure.

  Some embodiments include a method of planarizing over a plurality of conductive posts extending to a semiconductor substrate. The liner is formed over the substrate surface and along the sidewall surface and top surface of the post. Filler material is formed on the liner and between the posts. The charging material includes one or more organic compositions. The planarized surface is formed to extend over the post and over one or both of the liner and filler material.

  Some embodiments include a method of planarizing a plurality of conductive posts extending to a semiconductor substrate. The liner is formed over the substrate surface and along the sidewall surface and top surface of the post. The liner may include one or more inorganic compositions. Filler material is formed on the liner and between the posts. The filler material includes one or more organic compositions. The planarized surface is formed to extend across the filler material and post. After the planarized surface is formed, etching is used to remove the filler material from between the posts, leaving a liner across the substrate surface between the posts along the sidewall surfaces of the posts. The etch used to remove the fill material includes, for example, a suitable wet chemistry or a suitable dry chemistry, and in some embodiments an oxidant may be used.

  Some embodiments include a method of planarizing a plurality of conductive posts extending to a semiconductor substrate. The liner is formed on the substrate surface and along the sidewall surface and top surface of the post. Filler material is formed on the liner and between the posts. The planarized surface is formed to extend across the post and liner. A conductive material is formed on the planarized surface. The conductive cap is formed on the conductive material. Forming a conductive cap forms a patterned mask on the conductive material and grows a copper-containing layer on the conductive material in an opening extending through the patterned mask. Forming one or both of nickel and palladium on the copper-containing layer in the opening in the patterned mask (the copper-containing layer having one or both of nickel and palladium is conductive) Forming spaced laminates on the material), removing the conductive material from the space between the laminates.

  Some embodiments include a semiconductor structure. The structure has conductive posts that extend through the semiconductor die. The post has a top surface on the back side surface of the die and a sidewall surface extending between the back side surface and the top surface of the die. The liner is along the sidewall surface of the post. The conductive cap has a rim that faces the top surface of the post and is spaced from the sidewall surface along the sidewall surface of the post and by the liner.

Claims (34)

A method of planarizing a plurality of conductive posts extending to a semiconductor substrate,
Forming a liner over the substrate surface and along the plurality of sidewall surfaces and the plurality of top surfaces of the plurality of posts;
Forming a filler material on the liner and between the plurality of posts, wherein the filler material includes one or more organic compositions;
Planarizing to form a planarized surface extending across the plurality of posts and over one or both of the liner and the filler material;
including,
A method characterized by that. The filling material includes a photoresist;
The method according to claim 1. The substrate includes a semiconductor die, the surface is a backside surface of the die, and the plurality of conductive posts extend through the die;
The method according to claim 1. The planarizing forms the planarized surface for extending across the liner and the plurality of posts, and the method faces the planarized surfaces of the plurality of posts; And forming a plurality of conductive caps corresponding one-to-one with the plurality of posts,
The method according to claim 1. The planarizing forms the planarized surface for extending across the filler material and the plurality of posts, and the method includes forming the planarized surface and then forming the plurality of posts. Further removing the filler material between the plurality of posts, leaving the liner along a plurality of sidewall surfaces of the plurality of posts and across the substrate surface between the plurality of posts;
The method according to claim 1. The removal of the filler material comprises wet or dry chemistry;
6. The method of claim 5, wherein: Further comprising forming a plurality of conductive caps facing a plurality of planarized top surfaces of the plurality of posts and along the plurality of sidewall surfaces of the plurality of posts. A plurality of regions of the plurality of conductive caps along the plurality of sidewall surfaces are spaced from the plurality of sidewall surfaces by the liner;
6. The method of claim 5, wherein: After the planarization, forming a patterned electrically insulating material over the liner, the patterned electrically insulating material being planarized of the plurality of posts Forming a plurality of insertion regions around the plurality of top surfaces formed;
Forming a plurality of conductive caps within the plurality of insertion regions and facing the planarized top surfaces of the plurality of posts along the plurality of sidewall surfaces of the plurality of posts; Forming a plurality of regions of the plurality of conductive caps along the plurality of side wall surfaces of the plurality of posts so as to be spaced from the plurality of side wall surfaces by the liner;
Further including
6. The method of claim 5, wherein: The patterned electrically insulating material comprises polyimide;
The method according to claim 8, wherein: The liner includes silicon nitride having one or more pinholes extending therein, and the patterned electrically insulating material fills the one or more pinholes;
The method according to claim 8, wherein: The plurality of conductive posts include copper;
The method according to claim 1. The liner includes silicon nitride;
The method according to claim 11. The liner includes ruthenium;
The method according to claim 11. A method of planarizing a plurality of conductive posts extending to a semiconductor substrate,
Forming a liner on a substrate surface and along a plurality of sidewall surfaces and a plurality of upper surfaces of the plurality of posts, wherein the liner includes one or more inorganic compositions; ,
Forming a filler material on the liner and between the plurality of posts, wherein the filler material includes one or more organic compositions;
Planarizing to form a planarized surface extending across the filler material and the plurality of posts;
After the planarization, removing the filler material from between the plurality of posts, leaving the liner along a plurality of sidewall directions of the plurality of posts and across the substrate surface between the plurality of posts; ,
including,
A method characterized by that. The substrate includes a semiconductor die, the surface is a backside surface of the die, and the plurality of conductive posts are a plurality of copper-containing posts that extend through the die as a whole.
15. The method of claim 14, wherein: Forming a conductive material to face a plurality of planarized top surfaces of the plurality of posts and to face the liner along the plurality of sidewall surfaces of the plurality of posts;
Growing copper on the conductive material to form a plurality of conductive caps on the planarized top surfaces of the plurality of posts;
Further including
15. The method of claim 14, wherein: After the planarization, forming a patterned electrically insulating material across the liner, wherein the patterned electrically insulating material is a plurality of planar surfaces of the plurality of posts. Forming a plurality of insertion regions around the structured upper surface;
Facing a plurality of planarized upper surfaces of the plurality of posts and facing the liner along the plurality of sidewall surfaces of the plurality of posts to form a conductive material;
Growing copper on the conductive material to form a plurality of conductive caps on the planarized top surfaces of the plurality of posts;
Further including
15. The method of claim 14, wherein: A method of planarizing over a plurality of conductive posts extending to a semiconductor substrate,
Forming a liner over a substrate surface and along a plurality of sidewall surfaces and a plurality of top surfaces of the plurality of posts;
Forming a filler material on the liner and between the plurality of posts;
Planarizing to form a planarized surface extending across the plurality of posts and the liner;
Forming a conductive material on the planarized surface;
Forming a plurality of conductive caps on the conductive material;
Forming a patterned mask on the conductive material;
Growing a copper-containing layer on the conductive material in a plurality of openings extending through the patterned mask;
Forming one or both of nickel and palladium on the copper-containing layer in the plurality of openings in the patterned mask, the copper-containing having one or both of nickel and palladium Forming a layer to form a plurality of spaced-apart stacks on the conductive material;
Removing the patterned mask;
Removing the conductive material from a plurality of spaces between the plurality of stacks;
Forming a plurality of conductive caps comprising:
including,
A method characterized by that. The liner includes silicon nitride;
The method according to claim 18, wherein: The liner includes ruthenium;
The method according to claim 18, wherein: The liner comprises only one homogeneous substance,
The method according to claim 18, wherein: The liner includes two or more substances;
The method according to claim 18, wherein: The liner comprises silicon dioxide on silicon nitride;
23. The method of claim 22, wherein: The filler material includes carbon;
The method according to claim 18, wherein: The filling material includes a photoresist;
The method according to claim 18, wherein: A plurality of conductive posts extending through a semiconductor die, the plurality of posts having a plurality of top surfaces on the back side surface of the die, wherein the back side surface of the die and the plurality of top surfaces A plurality of conductive posts having a plurality of sidewall surfaces extending therebetween;
A liner along the backside surface of the plurality of posts;
A plurality of conductive caps facing the plurality of top surfaces of the plurality of posts, the plurality of caps being along the plurality of sidewall surfaces of the plurality of posts and from the plurality of sidewall surfaces by the liner; A plurality of conductive caps having a plurality of spaced rims;
including,
A semiconductor structure characterized by that. And further comprising a patterned electrically insulating material defining a plurality of insertion regions around the plurality of top surfaces of the plurality of posts, wherein the plurality of cap rims includes the plurality of insertion regions. Elongate,
27. The structure of claim 26. The patterned electrically insulating material includes polyimide,
28. The structure of claim 27, wherein: The liner is composed of only one homogeneous material,
27. The structure of claim 26. The liner is made of silicon nitride;
30. The structure of claim 29, wherein: The liner includes ruthenium;
30. The structure of claim 29, wherein: The plurality of conductive posts include copper;
32. The structure of claim 31 wherein: The liner includes two or more substances;
27. The structure of claim 26. The plurality of conductive caps include one or both of nickel and palladium.
27. The structure of claim 26.

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