JP2015506039A5 - - Google Patents

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Publication number
JP2015506039A5
JP2015506039A5 JP2014547436A JP2014547436A JP2015506039A5 JP 2015506039 A5 JP2015506039 A5 JP 2015506039A5 JP 2014547436 A JP2014547436 A JP 2014547436A JP 2014547436 A JP2014547436 A JP 2014547436A JP 2015506039 A5 JP2015506039 A5 JP 2015506039A5
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JP
Japan
Prior art keywords
data
data bits
state
masked
bit pattern
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JP2014547436A
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English (en)
Japanese (ja)
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JP2015506039A (ja
JP5947398B2 (ja
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Priority claimed from US13/325,648 external-priority patent/US8726139B2/en
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Publication of JP2015506039A publication Critical patent/JP2015506039A/ja
Publication of JP2015506039A5 publication Critical patent/JP2015506039A5/ja
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Publication of JP5947398B2 publication Critical patent/JP5947398B2/ja
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JP2014547436A 2011-12-14 2012-12-13 統合データマスキング、データポイズニング及びデータバス反転シグナリング Active JP5947398B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/325,648 2011-12-14
US13/325,648 US8726139B2 (en) 2011-12-14 2011-12-14 Unified data masking, data poisoning, and data bus inversion signaling
PCT/US2012/069541 WO2013090599A1 (en) 2011-12-14 2012-12-13 Unified data masking, data poisoning, and data bus inversion signaling

Publications (3)

Publication Number Publication Date
JP2015506039A JP2015506039A (ja) 2015-02-26
JP2015506039A5 true JP2015506039A5 (https=) 2016-02-04
JP5947398B2 JP5947398B2 (ja) 2016-07-06

Family

ID=47472088

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014547436A Active JP5947398B2 (ja) 2011-12-14 2012-12-13 統合データマスキング、データポイズニング及びデータバス反転シグナリング

Country Status (6)

Country Link
US (1) US8726139B2 (https=)
EP (1) EP2791809B1 (https=)
JP (1) JP5947398B2 (https=)
KR (1) KR101879708B1 (https=)
CN (1) CN103988192B (https=)
WO (1) WO2013090599A1 (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8677211B2 (en) * 2010-12-23 2014-03-18 International Business Machines Corporation Data bus inversion using spare error correction bits
US20130117593A1 (en) * 2011-11-07 2013-05-09 Qualcomm Incorporated Low Latency Clock Gating Scheme for Power Reduction in Bus Interconnects
US9529749B2 (en) 2013-03-15 2016-12-27 Qualcomm Incorporated Data bus inversion (DBI) encoding based on the speed of operation
US9864536B2 (en) * 2013-10-24 2018-01-09 Qualcomm Incorporated System and method for conserving power consumption in a memory system
US9383809B2 (en) 2013-11-13 2016-07-05 Qualcomm Incorporated System and method for reducing memory I/O power via data masking
US9270417B2 (en) 2013-11-21 2016-02-23 Qualcomm Incorporated Devices and methods for facilitating data inversion to limit both instantaneous current and signal transitions
US9817738B2 (en) * 2015-09-04 2017-11-14 Intel Corporation Clearing poison status on read accesses to volatile memory regions allocated in non-volatile memory
US9922686B2 (en) * 2016-05-19 2018-03-20 Micron Technology, Inc. Apparatuses and methods for performing intra-module databus inversion operations
US10754970B2 (en) * 2017-01-27 2020-08-25 International Business Machines Corporation Data masking
US11237729B1 (en) 2020-10-13 2022-02-01 Sandisk Technologies Llc Fast bus inversion for non-volatile memory
US12235720B2 (en) 2020-12-26 2025-02-25 Intel Corporation Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)
KR20230046362A (ko) 2021-09-29 2023-04-06 삼성전자주식회사 메모리 모듈의 동작 방법, 메모리 컨트롤러의 동작 방법, 및 메모리 시스템의 동작 방법
US11822484B2 (en) * 2021-12-20 2023-11-21 Advanced Micro Devices, Inc. Low power cache
US12050784B2 (en) * 2022-04-27 2024-07-30 Micron Technology, Inc. Data masking for memory

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6898648B2 (en) * 2002-02-21 2005-05-24 Micron Technology, Inc. Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
JP2004207942A (ja) * 2002-12-25 2004-07-22 Sony Corp データ転送装置とデータ転送方法
US8201071B2 (en) * 2006-11-15 2012-06-12 Qimonda Ag Information transmission and reception
US8245087B2 (en) 2007-03-26 2012-08-14 Cray Inc. Multi-bit memory error management
US7616133B2 (en) * 2008-01-16 2009-11-10 Micron Technology, Inc. Data bus inversion apparatus, systems, and methods
US8363707B2 (en) * 2008-03-21 2013-01-29 Micron Technology, Inc. Mixed-mode signaling
US8223042B2 (en) * 2008-04-02 2012-07-17 Rambus Inc. Encoding data with minimum hamming weight variation
US8498344B2 (en) * 2008-06-20 2013-07-30 Rambus Inc. Frequency responsive bus coding
US8271747B2 (en) 2008-07-31 2012-09-18 Rambus Inc. Mask key selection based on defined selection criteria
KR20100053202A (ko) * 2008-11-12 2010-05-20 삼성전자주식회사 Ｒｄｂｉ 기능을 지원하는 반도체 메모리 장치 및 그 테스트 방법
EP2894571B1 (en) * 2009-07-13 2017-03-08 Rambus Inc. Encoding data using combined data mask and data bus inversion
KR101688050B1 (ko) * 2009-12-22 2016-12-21 삼성전자 주식회사 반도체 장치 및 반도체 장치의 리드 또는 라이트 동작 수행 방법
US8260992B2 (en) * 2010-04-12 2012-09-04 Advanced Micro Devices, Inc. Reducing simultaneous switching outputs using data bus inversion signaling
US8706958B2 (en) * 2011-09-01 2014-04-22 Thomas Hein Data mask encoding in data bit inversion scheme
US8495437B2 (en) * 2011-09-06 2013-07-23 Samsung Electronics Co., Ltd. Semiconductor memory device

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