JP2015233163A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure capable of improving adhesion of an insulation film provided on a lateral face of a semiconductor substrate where a semiconductor element is formed on one principal surface to the semiconductor substrate; and provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device comprises a single crystal silicon substrate 10 which has a principal surface 18 equipped with a semiconductor element 20, a rear face 19 opposite to the principal surface and a lateral face 21 including a processed surface 12 and a processed surface 14 each covered with encapsulation resin 60, for connecting the principal surface 18 and a bottom surface 19. The processed surface 12 has a crystal surface which is connected to an edge line 13 of an end face 11 with one side being connected to the rear face 19 and which has a plane direction forming an angle within a range of -5°-+5° with a plane direction of the principal surface 18. The processed surface 14 is connected to the processed surface 12 obtusely and has a crystal surface.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a wafer level chip size package (W-CSP) and a method for manufacturing the same.

  In recent years, as a representative example of mobile devices such as mobile phones and personal digital assistants, there is a strong demand from the industry to achieve further miniaturization, thickness reduction, and weight reduction while promoting higher performance. Of course, there is a need to reduce the size, thickness and weight of individual semiconductor devices (semiconductor packages) on module boards mounted on these devices, and one of the leading means to achieve this is W- CSP technology.

  In this W-CSP technology, on a semiconductor element having various functions such as a diode and a transistor formed on a silicon wafer or a compound semiconductor wafer, a connection terminal for electrical connection with a module substrate is provided, and an electric signal is transmitted to a semiconductor. This is a technique for completing package processing by forming the wafer directly in the wafer state without using a gold wire (wire bond) for drawing out from the apparatus, and then, for example, by using a dicing saw. By using this W-CSP technology, the mounting area and weight can be reduced to 1/10 or less as compared with the conventional package using dice bond / wire bond. Thus, in response to the reduction in package size (downsizing, thinning, and weight reduction), the W-CSP technology provides a connection terminal for a module substrate directly above an active region in which semiconductor elements such as diodes and transistors are formed. Since it is formed directly, it has an excellent feature that an essentially wasted area is extremely small. Further, since the terminal formation is performed in the wafer state, the productivity is very excellent.

  FIG. 11 is a schematic cross-sectional view for explaining a conventional method for forming a W-CSP. An interlayer insulating film 30 is formed on the single crystal silicon substrate 10 on which semiconductor elements having various functions such as diodes and transistors are formed, and via via holes (not shown) provided in the interlayer insulating film 30 on the interlayer insulating film 30. Then, a metal pad 36 connected to the semiconductor element is formed, a passivation film 38 is formed thereon, and a via hole (not shown) exposing the metal pad 36 is formed in the passivation film 38. This is the so-called pre-process.

  Thereafter, an insulating film 40 of polyimide or the like is formed, and a via hole (not shown) exposing the metal pad 36 is formed in the insulating film 40. Thereafter, the metal rewiring 44 is formed on the insulating film 40, and the metal rewiring 44 is connected to the metal pad via the via hole (not shown) formed in the insulating film 40 and the via hole (not shown) formed in the passivation film 38. 36 is connected. Thereafter, a metal post 46 is formed on the metal rewiring 44, a sealing resin 50 is then formed, and then a solder terminal 48 is formed on the metal post 46. Thereafter, the sealing resin 50 and the single crystal silicon substrate 10 are diced by a dicing blade 90.

  However, as shown in FIG. 12, in the W-CSP, the diced side surface after forming the sealing resin 50 becomes the final side surface of the package as it is, and thus has some weak points. One of them is the problem of moisture absorption from the side of the package. As shown in FIG. 12, the interlayer insulating film 30 is exposed on the side surface of the package after dicing. This interlayer insulating film 30 is a silicon oxide film formed mainly by plasma CVD or atmospheric pressure CVD, and its moisture resistance is higher than that of a silicon nitride film used for a passivation film or a mold resin used for sealing. Is significantly inferior.

  In order to prevent moisture absorption through the interlayer insulating film 30 on the side wall of the package, a dicing cut is made in the middle of the single crystal silicon substrate 10 (half cut) in the region where the interlayer insulating film 30 is exposed before sealing with the mold resin. A structure and a manufacturing method for preventing the exposure of the interlayer insulating film 30 by subsequent resin sealing have been proposed in the following patent documents.

JP-A-10-79362 JP 2000-260910 A JP 2006-1000053 A

  In these techniques, since the interlayer insulating film 30 exposed on the side wall of the package is covered with the mold resin, there is a problem in adhesion and the like.

  Accordingly, a main object of the present invention is to provide a semiconductor device having a structure capable of improving the adhesion of a mold resin provided on a side surface of a semiconductor substrate having a semiconductor element formed on one main surface to the semiconductor substrate, and a method for manufacturing the same. There is.

According to a first aspect of the invention,
A main surface including a semiconductor element, a bottom surface facing the main surface, a first surface and a second surface each covered with a first insulator, and a side surface connecting the main surface and the bottom surface A semiconductor device comprising a semiconductor single crystal substrate having:
The side surface includes a third surface having one side connected to the bottom surface,
The first surface is connected to the other side of the third surface opposite to the one side, and has a surface orientation that forms an angle between −5 ° to + 5 ° with the surface orientation of the main surface. With crystal face,
The semiconductor device is provided, wherein the second surface is connected to the first surface at an obtuse angle and has a crystal plane.

  In this way, the adhesion of the first insulator to the semiconductor substrate can be improved. Therefore, according to the first aspect, the problem of improving the adhesion of the first insulator to the semiconductor substrate can be solved.

  Preferably, the first surface is a surface having a surface orientation that forms an angle between −3.5 ° and + 3.5 ° with the surface orientation of the main surface.

  Preferably, the first surface is a surface having the same surface orientation as the surface orientation of the main surface.

  Preferably, the side surface includes a fourth surface that is covered with the first insulator and connects the main surface and the second surface.

  In addition, preferably, a second insulator covering the main surface is further provided, and the first insulator covers an end portion of the second insulator.

  Preferably, a sealing resin for covering the second insulator is further provided, and the first insulator covers an end portion of the sealing resin.

  Preferably, the apparatus further includes a metal rewiring provided on the main surface and electrically connected to the semiconductor element, and an external connection terminal provided in connection with the metal rewiring.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device of the structure which can improve the adhesiveness with respect to the semiconductor substrate of the insulating film provided in the side surface of the semiconductor substrate in which the semiconductor element was formed in the main surface, and its manufacturing method are provided.

FIG. 1 is a schematic perspective view for explaining a semiconductor device according to a preferred embodiment of the present invention. 2 is a cross-sectional view taken along line XX of FIG. FIG. 3 is a schematic longitudinal sectional view for explaining the structure and manufacturing method of the semiconductor device according to the preferred embodiment of the present invention. 4 is a partially enlarged schematic cross-sectional view of a portion A in FIG. FIG. 5 is an SEM photograph of a portion corresponding to FIG. FIG. 6 is a schematic longitudinal sectional view for explaining a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention. FIG. 7 is a process diagram for explaining a method of manufacturing a semiconductor device according to a preferred embodiment of the present invention. FIG. 8A is a schematic longitudinal sectional view for explaining the method for manufacturing the semiconductor device according to the preferred embodiment of the present invention. FIG. 8B is a schematic longitudinal sectional view for explaining the method for manufacturing the semiconductor device according to the preferred embodiment of the present invention. FIG. 8C is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the preferred embodiment of the present invention. FIG. 8D is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the preferred embodiment of the present invention. FIG. 8E is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the preferred embodiment of the present invention. FIG. 8F is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the preferred embodiment of the present invention. FIG. 8G is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the preferred embodiment of the present invention. FIG. 8H is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the preferred embodiment of the present invention. FIG. 8I is a schematic longitudinal sectional view for explaining the method for manufacturing the semiconductor device according to the preferred embodiment of the present invention. FIG. 8J is a schematic longitudinal sectional view for illustrating the method for manufacturing the semiconductor device according to the preferred embodiment of the present invention. FIGS. 9A and 9B are a schematic longitudinal sectional view and a schematic plan view for explaining a method for measuring the bending strength of the structure according to the preferred embodiment of the present invention and the conventional structure, respectively. is there. FIG. 10 is a diagram showing the maximum load in the bending strength evaluation of the structure according to the preferred embodiment of the present invention and the conventional structure. FIG. 11 is a schematic longitudinal sectional view for explaining a conventional method for manufacturing a semiconductor device. FIG. 12 is a schematic longitudinal sectional view for explaining a semiconductor device manufactured by the conventional method of manufacturing a semiconductor device shown in FIG.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  Referring to FIGS. 1 and 2, in the W-CSP 100 which is the semiconductor device of the present embodiment, a semiconductor element 20 having various functions such as a diode and a transistor is formed on one main surface 18 of the single crystal silicon substrate 10. ing. An interlayer insulating film 30 is formed on one main surface 18 of the single crystal silicon substrate 10. A via hole 32 is provided in the interlayer insulating film 30. A metal pad 36 connected to the semiconductor element 20 via a buried electrode 34 provided in the via hole 32 is formed on the interlayer insulating film 30. A passivation film 38 is formed on the interlayer insulating film 30 so as to cover the metal pad 36. The passivation film 38 is provided with a via hole 39 that exposes the metal pad 36. On the passivation film 38, an insulating film 40 such as polyimide is provided. The insulating film 40 is provided with a via hole 42 that communicates with the via hole 39 and is connected to the metal pad 36. A metal rewiring 44 connected to the metal pad 36 via the via hole 42 and the via hole 39 is provided on the insulating film 40. A metal post 46 is provided on the metal rewiring 44. On the insulating film 40, a sealing resin 50 for embedding the metal post 46 is provided. Solder terminals 48 are exposed from the sealing resin 50 on the metal posts 46. The solder terminal 48 is used as a connection terminal for electrical connection with a module substrate (not shown).

  The single crystal silicon substrate 10 includes a main surface 18, a bottom surface 19, and four side surfaces 21. In this embodiment, a (100) substrate is used, and the main surface 18 and the bottom surface 19 are (100) planes. The side surface 21 includes an end surface 11, a processed surface 12, a processed surface 14, and a processed surface 16 in order from the bottom surface side. As will be described later, the end surface 11 is a surface cut by a dicing blade 94 (see FIG. 8J) and is substantially perpendicular to the main surface 18. The processed surfaces 12, 14, and 16 are surfaces formed by anisotropically etching the half-cut groove 70 formed by the dicing blade 92 (see FIG. 8D) with a KOH aqueous solution, as will be described later. The processing surface 12 is a (100) surface and is a surface parallel to the main surface 18. The processing surface 14 is a (111) surface, and the angle θ formed with the processing surface 12 is about 125 °. The processing surface 16 is a (110) surface and is a surface perpendicular to the main surface 18. Note that the end portion 13 of the processed surface 12 is a line cut by a dicing blade 94 (see FIG. 8J), and is an end portion of a boundary between the side surface 21 and the sealing resin 50.

  In the present embodiment, the processed surfaces 12, 14, 16, the end surface 31 of the interlayer insulating film 30, and the end surface 51 of the sealing resin 50 are covered with the sealing resin 60.

  Since the processing surface 12 is a (100) surface and is a surface parallel to the main surface 18, stress concentration based on a difference in thermal expansion coefficient between the single crystal silicon substrate 10 and the sealing resin 60 is reduced. it can. Furthermore, since the processing surface 14 that forms an angle of about 125 ° with the processing surface 12 is formed inside the processing surface 12, the stress can be further relaxed. The width of the processed surface 12 is preferably 2 to 15 μm. If it is less than 2 μm, it is difficult to control from the viewpoint of processing accuracy. If it exceeds 15 μm, it is necessary to expand the half-cut width A and make the Si etching amount less than 15 μm, which increases restrictions on grid line dimensions and makes it difficult to obtain sufficient substrate strength. .

  The end surface 31 of the interlayer insulating film 30 and the end surface 51 of the sealing resin 50 are surfaces cut by a dicing blade 92 (see FIG. 8D), as will be described later. In the state where the side surface of the single crystal silicon substrate 10 thereunder was also cut off by the dicing blade 92 (see FIG. 8D), the end surface 31 and the end surface 51 were flush, but by anisotropic etching with a KOH aqueous solution, The crystal plane (110) appears and moves inward by a distance d. The sealing resin 60 covering the processed surface 16 also extends inward from the end surface 31 and the end surface 51 by this distance d.

  As the sealing resin 60, a resin different from the sealing resin 50 is used, and a resin having good adhesion is used. Further, since the sealing resin 60 has bitten inward by the distance d, the adhesion in the <110> direction is further increased. As a result, in particular, it is possible to more effectively suppress or prevent moisture from entering from the end face 31 between the interlayer insulations 30 and to further improve the moisture resistance. The distance d is preferably 1 to 10 μm. Since the etching rate of the Si (110) surface with respect to KOH is substantially equal to that of the Si (100) surface, the preferred range of the distance d corresponds to the preferred range of the depth α on a one-to-one basis. With respect to etching of 1 μm of Si, the bending strength of the substrate is approximately doubled, and a sufficient strength can be expected. In addition, an effect of increasing the adhesion can be expected. On the other hand, when the thickness exceeds 10 μm, the improvement of the substrate strength is almost saturated, and it becomes difficult to secure the Si (111) surface-processed surface 12. When Si is etched by 1 μm, the processed surface 12 becomes narrower by 0.7 μm.

  3 and 4, the bottom and side portions of the half-cut groove 70 formed by anisotropic etching of the half-cut groove 70 formed by the dicing blade 92 (see FIG. 8D) with an aqueous KOH solution are illustrated. The shape is shown schematically.

  As described above, the shape of the half-cut bottom, that is, the processed surface 12 in FIG. 4 is parallel to the main surface 18 of the Si substrate. When the Si (100) substrate is used, the processed surface 12 is an Si (100) surface, and the shapes of the side portions constituted by the processed surface 16 and the processed surface 14 are Si (110) surface and Si (110), respectively. 111) plane. At this time, if the machining surface angle θ formed by the machining surface 14 and the machining surface 12 is defined as shown in FIG. 4, the machining surface angle θ = 180 ° −about 55 ° = about 125 °. Further, the processed surface 16 has a shape that enters (intrudes into) the active region side from the processed surface at the time of half-cut formation (end surface 51 of the sealing resin). In addition, the processed surface 12 remains after singulation processing (full cut).

  An SEM photograph of the prototype result is shown in FIG. There is no round shape at the bottom as shown in FIG. 17 as a conventional example, and as described above, the processed surface is characterized by the crystal plane of the substrate, and the processed surface 16 is indented inside the sealing resin edge. It has been realized.

  The planar structure in the present embodiment will be described in more detail with reference to FIG. About the half cut and full cut in a figure, the case where it forms using a diamond blade is demonstrated, respectively. However, this embodiment does not essentially depend on the half-cut and full-cut forming methods.

  The scribe line width (here, defined as the distance between the passivation films 38) is L, the first dicing width (width of the half-cut groove 70) is A, the half-cut depth entering the silicon substrate is H, and the second time. Dicing width (width of full cut groove 72) is B, clearance distance between half cut groove 70 and full cut groove 72 is W (here, defined as grip width), and silicon etching amount generated by processing after half cut (Here, defined as the depth from the bottom of the half cut) is defined as α, and the surface formed by the processing and characterized by the Si (111) surface is defined as the processed surface 14, and the scribe line and the first dicing are defined. It is desirable to secure an interval of (L−A) / 2 = about 5 to 10 μm. If the spacing is narrower than 5 μm, dicing may affect the element region (the region inside the end portion 37 of the passivation film 38) due to manufacturing variation factors such as variations in dicing groove width and misalignment during dicing. There is. When the interval is 10 μm or more, it is practically difficult to secure the grip width W defined here with a finite value. Further, it is desirable to secure a grip width W of about W = (A−B) / 2 = 10 μm or more. At this time, the maximum value α of the Si etching amount in the post-processing is α (maximum value) = (LA) / 2 when H × tan 35 °> (LA) / 2, and H × tan 35 ° <= (LA) / 2 or less, α (maximum value) = W / (tan 35 °) = less than about 1.43 × W μm. In the former case, when the silicon substrate 10 of (LA) / 2 μm or more is etched, the side etch region reaches the element region. In the latter case, when the silicon substrate 10 of about 1.43 × W μm or more is etched, the processed surface 12 (Si (100) surface) disappears due to the second dicing (full cut).

  In the case where the bottom shape after the half-cut groove 70 is formed by the dicing blade and before the etching is not a rectangle as shown in FIG. 6 (as shown in FIG. 15) but a round shape as shown in FIG. The processed surface 14 (Si (111) surface) generated by etching of the silicon substrate is shifted so as to circumscribe the round shape, and the maximum value α of the etching amount of the silicon substrate becomes larger (the chamfer amount increases). ), The blade shape used for half-cut is preferably closer to a rectangle.

  Next, the manufacturing method of this Embodiment is demonstrated with reference to the manufacturing flow of FIG. 7, and the cross-sectional flowchart of FIG. The manufacturing method is roughly divided into four steps. A semiconductor element 20 such as a diode or a transistor is formed on the main surface 18 of the silicon substrate 10, and then a metal pad 36 for external connection is formed on the main surface 18. A first step of forming a passivation film 38 (generally referred to as a semiconductor pre-process), a solder terminal 48 (to be described later) and a metal for electrically connecting to the module substrate on the passivation film 38 A second step of forming the metal rewiring 44 and the metal post 46 for electrically relaying the pad 36; and a third step of forming a sealing resin 50 covering the metal rewiring 44 and the metal post 46. The fourth step is to finish the thickness of the sealing resin 50 and the thickness of the silicon substrate 10 to desired thicknesses and finally separate them into individual pieces.

  First, a 1st process is demonstrated (step S1). As shown in FIG. 8A, a semiconductor element 20 such as a diode or a transistor is formed on the main surface 18 of the single crystal silicon substrate 10, and then an interlayer insulating film 30 is formed on the main surface 19 of the single crystal silicon substrate 10. A via hole 32 is provided in the interlayer insulating film 30, the via hole 32 is filled with a buried electrode 34, and the external connection is made on the interlayer insulating film 30 and connected to the semiconductor element 20 via the buried electrode 34 provided in the via hole 32. The metal pad 36 is formed. Thereafter, a passivation film 38 is formed so as to cover the metal pad 36, and a via hole 39 exposing the metal pad 36 is formed in the passivation film 38. The process so far is a so-called pre-process.

  Thereafter, an insulating film 40 such as polyimide is formed, and a via hole 42 exposing the metal pad 36 is formed in the insulating film 40. Thereafter, the metal rewiring 44 is formed on the insulating film 40, and the metal rewiring 44 is connected to the metal pad 36 through the via hole 42 formed in the insulating film 40 and the via hole 39 formed in the passivation film 38. Thereafter, a metal post 46 is formed on the metal rewiring 44. (Step S2)

  Thereafter, as shown in FIG. 8B, a first sealing resin 50 is formed so as to cover the metal rewiring 44 and the metal post 46 (step S31). The sealing resin 50 can be formed by press-fitting using a mold, spin coating, spray coating, screen printing, or the like.

  Thereafter, as shown in FIG. 8C, the first resin grinding is performed (step S32).

  In this first resin grinding, it is preferable to cue the metal post 46 and stop it shallower (final resin thickness) than the final resin film thickness. However, when the sealing resin 50 is a resin transparent to visible light, the first resin grinding is not necessarily required.

  By making the sealing resin 50 into a thin film in advance and exposing the surface of the metal post 46 on the sealing resin 50, the alignment accuracy at the time of dicing (half-cut) in the next process is improved, and the second sealing resin It becomes possible to improve the embedding property.

  Next, as shown in FIG. 8D, a dicing blade 92 is used to form a half cut groove 70 for embedding the second resin along the scribe line on the semiconductor substrate 10 (step S33). However, the effect of the present embodiment is that when the half-cut groove 70 is formed, that is, after the sealing resin 50 is formed in advance, the half-cut groove 70 is formed, or the half-cut groove 70 is formed in advance. After forming, essentially does not depend on whether the sealing resin 50 is formed, and is effective in either case.

  It is essential that the depth of the half-cut groove 70 is deeper than that of the interlayer insulating film 30. As a preferable example, the bottom of the half-cut groove 70 is the surface (main surface) of the silicon substrate on which the semiconductor element 20 is formed. 18) to 50 to 200 μm. If the depth is 50 μm or more, it is possible to stably form a groove deeper than the interlayer insulating film 30 in the manufacturing process. By setting the depth to 200 μm or less, it is possible to maintain sufficient wafer strength during manufacturing. Thus, it is possible to suppress wafer cracking caused by the half-cut groove 70 in the subsequent process. In addition, it is essential that the width of the half-cut groove 70 be wider than the width of the subsequent second dicing (full cut) (AB> 0: see FIG. 6). As described above, (AB) / 2 is desirably about 10 μm or more.

  After the formation of the half-cut groove 70, as shown in FIG. 8E, a processing for making the bottom and side walls of the half-cut groove 70 into the shapes shown in FIGS. 4 and 5 is performed (step S34).

For this processing, potassium hydroxide (KOH), sodium hydroxide (NaOH), TMAH (tetramethylammonium hydroxide), or hydrazine (N ₂ H ₄ ) can be used. In wet etching of a single crystal silicon substrate using these etchants, the etching rate of the (111) plane is extremely small compared to other planes, for example, the (100) plane and the (110) plane, so anisotropic etching is performed. It can be carried out.

  In view of the use in the semiconductor production line, KOH treatment is the easiest to handle among these etchants, and a KOH aqueous solution was used in the prototype of this embodiment. The KOH aqueous solution selectively etches only the silicon substrate (100) surface and the (110) surface, and does not corrode other sealing resins, metal posts (for example, Cu), silicon nitride films, etc. (having a sufficient selection ratio). 5), the shape of FIG. 5 can be obtained.

  As an example, when the scribe line width is about 80 μm, the width of the half-cut groove 70 is about 60 μm, the silicon etching amount (Si (100) plane etching rate conversion) is about 1 to 10 μm, and the full-cut groove 72 (see FIG. 8J). It is preferable that the width of this is about 40 μm. At this time, after dicing (full cut), the shapes of the half-cut bottom part and the side wall part described with reference to FIGS. 4 and 5 can be realized.

  Thereafter, as shown in FIG. 8F, the second sealing resin 60 is formed in the half-cut groove 70 subjected to the etching process (step S35). For this method, a production method in which a large pressure is not applied to the silicon substrate, such as screen printing, dispensing method, spin coating method, spray coating method or the like is preferable. FIG. 8F shows a case where screen printing is used.

  Thereafter, as shown in FIG. 8G, a second resin grinding is performed to obtain a desired resin thickness (step S41). At this time, unnecessary resin other than embedding the half-cut groove 70 is ground and removed by the second sealing resin 60.

  Next, as shown in FIG. 8H, the silicon substrate 10 is ground to finish the silicon substrate 10 to a desired thickness (step S42).

  Next, as shown in FIG. 8I, after forming the solder terminal 48 on the metal post 46 (step D43), as shown in FIG. 8J, a dicing groove 72 is formed using a dicing blade 94, and the semiconductor By performing dicing (full cut) for dividing the device into pieces (step S44), packaging of the semiconductor device is completed.

  In the present embodiment described above, the stress concentrated on the bottom of the half-cut groove 70 is reduced for several minutes by changing the shape of the bottom of the half-cut groove 70 from the conventional shape of FIG. 16 to the shape of FIG. 1 can be relaxed. Further, the shape of the bottom of the half-cut groove 70 is changed from a complete rectangle (working surface angle 90 °) in FIG. 15 to an obtuse angle larger than 90 ° (about 125 ° in this embodiment) as shown in FIG. By doing so, it becomes possible to further relax the maximum stress. In addition, since the processed surface 16 is moved inward by etching, the grip region in the Si <110> axial direction is expanded, and the second sealing resin 60 formed in the grip region is formed on the semiconductor substrate 10. Therefore, the anchor effect improves the adhesion between the second sealing resin 60 and the semiconductor substrate 10.

  Further, as a secondary effect by the etching processing for realizing the configuration of the present embodiment, defects and microcracks introduced into the silicon substrate 10 when the half cut groove 70 is formed can be removed by etching. It becomes possible to dramatically increase the mechanical strength inherent to it.

  In order to prove the improvement in strength, a half-cut groove 70 is formed using a dicing blade 92 in FIG. 10, and a half-cut groove 70 is formed using a conventional structure that is not subjected to an etching process and the dicing blade 92. Then, a comparison result of mechanical strength (bending strength) with the structure of the present embodiment which has been subjected to etching treatment is shown. It was confirmed that the structure of the present embodiment has a mechanical strength three times or more that of the conventional structure. As a result, the mechanical strength of the silicon substrate 10 is greatly improved, and cracks in the silicon substrate 10 can be suppressed even in an environment where a temperature cycle after packaging is applied. As shown in FIG. 9, the bending strength is measured on a main surface 18 of a silicon substrate 10 having a length of 6.4 mm, a width of 4.8 mm, and a thickness of 0.72 mm. A sample having a conventional structure in which a half-cut groove 70 is formed using a dicing blade 92 in the center of the one in which the stop resin 50 is formed is used as a sample having a conventional structure, and a sample obtained by further etching is used as a sample in this embodiment. The depth of the half cut groove 70 with respect to the silicon substrate was 60 μm, and the width of the half cut groove 70 was 60 μm.

  The side of the sample prepared in this way, on which the sealing resin 50 is formed, is the lower side, supported by two fulcrums 82 having a distance between fulcrums of 3.00 mm, and the load blade 81 for applying a linear load is lowered at a speed of 1 mm / min. It was moved to the side and measured.

DESCRIPTION OF SYMBOLS 10 Single crystal silicon substrate 11 End surface 12 Processing surface 13 Edge line 14 Processing surface 16 Processing surface 18 Main surface 19 Main surface 19 Back surface 20 Semiconductor element 21 Side surface 30 Interlayer insulation film 31 End surface 32 Via hole 34 Embedded electrode 36 Metal pad 37 End part 38 Passivation film 39 Via hole 40 Insulating film 42 Via hole 44 Metal rewiring 46 Metal post 48 Solder terminal 50 Sealing resin 51 End surface 60 Sealing resin 70 Half cut groove 72 Full cut groove 81 Load blade 82 Support point 90, 92, 94 Dicing blade 100 W- CSP

Claims (7)

A main surface including a semiconductor element, a bottom surface facing the main surface, a first surface and a second surface each covered with a first insulator, and a side surface connecting the main surface and the bottom surface A semiconductor device comprising a semiconductor single crystal substrate having:
The side surface includes a third surface having one side connected to the bottom surface,
The first surface is connected to the other side of the third surface opposite to the one side, and has a surface orientation that forms an angle between −5 ° to + 5 ° with the surface orientation of the main surface. With crystal face,
The second surface is connected to the first surface at an obtuse angle and includes a crystal plane;
A semiconductor device.   2. The semiconductor device according to claim 1, wherein the first surface is a surface having a surface orientation that forms an angle of −3.5 ° to + 3.5 ° with the surface orientation of the main surface.   The semiconductor device according to claim 1, wherein the first surface is a surface having the same surface orientation as that of the main surface. The side surface
4. The semiconductor device according to claim 1, further comprising a fourth surface that is covered by the first insulator and connects the main surface and the second surface. 5. A second insulator covering the main surface;
5. The semiconductor device according to claim 1, wherein the first insulator covers an end portion of the second insulator. 6. A sealing resin that covers the second insulator;
The semiconductor device according to claim 5, wherein the first insulator covers an end portion of the sealing resin.   The metal rewiring provided on the main surface and electrically connected to the semiconductor element, and an external connection terminal provided in connection with the metal rewiring, further comprising: The semiconductor device described.