JP2015222520A5 - - Google Patents

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Publication number
JP2015222520A5
JP2015222520A5 JP2014106919A JP2014106919A JP2015222520A5 JP 2015222520 A5 JP2015222520 A5 JP 2015222520A5 JP 2014106919 A JP2014106919 A JP 2014106919A JP 2014106919 A JP2014106919 A JP 2014106919A JP 2015222520 A5 JP2015222520 A5 JP 2015222520A5
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JP
Japan
Prior art keywords
calculation
units
output data
arithmetic
calculation units
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JP2014106919A
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Japanese (ja)
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JP6600128B2 (en
JP2015222520A (en
Filing date
Publication date
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Priority to JP2014106919A priority Critical patent/JP6600128B2/en
Priority claimed from JP2014106919A external-priority patent/JP6600128B2/en
Priority to GB1506268.0A priority patent/GB2526917B/en
Priority to DE102015208989.4A priority patent/DE102015208989A1/en
Priority to CN201510260992.6A priority patent/CN105093979B/en
Publication of JP2015222520A publication Critical patent/JP2015222520A/en
Publication of JP2015222520A5 publication Critical patent/JP2015222520A5/ja
Application granted granted Critical
Publication of JP6600128B2 publication Critical patent/JP6600128B2/en
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Claims (6)

同時に同一の演算を行い、かつ相互に出力データを監視する機能を有する複数の演算部と、
前記演算部毎の出力データを一時記憶し、前記複数の演算部のいずれかからの指示により前記一時記憶した演算部毎の出力データを外部に出力する機能を有する出力制御部と、
前記演算部毎に設ける複数の電源と
を備え、
前記複数の電源のいずれかは、対応する前記演算部に加えて前記出力制御部にも電力を供給する
ことを特徴とするフェールセーフ演算装置。 A plurality of calculation units having the function of simultaneously performing the same calculation and mutually monitoring output data;
An output control unit that temporarily stores output data for each of the calculation units, and has a function of outputting the output data for each of the calculation units temporarily stored according to an instruction from any of the plurality of calculation units;
A plurality of power supplies provided for each of the arithmetic units,
Any one of the plurality of power supplies supplies power to the output control unit in addition to the corresponding calculation unit. 請求項１に記載のフェールセーフ演算装置であって、
前記複数の電源の中で少なくとも一つの電源を他の電源と異なる電源容量にする
ことを特徴とするフェールセーフ演算装置。 The fail-safe arithmetic device according to claim 1,
A fail-safe arithmetic device characterized in that at least one of the plurality of power sources has a power capacity different from that of other power sources. 請求項１または請求項２に記載のフェールセーフ演算装置であって、
前記複数の演算部のいずれかは、相互に監視する前記出力データが一致する場合に前記出力制御部に対して前記指示を出す
ことを特徴とするフェールセーフ演算装置。 The fail-safe arithmetic device according to claim 1 or 2,
Any of the plurality of arithmetic units outputs the instruction to the output control unit when the output data to be monitored match each other. 請求項１から請求項３のいずれか１項に記載のフェールセーフ演算装置であって、
前記複数の演算部それぞれは、他の前記複数の演算部に対してリセット信号を送信する機能を有する
ことを特徴とするフェールセーフ演算装置。 A failsafe arithmetic unit according to any one of claims 1 to 3,
Each of the plurality of calculation units has a function of transmitting a reset signal to the other plurality of calculation units. 請求項４に記載のフェールセーフ演算装置であって、
前記複数の演算部それぞれは、相互に監視する前記出力データが不一致の場合に前記リセット信号を送信する
ことを特徴とするフェールセーフ演算装置。 The fail-safe arithmetic device according to claim 4,
Each of the plurality of arithmetic units transmits the reset signal when the output data monitored with each other does not coincide with each other. 請求項４または請求項５に記載のフェールセーフ演算装置であって、
前記複数の演算部それぞれは、前記リセット信号を受信すると自らの演算を停止する
ことを特徴とするフェールセーフ演算装置。
The failsafe arithmetic device according to claim 4 or 5, wherein
Each of the plurality of calculation units stops its calculation when it receives the reset signal.
JP2014106919A 2014-05-23 2014-05-23 Arithmetic processing unit Active JP6600128B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2014106919A JP6600128B2 (en) 2014-05-23 2014-05-23 Arithmetic processing unit
GB1506268.0A GB2526917B (en) 2014-05-23 2015-04-14 Fail-safe processing apparatus
DE102015208989.4A DE102015208989A1 (en) 2014-05-23 2015-05-15 Fail-safe processing device
CN201510260992.6A CN105093979B (en) 2014-05-23 2015-05-21 Failure safe arithmetic processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014106919A JP6600128B2 (en) 2014-05-23 2014-05-23 Arithmetic processing unit

Publications (3)

Publication Number Publication Date
JP2015222520A JP2015222520A (en) 2015-12-10
JP2015222520A5 true JP2015222520A5 (en) 2016-10-06
JP6600128B2 JP6600128B2 (en) 2019-10-30

Family

ID=53333722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014106919A Active JP6600128B2 (en) 2014-05-23 2014-05-23 Arithmetic processing unit

Country Status (4)

Country Link
JP (1) JP6600128B2 (en)
CN (1) CN105093979B (en)
DE (1) DE102015208989A1 (en)
GB (1) GB2526917B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110890884A (en) * 2018-09-10 2020-03-17 台湾积体电路制造股份有限公司 Fail-safe circuit, integrated circuit device, and method of controlling node of circuit

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04149743A (en) * 1990-10-15 1992-05-22 Mitsubishi Electric Corp Driving system for data processor
JPH06298105A (en) * 1993-04-15 1994-10-25 Nippondenso Co Ltd Rear wheel steering device control system
JP2001183490A (en) * 1999-12-22 2001-07-06 Hitachi Ltd Reactor core flow control system
JP2002116921A (en) 2000-10-06 2002-04-19 Matsushita Electric Ind Co Ltd Auxiliary device for central processing unit
US8143851B2 (en) * 2008-02-15 2012-03-27 Apple Inc. Power source having a parallel cell topology
JPWO2011068177A1 (en) * 2009-12-02 2013-04-18 日本電気株式会社 Redundant calculation system and redundant calculation method
JP2011198205A (en) * 2010-03-23 2011-10-06 Railway Technical Research Institute Redundant system control system
CN101996110B (en) * 2010-11-17 2012-12-19 中国航空工业集团公司第六三一研究所 Three-redundancy fault-tolerant computer platform based on modular structure

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