JP2015211392A - Band pass filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a band pass filter which can suppress the deterioration of attenuation, by making unnecessary a duty conversion circuit.SOLUTION: A 4-phase band pass filter includes: a load element 12 which converts an input current signal into an output voltage signal; an impedance element group 14 including four impedance elements Z141-Z144; and four switch groups 131-134. The switch groups 131-134 include four switches SW1311-SW1314, switches SW1321-SW1324, switches SW1331-SW1334 and switches SW1341-SW1344, respectively. The connection/non-connection of the switch SW1311, the switch SW1342 etc. is controlled by clocks LO1-LO8.

Description

  The present invention relates to a bandpass filter (bandpass filter; BPF), and more particularly, to a circuit technology of a reception system including a bandpass filter that can suppress deterioration of attenuation and attenuation of gain of a desired wave.

Conventionally, in a radio signal receiving system, a SAW filter (surface acoustic wave filter) is used between an antenna and a receiver to sufficiently demodulate a desired wave. There are many cases. This SAW filter is an element that takes out an electric signal in a specific frequency band by a regular comb-shaped electrode (IDT) formed on a piezoelectric thin film or substrate, and has a structure period of the comb-shaped electrode (IDT). The center frequency and band can be determined by the physical properties of the piezoelectric body and electrodes.
However, in order to reduce the size of the system and reduce the cost, a SAW filterless receiving system is desirable. In recent years, in a SAW filterless receiving system, many means using an M-phase bandpass filter in an IC chip have been adopted as an alternative to a SAW filter (for example, see Patent Document 1 and Non-Patent Document 1).

FIG. 7 is a circuit configuration diagram of a general M-phase bandpass filter. The M-phase bandpass filter 70 includes a load element 72 that converts an input current signal into a voltage signal and outputs the voltage signal, a switch group 73, and an impedance element group 74. The load element 72 may be an amplifier load element such as a low noise amplifier. The switch group 73 includes M switches SW731 to 73M. However, M is an integer of 2 or more.
The impedance element group 74 includes M impedance elements Z741 to Z74M. The switch SW73i connects the output signal and the impedance element Z74i. However, i is an integer of 1 to M. In the impedance element Z74i, the other terminal not connected to the switch SW73i is connected to the ground. The connection / disconnection of the switch SW73i is controlled by the M-phase clock LOi (LO71 to LO7M).

FIG. 8 is a timing chart of the M-phase clock group shown in FIG. The period of the M-phase clock LOi is T, and the High period is T / M, that is, a signal with a duty ratio of 100 / M%. Further, there is a T / M delay difference from each other, that is, the phases are shifted by 360 / M degrees.
For example, when the switch SW73i is configured with an NMOS transistor, the switch SW73i is in a connected state when the M-phase clock LO7i is High, and the switch SW73i is in a disconnected state when the M-phase clock LOi is Low. That is, none of SW731 to SW73M is connected at the same time, and one is always connected only for the T / M section.
Hereinafter, in order to show the characteristics of the M-phase bandpass filter, a case where M = 4 will be described as an example.
FIG. 9 is a circuit configuration diagram of a general four-phase bandpass filter. In the four-phase bandpass filter 80, the load element 72 in FIG. 7 is replaced with a load resistor 92, and the impedance element group 74 is replaced with a capacitor group 94 (941 to 944) composed of capacitors. SW931 to SW934 indicate switch groups, and LO91 to LO94 indicate four-phase clock groups.

FIG. 10 is a timing chart of a four-phase clock group that controls connection / disconnection of the four switch groups shown in FIG. The period of the four-phase clocks LO91 to LO94 is T, and the high period is T / 4, that is, a signal with a duty ratio of 25%. Further, there is a T / 4 delay difference from each other, that is, the phases are shifted by 90 degrees.
FIG. 11 is a diagram showing the frequency characteristics of the four-phase bandpass filter shown in FIG. The horizontal axis indicates the logarithmic scale frequency. The center frequency FLO of the pass band corresponds to the frequency of the four-phase clocks LO91 to LO94. The vertical axis represents the gain, the band has a first-order slope, and the gain is G0 at the center frequency. The frequencies Fc1 and Fc2 indicate frequencies that become a gain of G0-3 dB from the passband. FLO-Fc1 and Fc2-FLO are given by 1 / (2π × 4RC).

FIG. 12 is a circuit configuration diagram of a direct conversion type receiver using an M-phase bandpass filter. An RF (Radio Frequency) input voltage signal of the receiver 120 is input to the GM cell 121, converted into an RF current signal, input to the M-phase bandpass filter 70, and output as a mixer input signal input to the mixer. Is done. Here, the combination of the GM cell 121 and the load element 72 of the M-phase bandpass filter 70 may be considered as a low noise amplifier.
The mixer input signal is multiplied by the mixer local signal in the mixer 122, converted into a baseband signal, and output. At this time, the frequency of the mixer local signal corresponds to the carrier frequency of the RF input signal. In many cases, since a high frequency accuracy is required for a local signal used for a mixer of a receiver, an accurate frequency is generated using a Phase Locked Loop (PLL) circuit. Here, the mixer local signal is an output of the PLL circuit 124.

Since the signal generated by the high-frequency PLL circuit is often generated by dividing or amplifying a sine wave, the duty ratio of the local signal output from the PLL circuit 124 is 50%. Therefore, a Duty 50 M-phase clock having a Duty ratio of 50% is converted into a Duty ratio required for the M-phase bandpass filter 70 by the Duty conversion circuit 123, and an M-phase clock is obtained.
Since the frequency of the M-phase clock is the carrier frequency of the RF signal, the center frequency of the passband of the M-phase bandpass filter 70 is equivalent to the carrier frequency of the RF input signal with high accuracy. That is, the center frequency of the passband of the four-phase bandpass filter can be set with high accuracy.

When there are a plurality of frequency bands or channels of the RF input signal and the carrier frequency changes according to the frequency band or channel, the PLL circuit uses a synthesizer PLL circuit that can change the output frequency. In this case, since the frequency of the M-phase clock is always the carrier frequency, the center frequency of the pass band of the M-phase bandpass filter 70 is always the carrier frequency of the RF input signal.
As described above, the M-phase bandpass filter 70 can use a clock having the same frequency as that of a local signal used for a frequency converter of a normal receiver, has high frequency accuracy, and is suitable for a frequency band or channel. Since the center frequency of the pass band can be changed accordingly, it is a very effective means as a band pass filter for RF signals.

13 is a circuit configuration diagram of the duty conversion circuit shown in FIG. 12, and FIG. 14 is a timing diagram of the IQ local signal and four-phase clock shown in FIG. When M = 4, as shown in FIG. 10, each phase difference of the four-phase clock is 90 degrees. When the mixer 122 is an IQ orthogonal mixer, the mixer local signals are IQ local signals that are 90 degrees out of phase with each other.
The AND circuits 231 to 234 shown in FIG. 13 perform a logical product operation, and the output becomes High only when the two input levels are both High. The AND circuit 231 receives LQP and LIP and outputs LO 91, the AND circuit 232 receives LIP and LQN and outputs LO 92, and the AND circuit 233 receives LQN and LIN and LO 93. And LIN and LQP are input to the AND circuit 234 and LO94 is output.
At this time, the current consumption of the AND circuits 231 to 234 shown in FIG. 13 increases as the frequency of the local signal increases. In addition, when the waveform of the M-phase clock is dull, the switch-on time is deviated from 1 / M of the original clock cycle, causing deterioration of characteristics such as a decrease in attenuation. In order to obtain a sharp M-phase clock at a high frequency, a manufacturing cost increases, for example, a fine manufacturing process is required.

FIG. 15 is a circuit configuration diagram of a four-phase bandpass filter when the switches in FIG. 9 are connected in two stages in series. The four-phase bandpass filter 150 shown in FIG. 15 inputs LIP to the switches 1535 and 1532, inputs LIN to the switches 1537 and 1534, inputs LQP to the switches 1531 and 1538, and switches to the switches 1536 and 1538. LQN is input to 1533.
That is, the combination of local signals input to each of the AND circuits 131 to 134 shown in FIG. 13 and the appropriate combination of inputs to the two switches connected in series shown in FIG. 15 are the same. The output signal and the impedance element are connected only when the local signals input to the two switches connected in series simultaneously become High. Therefore, an operation equivalent to that using a four-phase clock can be achieved without using a four-phase clock generation circuit. By eliminating the need for the four-phase clock generation circuit in this way, it is possible to avoid an increase in power consumption and to suppress an increase in cost due to the miniaturization of a necessary manufacturing process.

JP 2011-82875 A

“Architecture Evolution of Integrated M-Phase High-Q Bandpass Filters” Ahammad Mirzai et al. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGRLAR PAPERS, VOL. 59, NO. 1 JAN. 2012

However, in the bandpass filter shown in FIG. 15, when the frequency of the RF signal to be passed increases, the frequency of the local signal needs to be increased accordingly, the M-phase clock becomes dull, and the attenuation of the bandpass filter decreases. There is a problem of causing deterioration of characteristics. By increasing the power consumption, the M-phase clock can be sharpened to some extent, but there is a limit due to the influence of the parasitic capacitance of the transistor and wiring. Parasitic capacitance can be reduced by selecting a finer manufacturing process, but the cost increases.
The present invention has been made in view of such a problem, and an object of the present invention is to eliminate the need for a duty conversion circuit for performing duty conversion, while suppressing an increase in cost due to necessary miniaturization of the manufacturing process. An object of the present invention is to provide a band-pass filter that can suppress the deterioration of the amount.

  The present invention has been made to achieve such an object. The invention according to claim 1 is directed to a load element (12, 32, 52) for converting an input current signal into an output voltage signal, and M elements. (M is an integer of 2 or more) impedance elements (14, 34, 54) composed of impedance elements (Z141 to Z144, Z341 to Z34M, Z541 to Z54M), and M sets of M elements associated with each impedance element Switch groups (131 to 134, 331 to 33 (M), 531 to 53 (M)), and the switch groups (131 to 134, 331 to 33 (M), 531 to 53 (M)) are 2 N sets (N is an even number) of series connection switches connected in series one by one (N is an even number) (SW1311 to SW1314, SW3311 to SW3314, SW5311) SW531 (N)), the first switch of the series connection switches is connected to the output voltage signal, the second switch of the series connection switches is connected to the associated impedance element, and the M The N sets of series connection switches (SW1311 to SW1344, SW3311 to SW33M4, SW5311 to SW53 (M) (N)) of the switch group (131 to 134, 331 to 33 (M), 531 to 53 (M)) The connection / disconnection of the band pass filter (10, 30, 50) is controlled by a clock group (LO1 to LO (M × N)) composed of M × N clocks. (FIGS. 1, 3 and 5; Examples 1 to 3).

  The invention according to claim 2 is the invention according to claim 1, wherein each clock for controlling connection / disconnection of the serial connection switch of each switch group is (360 / (M × N)) degrees. The clocks controlling the connection / non-connection of the first switch of the series-connected switches and the clocks controlling the connection / non-connection of the second switch are both high times 1 / of the clock cycle. A phase relationship of (M × N) is established, and the N clocks that control connection / disconnection of all the first switches have phases different from each other by (360 / N) degrees.

  According to the present invention, even when the passband frequency becomes high, a clock having a frequency lower than that of the passband is used to suppress deterioration of attenuation in order to suppress a manufacturing process miniaturization and increase in cost. In addition, an M-phase RF bandpass filter can be realized.

It is a circuit block diagram for demonstrating the 4 phase band pass filter of the double frequency of the clock of Example 1 in the band pass filter which concerns on this invention. FIG. 2 is a timing chart of a clock group that controls connection / disconnection of the switch illustrated in FIG. 1. It is a circuit block diagram for demonstrating the M phase band pass filter of the double frequency of the clock of Example 2 in the band pass filter which concerns on this invention. FIG. 4 is a timing chart of a clock group that controls connection / disconnection of the switch illustrated in FIG. 3. It is a circuit block diagram for demonstrating the M phase differential band pass filter of N frequency of the clock of Example 3 in the band pass filter which concerns on this invention. FIG. 6 is a timing chart of a clock group that controls connection / disconnection of the switch illustrated in FIG. 5. It is a circuit block diagram of a general M phase band pass filter. FIG. 8 is a timing diagram of the M-phase clock group illustrated in FIG. 7. It is a circuit block diagram of a general 4 phase band pass filter. FIG. 10 is a timing diagram of a four-phase clock group that controls connection / disconnection of the four switch groups illustrated in FIG. 9. It is a figure which shows the frequency characteristic of the 4-phase band pass filter shown in FIG. It is a circuit block diagram of the receiver of the direct conversion system using an M phase band pass filter. It is a circuit block diagram of the Duty conversion circuit shown in FIG. FIG. 14 is a timing diagram of the IQ local signal and the four-phase clock shown in FIG. 13. FIG. 10 is a circuit configuration diagram of a four-phase bandpass filter when the switches in FIG. 9 are connected in two stages in series.

  Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram for explaining a double-phase four-phase band-pass filter of the clock according to the first embodiment in the band-pass filter according to the present invention. In the figure, reference numeral 10 is a four-phase bandpass filter, 12 is a load element, 13 is a switch group, and 14 is an impedance element group.
The bandpass filter 10 according to the first embodiment includes a load element 12 that converts an input current signal into an output voltage signal, an impedance element group 14 that includes four impedance elements Z141 to Z144, and the four impedance elements Z141 to Z141. 4 sets of switch groups 131 to 134 associated with each Z144.

Each of the four switch groups 131 to 134 is connected in series, and two sets of series connection switches are composed of two sets SW1311 and SW1312, SW1313 and SW1314, and the first switches SW1311 and SW1313 among the series connection switches. Are connected to the output voltage signal, and the second switches SW1312 and SW1314 among the series connected switches are connected to the associated impedance element Z141.
In addition, the connection / non-connection of the two sets of serial connection switches SW1311 to SW1344 of the four sets of switch groups 131 to 134 is controlled by clock groups LO1 to LO8 composed of 4 × 2 clocks.

In addition, the clocks for controlling the connection / non-connection of the series connection switches of each switch group have different phases by (360 / (4 × 2)), and the connection / non-connection of the first switch of the series connection switches is determined. Both the clock to be controlled and the clock to control connection / disconnection of the second switch have a phase relationship in which the High time is 1 / (4 × 2) of the clock cycle, and all the first switches are connected / disconnected. The N clocks that control are different in phase by (360/2) degrees.
That is, the four-phase bandpass filter according to the first embodiment includes a load element 12 that converts an input current signal into an output voltage signal, and M impedance elements Z141 to M (four phases with M = 4 in the first embodiment). An impedance element group 14 made of Z144 and four switch groups 131 to 134 are provided.

The switch group 131 includes four switches SW1311 to SW1314, the switch group 132 includes four switches SW1321 to SW1324, the switch group 133 includes four switches SW1331 to SW1334, and the switch group 134 includes It consists of four switches SW1341 to SW1344.
The switch SW13 (n) 1 and the switch SW13 (n) 2 are connected in series. The switch SW13 (n) 3 and the switch SW13 (n) 4 are connected in series. The switches SW13 (n) 1 and SW13 (n) 3 are connected to the output signal. Here, n is an integer from 1 to 4. The switches SW1312 and SW1314 are connected to the impedance element 141, the switches SW1322 and SW1324 are connected to the impedance element 142, the switches SW1332 and SW1334 are connected to the impedance element 143, and the switches SW1342 and SW1344 are connected to the impedance element 144. It is connected to the.

The connection / disconnection of the switch SW1311 and the switch SW1342 is controlled by the clock LO1, the connection / disconnection of the switch SW1321 and the switch SW1314 is controlled by the clock LO2, and the connection / disconnection of the switch SW1331 and the switch SW1324 is controlled by the clock LO3. The connection / disconnection of the switch SW1341 and the switch SW1334 is controlled by the clock LO4.
The connection / disconnection of the switch SW1313 and the switch SW1344 is controlled by the clock LO5, the connection / disconnection of the switch SW1323 and the switch SW1312 is controlled by the clock LO6, and the connection / disconnection of the switch SW1333 and the switch SW1322 is controlled by the clock LO7. The connection / disconnection of the switch SW 1343 and the switch SW 1332 is controlled by the clock LO8.
The clock groups LO1 to LO8 are clocks having a duty ratio of 50%, the phases of which differ by 45 degrees.

FIG. 2 is a timing chart of the clock groups LO1 to LO8 shown in FIG. The clock groups LO1 to LO8 are signals having a period of T and a high period and a low period of T / 2, that is, a duty ratio of 50%. Further, the time difference between the rising edges of the clocks LO1 to LO8 from Low to High is indicated by τ1 to τ8. τ1 to τ8 are T / 8 in equal time. That is, LO1 to LO8 are out of phase by 45 degrees.
When the clocks LO1 and LO6 are both high, that is, during the time τ1, the switches SW1311 and SW1312 are turned on. When the clocks LO5 and LO2 are both high, that is, during the time τ5, the switches SW1313 and SW1314 are turned on. To do. Therefore, the output signal and the impedance element Z141 are connected during the time τ1 and τ5.

When the clocks LO2 and LO7 are both high, that is, during the time τ2, the switches SW1321 and SW1322 are turned on, and when both the clocks LO6 and LO3 are high, that is, during the time τ6, the switches SW1323 and SW1324 are turned on. To do. Therefore, the output signal and the impedance element Z142 are connected during the times τ2 and τ6.
When the clocks LO3 and LO8 are both High, that is, during the time τ3, the switches SW1331 and SW1332 are turned on. When both the clocks LO7 and LO4 are High, that is, during the time τ7, the switches SW1333 and SW1334 are turned on. To do. Therefore, the output signal and the impedance element Z143 are connected during the time τ3 and τ7.
When the clocks LO4 and LO1 are both high, that is, during the time τ4, the switches SW1341 and SW1342 are turned on, and when both the clocks LO8 and LO5 are high, that is, during the time τ8, the switches SW1343 and SW1344 are turned on. To do. Therefore, the output signal and impedance element Z144 are connected during times τ4 and τ8.

  With such a configuration, the impedance elements Z141 to Z144 are connected to the output signal for a period of T / 8 with a period of T / 2, that is, the same function as a four-phase bandpass filter with a period of T / 2. I understand that. In this manner, a four-phase bandpass filter can be configured using a clock group having a frequency that is half the frequency that is desired to pass. The slower the frequency, the steeper the clock, so that it is possible to realize a four-phase RF bandpass filter that suppresses deterioration in attenuation while suppressing cost increase due to miniaturization of the manufacturing process.

FIG. 3 is a circuit configuration diagram for explaining an M-phase band-pass filter having a double speed of the clock of the second embodiment in the band-pass filter according to the present invention. In the figure, reference numeral 30 denotes an M-phase bandpass filter, 32 denotes a load element, 33 denotes a switch group, and 34 denotes an impedance element group.
The bandpass filter 30 according to the second embodiment includes a load element 32 that converts an input current signal into an output voltage signal, an impedance element group 34 that includes M impedance elements Z341 to Z34M (M is an integer of 2 or more), There are provided M sets of switch groups 331 to 33M associated with each impedance element.

The switch groups 331 to 33M are connected in series two by two, and the set of series connection switches is composed of two sets SW3311, SW3312, SW3313, and SW3314. Of the series connection switches, the first switches SW3311 and SW3313 are output voltage signals. The second switches SW3312 and SW3314 among the serial connection switches are connected to the associated impedance elements.
Further, the connection / non-connection of the two series connection switches SW3311 to SW33M4 of the M group of switch groups 331 to 33M is controlled by a clock group (LO1 to LO (M × 2)) composed of M × 2 clocks. The

That is, the M-phase bandpass filter of the second embodiment includes a load element 32 that converts an input current signal into an output voltage signal, an impedance element group 34 that includes M impedance elements Z341 to Z34 (M), and M elements. Switch groups 331 to 33 (M).
The switch group 33 (n) includes four switches SW33 (n) 1 to SW33 (n) 4. The switch SW33 (n) 1 and the switch SW33 (n) 2 are connected in series. The switch SW33 (n) 3 and the switch SW33 (n) 4 are connected in series. The switches SW33 (n) 1 and SW33 (n) 3 are connected to the output signal. The switches SW33 (n) 2 and SW33 (n) 4 are connected to the impedance element 34 (n). Here, n is an integer from 1 to M.

Connection / non-connection of the switch SW3311 is controlled by the clock LO1, connection / non-connection of the switch SW3312 is controlled by the clock LO (M + 2), connection / non-connection of the switch SW3313 is controlled by the clock LO (M + 1), and the switch SW3314 The connection / disconnection is controlled by the clock LO2. For an integer i from 2 to M, connection / disconnection of the switch SW33 (i) 1 is controlled by the clock LO (i), and connection / disconnection of the switch SW33 (i) 2 is controlled by the clock LO (i + M + 1). The connection / disconnection of the switch SW33 (i) 3 is controlled by the clock LO (i + M), and the connection / disconnection of the switch SW33 (i) 4 is controlled by the clock LO (i + 1).
The clock groups LO1 to LO (2M) are clocks with a duty ratio of 50%, the phases of which differ by (180 / M) degrees.

FIG. 4 is a timing chart of the clock groups LO1 to LO (2M) shown in FIG. The clock groups LO1 to LO (2M) are signals having a period of T and a high period and a low period of T / 2, that is, a duty ratio of 50%. Further, the time difference between the rising edges of the clocks LO1 and LO (2M) from Low to High is indicated by τ1 to τ (2M). τ1 to τ (2M) are T / (2M) at equal time. That is, the phase of LO1 to LO (2M) is shifted by (180 / M) degrees.
When the clocks LO1 and LO (M + 2) are both high, that is, during the time τ1, the switches SW3311 and SW3312 are turned on, and when both the clocks LO (M + 1) and LO2 are high, that is, the time τ (M + 1). During this period, the switches SW3313 and SW3314 are turned on. Therefore, the output signal and the impedance element Z341 are connected during the time τ1 and τ (M + 1).

  For the integer i from 2 to M, when the clocks LO (i) and LO (i + M + 1) are both high, that is, during the time τ (i), the switches SW33 (i) 1 and SW33 (i) 2 are When the clocks LO (i + M) and LO (i + 1) are both high, that is, during the time τ (i + M), the switches SW33 (i) 3 and SW33 (i) 4 are turned on. Therefore, the output signal and the impedance element Z34 (i) are connected during the time τ (i) and τ (i + M).

  With such a configuration, the impedance elements Z341 to Z34 (M) are connected to the output signal for a period of T / 2M in a period of T / 2, that is, the same as the M-phase bandpass filter having a period of T / 2. I understand that it works. In this way, an M-phase bandpass filter can be configured using a clock group having a frequency that is half the frequency that is desired to pass. The slower the frequency, the steeper the clock, so that an M-phase RF band-pass filter with reduced deterioration of attenuation can be realized while suppressing cost increase due to miniaturization of the manufacturing process.

FIG. 5 is a circuit configuration diagram for explaining an N-phase M-phase band-pass filter of the clock of the third embodiment in the band-pass filter according to the present invention. In the figure, reference numeral 50 denotes an M-phase bandpass filter, 52 denotes a load element, 53 denotes a switch group, and 54 denotes an impedance element group.
The bandpass filter 50 according to the third embodiment includes a load element 52 that converts an input current signal into an output voltage signal, an impedance element group 54 including M impedance elements Z541 to Z54M (M is an integer of 2 or more), M sets of switch groups 531 to 53M associated with each impedance element are provided.

In addition, the switch groups 531 to 53M are connected in series two by two, and N series (N is an even number) set of series connected switches are SW5311 to SW531N, and the first switch among the series connected switches is an output voltage signal. The second switch among the series connected switches is connected to the associated impedance element.
Further, the connection / disconnection of the N series connection switches SW5311 to SW53MN of the M group of switch groups 531 to 53M is controlled by a clock group (LO1 to LO (M × N)) composed of M × N clocks. The

That is, the M-phase bandpass filter according to the third embodiment includes a load element 52 that converts an input current signal into an output voltage signal, an impedance element group 54 that includes M impedance elements Z541 to Z54 (M), and M elements. Switch groups 531 to 53 (M).
The switch group 53 (n) includes 2N switches SW53 (n) 1 to SW53 (n) (2N) for an even number N. The switch SW53 (n) (2k-1) and the switch SW53 (n) (2k) are connected in series. The switch SW53 (n) (2k-1) is connected to the output signal. In addition, the switch SW53 (n) (2k) is connected to the impedance element 54 (n). Here, k is an integer from 1 to N, and n is an integer from 1 to M.

  Connection / non-connection of the switch SW5311 is controlled by the clock LO1, and connection / non-connection of the switch SW5312 is controlled by the clock LO (M × N / 2 + 2). For an integer j from 2 to N−1, connection / disconnection of the switch SW531 (2j−1) is controlled by the clock LO (M × j + 1), and connection / disconnection of the switch SW531 (2j + 1) is controlled by the clock LO. Controlled by (M × N / 2 + j + 1). The connection / disconnection of the switch SW531 (2N-1) is controlled by the clock LO (M × (N−1) +1), and the connection / disconnection of the switch SW531 (2N) is controlled by the clock LO (M × (N / 2−). 1) Controlled by +2).

  For an integer i from 2 to M, connection / disconnection of the switch SW53 (i) 1 is controlled by the clock LO (i), and connection / disconnection of the switch SW53 (i) 2 is controlled by the clock LO (M × N / 2 + i + 1). The connection / disconnection of the switch SW53 (i) (2j-1) is controlled by the clock LO (M × (j + 1) + i), and the connection / disconnection of the switch SW53 (i) (2j + 1) is controlled by the clock LO (M × ( N / 2 + j) + i + 1). The connection / disconnection of the switch SW53 (i) (2N−1) is controlled by the clock LO (M × (N−1) + i), and the connection / disconnection of the switch SW53 (i) (N) is controlled by the clock LO (M X (N / 2-1) + i + 1).

FIG. 6 is a timing chart of the clock groups LO1 to LO (M × N) shown in FIG. The clock group LO1 to LO (M × N) is a signal having a period of T and a high period and a low period of T / 2, that is, a duty ratio of 50%. Further, the time difference between rising edges from clock Low to high (M × N) from Low to High is represented by τ1 to τ (M × N). τ1 to τ (M × N) are T / (M × N) at equal time. That is, the phases of LO1 to LO (M × N) are shifted by (360 / (M × N)) degrees.
When the clocks LO1 and LO (M × N / 2 + 2) are both High, that is, during the time τ1, the switches SW5311 and SW5312 are turned on. For an integer j from 1 to N−2, when both the clocks LO (M × j + 1) and LO (M × (N / 2 + j) +2) are High, that is, during the time τ (M × j + 1). The switches SW531 (2j-1) and SW531 (2j) are turned on. Further, when both of the clocks LO (M × (N−1) +1) and LO (M × (N / 2−1) +2) are High, that is, during the time τ (M × (N−1) +1). The switches SW531 (2N-1) and SW531 (2N) are turned on. Therefore, the output signal and the impedance element Z541 are connected during the time τ1, τ (M × j + 1) and τ (M × (N−1) +1). That is, the output signal and the impedance element Z541 are connected for a time of T / (M × N) with a period of T / N.

  For an integer i from 2 to M−1, when the clocks LO (i) and LO (M × N / 2 + i + 1) are both high, that is, during time τ (i), the switch SW53 (i) 1 and SW53 (i) 2 is turned on. Further, when the clock LO (M × j + i) and LO (M × (N / 2 + j) + i + 1) are both high for an integer j from 1 to N−2, that is, at time τ (M × j + i). Meanwhile, the switches SW53 (i) (2j-1) and SW53 (i) (2j) are turned on. Further, when both the clocks LO (M × (N−1) + i) and LO (M × (N / 2−1) + i + 1) are High, that is, during the time τ (M × (N−1) + i). The switches SW53 (i) (2N-1) and SW53 (i) (2N) are turned on.

Therefore, the output signal and the impedance element Z54 (i) are connected during the time τ (i), τ (M × j + i) and τ (M × (N−1) + i). That is, the output signal and the impedance element Z54 (i) are connected for a time of T / (M × N) with a period of T / N.
When the clocks LO (M) and LO (M × (N / 2 + 1) +1) are both High, that is, during the time τ (M), the switches SW53 (M) 1 and SW53 (M) 2 are turned on. When the clocks LO (M × (j + 1)) and LO (M × (N / 2 + j + 1) +1) are both high for an integer j from 1 to N−2, that is, time τ (M × ( j + 1)), the switches SW53 (M) (2j-1) and SW53 (M) (2j) are turned on. When the clocks LO (M × N) and LO (M × N / 2 + 1) are both High, that is, during the time τ (M × N), the switches SW53 (M) (2N−1) and SW53 (M ) (2N) is turned on.

Accordingly, the output signal and the impedance element Z54 (M) are connected during the time τ (M), τ (M × (j + 1)), and τ (M × N). That is, the output signal and the impedance element Z54 (M) are connected for a time of T / (M × N) with a period of T / N.
With such a configuration, the impedance elements Z541 to Z54 (M) are connected to the output signal for a period of T / (M × N) with a period of T / N, that is, an M-phase band with a period of T / N. It turns out that it becomes the same work as a pass filter. In this way, an M-phase bandpass filter can be configured using a clock group having a frequency 1 / N of the frequency to be passed. The slower the frequency, the steeper the clock, so that an M-phase RF band-pass filter with reduced deterioration of attenuation can be realized while suppressing cost increase due to miniaturization of the manufacturing process.

  It should be noted that the technical scope of the present invention is not limited to the illustrated and described exemplary embodiments, and includes all embodiments that bring about effects equivalent to those intended by the present invention. It is a waste. Further, the technical scope of the present invention can be constituted by any desired combination of specific features among all the disclosed features.

10, 90, 150 Four-phase bandpass filters 12, 32, 52, 72 Load elements 14, 34, 54, 74 Impedance element groups 30, 50, 70 M-phase bandpass filters 92, 152 Load resistors 94, 154 Capacitor groups 120 Receiver 121 GM cell 122 Mixer 123 Duty conversion circuit 124 PLL circuits 131 to 134, 331 to 33 (M), 511 to 5NM, 73, 93, 153 Switch groups 231 to 234 AND circuits

Claims (2)

A load element that converts an input current signal into an output voltage signal;
An impedance element group composed of M impedance elements (M is an integer of 2 or more);
A set of M switches associated with each impedance element;
The switch group is connected in series two by two, and a set of series connected switches is composed of N sets (N is an even number), and a first switch of the series connected switches is connected to the output voltage signal, The second switch of the series connection switches is connected to the associated impedance element,
The band-pass filter according to claim 1, wherein connection / disconnection of the N sets of serial connection switches of the M sets of switches is controlled by a clock group including M × N clocks. Each clock for controlling the connection / disconnection of the serial connection switch of each switch group is different in phase by (360 / (M × N)).
The clock for controlling the connection / disconnection of the first switch of the series connection switch and the clock for controlling the connection / disconnection of the second switch are both high times 1 / (M × N) of the clock cycle. And the phase relationship
2. The band-pass filter according to claim 1, wherein the N clocks that control connection / disconnection of all the first switches have phases different from each other by (360 / N) degrees.

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