JP2015211063A - Field effect transistor using nitride semiconductor and recess gate electrode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that although it is effective to form a recess, embed a gate electrode in the recess, and introduce negative fixed charges to the bottom surface of the recess for normally-off operation of a field effect transistor, where a gate electrode faces a nitride semiconductor via a gate insulating film, by pulling up the threshold voltage thereof, but the threshold voltage rises unintendedly.SOLUTION: The formation range of a negative fixed charge introduction region 22 does not spread to the whole area of the bottom surface of a recess 18a, but is confined within a formation range of the lower surface 16a of the gate electrode 16. A channel is formed with an intended threshold voltage, and the resistance between source-drain lowers. Transistors having an arranged threshold voltage can be mass-produced with good yield.

Description

  In this specification, the gate electrode is opposed to the nitride semiconductor through the gate insulating film, and when a voltage is applied to the gate electrode, a channel is formed in the nitride semiconductor and the resistance between the source and the drain is reduced. An effect transistor is disclosed.

  The above-mentioned field effect transistor tends to be normally on because the threshold voltage becomes a negative voltage. Japanese Patent Application Laid-Open No. H10-228667 describes a technique for raising the threshold voltage to a positive voltage to make it normally off.

As shown in FIG. 19, the field effect transistor described in Patent Document 1 has a heterojunction structure of a GaN layer 4 and an AlGaN layer 6 a, and the lower surface 16 a of the gate electrode 16 is interposed via the gate insulating film 14. And a structure facing the heterojunction interface.
In order to raise the threshold voltage to a positive voltage and make it normally off, in the technique of Patent Document 1, a recess 18c reaching an intermediate depth from the upper surface of the AlGaN layer 6a is provided, and the gate electrode 16 is filled in the recess 18c. In this specification, the gate electrode embedded in the recess is referred to as a recess gate electrode. In the technique of Patent Document 1, fluorine ions are further implanted from the bottom surface of the recess 18c (implanted before the formation of the recess gate electrode 16) to form the region 22 into which negative fixed charges are introduced. When the region 22 into which a negative fixed charge is introduced is provided, the channel is closed by the presence of the region 22 in a state where no potential is applied to the gate electrode 16. When a potential is applied to the gate electrode 16, the channel opens. When the region 22 into which a negative fixed charge is introduced is provided, the channel is difficult to open and the threshold voltage is increased. Reference numeral 2 is a substrate, 20 is a source electrode, and 12 is a drain electrode.
In the technique of Patent Document 1, the threshold voltage is raised toward the plus side by employing the recess gate electrode 16, and the threshold voltage is raised to the plus voltage by forming the negative fixed charge introduction region 22.

JP 2012-124442 A

The technique of Patent Document 1 is a useful technique for raising the threshold voltage of a field effect transistor using a nitride semiconductor to a positive voltage to make it normally off, but the threshold voltage rises higher than the designed threshold voltage. A phenomenon occurs. Alternatively, a phenomenon occurs in which the on-resistance when the designed threshold voltage is applied is higher than the designed on-resistance.
The present specification discloses a semiconductor structure that enables the manufacture of a field effect transistor in which the designed threshold voltage and the actual threshold voltage are in good agreement.

According to the structure of FIG. 19, the cause of the actual threshold voltage rising from the designed threshold voltage was studied.
In the structure of FIG. 19, the design threshold voltage is applied to the recess gate electrode 16 with respect to the film thickness of the gate insulating film 14 and the charge density introduced into the negative fixed charge introduction region 22 in order to adjust the design threshold voltage. When the voltage is applied, conditions are set such that a channel is formed in the negative fixed charge introduction region 22 at a position facing the lower surface 16a of the recess gate electrode 16 through the gate insulating film.
However, in the technique of Patent Document 1, the negative fixed charge introduction region 22 extends not only in the range A facing the lower surface 16a of the recess gate electrode 16 but also in the range B where the bottom surface of the recess 18c is expanded. Since the gate insulating film 14 has a portion 14a that covers the side wall of the recess, the relationship of range A <range B is satisfied. In the structure of FIG. 19, it is necessary to form a channel not only in the negative fixed charge introduction region 22 in the range A but also in the negative fixed charge introduction region 22 in the range B. That is, it is necessary to form a channel also in the negative fixed charge introduction region 22 facing the vicinity of the corner portion of the recess 18c. In the structure of FIG. 19, the gate insulating film 14 includes a portion that covers the recess sidewall (hereinafter referred to as the gate insulating film side surface portion 14a) and a portion that covers the bottom surface of the recess (hereinafter referred to as the gate insulating film bottom surface portion 14b). ing. Therefore, the shortest distance from the gate electrode 16 to the corner portion of the recess 18c is ^1/2 (the square of the film thickness of the side surface portion 14a of the gate insulating film + the square of the film thickness of the bottom surface portion 14b of the gate insulating film). Even if a threshold voltage for forming a channel in the negative fixed charge introduction region 22 located at a position separated from the lower surface 16a of the recess gate electrode 16 by the thickness of the gate insulating film bottom surface portion 14b is applied to the gate electrode 16, a longer distance than that is applied. A channel is not formed in the negative fixed charge introduction region 22 facing the corner portion of the recess 18c that is separated from the recess 18c, and the resistance is high. Therefore, the actual on-resistance does not decrease to the designed on-resistance in a state where the designed threshold voltage is applied. In order to lower the design on-resistance, a voltage larger than the design threshold voltage is applied to the gate electrode 16 to form a channel in the negative fixed charge introduction region 22 facing the corner of the recess 18c. There is a need.

  From the above, when the threshold voltage is applied to the gate electrode 16, the negative fixed charge introduction region 22 facing the corner portion of the recess 18 c, not the range A facing the lower surface 16 a of the recess gate electrode 16. It has been found that it is reasonable to design the thickness of the gate insulating film 14 and the charge density introduced into the negative fixed charge introduction region 22 using the conditions for forming the channel as an index. According to the design method, the actual threshold voltage can be made to closely match the designed threshold voltage.

However, even with this design method, it has been found that it is difficult to mass-produce field-effect transistors with actual threshold voltages that closely match the designed threshold voltages with a high yield.
(1) As described above, the shortest distance from the gate electrode 16 to the corner portion of the recess 18c is the square root of the sum of the square of the film thickness of the gate insulating film side surface portion 14a and the square of the film thickness of the gate insulating film bottom surface portion 14b. Become. In order to suppress the variation in threshold voltage, it is necessary to suppress the variation in the shortest distance. To that end, both the film thickness of the gate insulating film side surface portion 14a and the film thickness of the gate insulating film bottom surface portion 14b are intended. It is necessary to adjust to the value that was made, and it is actually difficult.
(2) The electric field strength at the position facing the lower surface 16a of the gate electrode is inversely proportional to the distance from the lower surface 16a of the gate electrode, whereas the electrode strength near the corner portion of the recess 18c is the corner of the gate electrode 16. It is inversely proportional to the square of the distance from the part. In the vicinity of the corner portion of the recess 18c, a change in distance sensitively affects the electric field strength. In the vicinity of the corner portion of the recess 18c, the change in the thickness of the gate insulating film sensitively affects the electric field strength. In the structure of FIG. 19, it is difficult to stabilize the threshold voltage.
This specification discloses a transistor structure that can overcome the above-described phenomenon and can mass-produce field effect transistors with small variations in threshold voltage with high yield.

  In the field effect transistor disclosed in this specification, a gate electrode (recess gate electrode) embedded in a recess faces a nitride semiconductor through a gate insulating film, and a channel is formed in the nitride semiconductor by a potential applied to the recess gate electrode. As a result, the resistance between the source and the drain decreases. The gate electrode is in contact with a gate insulating film (gate insulating film side surface portion) covering the side surface of the recess and a gate insulating film (gate insulating film bottom surface portion) covering the bottom surface of the recess. A negative fixed charge is introduced into a part of the nitride semiconductor. In the field effect transistor disclosed in this specification, the negative fixed charge introduction region is in contact with the bottom surface of the gate insulating film, and within a range in which the bottom surface of the gate insulating film and the gate electrode are in contact when the semiconductor substrate is viewed in plan view. Stay on.

With the above structure, a negative fixed charge is not introduced into the nitride semiconductor facing the corner of the recess, and a channel must be formed to reduce the resistance between the source and drain There is no. In the above structure, if the channel is formed in the negative fixed charge introduction region that remains in the range where the bottom surface of the gate insulating film and the gate electrode are in contact with each other, the on-resistance is lowered.
According to the present technology, the problem described in Paragraph 0006 does not occur, and the design threshold voltage and the actual threshold voltage are well matched by the conventional design method, and the design on-resistance and the actual on-resistance are well matched. A field effect transistor can be manufactured. In addition, the field effect transistor with little variation in threshold voltage without causing the problem described in paragraph 0008 can be mass-produced with high yield.

  As a field effect transistor using a nitride semiconductor, a HEMT (High Mobility Electron Transistor) using a heterojunction structure of a nitride semiconductor having a narrow band gap and a nitride semiconductor having a wide band gap is well known. Not limited to that. The technique described in this specification can be applied to a field-effect transistor in which electrons travel through an n-type nitride semiconductor layer.

When a heterojunction of a nitride semiconductor having a narrow band gap and a nitride semiconductor having a wide band gap exists, the former is an electron transit layer and the latter is an electron supply layer.
In the case where the technique described in this specification is applied to a HEMT in which a nitride semiconductor layer serving as an electron supply layer and a nitride semiconductor layer serving as an electron transit layer are stacked, gate insulation covers the bottom surface of the recess. The heterojunction interface may be opposed via the film, or the recess may penetrate the electron supply layer and reach the electron transit layer.
In many cases, an insulating layer is formed on the top surface of the nitride semiconductor layer serving as the electron supply layer. When a recess that penetrates the insulating layer and reaches the upper surface of the electron supply layer is used, or a recess that penetrates the insulating layer and reaches the intermediate depth of the electron supply layer, the gate electrode Thus, a structure facing the heterojunction interface is obtained. Instead of the above, the recess may penetrate the electron supply layer and reach the upper surface of the electron transit layer, or may penetrate the electron supply layer and reach the intermediate depth of the electron transit layer. It's okay. The technique disclosed in this specification can also be applied to this structure.

  Instead of raising the threshold voltage toward the positive side by introducing a negative fixed charge into the nitride semiconductor located at the position facing the gate electrode through the gate insulating film, a negative fixed charge is introduced into the gate insulating film be able to. The technique disclosed in this specification can be applied to the latter technique. In that case, negative fixed charges are introduced into the gate insulating film in a range where the bottom surface of the gate insulating film is in contact with the gate electrode when the semiconductor substrate is viewed in plan.

  According to the technology disclosed in this specification, a phenomenon in which the threshold voltage increases more than intended is not generated. Similarly, a phenomenon in which the on-resistance increases more than intended is not generated. It becomes possible to mass-produce field effect transistors with uniform threshold voltages with a high yield.

1 shows a cross-sectional structure of a field effect transistor according to a first embodiment. 2 shows a cross-sectional structure of a field effect transistor according to a second embodiment. 3 shows a cross-sectional structure of a field effect transistor according to a third embodiment. The 1st step of the manufacturing process of the field effect transistor of 3rd Example is shown. The 2nd step of the manufacturing process of the field effect transistor of 3rd Example is shown. The 3rd step of the manufacturing process of the field effect transistor of 3rd Example is shown. The 4th step of the manufacturing process of the field effect transistor of 3rd Example is shown. The 5th step of the manufacturing process of the field effect transistor of 3rd Example is shown. The 6th step of the manufacturing process of the field effect transistor of 3rd Example is shown. The 7th step of the manufacturing process of the field effect transistor of 3rd Example is shown. The 1st step of another manufacturing process of the field effect transistor of 3rd Example is shown. The 2nd step of another manufacturing process of the field effect transistor of 3rd Example is shown. The 3rd stage of another manufacturing process of the field effect transistor of 3rd Example is shown. The 4th step of another manufacturing process of the field effect transistor of 3rd Example is shown. The 5th step of another manufacturing process of the field effect transistor of 3rd Example is shown. The 6th step of another manufacturing process of the field effect transistor of 3rd Example is shown. 2 shows cross-sectional structures of two field-effect transistors that compare on-resistances. A comparison result is shown. 2 shows a cross-sectional structure of a conventional field effect transistor.

The features of the technology disclosed in this specification will be summarized below. The items described below have technical usefulness independently.
(First Feature) A nitride semiconductor is exposed to a substance containing F, Cl, C, Mg, Zn, and Fe, and a negative fixed charge is introduced into the nitride semiconductor forming the recess bottom surface.
(Second feature) A thin recess is formed, a negative fixed charge is introduced into the bottom surface thereof, the recess is widened, a gate insulating film is formed, and the gate electrode is filled in order.
(Third feature) Forming a recess, forming a protective film on the side surface of the recess, introducing a negative fixed charge into the bottom surface of the recess whose side surface is covered with the protective film, removing the protective film, and forming a gate insulating film In this order, the gate electrodes are filled.

(First embodiment)
In FIG. 1 showing the cross-sectional structure of the first embodiment, the reference numerals indicate the following.
2: substrate, 4: i-GaN layer (may be p-GaN layer), 6: n-GaN layer (becomes an electron transit layer), 8: insulating film, 10: interlayer insulating film, 12: drain electrode, 14 : Gate insulating film, 16: gate electrode, 18: recess, 20: source electrode, 22: negative fixed charge introduction region (in the embodiment, F is introduced. Instead of F, Cl, C, Mg, Zn or Fe May be introduced). The negative fixed charge introduction region 22 is formed deeper than the n-GaN layer 6 and divides the n-GaN layer 6 left and right between the source electrode 20 and the drain electrode 12.

  In a state where a positive voltage is not applied to the gate electrode 16 of the transistor of FIG. 1, electrons do not move between the n-GaN layers 6 divided to the left and right by the negative fixed charge introduction region 22, and the source electrode 20 and the drain electrode 12. The resistance between is high. When a positive threshold voltage is applied to the gate electrode 16, a channel is formed in the negative fixed charge introduction region 22 in a range facing the gate electrode 16 through the gate insulating film 14, and the resistance between the source electrode 20 and the drain electrode 12 is formed. Decreases.

  In the structure of FIG. 1, the formation range of the negative fixed charge introduction region 22 and the range A in which the lower surface 16a of the gate electrode 16 extends coincide. The bottom surface of the recess extends in range B, where range A <range B. The gate insulating film 14 includes a portion that covers the side surface of the recess 18 (gate insulating film side surface portion 14 a) and a portion that covers the bottom surface of the recess 18 (gate insulating film bottom surface portion 14 b). The side surface portion 14a is in contact with the gate insulating film bottom surface portion 14b. The range where the lower surface 16a of the gate electrode 16 extends can be said to be the range where the gate insulating film bottom surface portion 14b and the gate electrode 16 are in contact. The formation range of the negative fixed charge introduction region 22 is a part of the bottom surface of the recess 18 and remains within the range A where the gate insulating film bottom surface portion 14b and the gate electrode 16 are in contact with each other.

Therefore, the shortest distance from the range where the channel needs to be formed by the voltage applied to the gate electrode 16 in the negative fixed charge introduction region 22 to the gate electrode 16 does not depend on the position. It is equal to the thickness of 14b. When a design threshold voltage is applied to the gate electrode 16, the channel is formed in the negative fixed charge introduction region 22 at a position separated by the thickness of the bottom surface portion 14b of the gate insulating film. Works as it did. The threshold voltage and on-resistance do not increase unintentionally. In addition, field effect transistors with uniform threshold voltages can be mass-produced with a high yield.
In the present embodiment, the formation range of the negative fixed charge introduction region 22 = the formation range A of the lower surface 16a of the gate electrode 16, but the formation range of the negative fixed charge introduction region 22 <the range A may be satisfied. .

(Second embodiment)
Other embodiments will be described below. In the following, the same or similar parts are denoted by the same reference numerals, and redundant description is omitted.
In the transistor of the second embodiment shown in FIG. 2, an AlGaN layer 6a is used instead of the n-GaN layer 6 used in the first embodiment. The band gap of AlGaN forming the layer 6a is larger than the band gap of GaN forming the layer 4, and a heterojunction interface is formed between the AlGaN layer 6a and the GaN layer 4, and the heterojunction interface in the GaN layer 4 is formed. A two-dimensional electron gas is generated along the range. The AlGaN layer 6a becomes an electron supply layer, and the GaN layer 4 becomes an electron transit layer.
Also in this embodiment, a negative fixed charge is introduced into part of the nitride semiconductor (AlGaN layer 6a in this embodiment) in a range facing the gate electrode 16 through the gate insulating film bottom surface portion 14b. . The range of the negative fixed charge introduction region 22a = the range where the gate insulating film bottom surface portion 14b and the gate electrode 16 contact = the formation range A of the bottom surface 16a of the gate electrode 16 <the formation range B of the bottom surface of the recess 18. It is not necessary to form a channel near the corner of the recess, the threshold voltage and the on-resistance do not increase unintentionally from the design values, and the threshold voltage can be prevented from varying during mass production.

  Also in this embodiment, the range of the negative fixed charge introduction region 22a may be included in a part of the range where the gate insulating film bottom surface portion 14b and the gate electrode 16 are in contact with each other. In this embodiment, the negative fixed charge introduction region 22a is thinner than the AlGaN layer 6a, but the negative fixed charge introduction region 22a is thicker than the AlGaN layer 6a and penetrates into the GaN layer 4. Good.

(Third embodiment)
In the third embodiment shown in FIG. 3, the recess 18a is formed deep and reaches the electron transit layer 4 through the electron supply layer 6a. Also in this embodiment, the range of the negative fixed charge introduction region 22 = the range where the gate insulating film bottom surface portion 14b and the gate electrode 16 contact = the formation range A of the bottom surface 16a of the gate electrode 16 <the formation range B of the bottom surface of the recess 18. It is left. The threshold voltage and the on-resistance do not increase unintentionally from the design values, and the threshold voltage can be prevented from varying during mass production.
The bottom surface of the recess may coincide with the upper surface of the electron supply layer 6a as indicated by reference numeral 18 in FIG. 2, or may be at an intermediate depth of the electron supply layer 6a as indicated by reference numeral 18c in FIG. Alternatively, as indicated by reference numeral 18a in FIG. 3, the electron transit layer 4 may be reached through the electron supply layer 6a.

(First manufacturing method)
With reference to FIGS. 4 to 10, a method of manufacturing the transistor of the third embodiment will be described.
FIG. 4: A GaN layer 4, an AlGaN layer 6 a, and an insulating layer 8 are stacked in this order on the upper surface of the substrate 2.
FIG. 5: A resist layer 24 is formed on the upper surface of the insulating layer 8. An opening 24a is provided at the position where the recess 18a is formed. Since the recess is widened in the process of FIG. 8 described later, an opening 24a narrower than the width of the recess 18a is provided at this stage.
FIG. 6: Using the resist layer 24 as a protective film, anisotropic etching is performed from the opening 24a. Here, etching is continued until it reaches the GaN layer 4 through the insulating layer 8 and the AlGaN layer 6a.
FIG. 7: Exposure to plasma containing an element that enters the nitride semiconductor and becomes a negative fixed charge. F, Cl, C, Mg, Zn, and Fe are suitable for an element that has a negative fixed charge. In FIG. 7, 24b represents the range of the resist layer 24 into which negative fixed charges are introduced, 8b represents the range of the insulating layer 8 into which negative fixed charges have been introduced, and 6b represents AlGaN into which negative fixed charges have been introduced. The range of the layer 6a is shown, 4b shows the side surface of the GaN layer 4 into which the negative fixed charge is introduced, and 4c shows the upper surface of the GaN layer 4 into which the negative fixed charge is introduced. Instead of exposing to plasma, a negative fixed charge injection method may be used.
FIG. 8: The resist layer 24 is removed by washing. Next, the insulating layer 8 and the nitride semiconductors 6a and 4 are etched using an alkaline solution. As the alkaline solution, NaOH, KOH, TMAH, NH ₄ OH, or the like can be used. When the nitride semiconductors 6a and 4 are etched using an alkaline solution, the etching rate in the horizontal direction in the figure becomes high, and the etching rate in the downward direction in the figure becomes low. As a result, the regions indicated by 8b, 6b and 4b are etched, and the width of the recess is widened. In FIG. 8, after the regions 8b, 6b, and 4b are removed, the etching is continued to further increase the width of the recess. Even when the width of the recess is expanded to the width of the recess 18a shown in FIG. 3, the region 4c on the upper surface (bottom surface of the recess) of the GaN layer 4 into which the negative fixed charge has been introduced remains.
The recess width in FIG. The thickness of the region 4b is b. In FIG. 8, the etching is continued until the recess width = a + 2b + 2c. Here, the thickness b is set to a value at which the region 4c remains after etching. The c is equal to or greater than the thickness of the gate insulating film 14 provided in FIG. With respect to the values of b and c thus set, a + 2b + 2c = the value of a which is the width of the recess 18a is obtained, and a recess of width a is formed in the stage of FIG.
When the etching shown in FIG. 8 is performed, high-speed etching is performed in the horizontal direction above the region 4c, so that the width of the recess = a + 2b + 2c = the width of the recess 18a. At that stage, the etching is finished. The region 4c remains even after the etching is finished. At the stage where the etching is completed, a region 4c having a width equal to a + 2b remains at the center position in the width direction of the bottom surface of the recess 18a whose width is equal to a + 2b + 2c. This is the negative fixed charge introduction region 22 shown in FIG. The negative fixed charge introduction region 22 does not extend over the entire width (a + 2b + 2c) of the recess 18a, but is separated from the corner portion of the recess 18a by a distance c. As described above, the distance c is larger than the film thickness of the gate insulating film 14 formed in FIG. As a result, a relationship in which the range of the negative fixed charge introduction region 22 is included in the range A in which the lower surface 16a of the gate electrode 16 extends can be obtained.
FIG. 9: A gate insulating film 14 is formed on the bottom and side surfaces of the recess 18 a that has been widened by etching and on the top surface of the insulating film 8. Thereafter, the gate electrode 16 is deposited, and the recess 18 a is filled with the gate electrode 16. Thereafter, the gate electrode 16 is formed by patterning the shape of the gate electrode formed outside the recess.
The width of the lower surface 16a of the gate electrode 16 is a + 2b + 2c-2d. Here, d is the thickness of the gate insulating film 14 and is thinner than c. Therefore, the relationship of the width of the lower surface 16a of the gate electrode 16 (= a + 2b + 2c-2d)> the width of the negative fixed charge introduction region 22 (= a + 2b) is obtained. By the above manufacturing method, the negative fixed charge introduction region 22 that remains in the formation range A of the lower surface 16a of the gate electrode 16 can be formed.
FIG. 10: The interlayer insulating film 10 is formed. An opening 10b is formed in the source electrode formation portion of the interlayer insulating film 10, and an opening 10a is formed in the drain electrode formation portion. When the source electrode 20 is formed in the opening 10b and the drain-in electrode 12 is formed in the opening 10a, the structure of FIG. 3 is completed.

(Second manufacturing method)
The second manufacturing method will be described with reference to FIGS.
FIG. 11: Equivalent to FIG.
FIG. 12: almost the same as FIG. At this stage, an opening 24c equal to the width of the recess 18 is formed.
FIG. 13: A deep recess 18a reaching the GaN layer 4 from the opening 24c is formed.
FIG. 14: The resist layer 24 is removed and a new resist layer 25 is formed. An opening 25 a is provided in the resist layer 25. A part of the bottom surface of the deep recess 18a is exposed at the bottom of the opening 25a. The side surface of the deep recess 18a is covered with a resist film 25b extending along the side surface. The film thickness of the resist film 25b covering the side surface of the deep recess 18a is made thicker than the film thickness of the gate insulating film 14 formed in a later-described process.
FIG. 15: Exposure to plasma containing an element that enters the nitride semiconductor and becomes a negative fixed charge. F, Cl, C, Mg, Zn, and Fe are suitable for an element that has a negative fixed charge. Instead of exposing to plasma, a negative fixed charge injection method may be used. The side surface of the recess 18a is covered with a resist 25b layer. Negative fixed charges are introduced into part of the bottom surface of the recess exposed in the opening 25a of the resist layer 25.
FIG. 16: The resist layer 25 is removed by washing. This state is equivalent to FIG. In this method, since the thickness of the resist film 25b> the thickness of the gate insulating film 14, the relationship of the width A of the lower surface 16a of the gate electrode 16> the width of the negative fixed charge introduction region 22 is obtained in the stage of FIG. be able to. Also by this method, the relationship of the range of the negative fixed charge introduction region 22 <the range in which the gate electrode 16 is in contact with the gate insulating film bottom surface portion 14b (the formation range of the lower surface 16a of the gate electrode 16) can be obtained.
If the state of FIG. 16 is obtained, the transistor of the third embodiment is obtained by performing the steps shown in FIGS. 9 and 10 thereafter.

17A shows the transistor of the third embodiment shown in FIG. 3, and FIG. 17B shows a comparative example. In the comparative example, the negative fixed charge introduction region 22 exceeds the range of the lower surface 16a of the gate electrode 16 and extends over the entire bottom surface of the recess 18a.
FIG. 18 shows the on-resistance when the same voltage is applied to the gate electrode 16. According to the third example, it can be seen that the on-resistance can be kept low.

  In the above embodiment, the negative fixed charge is introduced into the nitride semiconductor facing the gate electrode through the gate insulating film to raise the threshold voltage to the plus side. Instead, by introducing a negative fixed charge into the gate insulating film, the threshold voltage can be raised to the positive side. Also in this case, it is possible to prevent the threshold voltage from rising more than intended by keeping the range where the negative fixed charge is introduced within the range facing the lower surface of the gate electrode.

With the structure of FIG. 19, the threshold voltage can be adjusted using as an index the phenomenon that a channel is formed in the electron transit layer at a position facing the corner of the recess. Thus, when the threshold voltage is designed, the gate voltage when the channel is formed in the electron transit layer in the range A is lower than that. Therefore, if a voltage at which a channel is formed in the electron transit layer at a position facing the corner portion of the recess is applied to the gate electrode, the electron transit layer in the range A may have a low resistance. When the threshold voltage is adjusted using the phenomenon at the corner of the recess as an index, the off-state is realized by utilizing the high resistance of the electron travel layer in a small range facing the corner, May have low resistance. If the threshold voltage is set using the phenomenon of the corner portion as an index with the structure of FIG. 19, there is a problem that the leakage current flows in the range A because of a low resistance despite being in the OFF state.
On the other hand, in the above-described embodiment, for example, the electron transit layer in the range A in FIG. The length of the range A can be adjusted. The length of the high resistance range that realizes the off state can be freely adjusted to a necessary distance.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2: Substrate 4: i-GaN layer (electron transit layer)
4b: negative fixed charge introduction region 4c on the side surface: negative fixed charge introduction region 6 on the bottom surface 6: n-GaN layer 6a: AlGaN layer (electron supply layer)
6b: Negative fixed charge introducing region 8: Insulating film 8b: Negative fixed charge introducing region 10: Interlayer insulating film 10a, 10b: Opening 12: Drain electrode 14: Gate insulating film 14a: Side surface portion 14b of gate insulating film: Bottom surface of gate insulating film Portion 16: Gate electrode 16a: Gate electrode lower surface 18: Recess 18a: Deep recess 18b: Thin recess 18c: Shallow recess 20: Source electrode 22: Negative fixed charge introduction region 22a: Negative fixed charge introduction region 24: Resist layer 24a: Opening 24b: Negative fixed charge introduction region 24c: Opening 25: Resist layer 25a: Opening 25b: Resist layer covering side surface of recess A: Width of lower surface of gate electrode B: Recess width a: Width of narrow recess b: Negative fixing Charge introduction distance c: Further etching distance d: Gate insulating film thickness e: Film thickness of resist layer covering side surface of recess

Claims (4)

The gate electrode embedded in the recess faces the nitride semiconductor via the gate insulating film,
A field effect transistor in which a channel is formed in the nitride semiconductor by a potential applied to the gate electrode;
The gate electrode is in contact with a gate insulating film covering a side surface of the recess and a gate insulating film covering a bottom surface of the recess,
A negative fixed charge is introduced into a part of the nitride semiconductor,
The introduction region is in contact with the gate insulating film covering the bottom surface of the recess, and remains in a range where the gate electrode is in contact with the gate insulating film covering the bottom surface of the recess when the semiconductor substrate is viewed in plan view. A field effect transistor.   The gate electrode is opposed to an electron supply layer formed of a nitride semiconductor and an electron transit layer formed of a nitride semiconductor through a gate insulating film covering the bottom surface of the recess. The field effect transistor according to claim 1.   2. The field effect transistor according to claim 1, wherein the recess reaches an electron transit layer formed of a nitride semiconductor through an electron supply layer formed of a nitride semiconductor. The gate electrode embedded in the recess faces the nitride semiconductor via the gate insulating film,
A field effect transistor in which a channel is formed in the nitride semiconductor by a potential applied to the gate electrode;
The gate electrode is in contact with a gate insulating film covering a side surface of the recess and a gate insulating film covering a bottom surface of the recess,
Negative fixed charges are introduced into a part of the gate insulating film covering the bottom surface of the recess,
The field effect transistor characterized in that the introduction region remains in a range where the gate electrode is in contact with the gate insulating film covering the bottom surface of the recess when the semiconductor substrate is viewed in plan.

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