JP2015201026A - Arithmetic processing device and method for controlling arithmetic processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an increase in the circuit scale of a circuit for controlling a data bypass.SOLUTION: An execution control unit 2 holds the instruction decoded by a decoder unit 1 and outputs executable instructions successively. A memory control unit 4 outputs an access request to a memory 5 on the basis of the memory access instruction received from the execution control unit 2. A second register 8 temporarily holds the data allocated in correspondence to a first register 7 that holds the data used for arithmetic by an arithmetic execution unit 3 and read out from the memory 5, before it is transferred to the first register 7. When the memory control unit 4 outputs a plurality of access requests on the basis of the memory access instruction and successively transfers the data read out from the memory 5 separately a number of times to the second register 8, a bypass control unit 6 causes the execution control unit 2 to output an arithmetic instruction at the time the data last read out from the memory 5 and transferred to the second register 8 is bypassed from the second register 8 to the arithmetic execution unit 3.

Description

  The present invention relates to an arithmetic processing unit and a control method for the arithmetic processing unit.

  An arithmetic processing unit that executes an arithmetic operation has, for example, a bypass function that causes an arithmetic unit to bypass data before data obtained by execution of a preceding instruction is stored in a register. This type of arithmetic processing unit has a circuit that detects a dependency relationship between a register used in a preceding instruction and a register used in a subsequent instruction, and enables the bypass function when there is a dependency relationship. In addition, the double precision floating point register of this type of arithmetic processing apparatus can store one double precision floating point data or two single precision floating point data. For example, by storing one single-precision floating-point data on the upper bit side of a double-precision floating-point register, detection of register dependency in the bypass function can be realized using an existing circuit. In addition, this type of arithmetic processing device has a renaming register that temporarily holds data obtained by arithmetic operations and data read from the data cache (see, for example, Patent Document 1).

JP 2009-230339 A

  For example, when two single-precision floating-point data stored in the double-precision floating-point register are held in different cache lines in the data cache, the two single-precision floating-point data are read from the data cache at different timings. . In this case, a buffer that sequentially holds data read from each cache line and a circuit that determines a timing at which data can be bypassed to the arithmetic unit are provided in the arithmetic processing unit. However, the addition of new circuits increases the circuit scale of the arithmetic processing unit.

  The arithmetic processing device and the control method of the arithmetic processing device disclosed herein suppress an increase in the circuit scale of a circuit that controls data bypass when data is read from a memory in a plurality of times based on a memory access instruction. With the goal.

  According to one aspect, the arithmetic processing device includes a decoder unit that decodes instructions, an execution control unit that holds instructions decoded by the decoder unit, and sequentially outputs executable instructions, and an operation received from the execution control unit An operation execution unit that executes an operation based on an operation instruction indicating execution of the operation, a memory that stores data used in the operation execution unit, and a plurality of first registers that hold data used for the operation executed by the operation execution unit A plurality of second registers that are allocated corresponding to the first register used for the operation and temporarily hold before transferring the data obtained by executing the operation instruction or the memory access instruction to the first register; Memory that retains the allocation relationship between one register and the second register, and that reads data from a register management unit that is referred to by the execution control unit and a memory that is received from the execution control unit A memory control unit that outputs an access request to the memory based on the access instruction, and the memory control unit outputs a plurality of access requests based on the memory access command, and the data read out from the memory in a plurality of times is stored in the second register In the case of sequential transfer, a bypass control unit that outputs an operation instruction to the execution control unit at a timing when data is read from the memory to the second register after the data is transferred to the second register and then is bypassed from the second register to the operation execution unit. Have.

  According to another aspect, a decoder unit that decodes an instruction, an execution control unit that holds instructions decoded by the decoder unit and sequentially outputs executable instructions, and an operation that indicates execution of an operation received from the execution control unit An operation execution unit that executes an operation based on an instruction, a memory that stores data used in the operation execution unit, a plurality of first registers that hold data used for an operation executed by the operation execution unit, and an operation used A plurality of second registers, which are allocated corresponding to the first registers to be stored, and temporarily hold before transferring the data obtained by executing the operation instruction or the memory access instruction to the first register, the first register and the second register A method for controlling an arithmetic processing unit having a register management unit that retains an allocation relationship with a register and is referenced by an execution control unit is executed by a memory control unit included in the arithmetic processing unit. An access request is output to the memory based on a memory access instruction for reading data from the memory received from the control unit, and the memory control unit outputs a plurality of access requests based on the memory access instruction, and is read out from the memory in multiple times. When sequentially transferring data to the second register, the bypass control unit included in the arithmetic processing unit bypasses the data from the second register to the arithmetic execution unit after the data read last from the memory is transferred to the second register At the timing, the execution control unit is caused to output an operation instruction.

  The arithmetic processing device and the control method of the arithmetic processing device disclosed herein suppress an increase in the circuit scale of a circuit that controls data bypass when data is read from a memory in a plurality of times based on a memory access instruction. Can do.

It is a figure which shows one Embodiment of the arithmetic processing apparatus and the control method of an arithmetic processing apparatus. It is a figure which shows another embodiment of the arithmetic processing apparatus and the control method of an arithmetic processing apparatus. FIG. 3 is a diagram illustrating an example of a floating point register unit and a fixed point register unit illustrated in FIG. 2. It is a figure which shows the example of the renaming register part shown in FIG. FIG. 3 is a diagram illustrating an example of a register management table illustrated in FIG. 2. It is a figure which shows the example which loads data from the data cache shown in FIG. It is a figure which shows the example of the set signal generation circuit provided in the bypass control part shown in FIG. It is a figure which shows the example of the bypass management table and table control circuit which are provided in a bypass control part. It is a figure which shows the example of operation | movement of the bypass control part shown to FIG. 7 and FIG. It is a figure which shows the example of operation | movement of the arithmetic processing unit shown in FIG. It is a figure which shows another example of operation | movement of the arithmetic processing unit shown in FIG. It is a figure which shows another example of operation | movement of the arithmetic processing unit shown in FIG. It is a figure which shows another example of operation | movement of the arithmetic processing unit shown in FIG.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an embodiment of an arithmetic processing unit and a control method for the arithmetic processing unit. The arithmetic processing unit OPD1 shown in FIG. 1 includes a decoder unit 1, an execution control unit 2, an operation execution unit 3, a memory control unit 4, a memory 5, a bypass control unit 6, a plurality of first registers 7, and a plurality of second registers 8. And a register management unit 9.

  The decoder unit 1 decodes an instruction received from an instruction buffer or the like, and outputs the decoded instruction to the execution control unit 2. The execution control unit 2 holds the instructions decoded by the decoder unit 1 and sequentially outputs executable instructions to the arithmetic execution unit 3 or the memory control unit 4. That is, the execution control unit 2 controls out-of-order execution that changes the execution order of instructions. When the instruction is an operation instruction indicating execution of an operation, the execution control unit 2 outputs the operation instruction to the operation execution unit 3. When the instruction is a memory access instruction for reading data from the memory 5, the execution control unit 2 transmits the memory access instruction to the memory control unit. 4 is output.

  The operation execution unit 3 executes an operation using the data stored in the first register 7 based on the operation instruction received from the execution control unit 2. When the data used for the calculation is stored in the second register 8, the calculation execution unit 3 does not go through the first register 7, but passes through the bypass path indicated by the thick dashed arrow in FIG. It is possible to receive data from the register 8 and execute an operation. The bypass control unit 6 determines whether or not the data from the second register 8 can be bypassed. When the bypass control unit 6 determines that the bypass is possible, the execution control unit 2 inputs the calculation instruction to the calculation execution unit 3 at a timing at which the bypass can be performed. The operation execution unit 3 outputs data obtained by executing the operation to the second register 8.

  The memory control unit 4 outputs an access request to the memory 5 based on a memory access instruction (for example, a load instruction) received from the execution control unit 2. For example, when data read by a memory access instruction is stored in an area to which one address is allocated in the memory 5, the memory control unit 4 generates one access request based on the memory access instruction. Data read from the memory 5 in response to the access request is stored in the second register 8 at a time.

  On the other hand, when the data read by the memory access instruction is stored in an area to which a plurality of addresses are allocated in the memory 5, the memory control unit 4 sequentially generates a plurality of access requests based on the memory access instruction. Data read from the memory 5 in response to a plurality of access requests is sequentially stored in the second register 8. That is, when the data read by the memory access instruction is stored in an area in the memory 5 to which a plurality of addresses are assigned, load data timing shift occurs.

  The data read in a plurality of times based on the memory access instruction is stored in the second register 8 when the data read from the memory 5 corresponding to the last access request is stored in the second register 8. It's aligned. In other words, when the data read by the memory access instruction is read from the memory 5 by a plurality of access requests, the data can be waited using the second register 8. As a result, the arithmetic processing unit OPD1 can wait for data without providing a new circuit even when reading data from the memory 5 in a plurality of times based on a memory access instruction, and suppresses an increase in circuit scale. can do.

  The memory 5 stores data used in the operation execution unit 3, and outputs the stored data based on the access request. Data read from the memory 5 is transferred to the first register 7 via the second register 8.

  Each of the first registers 7 holds data used for an operation executed by the operation execution unit 3. Each of the second registers 8 is assigned corresponding to the first register 7 used for the operation. The second register 8 assigned corresponding to the first register 7 temporarily holds data obtained by execution of the arithmetic instruction or the memory access instruction before transferring it to the first register 7.

  The register management unit 9 holds the allocation relationship between the first register 7 and the second register 8. The execution control unit 2 refers to the register management unit 9 to recognize, for example, the second register 8 to which the first register 7 designated by the instruction operand is assigned. For example, when the decoder unit 1 decodes the instruction, the decoder unit 1 determines the second register 8 to which the first register 7 is allocated, and stores information indicating the determined allocation in a table included in the register management unit 9. The decoder unit 1 assigns the second register 8 corresponding to the first register 7 used for the operation, so that the first register 7 is redundantly indicated by the operand of the instruction and a dependency relationship occurs. Arithmetic can be performed as an unrelated source. As a result, the calculation efficiency of the calculation execution unit 3 can be improved as compared with the case where the second register 8 is not used.

  For example, the bypass control unit 6 can bypass the data read from the memory 5 and stored in the second register 8 to the arithmetic execution unit 3 based on information indicating the access status of the memory 5 received from the memory control unit 4. It is determined whether or not. Further, the bypass control unit 6 calculates the data obtained by the calculation of the calculation execution unit 3 and stored in the second register 8 based on the information indicating the execution status of the calculation by the calculation execution unit 3 received from the execution control unit 2. It is determined whether the execution unit 3 can be bypassed.

  When the memory control unit 4 reads data from the memory 5 at a time based on the memory access instruction, the bypass control unit 6 determines that the data can be bypassed after being transferred from the memory 5 to the second register 8. . In this case, the data read from the memory 5 is both the first data and the last data. The bypass control unit 6 then sends an operation instruction to the execution control unit 2 at a timing to bypass the data from the second register 8 to the operation execution unit 3 after the last data is transferred from the memory 5 to the second register 8. Is output.

  On the other hand, when the memory control unit 4 reads data from the memory 5 in a plurality of times based on the memory access instruction, the bypass control unit 6 bypasses the data and transfers the last data from the memory 5 to the second register 8. Judge that it will be possible after. The bypass control unit 6 then causes the execution control unit 2 to bypass the data from the second register 8 to the calculation execution unit 3 at the timing when the last data is transferred from the memory 5 to the second register 8. Output operation instructions.

  As described above, in the embodiment illustrated in FIG. 1, the bypass control unit 6 notifies the execution control unit 2 that the data can be bypassed after all the data read from the memory 5 is stored in the second register 8. . As a result, even when the timing of data loaded from the memory 5 to the second register 8 is shifted, the data can be waited using the existing second register 8. In other words, data can be queued without providing a new circuit, and an increase in the circuit scale of the arithmetic processing unit OPD1 can be suppressed.

  In addition, the bypass control unit 6 does not depend on whether the data is read from the memory 5 once or divided into a plurality of times based on the memory access instruction. It is determined that bypass is possible after being transferred. Thereby, control of the bypass timing by the bypass control part 6 can be simplified similarly to the past. As a result, the circuit scale of the arithmetic processing unit OPD1 increases even when the bypass timing is changed between when the data is read from the memory 5 once based on the memory access instruction and when the data is read in multiple times. Can be suppressed. Furthermore, by suppressing an increase in circuit scale, an increase in power consumption of the arithmetic processing unit OPD1 can be suppressed, and an operating frequency of the arithmetic processing device OPD1 can be improved.

  FIG. 2 shows another embodiment of the arithmetic processing device and the control method of the arithmetic processing device. A thick solid line arrow in FIG. 2 indicates the transfer path of the floating point data when the load instruction is executed. The thick dashed arrows in FIG. 2 indicate the floating point data bypass path during execution of the load instruction. Note that the bypass path for fixed-point data is not shown.

  The arithmetic processing unit OPD2 illustrated in FIG. 2 includes an instruction cache 10, an instruction buffer 12, a decoder unit 14, a register management table 16, a reservation station 18, an address generation unit 20, a data cache 22, and a bypass control unit 24. The arithmetic processing unit OPD2 includes a floating point arithmetic unit 26, a fixed point arithmetic unit 28, a load register 30, result registers 32 and 34, renaming register units 36 and 38, a floating point register unit 40, a fixed point register unit 42, and A commit control unit 44 is included.

  For example, the instruction cache 10 is a primary instruction cache that stores instructions transferred from a secondary instruction cache or a main memory. The instruction buffer 12 holds instructions sequentially transferred from the instruction cache 10 and sequentially transfers the held instructions to the decoder unit 14.

  The decoder unit 14 sequentially decodes instructions transferred from the instruction buffer 12, and stores information INS (hereinafter referred to as instruction information INS) included in the decoded instructions in the reservation station 18. For example, the command information INS is stored in any of the reservation stations RSFLT, RSFIX, and RSMA included in the reservation station 18 according to the type of the command.

  When the decoded instruction indicates that the floating point register in the floating point register unit 40 is used as the data storage destination, the decoder unit 14 determines the floating point register to be used as the renaming register in the renaming register unit 36. Assign to one. For example, the decoder unit 14 outputs the register number RN of the floating-point register used as the data storage destination and the address UBA indicating the renaming register to be allocated to the register management table 16 and the commit control unit 44 together with the write request WE. . For example, the address UBA is an abbreviation for “Update Buffer Address”. When the renaming register unit 36 has 32 renaming registers, the address UBA is 5 bits. The address UBA is also output to the reservation station 18. An example of the floating point register unit 40 is shown in FIG. 3, and an example of the renaming register unit 36 is shown in FIG.

  Similarly, when the decoded instruction indicates that the decoded instruction uses the fixed-point register in the fixed-point register unit 42 as the data storage destination, the decoder unit 14 converts the fixed-point register to be used into the rename register in the renaming register unit 38. Assign to one of the naming registers. For example, the decoder unit 14 sends the register number RN indicating the fixed-point register used as the data storage destination and the address UBA indicating the assigned renaming register to the register management table 16 and the commit control unit 44 together with the write request WE. Output. The decoder unit 14 outputs a register number RN and an address UBA that can identify the floating point register unit 40 and the fixed point register. An example of the fixed-point register unit 42 is shown in FIG. 3, and an example of the renaming register unit 38 is shown in FIG.

  The register management table 16 includes a floating-point register table RMTBL1 and a fixed-point register table RMTBL2. The register management table 16 updates information stored in one of the tables RMTBL1 and RMTBL2 according to the register number RN, address UBA, and write request WE received from the decoder unit 14. The register management table 16 outputs the address UBA and the bit value P stored in the tables RMTBL1 and RMTBL2 to the reservation station 18 in response to a read request from the reservation station 18. The register management table 16 invalidates the address UBA registered in either of the tables RMTBL1 and RMTBL2 based on the reset request RST1 from the commit control unit 44. The register management table 16 is an example of a register management unit that holds an allocation relationship between the floating-point register FR and the renaming register RNFR and is referred to by the reservation station RSFLT. An example of the register management table 16 is shown in FIG.

  The reservation station 18 includes three reservation stations RSFLT, RSFIX, and RSMA. The reservation station 18 is an example of an execution control unit that holds instructions (command information INS) decoded by the decoder unit 14 and sequentially outputs executable instructions. The reservation station RSFLT holds instruction information INS included in instructions for calculating floating point data. The reservation station RSFIX holds instruction information INS included in instructions for calculating fixed-point data. The reservation station RSMA holds command information INS included in the memory access command.

  The reservation station 18 holds an address UBA and a bit value P indicating a renaming register to which a floating point register (or a fixed point register) obtained by referring to the register management table 16 is assigned based on the instruction information INS. The held bit value P is invalidated based on the reset request RST2 received from the commit control unit 44 when the execution of the instruction is completed, and the address UBA of the instruction that has been executed is discarded due to the invalidation of the bit value P.

  The reservation station 18 receives the address UBA of the renaming register to which the floating point register (or fixed point register) for storing data is assigned from the decoder unit 14 together with the instruction information INS. The reservation station 18 also reads from the register management table 16 the address UBA of the renaming register to which the floating-point register (or fixed-point register) from which data is read is assigned. Hereinafter, the floating-point register (or fixed-point register) that stores data is also referred to as a destination register, and the floating-point register (or fixed-point register) that reads data is also referred to as a source register.

  The reservation station 18 determines the dependency relationship of the held instruction based on the address UBA read from the register management table 16 and the bypass enable signal BPEN (BPEN0-BPEN31) output from the bypass control unit 24. Then, the reservation station 18 sequentially inputs an executable operation instruction from the held instructions to the floating point arithmetic unit 26 or the fixed point arithmetic unit 28. Alternatively, the reservation station 18 sequentially inputs an executable load instruction or store instruction from among the held instructions to the address generation unit 20 as an access request MREQ. An access request MREQ indicating a load instruction is an example of a memory access instruction for reading data from the data cache 22. The reservation station 18 is an example of an execution control unit that controls out-of-order execution that changes the execution order of instructions.

  The reservation station 18 outputs the control signal B1FP and the address B1FPUBA to the bypass control unit 24 when the data obtained by the calculation of the floating point arithmetic unit 26 can be bypassed from the result register 32 or the renaming register unit 36. The control signal B1FP is a start signal indicating the timing at which the floating point arithmetic unit 26 starts operation. The output timing of the control signal B1FP indicates the timing at which the flag area FLG (FIG. 8) of the bypass management table of the bypass control unit 24 is set. “B1” at the head of the control signal B1FP and the address B1FPUBA indicates that the control signal B1FP and the address B1FPUBA are generated in a B1 cycle to be described later. The operation of bypass control unit 24 when receiving control signal B1FP and address B1FPUBA will be described with reference to FIG.

  The address generation unit 20 generates an access request MREQC to be output to the data cache 22 based on the access request MREQ output from the reservation station 18. The address generation unit 20 outputs the control signals ALDL and ALDH and the address ALDUBA to the bypass control unit 24 together with the access request MREQC for reading the floating point data from the data cache 22. The control signals ALDL and ALDH are an example of a start signal indicating a timing at which loading of data from the data cache 22 is started. For example, the control signals ALDL and ALDH are generated in synchronization with the access request MREQC. The control signal ALDL is generated when lower 4 bytes of data are loaded, and the control signal ALDH is generated when upper 4 bytes of data are loaded. The lower 4 bytes of data and the upper 4 bytes of data are examples of data groups.

  “A” at the head of the control signals ALDL and ALDH and the address ALDUBA indicates that the control signals ALDL and ALDH and the address ALDUBA are generated in an A cycle described later. The value of the address ALDUBA indicates the renaming register RNFR (FIG. 4) to which bypassable data is transferred. The number of bits of the address ALDUBA is 6 bits that can identify 64 renaming registers RNFR.

  When data can be read from one cache line in the data cache 22 based on the access request MREQ, the address generation unit 20 generates one access request MREQC. On the other hand, there is a case where the data is held in two cache lines in the data cache 22 based on the access request MREQ, or a case where a part of the data is not held in the data cache 22 (cache miss). In this case, the address generation unit 20 generates an access request MREQC for reading data from one cache line, and then generates an access request MREQC for reading data from another cache line at a time interval. That is, there is a timing shift in the load data read from the data cache 22.

  For example, when the 8-byte data to be transferred to the renaming register unit 36 is read from the data cache 22 at a time by one access request MREQC, the address generation unit 20 generates both control signals ALDL and ALDH. When the address generation unit 20 reads out the 8-byte data to be transferred to the renaming register unit 36 from the data cache 22 every two 4-byte data according to the two access requests MREQC, the control signals ALDL and ALDH have different timings from each other. Generate with

  For example, when the 8-byte data is read from the data cache 22 in units of 4 bytes, the address generation unit 20 reads the upper 4 bytes and then the lower 4 bytes. Therefore, at the timing when the control signal ALDL is output, the upper 4 bytes of data are output from the data cache 22 and sequentially transferred to the load register 30 and the renaming register unit 36. The operation of the bypass control unit 24 when receiving the control signals ALDL and ALDH and the address ALDUBA will be described with reference to FIG. The address generation unit 20 is an example of a memory control unit that outputs an access request MREQC to the data cache 22 based on an access request MREQ (memory access instruction) received from the reservation station RSFLT.

  For example, the data cache 22 is a primary data cache that stores data transferred from a secondary data cache or a main memory. The data cache 22 is accessed by an access request MREQC from the address generation unit 20. When the data cache 22 holds data corresponding to the access request MREQC (cache hit), the data cache 22 outputs the held data to the load register 30. When the data cache 22 does not hold data corresponding to the access request MREQC (cache miss), the data cache 22 reads data from the secondary data cache, the main memory, or the like, and stores the read data in the storage area of the data cache 22.

  Further, the data cache 22 outputs a completion signal CE to the bypass control unit 24 in a cycle of outputting data to the load register 30 when a cache hit occurs. The data cache 22 prohibits the output of the completion signal CE when a cache miss occurs.

  The bypass control unit 24 includes a bypass management table BPTBL that holds information indicating whether or not the floating-point data can be bypassed for each renaming register included in the renaming register unit 36. The bypass control unit 24 outputs a bypass enable signal BPEN (BPEN0-BPEN31) based on the information held in the bypass management table BPTBL. Further, the bypass control unit 24 has a bypass management table (not shown) that holds information indicating whether or not fixed-point data can be bypassed for each renaming register of the renaming register unit 38.

  The bypass control unit 24 sets the bypass enable signal BPEN (any one of BPEN0 to BPEN31) corresponding to the addresses B1FPUBA and ALDUBA to an effective level based on the control signals B1FP, ALDL, and ALDH. The bypass control unit 24 sets the bypass enable signal BPEN corresponding to the address WCMTUBA to an invalid level based on the control signal WCMT. Based on the completion signal CE, the bypass control unit 24 sets the bypass enable signal BPEN indicated by the address ALDUBA corresponding to the cache-missed access instruction MREQC to an invalid level. Examples of the bypass control unit 24 are shown in FIGS. 7 and 8.

  The floating point arithmetic unit 26 executes an operation based on the instruction transferred from the reservation station RSFLT and stores the execution result in the result register 32. The floating point arithmetic unit 26 is an example of an operation execution unit that executes an operation based on an operation instruction indicating execution of an operation received from the reservation station RSFLT. The calculation by the floating point arithmetic unit 26 is executed using data stored in at least one of the floating point register unit 40, the renaming register unit 36, the result register 32, and the load register 30.

  The fixed point arithmetic unit 28 performs an operation based on an instruction transferred from the reservation station RSFIX, and stores the execution result in the result register 34. The calculation by the fixed-point calculator 28 is executed using data stored in at least one of the fixed-point register unit 42, the renaming register unit 38, the result register 34, and the load register 30.

  The load register 30 temporarily holds data read from the data cache 22 based on the execution of the load instruction, and transfers the held data to the renaming register unit 36 or the renaming register unit 38 via the data line LDD. . The load register 30 is arranged between the data cache 22 and the renaming register RNFR (FIG. 4), and is a third register that temporarily holds data read from the data cache 22 before transferring it to the renaming register RNFR. It is an example.

  The result register 32 temporarily holds the calculation result by the floating point calculator 26 and transfers the held data to the renaming register unit 36 via the data line EXD1. The result register 34 temporarily holds the calculation result by the fixed-point calculator 28 and transfers the held data to the renaming register unit 38 via the data line EXD2.

  For example, the renaming register unit 36 has 32 renaming registers RNFR that temporarily hold floating point data obtained by an operation executed by the floating point arithmetic unit 26 or floating point data transferred from a data cache (see FIG. 4). The data held in each renaming register RNFR is transferred to the floating point register unit 40 in response to a read request RCMT1 output from the commit control unit 44 based on the completion of the instruction. The renaming register RNFR is assigned corresponding to the floating-point register FR (FIG. 3), and temporarily holds the data obtained by executing the operation instruction or the memory access instruction before transferring it to the floating-point register FR. It is an example of a register.

  For example, the renaming register unit 38 temporarily stores the 32 renaming registers RNR (see FIG. 5) that hold the fixed-point data obtained by the calculation executed by the fixed-point calculator 28 or the fixed-point data transferred from the data cache. 4). The data held in each renaming register RNR is transferred to the fixed-point register unit 42 in response to a read request RCMT2 output from the commit control unit 44 based on the completion of the instruction. An example of the renaming register units 36 and 38 is shown in FIG.

  For example, the floating-point register unit 40 has 64 floating-point registers FR (FIG. 3) that hold floating-point data obtained by an operation executed by the floating-point calculator 26 or floating-point data transferred from the data cache 22. Have The floating point register FR is an example of a first register that holds data used for an operation executed by the floating point arithmetic unit 26. The floating point register unit 40 stores the data transferred from the renaming register unit 36 in response to the write request WCMT1 output from the commit control unit 44 based on the completion of the instruction.

  For example, the fixed-point register unit 42 has 32 fixed-point registers R that hold fixed-point data obtained by the operation executed by the fixed-point calculator 28 or fixed-point data transferred from the data cache 22 (FIG. 3). Have The fixed-point register unit 42 stores data transferred from the renaming register unit 38 in response to the write request WCMT2 output from the commit control unit 44 based on the completion of the instruction. Examples of the floating point register unit 40 and the fixed point register unit 42 are shown in FIG.

  The commit control unit 44 outputs a reset request RST1 to the register management table 16 and outputs a reset request RST2 to the reservation station 18 based on the completion of execution of the instruction. Further, the commit control unit 44 outputs a control signal WCMT and an address WCMTUBA to the bypass control unit 24 based on completion of execution of the instruction. The commit control unit 44 holds the register number RN and the address UBA output by the decoder unit 14 based on the decoding of the instruction for each instruction. The commit control unit 44 outputs a read request RCMT1 (or RCMT2) for reading data from the renaming register RNFR indicated by the address UBA corresponding to the instruction that has been executed among the held addresses UBA. The commit control unit 44 outputs a write request WCMT1 (or WCMT2) for writing data to the destination register indicated by the register number RN corresponding to the instruction that has been executed among the held register numbers RN.

  FIG. 3 shows an example of the floating point register unit 40 and the fixed point register unit 42 shown in FIG. The floating point register unit 40 includes 64 floating point registers FR (FR0 to FR63) for storing double precision (8 bytes) floating point data. The floating point register unit 40 includes a write control unit WCNT1 that controls writing of data to the floating point register FR and a read control unit RCNT1 that controls reading of data from the floating point register FR.

 Each floating point register FR has an 8-byte storage area for storing 8-byte double data DD (double-precision floating-point data) or 4-byte two single data SD (single-precision floating-point data). Yes. That is, each floating-point register FR can store two single-precision (4-byte) floating-point data. FIG. 3 shows a state in which double data DD is stored in the floating-point register FR0 and two single data SD are stored in the floating-point register FR1.

  By storing two single data SD in one floating point register FR, two single data SD can be used according to the number of one floating point register FR. Thereby, the calculation performance of single-precision floating-point data is improved as compared with the case where single data SD is stored in each of the two floating-point registers FR. Hereinafter, the floating-point register FR that stores two single data SD is also referred to as a double-width single-precision floating-point register, and the data stored in the double-width single-precision floating-point register is also referred to as double-width single-precision floating-point data. Is done.

  The fixed-point register unit 42 has 32 fixed-point registers R (R0 to R31) that store 8-byte fixed-point data. The fixed-point register unit 42 includes a write control unit WCNT2 that controls writing of data to the fixed-point register R and a read control unit RCNT2 that controls reading of data from the fixed-point register R. Each fixed-point register R has an 8-byte storage area for storing 8-byte double data DD. FIG. 3 shows a state in which double data DD is stored in the fixed-point register R1.

  FIG. 4 shows an example of the renaming register units 36 and 38 shown in FIG. The renaming register unit 36 includes 32 renaming registers RNFR (RNFR0 to RNFR31) to which any of the floating-point registers FR illustrated in FIG. 3 is assigned, a write control unit WCNT3, and a read control unit RCNT3. Each renaming register RNFR has an 8-byte storage area including two 4-byte storage areas. The write control unit WCNT3 includes a selector SEL3 that selects either the data EXD1 transferred from the result register 32 when the arithmetic instruction is executed or the data LDD transferred from the load register 30 when the load instruction is executed. For example, the renaming register RNFR into which data is written by the write control unit WCNT3 is specified by the reservation station 18 based on information stored in the register management table 16.

  When the selector SEL3 stores data in the upper 4 bytes of each renaming register RNFR, the selector SEL3 outputs the write control signal WE1H and 4 bytes (that is, 32 bits) of data EXD1H to the renaming register RNFR. When the selector SEL3 stores data in the lower 4 bytes of the renaming register RNFR, the selector SEL3 outputs the write control signal WE1L and 4 bytes (that is, 32 bits) of data EXD1L to the renaming register RNFR. For example, the write control signals WE1H and WE1L are generated based on reception of data EXD1 and LDD (64 bits each) by the write control unit WCNT3.

  Data transferred from the floating point arithmetic unit 26 to the result register 32 and data EXD1 transferred from the result register 32 to the renaming register unit 36 are 8 bytes. Therefore, when receiving the data EXD1, the write control unit WCNT3 generates the write control signals WE1H and WE1L, and stores the 8-byte data EXD1H and EXD1L in the renaming register RNFR.

  When the data LDD transferred from the load register 30 based on the load instruction is double precision floating point data (8 bytes), the write control unit WCNT3 generates the write control signals WE1H and WE1L. As a result, 8-byte data EXD1H and EXD1L (that is, double-precision floating-point data) are stored in the renaming register RNFR. Even when the data LDD transferred from the load register 30 based on the load instruction is double-width single precision floating point data (8 bytes), the write control unit WCNT3 generates the write control signals WE1H and WE1L.

  On the other hand, when the data LDD transferred from the load register 30 based on the load instruction is the upper 4 bytes of the double-width single precision floating point data, the write control unit WCNT3 generates the write control signal WE1H. As a result, 4-byte data EXD1H (that is, the upper 4 bytes of double-width single-precision floating-point data) is stored in the upper 4 bytes of the renaming register RNFR. Similarly, when the data LDD transferred from the load register 30 based on the load instruction is the lower 4 bytes of the double-width single precision floating point data, the write control unit WCNT3 generates the write control signal WE1L. As a result, 4-byte data EXD1L (that is, the lower 4 bytes of the double-width single-precision floating-point data) is stored in the lower 4 bytes of the renaming register RNFR.

  Here, when double-width single-precision floating-point data is included in one cache line of the data cache 22, it is transferred at once, and when it is included across two cache lines, it is divided into upper 4 bytes and lower 4 bytes. Are transferred sequentially.

  The read control unit RCNT3 reads data from one of the renaming registers RNFR0 to RNFR31 based on the read request RCMT1 output from the commit control unit 44, and outputs the read data to the floating point register unit 40. For example, the renaming register RNFR from which data is read by the read control unit RCNT3 is designated by the reservation station 18 based on information stored in the register management table 16.

  The renaming register unit 38 includes 32 renaming registers RNR (RNR0 to RNR31) to which any of the fixed-point registers R shown in FIG. 3 is assigned, a write control unit WCNT4, and a read control unit RCNT4. Each renaming register RNR has an 8-byte storage area. The write control unit WCNT4 includes a selector SEL4 that selects either the data EXD2 output from the result register 34 when the arithmetic instruction is executed or the data LDD output from the load register 30 when the load instruction is executed. For example, the renaming register RNR into which data is written by the write control unit WCNT4 is designated by the reservation station 18.

  When the selector SEL4 stores data in the renaming register RNR, the selector SEL4 outputs the write control signal WE2 and 8-byte (64-bit) data EXD2 to the renaming register RNR. For example, the write control signal WE2 is generated by the write control unit WCNT4 based on reception of data EXD2 and LDD (each 64 bits). The read control unit RCNT3 reads data from one of the renaming registers RNR0 to RNR31 based on the read request RCMT2 output from the commit control unit 44, and outputs the read data to the fixed-point register unit 42. For example, the renaming register RNR from which data is read by the read control unit RCNT4 is designated by the reservation station 18 based on information stored in the register management table 16.

  In FIG. 4, the circuit scale of the selector SEL3 appears larger than the circuit scale of the selector SEL4. However, the total width of the data EXD1H and EXD1L output from the selector SEL3 is 64 bits, which is the same as the width of the data EXD2 output from the selector SEL4. Therefore, the circuit scale of the write control unit WCNT3 when the upper 4 bytes of data and the lower 4 bytes of data are respectively stored in the renaming register RNFR can be made equal to the circuit scale of the write control unit WCNT4. . For example, the elements of the write control unit WCNT3 added to the write control unit WCNT4 are a logic circuit that generates the write control signals WE1H and WE1L and a wiring region for the write control signal WE1H. Therefore, the circuit scale of the renaming register section 36 is equivalent to the circuit scale of the existing renaming register section and the renaming register section 38.

  When double-width single-precision floating-point data is read from the data cache 22 separately in the upper 4 bytes and the lower 4 bytes, when the lower 4 bytes are stored in the renaming register RNFR, the 8-byte data is renamed. Aligned in register RNFR. That is, double-width single-precision floating-point data transferred separately into upper 4 bytes and lower 4 bytes are waited at the renaming register unit 36 and combined. When the renaming register unit 36 shown in FIG. 4 is not used, a new buffer circuit or the like that combines double-width single-precision floating-point data transferred separately in the upper 4 bytes and the lower 4 bytes is provided in the data cache 22, for example. Connected to output. As described above, the circuit scale of the renaming register unit 36 is equal to the circuit scale of the existing renaming register unit. For this reason, the arithmetic processing unit OPD2 having the renaming register unit 36 has a new buffer circuit that combines double-width single-precision floating-point data that is transferred divided into data groups of upper 4 bytes and lower 4 bytes. Compared with the processing apparatus, the circuit scale can be reduced.

  FIG. 5 shows an example of the register management table 16 shown in FIG. The table RMTBL1 of the register management table 16 has 64 areas for storing the bit value P and the address UBA corresponding to each of the 64 floating point registers FR0 to FR63 of the floating point register unit 40. In FIG. 5, the number shown at the left end of the table RMTBL1 indicates the number of the floating point register FR (that is, the register number RN).

  When the register management table 16 receives the register number RN indicating the floating point register FR and the address UBA together with the write request WE from the decoder unit 14, the register management table 16 stores the address UBA in an area corresponding to the register number RN in the table RMTBL1. The address UBA indicates a renaming register RNFR to which the floating point register FR is allocated. Then, the register management table 16 sets the bit value P of the area storing the address UBA. The bit value P indicates whether the address UBA is valid or invalid. As a result, the correspondence between the floating point register FR and the renaming register RNFR determined by the decoder unit 14 is held in the table RMTBL1.

  When receiving a read request referring to the table RMTBL1 from the decoder unit 14, the register management table 16 reads the bit value P and the address UBA from the area corresponding to the register number RN included in the read request. Then, the register management table 16 outputs the read bit value P and address UBA to the reservation station 18.

  The table RMTBL2 of the register management table 16 has 32 areas for storing the bit value P and the address UBA corresponding to each of the 32 fixed-point registers R0 to R31 of the fixed-point register unit 42. In FIG. 5, the number shown at the left end of the table RMTBL2 indicates the number of the fixed-point register R (that is, the register number RN).

  Similarly to the table RMTBL1, the register management table 16 stores the address UBA in the area corresponding to the register number R in the table RMTBL2, and sets the bit value P. The address UBA indicates a renaming register RNR to which the fixed point register R is assigned. Thereby, the correspondence between the fixed-point register R and the renaming register RNR determined by the decoder unit 14 is held in the table RMTBL2. Similarly to the table RMTBL 1, the register management table 16 reads the bit value P and the address UBA from the area corresponding to the register number R included in the read request from the reservation station 18, and outputs it to the reservation station 18.

  FIG. 6 shows an example of loading data from the data cache 22 shown in FIG. For example, the data cache 22 has 64 cache lines having a width of 128 bytes. “70”, “80”, and the like shown in FIG. 6 are hexadecimal numbers and indicate the lower 8 bits of the head addresses of two consecutive cache lines. A numerical value in parentheses on the right side of the hexadecimal address is a value representing the address in binary. In the following, it is assumed that data is continuously stored in two consecutive cache lines shown in FIG.

  For example, in a load instruction that loads double precision floating point data (8 bytes), the lower 3 bits of the address are set to “000”, and in a load instruction that loads double width single precision floating point data, the lower 2 bits of the address Is set to “00”. For this reason, the double-precision floating point data loaded from the data cache 22 does not straddle the boundary of the cache line (FIG. 6A). The double-width single-precision floating point data loaded from the data cache 22 does not cross the boundary of the cache line when the lower 3 bits of the head address are “000” (FIG. 6B). However, when the lower 3 bits of the head address are “100”, the double-width single-precision floating point data loaded from the data cache 22 may straddle the boundary of the cache line (FIG. 6C). FIG. 6D shows an example in which the lower 3 bits of the head address are “100” and the boundary of the cache line is not straddled.

  In the load instruction for loading double-width single-precision floating-point data, when a head address that crosses the boundary of the cache line is specified, the address generation unit 20 shown in FIG. 2 generates an access request MREQC for each cache line. That is, when the double-width single-precision floating point data is stored in the data cache 22 across the boundary of the cache line, the address generation unit 20 divides the double-width single-precision floating point data into two data caches 22. Read from. In this embodiment, as will be described with reference to FIG. 12, even when data is read from the data cache 22 in two steps by a load instruction, the increase in circuit scale is suppressed and data is floating-point operated at the correct timing. Can be bypassed.

  If the upper 4 bytes or the lower 4 bytes of the double-width single-precision floating-point data are not stored in the data cache 22 (cache miss), the data cache 22 receives 128 bytes from the secondary data cache 22 or the main memory. Read data. The data cache 22 stores the read 128-byte data in one of the cache lines. Then, after the data is stored in the data cache 22, the address generation unit 20 issues an access request MREQC for reading the upper 4 bytes or the lower 4 bytes of the double-width single precision floating point data to the data cache 22.

  FIG. 7 shows an example of the set signal generation circuit SSGEN provided in the bypass control unit 24 shown in FIG. The set signal generation circuit SSGEN includes two latch circuits FF1 and FF2 and cycle signal generation units ASGEN and MSGEN connected in series. The latch circuits FF1 and FF2 operate in synchronization with the clock signal CLK and latch the control signals ALDL, ALDH, and ALDBUA from the address generation unit 20.

  The cycle signal generator ASGEN includes an AND circuit AND1 that receives the control signals ALDL and ALDH. The cycle signal generator ASGEN sets the set signal ALDSET to an effective level when both the control signals ALDL and ALDH are at an effective level (for example, high level). One of the flag areas FLG of the bypass table BPTBL shown in FIG. 8 is set by the effective level set signal ALDSET. The flag area FLG to be set is indicated by an address ALDUBA. The set timing of the flag area FLG by the set signal ALDSET is an A cycle described later. The cycle signal generation unit ASGEN sets the set signal ALDSET to an invalid level when at least one of the control signals ALDL and ALDH is at an invalid level (for example, low level). The cycle signal generation unit ASGEN is an example of a first generation circuit that generates a set signal ALDSET based on reception of a plurality of control signals ALDL and ALDH at a common timing.

  The cycle signal generation unit MSGEN has an inverter IV1 connected to the output Q1 of the latch circuit FF2, and an AND circuit AND2 connected to the output Q0 of the latch circuit FF2 and the output of the inverter IV1. The latch circuit FF2 outputs a signal obtained by delaying the control signal ALDL by two clock cycles from the output Q0, and outputs a signal obtained by delaying the control signal ALDH by two clock cycles from the output Q2. The cycle signal generation unit MSGEN sets the set signal MLDSET to the valid level when the control signals ALDL and ALDH delayed by two clock cycles are at the valid level and the invalid level, respectively. One of the flag areas FLG of the bypass table BPTBL shown in FIG. 8 is set by an effective level set signal MLDSET. The flag area FLG to be set is indicated by an address MLDUBA. The set timing of the flag area FLG by the set signal MLDSET is an M cycle described later.

  The cycle signal generation unit MSGEN sets the set signal MLDSET to the invalid level when the control signal ALDL delayed by two clock cycles is at the invalid level or when the control signal ALDH delayed by two clock cycles is at the valid level. The cycle signal generation unit MSGEN is an example of a second generation circuit that generates the set signal MLDSET after a predetermined cycle from the reception of the last control signal ALDL.

  When both of the control signals ALDL and ALDH are at an invalid level, the address generation unit 20 does not output the access request MREQC to the data cache 22, so that the set signals ALDSET and MLDSET are not at the valid level. For this reason, the flag area FLG is not set.

  When both the control signals ALDL and ALDH are at a valid level, the address generation unit 20 outputs an access request MREQC that reads 8-byte data from the data cache 22. In this case, the set signal ALDSET becomes a valid level, the set signal MLDSET becomes an invalid level, and the flag area FLG is set in the A cycle.

  When the control signal ALDL is at the invalid level and the control signal ALDH is at the valid level, the address generation unit 20 outputs an access request MREQC for reading the upper 4 bytes of double-width single precision floating point data from the data cache 22. . In this case, both the set signals ALDSET and MLDSET do not become valid levels, and the flag area FLG is not set.

  When the control signal ALDL is at a valid level and the control signal ALDH is at an invalid level, the address generation unit 20 outputs an access request MREQC for reading the lower 4 bytes of double-width single precision floating point data from the data cache 22. . At this point, the upper 4 bytes of the double-width single-precision floating-point data are already loaded from the data cache 22, and the lower-order 4 bytes of data are read from the data cache 22, so that the 8-byte double-width single precision floating point data is read. The decimal point data is available. In this case, the set signal ALDSET becomes an invalid level, the set signal MLDSET becomes an effective level, and the flag area FLG is set in M cycles.

  In this embodiment, it is possible to determine whether 8-byte data is read from the data cache 22 by the cycle signal generation units ASGEN and MSGEN having a scale of several gates, and to generate the set signal ALDSET or the set signal MLDSET.

  FIG. 8 shows an example of the bypass management table BPTBL and the table control circuit TSCNT provided in the bypass control unit 24.

  The bypass management table BPTBL has 32 flag areas FLG (FLG0 to FLG31) each having a 1-bit latch circuit. The bypass management table BPTBL latches the logic of the input terminal in synchronization with the clock signal CLK and holds it in each flag area FLG, and outputs the held logic as a bypass enable signal BPEN (BPEN0-BPEN31).

  An effective level (for example, high level) bypass enable signal BPEN indicates that data can be bypassed using the bypass path indicated by a thick broken line in FIG. That is, the flag area FLG in the set state indicates that the data stored in the renaming register RNFR, the result register 32, or the load register 30 can be bypassed to the floating point arithmetic unit 26 without going through the floating point register unit 40. Show. Although the bypass control unit 24 has a bypass management table corresponding to the renaming register unit 38 corresponding to the fixed-point register unit 42, the illustration is omitted.

  In the arithmetic processing unit OPD2 shown in FIG. 2, when the double-byte single-precision floating-point data of 8 bytes is read from the data cache 22 by 4 bytes, the address generator 20 accesses to read out the upper 4 bytes and the lower 4 bytes. Request MREQC is generated sequentially. Thus, based on the fact that the lower 4 bytes of data are output from the data cache 22, it can be determined that all double-byte single-precision floating point data of 8 bytes has been read from the data cache 22. Therefore, the flag area FLG indicating that bypass is possible can be set based on the control signal ALDL indicating reading of the lower 4 bytes of data. As a result, even when 4-byte data is read out twice at different timings, the bypass operation can be permitted by the 1-bit flag area FLG, and an increase in the circuit scale of the bypass management table BPTBL is suppressed. can do.

  The table control circuit TSCNT includes set signal generation units ASSET, MSSET, B1SET, a reset signal generation unit WRST, and a table control unit TBLCNT.

  The set signal generation unit ASSET has a decoder ADEC that receives an address ALDUBA, and 32 AND circuits that are connected to the output of the decoder ADEC and receive a control signal ALDSET. The decoder ADEC decodes the value of the address ALDUBA, and sets any of the 32 output terminals corresponding to the flag area FLG indicated by the value of the address ALDUBA to an effective level. The corresponding flag area FLG is set by the high level output from the AND circuit that receives the effective level from the decoder ADEC and the control signal ALDSET. The set signal generation unit ASSET sets the flag area FLG when loading double precision floating point data or double width single precision floating point data (both are 8 bytes).

  The set signal generation unit MSSET has a decoder MDEC instead of the decoder ADEC, and is the same as the set signal generation unit ASSET except that it receives the address MLDUBA and the control signal MLDSET instead of the address ALDUBA and the control signal ALDSET. The set signal generation unit MSSET sets the corresponding flag area FLG according to the high level output from the AND circuit that receives the effective level from the decoder MDEC and the control signal MLDSET. The set signal generation unit MSSET sets the flag area FLG when loading double-width single-precision floating-point data at a timing different from each other by 4 bytes.

  The set signal generation unit B1SET is similar to the set signal generation unit ASSET except that it has a decoder BDEC instead of the decoder ADEC and receives the address B1FPUBA and the control signal B1FP instead of the address ALDUBA and the control signal ALDSET. The set signal generation unit B1SET sets the corresponding flag area FLG according to the high level output from the AND circuit that receives the effective level from the decoder BDEC and the control signal B1FP. The set signal generation unit B1SET sets the flag area FLG indicated by the address B1FPUBA in response to a control signal B1FP that holds a signal indicating the start of an operation based on a floating-point data operation instruction until a B1 cycle described later.

  The reset signal generation unit WRST includes a decoder WDEC that receives the address WCMTUBA, 32 NAND circuits that are connected to the output of the decoder WDEC and receive the control signal WCMT, and 32 AND circuits that are connected to the output of the NAND circuit. Have. Similarly to the decoder ADEC, the decoder WDEC decodes the value of the address WCMTUBA and sets any one of the 32 output terminals corresponding to the flag area FLG indicated by the value of the address WCMTUBA to an effective level. The NAND circuit that receives the effective level from the decoder WDEC and the control signal WCMT outputs a low level, and sets the output of an AND circuit connected to the output of the NAND circuit to a low level. As a result, the corresponding flag area FLG is reset.

  The output period of the control signals ALDSET, MLDSET, and B1FP is one clock cycle. Therefore, each set signal generation unit ASSET, MSSET, B1SET outputs a low level from the AND circuit except for the clock cycle that receives the control signals ALDSET, MLDSET, B1FP. On the other hand, the AND circuit connected to the output of the NAND circuit in the reset signal generation unit WRST receives the high level bypass enable signal BPEN and outputs the high level until the NAND circuit outputs the low level. Thus, the set state of the flag area FLG set by the set signal generation units ASSET, MSSET, and B1SET is maintained until the NAND circuit outputs a low level.

  The table control unit TBLCNT calculates OR logic of the outputs of the set signal generation unit ASSET, MSSET, B1SET and the reset signal generation unit WRST, and outputs a plurality of OR circuits that output the calculated logic to the input terminal of the bypass table BPTBL. Have.

  Based on the circuits shown in FIGS. 7 and 8, the bypass control unit 24 sets the flag of the bypass management table BPTBL indicated by the logic of the control signal ALDBUA at the timing according to the logic of the control signals ALDL and ALDH from the address generation unit 20. Region FLG (FIG. 8) is set. The bypass control unit 24 sets the flag area FLG of the bypass management table BPTBL indicated by the logic of the address B1FPUBA at the timing of the control signal B1FP from the reservation station 18.

  The bypass control unit 24 sets the bypassable signal BPEN (any one of BPEN0 to BPEN31) corresponding to the set flag area FLG to an effective level. The bypass control unit 24 resets the flag area FLG of the bypass management table BPTBL indicated by the logic of the address WCMTUBA at the timing of the control signal WCMT from the commit control unit 44. The bypass control unit 24 sets the bypassable signal BPEN (any one of BPEN0 to BPEN31) corresponding to the reset flag area FLG to an invalid level. The table control unit TBLCNT and the bypass management table BPTBL are an example of an output circuit that outputs a bypass enable signal BPEN based on the set signal ALDSET or the set signal MLDSET.

  If the bypass control unit 24 does not receive the completion signal CE from the data cache 22 after setting the flag area FLG of the bypass management table BPTBL, it resets the set flag area FLG. At the time of a cache miss by the data cache 22, data from the data cache 22 is not transferred to the load register 30 and the renaming register unit 36 in a desired cycle. In this case, since the load register 30 and the renaming register unit 36 do not hold the data to be bypassed to the floating point arithmetic unit 26, the flag area FLG is reset to prohibit the bypass. The logic for resetting the flag area FLG based on the completion signal CE is provided in the reset signal generation unit WRST, for example. For example, the reset signal generation unit WRST has an OR circuit that supplies an OR logic of an address indicating the flag area FLG to be reset and the address WCMTUBA corresponding to the completion signal CE to the decoder WDEC. Further, the reset signal generation unit WRST has an OR circuit that supplies an OR logic of the control signal WCMT and the completion signal CE to each NAND circuit.

  FIG. 9 shows an example of the operation of the bypass control unit 24 shown in FIGS. The address generator 20 shown in FIG. 2 reads the control signals ALDL and ALDH when reading 8-byte double-precision floating-point data or 8-byte double-width single-precision floating-point data from the data cache 22 with one access request MREQC. Generate at the same time. The address generation unit 20 sequentially generates control signals ALDH and ALDL when the double-width single-precision floating point data is read from the data cache 22 4 bytes at a time by two access requests MREQC. In this case, among the 8-byte double-width single-precision floating point data, the upper 4 bytes are read from the data cache 22 and then the lower 4 bytes are read from the data cache 22.

  For example, in the operation OP10, the bypass control unit 24 determines whether or not the control signal ALDL is generated. When the control signal ALDL is not generated, 8-byte double-precision floating point data or 8-byte double-width single-precision floating point data is not read from the data cache 22. When the control signal ALDL corresponding to the lower 4 bytes of the renaming register RNFR is not generated in the operation OP12, the bypass control unit 24 does not update the bypass table BPTBL.

  When the control signal ALDL is generated, 8-byte double-precision floating point data or 8-byte double-width single-precision floating point data is read from the data cache 22 at a time. The bypass control unit 24 determines whether or not the control signal ALDH is generated together with the control signal ALDL in the operation OP14.

  When the control signal ALDH is generated together with the control signal ALDL, 8-byte double-precision floating point data or 8-byte double-width single-precision floating point data is read from the data cache 22 with one access request MREQC. That is, there is no difference in timing when the upper 4 bytes and lower 4 bytes of the 8-byte data are loaded from the data cache 22. In this case, the bypass control unit 24 sets the flag area FLG of the bypass table BPTBL indicated by the address MALDUBA received together with the control signals ALDL and ALDH in the operation OP16.

  When the control signal ALDH is not generated together with the control signal ALDL, the 8-byte double-width single-precision floating point data is read from the data cache 22 in two steps. That is, a timing difference occurs when the upper 4 bytes and the lower 4 bytes of 8-byte data are loaded from the data cache 22. In this case, in the operation OP18, the bypass control unit 24 generates the set signal MLDSET and the address MLDUBA two clock cycles after receiving the control signal ALDL. Thereafter, in operation OP16, the bypass control unit 24 sets the flag area FLG of the bypass table BPTBL indicated by the address MLDUBA in synchronization with the set signal MLDSET. By setting the flag area FLG in synchronization with the set signal MLDSET, double-width single precision floating point data read from the data cache 22 in two steps is bypassed via the renaming register RNFR as shown in FIG. It becomes possible. As described with reference to FIG. 12, reading of data from the renaming register RNFR takes two clock cycles. Therefore, the bypass control unit 24 delays the start of the calculation using the data bypassed from the renaming register RNFR by generating the set signal MLDSET after two clock cycles from the control signal ALDL.

  FIG. 10 shows an example of the operation of the arithmetic processing unit OPD2 shown in FIG. In FIG. 10, a plurality of floating point data arithmetic instructions A, B, C, and D are executed after execution of the preceding floating point data load instruction. The load instruction in FIG. 10 shows an example in which double precision floating point data or double width single precision floating point data is read from one cache line of the data cache 22. Further, the arithmetic instructions A, B, C, and D are executed using data bypassed from the load register 30 or the renaming register RNFR before the data loaded by the load instruction is stored in the floating point register FR. The

In FIG. 10, the D, DT, P, PT, B1, B2, A, T, M, B, R, and RT cycles of the load instruction are the pipeline stages at the time of execution of the load instruction as shown below. Show.
(A) D (Decode): The decoder unit 14 decodes the instruction, and transfers the decoded instruction information INS to the memory access instruction reservation station RSMA.
(B) DT (Decode Transfer): The reservation station RSMA holds the instruction information INS output in the D cycle.
(C) P (Priority): The reservation station RSMA determines an instruction to be output to the address generation unit 20.
(D) PT (Priority Transfer): The reservation station RSMA outputs an instruction determined in the P cycle to the address generation unit 20.
(E) B1, B2 (Buffer): The address generation unit 20 determines data (source register) for generating an address for accessing the data cache 22 and the like.
(F) A (Address): The address generation unit 20 calculates an address for accessing the data cache 22 and the like.
(G) T (Tag): The data cache 22 accesses the tag area.
(H) M (Match): The address read by the data cache 22 from the tag area is compared with the address received from the address generation unit 20 to determine a cache hit or a cache miss.
(I) B (Buffer): Buffers data read in the data cache 22.
(J) R (Result): The access to the data cache 22 is completed, and the read data is transferred to the load register 30.
(K) RT (Result): The data transferred to the load register 30 in the R cycle is transferred to the renaming register unit 36.

In FIG. 10, cycles D, DT, P, PT, B1, B2, X1, X2, X3, and X4 of the operation instruction indicate pipeline stages when the operation instruction is executed, as shown below.
(L) D (Decode): The decoder unit 14 decodes the instruction, and transfers the decoded instruction information INS to the reservation station RSFLT for calculation of floating point data.
(M) DT (Decode Transfer): The reservation station RSFLT holds the instruction information INS output in the D cycle.
(N) P (Priority): The reservation station RSFLT determines an instruction to be input to the floating point arithmetic unit 26.
(O) PT (Priority Transfer): The reservation station RSFLT inputs the instruction determined in the P cycle to the floating point arithmetic unit 26.
(P) B1, B2 (Buffer): The floating point arithmetic unit 26 determines data (source register) necessary for the operation.
(Q) X1, X2, X3, X4 (Execute 1-4): The floating point arithmetic unit 26 executes the instruction. The calculation of floating point data is executed in four cycles of X1-X4. In the next cycle of the X4 cycle, the data obtained by the operation is stored in the renaming register unit 36.

  The load instruction in FIG. 10 indicates an operation at the time of a cache hit. At the time of a cache miss, the D, DT, P, PT, B1, B2, A, T, and M cycles are executed in the clock cycle before the first clock cycle. Then, the address generation unit 20 and the data cache 22 re-execute the A, T, and M cycles from the seventh clock cycle, and re-execute the B, R, and RT cycles following the M cycle when a cache hit occurs. In other words, the D, DT, P, PT, B1, and B2 cycles are deleted from FIG.

  2 is not limited to the order of instructions decoded by the decoder unit 14, but performs out-of-order execution of executing executable instructions. For this reason, in the arithmetic instructions A, B, C, and D, the number of clock cycles from the execution of the DT cycle to the execution of the P cycle varies depending on the execution order determination result by the reservation station RSFLT. For example, the D and DT cycles of the operation instruction A are executed in a clock cycle before the first clock cycle.

  In the load instruction, the address generation unit 20 determines that the data can be read in one access to the data cache in the A cycle, and issues an access request MREQC shown in FIG. The address generator 20 outputs the control signals ALDL and ALDH and the address ALDUBA to the bypass controller 24 together with the access request MREQC (FIG. 10A).

  The bypass control unit 24 generates the set signal ALDSET in response to the control signals ALDL and ALDH, and sets the bypassable signal BPEN to an effective level by setting the flag area FLG indicated by the address ALDUBA (FIG. 10B). ).

  The data cache 22 completes the read cycle in the R cycle of the load instruction, and transfers the read 8-byte data to the load register 30 (FIG. 10C). The data transferred to the load register 30 is transferred to the renaming register unit 36 in the RT cycle. The write control unit WCNT3 (FIG. 4) of the renaming register unit 36 generates the write control signals WE1H and WE1L at a common timing based on the 8-byte data transferred from the load register 30 (FIG. 10 (d)). ). Then, the write control unit WCNT3 stores 8-byte data in any of the renaming registers RNFR (FIG. 10 (e)). For example, the write control unit WCNT3 determines a renaming register RNFR that stores data based on information indicating the bypassable signal BPEN set to an effective level received from the reservation station 18. For example, since reading of data from the renaming register RNFR takes two clock cycles, bypassing of data from the renaming register RNFR is possible from the 14th clock cycle.

  The reservation station RSFLT determines that the bypass is possible in the eighth clock cycle after the reservation station RSMA determines the source register in the B1 and B2 cycles. Then, the reservation station RSFLT executes the P cycle of the arithmetic instruction A in the ninth clock cycle, and inputs the arithmetic instruction A to the floating point arithmetic unit 26 (FIG. 10 (f)).

  The floating point arithmetic unit 26 selects data to be bypassed from the load register 30 in the B2 cycle of the operation instruction A, and uses the selected data in the X1 cycle (FIG. 10 (g)). In FIG. 10, an arrow indicated by a thick broken line indicates that data is bypassed from the load register 30 or the renaming register RNFR to the floating point arithmetic unit 26. The floating point arithmetic unit 26 selects data to be bypassed from the load register 30 in the B1 cycle of the operation instruction B, and uses the selected data in the X1 cycle (FIG. 10 (h)).

  The floating point arithmetic unit 26 selects data to be bypassed from the renaming register RNFR in the B2 cycle of the operation instruction C, and uses the selected data in the X1 cycle (FIG. 10 (i)). The floating point arithmetic unit 26 selects data to be bypassed from the renaming register RNFR in the B2 cycle of the operation instruction D, and uses the selected data in the X1 cycle (FIG. 10 (j)).

  FIG. 11 shows another example of the operation of the arithmetic processing unit OPD2 shown in FIG. Detailed description of the same or similar operations as in FIG. 10 will be omitted. In FIG. 11, a plurality of floating-point data arithmetic instructions A, B, C, and D are executed after execution of the preceding floating-point data arithmetic instruction. In the operation instruction preceding in FIG. 11, double precision floating point data, double width single precision floating point data or single precision floating point data is used. The arithmetic instructions A, B, C, and D use data bypassed from the result register 32 or the renaming register RNFR before the data obtained by the preceding arithmetic instruction is stored in the floating point register FR. Executed.

  The reservation station RSFLT determines that the data used in the operation instructions A, B, C, and D can be bypassed from the result register 32 or the renaming register RNFR in the B1 cycle of the preceding operation instruction. The reservation station RSFLT outputs a control signal B1FP and an address B1FPUBA (FIG. 11 (a)).

  Bypass control unit 24 sets flag area FLG indicated by address B1FPUBA in response to control signal B1FP, thereby setting bypass enable signal BPEN to an effective level (FIG. 11 (b)).

  The floating point arithmetic unit 26 executes the preceding arithmetic instruction in the X1 to X4 cycles, and transfers the arithmetic result to the result register 32 in the X4 cycle (FIG. 11 (c)). The data transferred to the result register 32 is transferred to the renaming register RNFR in the next clock cycle (FIG. 11 (d)).

  The reservation station RSFLT executes the P cycle of the arithmetic instruction A in the seventh clock cycle, and inputs the arithmetic instruction A to the floating point arithmetic unit 26 (FIG. 11 (e)). The floating point arithmetic unit 26 selects data to be bypassed from the result register 32 in the X1 cycle of the operation instruction A, and starts the operation from the X1 cycle using the selected data (FIG. 11 (f)). The floating point arithmetic unit 26 selects data to be bypassed from the result register 32 in the B2 cycle of the operation instruction B, and uses the selected data in the X1 cycle (FIG. 11 (g)). The floating point arithmetic unit 26 selects data to be bypassed from the result register 32 in the B1 cycle of the operation instruction C, and uses the selected data in the X1 cycle (FIG. 11 (h)). The floating point arithmetic unit 26 selects data to be bypassed from the renaming register RNFR in the B2 cycle of the operation instruction D, and uses the selected data in the X1 cycle (FIG. 11 (i)). As described with reference to FIG. 10, since reading of data from the renaming register RNFR takes two clock cycles, the bypass of data from the renaming register RNFR can be performed from the thirteenth clock cycle.

  FIG. 12 shows still another example of the operation of the arithmetic processing unit OPD2 shown in FIG. Detailed description of the same or similar operations as in FIG. 10 will be omitted. In FIG. 12, 8-byte data is held across two cache lines of the data cache 22 in the preceding double-width single-precision floating-point data load instruction. The operation instructions A, B, C, and D are instructions for performing an operation on double-width single-precision floating-point data, and are read before the data obtained by the preceding load instruction is stored in the floating-point register FR. This is performed using data to be bypassed from the naming register RNFR.

  When double-width single-precision floating point data read by a load instruction is read from two cache lines, A, T, M, B, R, and RT cycles are executed twice at intervals (FIG. 12A). (B)). The address generator 20 shown in FIG. 2 reads the upper 4 bytes of the double-width single precision floating point data in the first read cycle, and reads the lower 4 bytes of the double width single precision floating point data in the second read cycle. .

  The address generation unit 20 outputs the control signal ALDH and the address ALDUBA to the bypass control unit 24 in the first A cycle for reading the upper 4 bytes of data from the data cache 22 (FIG. 12 (c)). In the first clock cycle, the set signal generation circuit SSGEN (FIG. 7) of the bypass control unit 24 receives the invalid level control signal ALDL and the valid level control signal ALDH, and maintains the set signal ASDSET at the invalid level ( FIG. 12 (d)). Therefore, in the bypass management table BPTBL, the flag area FLG indicated by the address ALDUBA is not set, and the bypass enable signal BPEN is not output (FIG. 12 (e)).

  The set signal generation circuit SSGEN delays the address ALDUBA by two clock cycles and outputs the address MLDUBA (FIG. 12 (f)). However, since the set signal MLDSET is maintained at the invalid level, the flag area FLG indicated by the address ALDUBA is not set, and the bypass enable signal BPEN is not output (FIG. 12 (g)).

  The data cache 22 transfers the upper 4 bytes of data read in the R cycle of the first access cycle to the load register 30 (FIG. 12 (h)). The write control unit WCNT3 (FIG. 4) of the renaming register unit 36 generates the write control signal WE1H based on the upper 4 bytes of data transferred from the load register 30 (FIG. 12 (i)). Then, the write control unit WCNT3 stores the upper 4 bytes of data in any of the renaming registers RNFR ((j) in FIG. 12). For example, the write control unit WCNT3 determines a renaming register RNFR that stores data based on information indicating the bypassable signal BPEN set to an effective level received from the reservation station 18.

  The address generation unit 20 outputs the control signal ALDL and the address ALDUBA to the bypass control unit 24 in the first A cycle for reading the lower 4 bytes of data from the data cache 22 (FIG. 12 (k)). In the ninth clock cycle, the set signal generation circuit SSGEN of the bypass control unit 24 receives the control signal ALDL at the valid level and the control signal ALDH at the invalid level, and maintains the set signal ASDSET at the invalid level (FIG. 12 (l )). Therefore, in the bypass management table BPTBL, the flag area FLG indicated by the address ALDUBA is not set, and the bypass enable signal BPEN is not output (FIG. 12 (m)).

  On the other hand, the cycle signal generation unit MSGEN in the set signal generation circuit SSGEN (FIG. 7) receives an effective level control signal ALDL, an invalid level control signal ALDH, and a signal delayed by two clock cycles in the eleventh clock cycle. Then, the cycle signal generation unit MSGEN sets the set signal MLDSET to an effective level (FIG. 12 (n)). The set signal generation circuit SSGEN outputs the address MLDUBA obtained by delaying the address ALDUBA by two clock cycles (FIG. 12 (o)). As a result, the flag area FLG indicated by the address ALDUBA is set in the bypass management table BPTBL, and the bypass enable signal BPEN is output (FIG. 12 (p)).

  The data cache 22 transfers the lower 4 bytes of data read in the R cycle of the second access cycle to the load register 30 ((q) in FIG. 12). The write control unit WCNT3 (FIG. 4) of the renaming register unit 36 generates the write control signal WE1L based on the lower 4 bytes of data transferred from the load register 30 (FIG. 12 (r)). Then, the write control unit WCNT3 stores the lower 4 bytes of data in any of the renaming registers RNFR (FIG. 12 (s)). For example, the write control unit WCNT3 determines a renaming register RNFR that stores data based on information indicating the bypassable signal BPEN set to an effective level received from the reservation station 18.

  As a result, double-byte single-precision floating point data of 8 bytes is aligned in the renaming register RNFR, and the double-width single-precision floating point data from the renaming register RNFR can be bypassed. When 8-byte double-width single-precision floating-point data is read from two cache lines, the load register 30 holds upper 4 bytes data or lower 4 bytes data at different timings. For this reason, the load register 30 is not used for bypassing double-width single precision floating point data. In other words, the bypass control unit 24 delays the output cycle of the bypass enable signal BPEN as compared with FIGS. 10 and 11 and prohibits the bypass of data from the load register 30 to the floating point calculator 26. By prohibiting bypass from the load register 30 where data is not available, malfunction of the arithmetic processing unit OPD2 can be suppressed.

  In each of the arithmetic instructions A, B, C, and D, the floating point arithmetic unit 26 selects data to be bypassed from the renaming register RNFR in the B2 cycle, and uses the selected data in the X1 cycle (FIG. 12 (t ), (U), (v), (w)).

  As shown in FIG. 12, when double-width single-precision floating point data is read from two cache lines, the bypass control unit 24 waits for reading of lower 4 bytes of data read after the upper 4 bytes of data. Further, the bypass control unit 24 sets the flag area FLG and outputs the bypass enable signal BPEN after two clock cycles from the generation of the control signal ALDL corresponding to the start of reading of the lower 4 bytes of data.

  Thereby, the reservation station RSFLT receives the enable signal BPEN two clock cycles later than in FIG. Data transfer from the data cache 22 to the load register 30 is executed in the same cycle as the P cycle of the operation instruction A. Therefore, in the P cycle of the operation instruction A, the reservation station RSFLT gives up bypassing the data from the load register 30 and decides to bypass the data from the renaming register RNFR. As a result, it is possible to prevent the data from being bypassed from the load register 30 before the double-width single-precision floating point data is arranged in the renaming register RNFR. In other words, the reservation station RSFLT assigns the P cycle of the operation instruction A to the earliest clock cycle that can bypass data from the renaming register RNFR. For example, since reading of data from the renaming register RNFR takes 2 clock cycles, the P cycle of the operation instruction A is set to the 13th clock cycle.

  FIG. 13 shows still another example of the operation of the arithmetic processing unit OPD2 shown in FIG. Detailed description of the same or similar operations as in FIG. 10 will be omitted. FIG. 13 shows the operation at the completion of the execution of the preceding floating point data load instruction or the preceding floating point data arithmetic instruction.

In FIG. 13, C and W cycles of the seventh and eighth clock cycles indicate pipeline stages by the commit control unit 44 when the execution of the instruction is completed, as will be described below.
(A) C (Commit): The commit control unit 44 determines whether or not the execution of the instruction is completed.
(B) W (Write): The commit control unit 44 updates the renaming registers RNFR and RNR, the floating-point register FR, the fixed-point register R, and the like used in the instruction that has been executed. In addition, the commit control unit 44 releases resources used in the instructions in the register management table 16, the reservation station 18, the bypass control unit 24, and the like.

  For example, the RT cycle of the preceding load instruction or the X4 cycle of the preceding arithmetic instruction is completed in the third clock cycle. Since the commit control unit 44 executes instruction completion processing in the order in which the decoder unit 14 decodes the instructions (program description order), the C cycle is executed after completion of the previously decoded instruction. . In this example, the C cycle is executed after 4 clock cycles of the X4 cycle or the RT cycle. Note that the C cycle is executed in the shortest clock cycle after the RT cycle or the X4 cycle.

  The commit control unit 44 outputs the control signal WCMT and the address WCMTUBA to the bypass control unit 24 in the W cycle (FIG. 13A). The address WCMTUBA indicates the renaming register RNFR used in the load instruction or the operation instruction.

  In the W cycle, the commit control unit 44 outputs the reset signal RST1 to the register management table 16, and outputs the reset signal RST2 to the reservation station 18 (FIG. 13 (b)). Further, the commit control unit 44 outputs a read request RCMT1 to the renaming register unit 36 in the W cycle (FIG. 13C). The commit control unit 44 outputs the write request WCMT1 to the floating point register unit 40 two clock cycles after the read request RCMT1 (FIG. 13 (d)). As described with reference to FIG. 10, two clock cycles are the time taken for reading from the renaming register RNFR.

  In FIG. 13, the reset signals RST1 and RST2 are shown as a single signal, but each of the reset signals RST1 and RST2 is a multi-bit signal. For example, the reset signals RST1 and RST2 include the same information as the address WCMTUBA. Similarly, each of the read request RCMT1 and the write request WCMT1 is indicated by a single signal, but each of the read request RCMT1 and the write request WCMT1 is a multi-bit signal. For example, the read request RCMT1 and the write request WCMT1 include information indicating the numbers of the renaming register RNFR and the floating point register FR.

  The bypass control unit 24 sets the bypassable signal BPEN to an invalid level by resetting the flag area FLG indicated by the address WCMTUBA in response to the control signal WCMT (FIG. 13 (e)).

  Based on the reset signal RST1, the register management table 16 resets the bit value P in the area corresponding to the renaming register RNFR indicated by the reset signal RST1 (FIG. 13 (f)). The reservation station 18 resets the bit value P held corresponding to the renaming register RNFR instructed by the reset signal RST2 based on the reset signal RST2.

  Based on the read request RCMT1, the renaming register unit 36 outputs data from the renaming register RNFR indicated by the read request RCMT1. Based on the write request WCMT1, the floating point register unit 40 stores the data output from the renaming register RNFR in the floating point register FR indicated by the write request WCMT1 (FIG. 13 (g)). That is, data is transferred from the renaming register RNFR to the floating point register FR.

  The reservation station RSFLT determines that data can be bypassed from the renaming register RNFR in the seventh clock cycle before the bit value P is reset. Then, the reservation station RSFLT executes the P cycle of the arithmetic instruction A in the eighth clock cycle, and inputs the arithmetic instruction A to the floating point arithmetic unit 26 (FIG. 13 (h)).

  Similarly, the reservation station RSFLT determines that data can be bypassed from the renaming register RNFR in the eighth clock cycle before the bit value P is reset. Then, the reservation station RSFLT executes the P cycle of the arithmetic instruction B in the ninth clock cycle, and inputs the arithmetic instruction B to the floating point arithmetic unit 26 (FIG. 13 (i)).

  The floating point arithmetic unit 26 selects data to be bypassed from the renaming register RNFR in the B2 cycle of the operation instruction A, and uses the selected data in the X1 cycle (FIG. 13 (j)). The floating point arithmetic unit 26 selects data to be bypassed from the renaming register RNFR in the B2 cycle of the operation instruction B, and uses the selected data in the X1 cycle (FIG. 13 (k)).

  On the other hand, the reservation station RSFLT determines that it is impossible to bypass data from the renaming register RNFR in the ninth clock cycle after the bit value P is reset. Then, the reservation station RSFLT executes the P cycle of the arithmetic instruction C in the tenth clock cycle, and inputs the arithmetic instruction C to the floating point arithmetic unit 26 (FIG. 13 (l)). The floating point arithmetic unit 26 reads data from the floating point register FR in the B2 cycle of the operation instruction C, and uses the read data in the X1 cycle (FIG. 13 (m)).

  As mentioned above, also in embodiment shown in FIGS. 2-13, the effect similar to embodiment shown in FIG. 1 can be acquired. That is, even when a timing shift occurs in data loaded from the data cache 22 to the renaming register RNFR, data can be waited using the existing renaming register RNFR. Further, the bypass control unit 24 can determine whether the data is read from the data cache 22 once or divided into a plurality of times by the simple circuit described with reference to FIG. As a result, an increase in the circuit scale of the arithmetic processing unit OPD2 can be suppressed, an increase in power consumption of the arithmetic processing device OPD2 can be suppressed, and the operating frequency of the arithmetic processing device OPD2 can be improved.

  For example, even when data is read from the data cache 22 in a plurality of times, as described with reference to FIG. 4, the circuit scale of the renaming register unit 36 can be made equivalent to the conventional one. In addition, since data read from the data cache 22 at different timings can be combined by the renaming register RNFR, a data combining circuit is not provided in the arithmetic processing unit OPD2.

  Further, when the data is read from the data cache 22 in a plurality of times, the bypass control unit 24 suppresses malfunction of the arithmetic processing unit OPD2 by prohibiting bypass from the load register 30 in which data is not prepared. Can do.

  On the other hand, for example, a flag area FLG that can store 2 bits is provided in the bypass management table BPTBL corresponding to the data of the upper 4 bytes and the lower 4 bytes, and it is determined that the data is ready when both 2 bits are set. Then, two 4-byte data may be combined. However, in this case, the size of the bypass management table BPTBL is increased, and a control circuit for setting each bit of the flag area FLG is added. Further, when the data of the upper 4 bytes and the lower 4 bytes are combined at the output of the data cache 22, the upper 4 bytes of data output first are held until the lower 4 bytes of data are output from the data cache 22. A buffer circuit is provided. For this reason, the circuit scale increases.

  The embodiment shown in FIGS. 2 to 13 is applied to bypass control when transferring fixed-point data output from the data cache 22 in a plurality of times to the fixed-point register R based on a load instruction. Also good.

  Further, the above-described embodiment may be applied to a SIMD (single instruction multiple data) type arithmetic processing apparatus. In this case, each floating point register FR shown in FIG. 3 has a plurality of areas for storing a plurality of data groups to be processed in parallel, and each renaming register RNFR shown in FIG. 4 has a plurality of data to be processed in parallel. It has a plurality of areas for storing groups. The floating point arithmetic unit 26 includes a plurality of arithmetic units that operate a plurality of data groups in parallel. When the data is read from the data cache 22 in three or more times based on the load instruction, the bypass control unit generates the bypassable signal BPEN based on the start signal (ALDL or the like) of the data to be read last. To do.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  DESCRIPTION OF SYMBOLS 1 ... Decoder part; 2 ... Execution control part; 3 ... Arithmetic execution part; 4 ... Memory control part; 5 ... Memory; 6 ... Bypass control part; 7 ... 1st register; 10 ... Instruction cache; 12 ... Instruction buffer; 14 ... Decoder unit; 16 ... Register management table; 18 ... Reservation station; 20 ... Address generation unit; 22 ... Data cache; 24 ... Bypass control unit; 28 ... Fixed point arithmetic unit; 30 ... Load register; 32, 34 ... Result register; 36, 38 ... Renaming register unit; 40 ... Floating point register unit; 42 ... Fixed point register unit; 44 ... Commit control unit; , ALDH ... control signal; ALDUBA ... address; ASGEN ... cycle signal generator; BPEN ... bypassable BPTBL ... Bypass management table; FLG ... Flag area; FR ... Floating point register; MREQ, MREQC ... Access request; MSGEN ... Cycle signal generator; OPD1, OPD2 ... Arithmetic processing unit; ... Table; RNFR, RNR ... Renaming register; RSFLT, RSFIX, RSMA ... Reservation station; SSGEN ... Set signal generation circuit; TSCNT ... Table

Claims (7)

A decoder unit for decoding instructions;
An execution control unit that holds instructions decoded by the decoder unit and sequentially outputs executable instructions;
An operation execution unit that executes an operation based on an operation instruction indicating execution of the operation received from the execution control unit;
A memory for storing data used in the calculation execution unit;
A plurality of first registers for holding data used for the calculation executed by the calculation execution unit;
A plurality of second registers assigned corresponding to the first register used for the operation and temporarily holding the data obtained by executing the operation instruction or the memory access instruction before transferring to the first register;
A register management unit that holds an allocation relationship between the first register and the second register and is referred to by the execution control unit;
A memory control unit that outputs an access request to the memory based on a memory access instruction for reading data from the memory received from the execution control unit;
When the memory control unit outputs a plurality of the access requests based on the memory access command and sequentially transfers the data read out from the memory in a plurality of times to the second register, it is read out last from the memory. And a bypass control unit that causes the execution control unit to output the arithmetic instruction at a timing to bypass the data from the second register to the arithmetic execution unit after the data to be transferred is transferred to the second register. Arithmetic processing unit. The memory control unit reads data including a plurality of data groups from the memory based on the memory access instruction, and bypasses a plurality of start signals indicating the start of reading of the plurality of data groups from the memory. Output to the control unit,
When the bypass control unit receives the start signal corresponding to the plurality of data groups at different timings, the bypass control unit allows the bypass control signal to permit bypassing of data from the second register to the arithmetic execution unit. When the start signal corresponding to all of the plurality of data groups is received at a common timing after the last start signal is received from the unit, the bypassable signal is received. Output based on
The execution control unit outputs the operation instruction to the operation execution unit at a timing enabling data bypass from the second register to the operation execution unit after receiving the bypass enable signal. The arithmetic processing apparatus according to claim 1. The bypass control unit
A first generation circuit that generates a first set signal based on reception of a plurality of the start signals at the common timing;
A second generation circuit for generating a second set signal after the predetermined cycle from reception of the last start signal;
The arithmetic processing apparatus according to claim 2, further comprising an output circuit that outputs the bypassable signal based on the first set signal or the second set signal. Each of the second registers has a plurality of storage areas for storing each of the plurality of data groups read from the memory in a plurality of times,
The arithmetic processing unit further includes:
When the plurality of data groups are read from the memory in a plurality of times, a plurality of write control signals for storing each of the plurality of data groups in the plurality of storage areas are sequentially generated for each data group, 4. The arithmetic processing device according to claim 2, further comprising: a write control unit configured to generate the plurality of write control signals at a common timing when the plurality of data groups are read from the memory at a time. . The memory has a data cache including a plurality of cache lines for storing data;
The memory control unit sequentially outputs the access request for each cache line when data read from the data cache based on the memory access instruction is held across the plurality of cache lines. The arithmetic processing apparatus according to claim 1, wherein: The arithmetic processing unit further includes:
A third register disposed between the memory and the second register and temporarily holding data read from the memory before being transferred to the second register;
The bypass control unit prohibits bypassing of data from the third register to the arithmetic execution unit when the memory control unit reads data from the memory in a plurality of times. The arithmetic processing device according to claim 5. A decoder unit that decodes an instruction, an execution control unit that holds instructions decoded by the decoder unit, and sequentially outputs executable instructions, and an operation based on an operation instruction that indicates execution of an operation received from the execution control unit A calculation execution unit that executes data, a memory that stores data used by the calculation execution unit, a plurality of first registers that hold data used for calculation performed by the calculation execution unit, and a first that is used for calculation A plurality of second registers that are allocated corresponding to the registers and temporarily hold before transferring the data obtained by executing the operation instruction or the memory access instruction to the first register; the first register; In a control method of an arithmetic processing unit having a register management unit that holds an allocation relationship with a second register and is referenced by the execution control unit,
The memory control unit included in the arithmetic processing unit outputs an access request to the memory based on a memory access instruction for reading data from the memory received from the execution control unit,
When the memory control unit outputs a plurality of the access requests based on the memory access instruction and sequentially transfers data read out from the memory in a plurality of times to the second register, the arithmetic processing unit has The bypass control unit outputs the arithmetic instruction to the execution control unit at a timing to bypass the data from the second register to the arithmetic execution unit after the data read last from the memory is transferred to the second register A control method for an arithmetic processing device, characterized in that:

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