JP2015198190A - Semiconductor device for protection using zener diode and thyristor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that, while there are cases where a p-type well region 22 is commonly used as a collector region of a pnp transistor constituting a thyristor, a base region of an npn transistor constituting the thyristor together with the pnp transistor, and an anode region of a Zener diode, an n-type region C3 formed in the p-type well region 22 can be used as a cathode region of a Zener diode, but, when a normal n-type region is formed, a device may be destroyed in the case of the breakdown of a Zener diode.SOLUTION: An n-type region C3 is formed deeply. A semiconductor device for protection has a structure where, when a concentration of n-type impurities is observed from a surface of a semiconductor substrate in a depth direction, local maximum values in the impurity concentration are observed at a shallow level near the surface of the substrate and at a deep level far from the surface of the substrate. Accordingly, a current concentration phenomenon is relieved, so that the device can be prevented from being destroyed.

Description

  The present specification discloses a semiconductor device that provides a protection circuit that prevents an overvoltage from being applied to an IC circuit or the like. In particular, a semiconductor device is disclosed that includes a Zener diode and a thyristor, and mounts a protection circuit that prevents the Zener diode from breakdown and the thyristor from igniting when an overvoltage occurs, and applying an overvoltage to an IC circuit or the like. . In this specification, a circuit that is protected from overvoltage by a protection circuit is called a protection target circuit.

  Patent Document 1 discloses a protection circuit that uses a Zener diode and a thyristor to protect a circuit to be protected from overvoltage. In the technique of Patent Document 1, when a surge voltage is applied to the power supply line of the circuit to be protected, the Zener diode breaks down and the thyristor is ignited. The protection circuit protects the circuit to be protected from overvoltage.

In the technique of Patent Document 1, a collector region of a pnp transistor constituting a thyristor and a base region of an npn transistor constituting a thyristor in combination with the pnp transistor are formed by a p-side well region, and the base region of the pnp transistor is The collector region of the npn transistor is formed by an n-side well region. A p ⁺ type region is formed in the p type well region, and an n ⁺ type region is formed at a position in contact with the p ⁺ type region and the n type well region. A zener diode is constituted by the p ⁺ type region and the n ⁺ type region.

US Pat. No. 7,538,997

In the technique of Patent Document 1, a p ⁺ type region in contact with the n ⁺ type region is formed in the p type well region. When the p ⁺ type region is formed in the p type well region, the breakdown voltage of the Zener diode formed by the p ⁺ type region and the n ⁺ type region can be lowered, and the power supply line voltage when the protection circuit becomes conductive is lowered. be able to.

However, in the technique of Patent Document 1, it is necessary to form a p ⁺ type region in the p type well region, which complicates the manufacturing process. If an n-type region is provided in the p-type well region and a zener diode can be formed by the p-type well region and the n-type region, the p ⁺ -type region is unnecessary, and the manufacturing process is simplified.

However, if the p ⁺ type region is not provided in the p type well region, but only the n type region is provided in the p type well region, the Zener diode formed by the p type well region and the n type region breaks down and a surge current is generated. When current flows, a current concentration phenomenon may occur and the semiconductor device may be destroyed. A simple protection circuit cannot be realized simply by omitting the p ⁺ -type region.

As a result of investigating the cause of the destruction of the semiconductor device when the Zener diode is formed by providing the n-type region in the p-type well region, the following has been found.
The n-type region provided in the p-type well region not only realizes a diode using a pn junction, but also serves as a contact region that ensures ohmic contact with the cathode electrode of the diode. For this purpose, at least the surface of the semiconductor substrate needs to be an n ⁺ type region. In the present specification, + means that the impurity concentration is in ohmic contact with the metal film formed on the surface of the semiconductor substrate. In order to form an n-type region having an impurity concentration in ohmic contact with the metal film on the surface of the semiconductor substrate, the n-type impurity is implanted shallowly from the surface of the semiconductor substrate and then diffused. The n-type region thus manufactured has a high impurity concentration on the surface and is in ohmic contact with the metal film. On the other hand, the n-type region thus manufactured is shallow.
If the n-type region is shallow, a current concentration phenomenon occurs near the surface of the semiconductor substrate when a surge current flows between the p-type well region and the n-type region due to breakdown of the Zener diode due to the surge voltage. It has been found that the breakdown occurs in the p-type well region located near the surface of the semiconductor substrate due to the phenomenon.
The technology disclosed in this specification was created based on the knowledge that if the occurrence of the current concentration phenomenon is suppressed, the semiconductor device can be prevented from being destroyed.

The semiconductor device disclosed in this specification incorporates a protection circuit that protects a protection target circuit such as an IC circuit that needs to be protected from overvoltage. The protection circuit includes a Zener diode and a thyristor. When an overvoltage occurs, the Zener diode breaks down and the thyristor is ignited.
The semiconductor device disclosed in this specification includes a p-side well region, and the p-side well region is coupled with a collector region of a pnp transistor constituting the thyristor and an npn constituting the thyristor together with the pnp transistor. The base region of the transistor is also used as the anode region of the Zener diode. That is, the p-side well region is used for the anode region of the Zener diode. This is different from the conventional technique in which a p ⁺ -type region is provided in the p-side well region in order to form a Zener diode.
The semiconductor device disclosed in this specification includes an n-type region that becomes a cathode region of a Zener diode. The n-type region is formed in a range facing the surface of the semiconductor substrate in the p-side well region (also serving as the anode region of the Zener diode). When the impurity concentration distribution in the n-type region that becomes the cathode region of the Zener diode is observed from the surface of the semiconductor substrate in the depth direction, the first maximum value is observed at a shallow level near the surface, and the maximum value is again reached at a deeper level. A value is observed. There should be at least two or more levels at which the maximum value of the impurity concentration is observed, and it does not exclude the presence of three or more levels.
When the maximum value of the impurity concentration is observed at a shallow level, the impurity concentration at the position facing the surface of the semiconductor substrate is also high, and the concentration can be in ohmic contact with the metal film. When the maximum value of the impurity concentration is observed even at a deep level, the phenomenon of surge current concentration near the surface is suppressed, and the semiconductor device can be prevented from being destroyed.

The n-type region serving as the cathode region of the Zener diode includes an implantation step of injecting n-type impurities into the p-type well region from the surface of the semiconductor substrate and a heating step of diffusing the n-type impurities implanted into the p-type well region. It can be manufactured after that.
At this time, if a heating process is performed after performing a plurality of implantation steps with different implantation energies, the maximum value of the impurity concentration is obtained when the impurity concentration distribution is observed in the depth direction from the surface of the semiconductor substrate. An n-type region observed at a depth level of 2 or more can be obtained.
However, the semiconductor device described in this specification does not necessarily require a plurality of implantation processes. By changing the implantation energy with time, it is possible to implant at a plurality of depths in a single implantation step. Alternatively, two or more kinds of impurities having different implantation energies can be implanted at a plurality of depths at the same time.

When the maximum value of the impurity concentration is observed at a depth level of 2 or more when the n-type region is observed in the depth direction, it can be said that the n-type region includes a shallow diffusion layer and a deep diffusion layer. . Since the shallow diffusion layer exists, the cathode region of the Zener diode and the cathode electrode can be in ohmic contact. Since the deep diffusion layer exists, when the Zener diode breaks down and a current flows, the current is not concentrated at a shallow level but is distributed to a deep level. As a result, the degree of current concentration in the p-type well region existing around the n-type region is relaxed, and damage can be prevented from occurring in the p-type well region. A practical protection circuit can be formed simply by omitting the p ⁺ type region and forming an n type region in the p type well region.

  The n-type region formed in the p-type well region may be a single continuous body when the semiconductor substrate is viewed in plan, or may be divided into a plurality of pieces. When the plurality of n-type regions divided into a plurality are distributed in a state of being separated from each other, current concentration is further suppressed.

According to the technique described in this specification, it is not necessary to provide a p ⁺ type region in the p type well region, and the manufacturing process is simplified. Further, the reliability of the semiconductor device is greatly improved by simply providing a deep n-type region in addition to the shallow n-type region.

The circuit diagram of the protection circuit of an Example is shown. A cross section of a semiconductor device of an example is shown. An enlarged cross section of an n-type region is shown. The n-type area | region divided | segmented into plurality is shown. The relationship between surge voltage and surge current is shown.

The features of the technology disclosed in this specification will be summarized below. The items described below have technical usefulness independently.
(First Feature) When viewed in plan, a cathode region of a Zener diode is formed by a set of a plurality of n-type regions divided into a plurality of regions.
(Second feature) The shape of each n-type region in plan view is either a triangle, a quadrangle, a pentagon or more polygon, or a circle.
(Third feature) The implantation process is repeated by switching the implantation energy of the n-type impurity.
(Fourth feature) The implantation step is performed while changing the implantation energy of the n-type impurity with time.
(Fifth feature) Two types of n-type impurities having different implantation energies are implanted simultaneously.

  FIG. 1 shows a protection circuit 6 for a protection target circuit (IC circuit in this embodiment) 4 that needs to be protected so that an excessive voltage is not applied when an excessive voltage is applied to the power line 2. Show. The protection circuit 6 is connected in parallel with the protection target circuit 4 between the power supply line 2 and the ground line 12. When an excessive voltage is applied to the power line 2, the protection circuit 6 operates to connect the power line 2 and the ground line 12, so that an excessive voltage is applied to the protection target circuit 4. To prevent.

The reference application number in FIG.
E1: Emitter region of a pnp transistor. E2: emitter region of npn transistor.
B1: Base region of the pnp transistor. B2: base region of npn transistor.
C1: Collector region of the pnp transistor. C2: collector region of the npn transistor.
A3: Zener diode anode region. C3: Zener diode cathode region.
2: Power line. 4: Protection target circuit such as an IC circuit. 6: Protection circuit. 8: Resistance. 10: Resistance. 12: Ground wire.
If the base region B1 of the pnp transistor and the collector region C2 of the npn transistor are formed by a common member, the collector region C1 of the pnp transistor, the base region B2 of the npn transistor, and the anode region A3 of the Zener diode are formed by a common member. The circuit of the protection circuit 6 can be realized.

FIG. 2 shows a cross-sectional structure of a semiconductor device that realizes the circuit of the protection circuit 6. The hatch is omitted for clarity of illustration. The p ⁺ type emitter region E1, the n type base region B1 (n type well region 20), and the p type collector region C1 (p type well region 22) constitute a pnp transistor. The n-type collector region C2 (n-type well region 20), the p-type base region B2 (p-type well region 22), and the n ⁺ -type emitter region E2 constitute an npn transistor. A thyristor is configured by the pnp transistor and the npn transistor. The p-type anode region A3 (p-type well region 22) and the n-type cathode region C3 constitute a Zener diode.

The n-type base region B1 of the pnp transistor and the n-type collector region C2 of the npn transistor are configured by a common portion (n-type well region 20). The p-type collector region C1 of the pnp transistor, the p-type base region B2 of the npn transistor, and the p-type anode region A3 of the Zener diode are configured by a common portion (p-type well region 22). Reference numeral 14 is an n ⁺ -type region in which the power supply line 2 and the n-type well region 20 are in ohmic contact, and reference numeral 16 is a p ⁺ -type region in which the ground line 12 and the p-type well region 22 are in ohmic contact. Reference numeral 18 denotes a LOCOS oxide film. The n-type well region 20 also serves as the resistor 8, and the p-type well region 22 also serves as the resistor 10. The circuit of the protection circuit 6 of FIG. 1 is obtained by the semiconductor device of FIG.

As shown in FIG. 2, the cathode region C3 of the Zener diode is formed in the p-type well region 22, and the p-type well region 22 itself becomes the anode region A3 of the Zener diode. No p ⁺ type region is formed to obtain the anode region. The structure of FIG. 2 is simple and easy to manufacture.
As shown in FIG. 2, the n-type region C3 that becomes the cathode region of the Zener diode is formed in the p-type well region 22 so as to face the surface of the semiconductor substrate. Further, it is formed deeper than the other high-concentration diffusion regions 14, E 1, E 2, and 16 formed in the range facing the surface of the semiconductor substrate.

The other high-concentration diffusion regions 14, E1, E2, and 16 are regions for obtaining ohmic contact with a metal film (not shown) formed on the surface of the semiconductor substrate and need to have a high impurity concentration on the surface. Therefore, the impurity is diffused after being implanted shallowly.
The n-type region C3 serving as the cathode region of the Zener diode is also a region for obtaining ohmic contact with a metal film (not shown) formed on the surface of the semiconductor substrate, and the impurity concentration on the surface needs to be high. For this purpose, it is necessary to diffuse impurities after they are implanted shallowly. However, if that is the case, when the Zener diode breaks down and a current flows, the current concentrates near the surface of the p-type well region 22 located around the n-type region C3 and damage occurs in the p-type well region 22. Sometimes.
Therefore, the n-type region C3 that becomes the cathode region of the Zener diode is manufactured through a process of implanting impurities shallowly and a process of implanting impurities deeply. Since the n-type region C3 is formed by diffusing from the shallow implantation level and the deep implantation level, the impurity concentration on the surface of the n-type region C3 is high (for that reason, ohmic contact with the cathode electrode) and reaches the deep part.

  According to the semiconductor device of FIG. 2, when a surge voltage is generated in the power supply line 2 and a surge current flows between the anode region A3 and the cathode region C3 of the Zener diode, the current is concentrated at a shallow level near the surface of the semiconductor substrate. Without flowing, it will flow to a deep level. Occurrence of the current concentration phenomenon is prevented, and damage to the semiconductor device is prevented.

  FIG. 3 shows an enlarged cross section of the n-type region C3. A cross indicates an impurity implantation level before diffusion. (1) shows the case where there is only one injection level. In this case, the n-type region C3 is too shallow and a current concentration phenomenon occurs. (2) shows a case where diffusion is performed after implantation at a shallow level and a deep level. The n-type region C3 reaches deep. This alleviates current concentration. (3) shows a case where the deep level implantation range is narrower than the shallow level implantation range. In this case, the radius of the curve constituting the contour of the n-type region C3 is increased, and current distribution is further promoted. Current concentration is well prevented.

In (2) and (3) of FIG. 3, the impurity concentration implanted at a shallow level is high, and the impurity concentration on the surface after the diffusion treatment is high. It is in ohmic contact with a cathode electrode (not shown) formed on the surface.
In (2) and (3) of FIG. 3, the impurity concentration implanted into the shallow level is the same as the impurity concentration implanted into the deep level. Alternatively, the impurity concentration implanted at a shallow level may be increased and the impurity concentration implanted at a deep level may be decreased. Alternatively, the impurity concentration implanted at a shallow level may be reduced and the impurity concentration implanted at a deep level may be increased under the condition that the concentration in ohmic contact with the cathode electrode is maintained.
When the impurity concentration of the n-type region diffused from (2) and (3) in FIG. 3 is observed in the depth direction from the surface of the semiconductor substrate, the impurity concentration becomes maximum at a shallow level near the surface, and the impurity concentration at a deeper level. The concentration becomes maximum again. If the level at which the impurity concentration becomes maximum is 2 or more, current concentration can be suppressed.

  FIG. 4 shows an embodiment in which the n-type region C3 serving as the cathode region of the Zener diode is divided into a plurality of parts. The shape of each region in plan view may be any of a polygon (the number of vertices is 3 or more), a circle, an oval, an ellipse, and the like. When the n-type region C3 that becomes the cathode region of the Zener diode is divided into a plurality of regions, current concentration is effectively suppressed.

FIG. 5 shows the relationship between voltage and current when a surge voltage is applied to the protection circuit 6.
The graph 40 shows the characteristics when the protection circuit 6 is composed of only thyristors and no zener diode is used. In this case, the protection circuit 6 does not operate until the surge voltage reaches VB1, and the protection target circuit 4 may not be completely protected.
The graph 42 shows the characteristics when the Zener diode is used, but the n-type region C3 that is the cathode region of the Zener diode is shallow (the same depth as the other high-concentration diffusion regions 14, E1, E2, and 16). By using the Zener diode, the voltage when the protection circuit 6 starts operating can be reduced to VB3. The voltage can be adjusted to a voltage necessary to protect the circuit 4 to be protected. When the n-type region C3 that is the cathode region of the Zener diode is shallow, current may concentrate and the semiconductor device may be destroyed. In addition, the hold voltage decreases to VH2. In order to increase the operating speed of the protection circuit 6, it is preferable that the hold voltage is high.
The graph 44 shows the case where the n-type region C3 which is the cathode region of the Zener diode is deep (deeper than the other high-concentration diffusion regions 14, E1, E2, 16 because it has been diffused after being injected to a level of 2 or more). Show the characteristics. By using the Zener diode, the voltage when the protection circuit 6 starts operating can be reduced to VB3. When the n-type region C3 serving as the cathode region of the Zener diode is deep, current concentration does not occur and the semiconductor device is not destroyed. The hold voltage is VH3. VH2 <VH3. When the n-type region C3 is deep, the operation speed of the protection circuit 6 can be increased.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

2: Power line 4: Protection target circuit (IC circuit)
6: protection circuit 8: resistor 10: resistor 12: ground line 14: n ⁺ region 16: p ⁺ region 18: LOCOS oxide film 20: n-type well region 22: p-type well region

Claims (3)

A collector region of a pnp transistor constituting the thyristor, a base region of the npn transistor constituting the thyristor, and a p-side well region also serving as an anode region of the Zener diode;
An n-type region serving as a cathode region of the Zener diode;
The n-type region is formed in the p-side well region, is formed in a range facing the surface of the semiconductor substrate, and the concentration of the n-type impurity at the position facing the surface of the semiconductor substrate is the metal film A semiconductor device characterized in that the concentration of n-type impurities is at least at a shallow level close to the surface of the semiconductor substrate and at a deeper level than the shallow level, the concentration being ohmic contact. The n-type region is manufactured through an implantation step of injecting an n-type impurity from the surface of the semiconductor substrate into the p-type well region and a heating step of diffusing the n-type impurity.
The apparatus according to claim 1, wherein a plurality of injection steps with different injection energies are performed.   The apparatus according to claim 1, wherein when the semiconductor substrate is viewed in plan, there are a plurality of the n-type regions separated from each other.

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