JP2015197898A - Device and method for controlling array type arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an array type arithmetic unit capable of switching a clock path following switching of a transfer path of a serial transfer bus inside an array type arithmetic unit, reducing a risk of developing hold timing contravention, and reducing a hold buffer insertion.SOLUTION: A data transfer control part determines a transfer path for transferring up-to-date structure information on the basis of the location of a constitutional information holding part that becomes an object to be updated when the data transfer control part is given one or more up-to-date constitutional information, and determines the arrangement of the up-to-date structure information at the transfer time. A clock path control part determines an inverse path for the transfer path of the up-to-date constitutional information determined by the data transfer control part, the constitutional information holding part of the object to be updated on the inverse path stores and updates the up-to-date constitutional information transferred in synchronizing with a clock, and the other constitutional information holding part except for the constitutional information holding part of the object to be updated is set so as to by-pass the clock. The clock control part supplies the number of clocks corresponding to a length of information showing the up-to-date constitutional information to the constitutional information holding part as the start edge on the inverse path.

Description

  The present invention relates to an apparatus and method for controlling an array type arithmetic unit.

  In recent years, a plurality of processor elements (hereinafter referred to as PEs) such as CPUs, DSPs, single arithmetic units, or arithmetic units are mounted on an LSI, and each PE is connected to each other via a data transfer bus. The device is drawing attention.

  The array type arithmetic unit has a feature that the processing contents of each PE and the data transfer path connecting the PEs can be changed by externally providing setting information called configuration information. Therefore, by switching the configuration information, it is possible to switch the function of the array type arithmetic unit according to the processing content, and application in a wide range of fields is expected.

  Conventionally, in order to reduce the number of signal wirings of a bus for transmitting configuration information of an array type arithmetic device, a bus (hereinafter referred to as a serial transfer bus) that transfers data in a daisy chain in synchronization with a clock for each bit is used. Sending configuration information.

  In general, the serial transfer bus has a merit that the bus wiring area can be reduced, but also has a demerit that a hold timing violation easily occurs. Conventionally, as a technique for alleviating hold timing violation in a scan path which is a kind of serial transfer bus, a technique of wiring a clock signal in the direction opposite to the connection path of the scan path has been devised (Patent Document 1).

JP-A-11-108999

  If a serial transfer bus is used as a transfer bus for configuration information of a large-scale array type arithmetic device, the transfer time of the configuration information is prolonged. For this reason, a transfer method capable of dynamically switching the path of the serial transfer bus has been used so that the configuration information can be transferred only to the PE that needs to change the configuration information.

  However, in the conventional hold timing violation mitigation technique, if the path of the serial transfer bus is dynamically switched, the clock signal cannot be wired in the opposite direction to the data transfer path of the serial transfer bus. For this reason, there has been a problem that a large number of hold buffers for eliminating hold violations are inserted and the circuit scale increases.

  The present invention has been made in view of such problems. Then, the present invention is capable of switching the clock path following the switching of the transfer path of the serial transfer bus, reducing the risk of occurrence of hold timing violation, and reducing the hold buffer insertion. I will provide a.

In order to solve this problem, for example, a control device for an array type arithmetic device of the present invention comprises the following arrangement. That is,
Configuration information for determining a plurality of arithmetic elements, processing contents of each arithmetic element and a data transfer path connecting the arithmetic elements can be stored, arranged in a matrix, and connected to each other via a serial transfer bus A control device for an array type arithmetic unit configured with a plurality of configuration information holding units,
When one or more new configuration information to be changed is given, a transfer path for transferring the new configuration information is determined and transferred based on the position of the configuration information holding unit to be updated with the new configuration information Data transfer control means for determining the arrangement of the new configuration information at the time,
New configuration information that is determined by the data transfer control means is determined in reverse to the transfer path of the new configuration information, and the configuration information holding unit to be updated on the reverse path is transferred in synchronization with the clock. And a clock path control means for setting the configuration information holding unit other than the configuration information holding unit to be updated to bypass the clock,
Clock control means for supplying a number of clocks corresponding to the length of information indicated by the new configuration information to a configuration information holding unit serving as a starting end on the reverse path.

  According to the present invention, the clock path can be switched following the switching of the transfer path of the serial transfer bus, and there is an effect of reducing the risk of holding timing violation and reducing the hold buffer insertion.

The block diagram which shows the characteristic structure of 1st Embodiment. The block diagram which shows the clock path | route switching structure of 1st Embodiment. FIG. 2 is a block diagram illustrating a clock control circuit configuration according to the first embodiment. The figure which shows the format of structure information. The figure which shows the setting value of the structure information of 1st Embodiment. 6 is a flowchart illustrating a flow of clock path switching processing according to the first embodiment. The block diagram which shows the clock path switching structure of 2nd Embodiment. The block diagram which shows the clock path switching structure of 2nd Embodiment. The figure which shows the setting value of the structure information of 2nd Embodiment.

  Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings. The configurations shown in the following embodiments are merely examples, and the present invention is not limited to the illustrated configurations.

[First Embodiment]
In this embodiment, when the configuration information setting path can be changed so that the configuration information setting time of the array type arithmetic unit ends in the shortest time, the clock is propagated in the opposite direction to the setting path following the change of the setting path. The clock configuration and the clock control method that can be performed will be described.

<System configuration diagram (FIG. 1)>
FIG. 1 is a block diagram showing a characteristic configuration of the present embodiment. The system configuration of the present embodiment will be described with reference to FIG.

  Reference numeral 100 in the figure denotes a data processing unit in the embodiment. The data processing unit 100 includes a plurality of calculation element units (PE) and a network circuit that connects the calculation element units, and changes the configuration information to change the processing contents of the calculation element unit and the calculation element unit. The connection form can be changed. In the present embodiment, the configuration information is stored in a configuration information holding unit described later. The configuration information holding unit can store the configuration information, is arranged in a matrix, and adjacent ones are connected by a serial transfer bus.

  Reference numerals 130, 131, 132, 133, 134, and 135 denote arithmetic element units (PE), which have arithmetic devices such as processors and ALUs and communication paths for exchanging data with other arithmetic element units. Further, the calculation element unit can change the calculation contents of the calculation element unit and the communication path between the calculation element units by changing the configuration information held in the configuration information holding unit described later.

  Reference numerals 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, and 121 are configuration information holding units that hold therein configuration information transmitted from a data transfer control unit described later. The configuration information holding unit has a serial transfer bus, and is connected to the adjacent configuration information holding unit by the serial transfer bus. The configuration information held in the configuration information holding unit has information for determining at least the calculation contents of the calculation element unit and the data exchange path between the calculation element units.

  Reference numerals 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, and 156 are serial transfer buses connecting the configuration information holding units.

  The serial transfer bus connecting the configuration information holding units is composed of a 1-bit data line and a 1-bit clock line. The data transfer direction and the clock transmission direction are fixed, and the transfer direction of all serial transfer buses will be described below.

  Reference numeral 160 denotes a serial transfer bus that connects the data transfer control unit 107 and the configuration information holding unit 110. Transfer data is output from the data transfer control unit 107 to the configuration information holding unit 110, and a clock is transmitted from the configuration information holding unit 110 to the data. The data is output to the transfer control unit 107.

  The serial transfer bus 140 connects the configuration information holding units 110 and 111, the transfer data is output from the configuration information holding unit 110 to the configuration information holding unit 111, and the clock is output from the configuration information holding unit 111 to the configuration information holding unit 110. The

  The serial transfer bus 141 connects the configuration information holding units 111 and 112, the transfer data is output from the configuration information holding unit 111 to the configuration information holding unit 112, and the clock is output from the configuration information holding unit 112 to the configuration information holding unit 111. The

  The serial transfer bus 142 connects the configuration information holding units 110 and 113, the transfer data is output from the configuration information holding unit 110 to the configuration information holding unit 113, and the clock is output from the configuration information holding unit 113 to the configuration information holding unit 110. The

  The serial transfer bus 143 connects the configuration information holding units 111 and 114, the transfer data is output from the configuration information holding unit 111 to the configuration information holding unit 114, and the clock is output from the configuration information holding unit 114 to the configuration information holding unit 111. The

  The serial transfer bus 144 connects the configuration information holding units 112 and 115, the transfer data is output from the configuration information holding unit 112 to the configuration information holding unit 115, and the clock is output from the configuration information holding unit 115 to the configuration information holding unit 112. The

  The serial transfer bus 145 connects the configuration information holding units 113 and 114, the transfer data is output from the configuration information holding unit 114 to the configuration information holding unit 113, and the clock is output from the configuration information holding unit 113 to the configuration information holding unit 114. The

  The serial transfer bus 146 connects the configuration information holding units 114 and 115, the transfer data is output from the configuration information holding unit 115 to the configuration information holding unit 114, and the clock is output from the configuration information holding unit 114 to the configuration information holding unit 115. The

  The serial transfer bus 147 connects the configuration information holding units 113 and 116, the transfer data is output from the configuration information holding unit 113 to the configuration information holding unit 116, and the clock is output from the configuration information holding unit 116 to the configuration information holding unit 113. The

  The serial transfer bus 148 connects the configuration information holding units 114 and 117, the transfer data is output from the configuration information holding unit 114 to the configuration information holding unit 117, and the clock is output from the configuration information holding unit 117 to the configuration information holding unit 114. The

  The serial transfer bus 149 connects the configuration information holding units 115 and 118, the transfer data is output from the configuration information holding unit 115 to the configuration information holding unit 118, and the clock is output from the configuration information holding unit 118 to the configuration information holding unit 115. The

  The serial transfer bus 150 connects the configuration information holding units 116 and 117, the transfer data is output from the configuration information holding unit 116 to the configuration information holding unit 117, and the clock is output from the configuration information holding unit 117 to the configuration information holding unit 116. The

  The serial transfer bus 151 connects the configuration information holding units 117 and 118, the transfer data is output from the configuration information holding unit 117 to the configuration information holding unit 118, and the clock is output from the configuration information holding unit 118 to the configuration information holding unit 117. The

  The serial transfer bus 152 connects the configuration information holding units 116 and 119, the transfer data is output from the configuration information holding unit 116 to the configuration information holding unit 119, and the clock is output from the configuration information holding unit 119 to the configuration information holding unit 116. The

  The serial transfer bus 153 connects the configuration information holding units 117 and 120, the transfer data is output from the configuration information holding unit 117 to the configuration information holding unit 120, and the clock is output from the configuration information holding unit 120 to the configuration information holding unit 117. The

  The serial transfer bus 154 connects the configuration information holding units 118 and 121, the transfer data is output from the configuration information holding unit 118 to the configuration information holding unit 121, and the clock is output from the configuration information holding unit 121 to the configuration information holding unit 118. The

  The serial transfer bus 155 connects the configuration information holding units 119 and 120, the transfer data is output from the configuration information holding unit 120 to the configuration information holding unit 119, and the clock is output from the configuration information holding unit 119 to the configuration information holding unit 120. The

  The serial transfer bus 156 is a serial transfer bus that connects the configuration information holding units 120 and 121. The transfer data is output from the configuration information holding unit 121 to the configuration information holding unit 120, and the clock is held from the configuration information holding unit 120. Is output to the unit 121.

  The serial transfer bus 180 is a serial data transfer clock, and the clock is output from the clock control unit 102 to the configuration information holding unit 119.

  Reference numeral 101 denotes a clock path control unit that outputs a clock control signal 170 of a clock used in the serial transfer bus included in the configuration information holding unit.

  Reference numeral 102 denotes a clock control unit, which generates a clock pulse used for serial data transfer and outputs the generated clock to the serial transfer bus 180 described above.

  Reference numeral 106 denotes a memory in which configuration information to be updated (new configuration information) is stored. Reference numeral 107 denotes a data transfer control unit, which reads out configuration information from the memory 106 described above, and generates serial data and a data transfer control signal 161.

  As described above, an arrow indicated by a solid line in each serial transfer bus indicates a data transfer direction on the bus, and a broken arrow indicates a clock transfer direction.

<Configuration of Configuration Information Holding Unit (FIG. 2)>
FIG. 2 is a block diagram showing the configuration of one configuration information holding unit in the present embodiment. Hereinafter, the configuration of the configuration information holding unit will be described with reference to FIG.

  Reference numeral 201 denotes a configuration information storage unit, which has a number of flip-flops necessary to store the configuration information of the arithmetic element unit, and each flip-flop is connected in a daisy chain. Reference numeral 210 denotes a clock buffer, which is arranged so that a clock delay occurs in the direction opposite to the data transfer direction of the flip-flop.

  Reference numerals 248, 250, 251, and 253 are data lines of a serial transfer bus connected to the configuration information holding unit.

  Reference numeral 2481 denotes a serial transfer bus clock line corresponding to the data line 248. Reference numeral 2501 denotes a serial transfer bus clock line corresponding to the data line 250. Reference numeral 2511 denotes a serial transfer bus clock line corresponding to the data line 251. Reference numeral 2531 denotes a serial transfer bus clock line corresponding to the data line 253.

  Reference numeral 202 denotes a multiplexer that selects data lines transmitted from the serial transfer bus 248 and the serial transfer bus 250, and selects the serial transfer bus according to the data transfer control signal 161 transmitted from the data transfer control unit.

  Reference numeral 204 denotes a multiplexer for bypassing the configuration information storage unit. When there is no need to rewrite the data in the configuration information storage unit, the multiplexer 204 responds to the data transfer control signal 161 transmitted from the data transfer control unit. Select the data to be output. The data output from the reference numeral 204 is transmitted to the data lines of the serial transfer buses 251 and 253. Reference numeral 206 denotes a multiplexer that selects clock lines output from the serial transfer buses 251 and 253, and performs clock selection according to the clock control signal 170 transmitted from the clock path control unit.

  Reference numeral 205 denotes a clock gating circuit, which performs gating of a clock used in the configuration information storage unit 201 in accordance with a clock control signal 170 transmitted from the clock control unit. Reference numeral 203 denotes a multiplexer for bypassing the clock. When there is no need to set data in the configuration information storage unit 201, the multiplexer 203 outputs the multiplexer 206 in response to the clock control signal 170 transmitted from the clock path control unit. Select the clock.

  The serial transfer bus connected to each configuration information holding unit differs depending on the position where the configuration information holding unit is arranged in FIG. The correspondence relationship between the serial transfer bus of the configuration information holding unit in FIG. 2 and the serial transfer bus in FIG. 1 will be described below.

  In the configuration information holding unit 110, the data line and the clock line of the serial transfer bus 160 in FIG. 1 are connected to the data line 250 and the clock line 2501. The data line 248 is fixed to the ground, and the clock line 2481 is open. Further, the data line and clock line of the serial transfer bus 140 in FIG. 1 are connected to the data line 251 and the clock line 2511, and the data line and clock line of the serial transfer bus 142 in FIG. 1 are connected to the data line 253 and the clock line 2531. Is connected.

  In the configuration information holding unit 111, the data line and the clock line of the serial transfer bus 140 in FIG. 1 are connected to the data line 250 and the clock line 2501. The data line 248 is fixed to the ground, and the clock line 2481 is open for output. Further, the data line and clock line of the serial transfer bus 141 in FIG. 1 are connected to the data line 251 and the clock line 2511, and the data line and clock line of the serial transfer bus 143 in FIG. 1 are connected to the data line 253 and the clock line 2531. Is connected.

  In the configuration information holding unit 112, the data line and the clock line of the serial transfer bus 141 in FIG. 1 are connected to the data line 250 and the clock line 2501. The data line 248 is fixed to the ground, and the clock line 2481 is open for output. The data line 251 is open for output, and the clock line 2511 is fixed to the ground. The data line 253 and the clock line 2531 are connected to the data line and clock line of the serial transfer bus 144 in FIG.

  In the configuration information holding unit 115, the data line 250 is fixed to the ground, and the clock line 2501 is open. A data line and a clock line of the serial transfer bus 144 in FIG. 1 are connected to the data line 248 and the clock line 2481. Further, the data line and clock line of the serial transfer bus 146 in FIG. 1 are connected to the data line 251 and the clock line 2511, and the data line and clock line of the serial transfer bus 149 in FIG. 1 are connected to the data line 253 and the clock line 2531. Is connected.

  In the configuration information holding unit 114, the data line and the clock line of the serial transfer bus 146 in FIG. 1 are connected to the data line 250 and the clock line 2501. A data line and a clock line of the serial transfer bus 143 in FIG. 1 are connected to the data line 248 and the clock line 2481. Further, the data line and clock line of the serial transfer bus 145 in FIG. 1 are connected to the data line 251 and the clock line 2511, and the data line and clock line of the serial transfer bus 148 in FIG. 1 are connected to the data line 253 and the clock line 2531. Is connected.

  In the configuration information holding unit 113, the data line and the clock line of the serial transfer bus 145 in FIG. 1 are connected to the data line 250 and the clock line 2501. A data line and a clock line of the serial transfer bus 142 in FIG. 1 are connected to the data line 248 and the clock line 2481. The data line 251 is open for output, and the clock line 2511 is fixed to the ground. A data line and a clock line of the serial transfer bus 147 in FIG. 1 are connected to the data line 253 and the clock line 2531.

  In the configuration information holding unit 116, the data line 250 is fixed to the ground, and the clock line 2501 is open. A data line and a clock line of the serial transfer bus 147 in FIG. 1 are connected to the data line 248 and the clock line 2481. Further, the data line and clock line of the serial transfer bus 150 in FIG. 1 are connected to the data line 251 and the clock line 2511, and the data line and clock line of the serial transfer bus 152 in FIG. 1 are connected to the data line 253 and clock line 2531. Is connected.

  In the configuration information holding unit 117, the data line and the clock line of the serial transfer bus 150 in FIG. 1 are connected to the data line 250 and the clock line 2501. A data line and a clock line of the serial transfer bus 148 in FIG. 1 are connected to the data line 248 and the clock line 2481. The data line and clock line of the serial transfer bus 151 in FIG. 1 are connected to the data line 251 and the clock line 2511, and the data line and clock line of the serial transfer bus 153 in FIG. 1 are connected to the data line 253 and the clock line 2531. Is connected.

  In the configuration information holding unit 118, the data line and the clock line of the serial transfer bus 151 in FIG. 1 are connected to the data line 250 and the clock line 2501. A data line and a clock line of the serial transfer bus 149 in FIG. 1 are connected to the data line 248 and the clock line 2481. The data line 251 is open for output, and the clock line 2511 is fixed to the ground. A data line and a clock line of the serial transfer bus 154 in FIG. 1 are connected to the data line 253 and the clock line 2531.

  In the configuration information holding unit 121, the data line 250 is fixed to the ground, and the clock line 2501 is open. A data line and a clock line of the serial transfer bus 154 in FIG. 1 are connected to the data line 248 and the clock line 2481. Further, the data line and the clock line of the serial transfer bus 156 in FIG. 1 are connected to the data line 251 and the clock line 2511, the output of the data line 253 is open, and the clock line 2531 is fixed to the ground.

  In the configuration information holding unit 120, the data line and the clock line of the serial transfer bus 156 in FIG. 1 are connected to the data line 250 and the clock line 2501. A data line and a clock line of the serial transfer bus 153 in FIG. 1 are connected to the data line 248 and the clock line 2481. Further, the data line and the clock line of the serial transfer bus 155 in FIG. 1 are connected to the data line 251 and the clock line 2511, the output of the data line 253 is open, and the clock line 2531 is fixed to the ground.

  In the configuration information holding unit 119, the data line and the clock line of the serial transfer bus 155 in FIG. 1 are connected to the data line 250 and the clock line 2501. A data line and a clock line of the serial transfer bus 152 in FIG. 1 are connected to the data line 248 and the clock line 2481. The data line 251 is open for output, and the serial transfer bus 180 shown in FIG. The data line 253 is open for output, and the clock line 2531 is fixed to the ground.

<Configuration of clock controller (FIG. 3)>
FIG. 3 is a block diagram showing the configuration of the clock control unit 102 in the present embodiment. The configuration of the clock control unit will be described with reference to FIG.

  Reference numeral 301 in the figure is a counter that counts the clock transmission period. When the clock generation start instruction signal 172 output from the clock path control unit 101 is asserted, the counter 301 receives and sets the bit length of the transfer data output from the data transfer control unit 107 in the counter. The counter 301 counts -1 in synchronization with the system clock, and stops counting when the counter value reaches zero.

  Reference numeral 302 denotes an OR circuit, which outputs a signal obtained by ORing all the bits of the counter. Reference numeral 303 denotes a latch circuit, which outputs a signal value output from the OR circuit 302 when the system clock changes to low. Reference numeral 304 denotes an AND circuit which outputs a signal obtained by ANDing the signal output from the latch 303 and the system clock to the serial data transfer clock 180.

  According to the above configuration, when the counter 301 is not zero, the signal output from the Latch 303 is High. Therefore, the serial data transfer clock output from the AND circuit 304 transmits the system clock for the number of cycles set in the counter 301. That is, the clock control unit 102 generates clocks by the number indicated by the set bit length of the transfer data.

<Example format of configuration information (FIG. 4)>
FIG. 4 is an example of a format of configuration information stored in the memory 106. Reference numeral 401 denotes an ID for specifying a calculation element part for which configuration information is set, and a unique value is assigned to each calculation element part. Reference numeral 402 denotes setting data indicating configuration information of the calculation element unit corresponding to the ID. In the present embodiment, description will be made assuming that the configuration information shown in FIG. 4 is given as the configuration information to be changed.

<Clock path change processing (FIGS. 5 and 6)>
The flow of processing for changing the clock path following the change of the path of the serial transfer bus will be described with reference to FIGS.

  FIG. 5 shows configuration information stored in the memory 106 in the present embodiment. The configuration information 501 indicates that the ID is “3” and the setting data is “0101010101”. The configuration information 502 is configuration information with an ID “5” and setting data “1111010100”.

  In this embodiment, the ID of the calculation element unit 130 is “0”, the ID of the calculation element unit 131 is “1”, the ID of the calculation element unit 132 is “2”, and the ID of the calculation element unit 133 is “3”. It is assumed that the ID of the calculation element unit 134 is “4” and the ID of the calculation element unit 135 is “5”. In FIG. 1, IDs are shown in parentheses in each calculation element.

  FIG. 6 is a flowchart showing a flow of processing for changing the clock path following the change of the path of the serial transfer bus.

  Step 601 is configuration information reception processing, in which the data transfer control unit 107 reads the configuration information from the memory 106, determines the shortest data transfer path using the Dijkstra method, which is one of the path search algorithms, and the control signal And processing for generating transfer data.

  The Dijkstra method is an algorithm for solving the shortest path problem by graph theory, and can efficiently obtain the shortest path between two vertices on the graph. The route search algorithm is not limited to the Dijkstra method, and other algorithms may be applied.

  The data transfer control unit 107 reads the configuration information 501 and 502 from the memory 106 and determines from the ID information of the read configuration information that the configuration information holding units that need to be set are the configuration information holding units 114 and 117.

  Since the configuration information holding units 114 and 117 need to be set, the data transfer control unit 107 uses the Dijkstra method to transfer the configuration information in the order of the configuration information holding units 110 → 111 → 114 → 117 → 120 → 119. To decide.

  When the transfer path is determined, the data transfer control unit 107 transmits the transfer path information to the clock path control unit 101 and outputs a data transfer control signal 161 for each configuration information holding unit. The data transfer control signal 161 output from the data transfer control unit 107 for each configuration information holding unit is used as a control signal for the serial bus selection multiplexer 202 and a control signal for the configuration information storage unit bypass multiplexer 204.

  Details of the data transfer control signal 161 output from the data transfer control unit 107 to each configuration information holding unit will be described below.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 160 as a control signal for the multiplexer 202 of the configuration information holding unit 110. In addition, a control signal for selecting a signal output from the multiplexer 202 is output to the multiplexer 204 of the configuration information holding unit 110.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 140 as a control signal for the multiplexer 202 of the configuration information holding unit 111. In addition, a control signal for selecting a signal output from the multiplexer 202 is output to the multiplexer 204 of the configuration information holding unit 111.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 143 as a control signal for the multiplexer 202 of the configuration information holding unit 114. In addition, a control signal for selecting a path output from the composition information storage unit 111 is output to the multiplexer 204 of the configuration information holding unit 114.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 148 as a control signal for the multiplexer 202 of the configuration information holding unit 117. Further, a control signal for selecting a path output from the configuration information storage unit 114 is output to the multiplexer 204.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 153 as a control signal for the multiplexer 202 of the configuration information holding unit 120. In addition, a control signal for selecting a signal output from the multiplexer 202 is output to the multiplexer 204 of the configuration information holding unit 120.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 155 as a control signal for the multiplexer 202 of the configuration information holding unit 119. In addition, a control signal for selecting a signal output from the multiplexer 202 is output to the multiplexer 204 of the configuration information holding unit 119.

  Next, the data transfer control unit 107 generates transfer data corresponding to the determined transfer path. The transfer data is generated in the order of transfer on the transfer path of the configuration information holding unit. That is, the transfer is performed earlier as it is located at the end of the transfer path. In the present embodiment, an example in which the transfer order of the configuration information holding unit is performed in the order of the configuration information holding unit 110 → 111 → 114 → 117 → 120 → 119 is described. Therefore, the data transfer control unit 107 generates a bit string “11110101000101010101” that becomes the setting data of the configuration information holding unit 114 after the setting data of the configuration information holding unit 117 as serial transfer data. The generated transfer data is transmitted to the data line of the serial transfer bus 160 in order from the leftmost bit when a clock for serial transfer is transmitted from the clock control unit 102.

  When generating the serial transfer data, the data transfer control unit 107 transmits the total number of bits “20” of the generated transfer data to the clock control unit 102.

  Step 602 is processing of the clock path control unit. Based on the data transfer path determined in step 601, the clock path control unit 101 generates a clock control signal 170 in which clock transmission is performed in a direction opposite to the transfer path. Is shown.

  When the clock path control unit 101 receives the data transfer path from the data transfer control unit 107, the clock output from the clock control unit 102 is transmitted in the order of the configuration information holding unit 119 → 120 → 117 → 114 → 111 → 110. To determine the clock path. That is, the clock longitude can be said to be the reverse path to the data transfer path.

  When the clock path is determined, the clock control unit 101 outputs a clock control signal 170 toward the starting end position so that the clock propagates along the clock path.

  The clock control signal 170 output from the clock path control unit 101 for each configuration information holding unit is a control signal for the clock selection multiplexer 206, a control signal for the clock bypass multiplexer 203, and a control signal for the clock gating circuit 205. .

  Details of the clock control signal 170 output from the clock control unit 101 to each configuration information holding unit on the clock path will be described below.

  The clock path control unit 101 outputs a control signal for selecting the clock 180 to the multiplexer 206 of the configuration information holding unit 119. In addition, a control signal for selecting the clock output from the multiplexer 206 is output to the multiplexer 203 of the configuration information holding unit 119. In addition, a control signal for stopping the clock supplied to the storage unit 201 of the configuration information holding unit 119 is output to the clock gating circuit 205. Thereby, the storage content of the storage unit 201 in the configuration information holding unit 119 is not changed.

  The clock path control unit 101 outputs a control signal for selecting a clock from the serial transfer bus 155 to the multiplexer 206 of the configuration information holding unit 120. In addition, a control signal for selecting the clock output from the multiplexer 206 is output to the multiplexer 203 of the configuration information holding unit 120. Further, a control signal for stopping the clock supplied to the storage unit 201 of the configuration information holding unit 120 is output to the clock gating circuit 205.

  The clock path control unit 101 outputs a control signal for selecting a clock from the serial transfer bus 153 to the multiplexer 206 of the configuration information holding unit 117. Further, a control signal for selecting a path from the storage unit 201 is output to the multiplexer 203 of the configuration information holding unit 117. In addition, a control signal for enabling the clock supplied to the storage unit 201 of the configuration information holding unit 117 is output to the clock gating circuit 205. As a result, the corresponding new configuration information is stored and held in the storage unit 201 in the configuration information holding unit 117.

  The clock path control unit 101 outputs a control signal for selecting a clock from the serial transfer bus 148 to the multiplexer 206 of the configuration information holding unit 114. Further, a control signal for selecting a path from the storage unit 201 is output to the multiplexer 203 of the configuration information holding unit 114. In addition, a control signal for enabling a clock supplied to the storage unit 201 of the configuration information holding unit 114 is output to the clock gating circuit 205. As a result, the storage unit 201 in the configuration information storage unit 117 is updated and stored with new configuration information.

  The clock path control unit 101 outputs a control signal for selecting a clock from the serial transfer bus 143 to the multiplexer 206 of the configuration information holding unit 111. Further, a control signal for selecting a bypass (clock from the multiplexer 206) is output to the multiplexer 203 of the configuration information holding unit 111. Also, a control signal for stopping the clock supplied to 201 of the configuration information holding unit 111 is output to the clock gating circuit 205.

  The clock path control unit 101 outputs a control signal for selecting the clock 140 to the multiplexer 206 of the configuration information holding unit 110. In addition, a control signal for selecting bypass is output to the multiplexer 203 of the configuration information holding unit 110. In addition, a control signal for stopping the clock supplied to the storage unit 201 of the configuration information holding unit 110 is output to the clock gating circuit 205.

  Further, the clock path control unit 101 outputs to the clock gating circuit 205 a control signal for stopping the clock supplied to the storage units 201 of the configuration information holding units 112, 113, 115, 116, 118, and 121 other than those described above. .

  When the clock path control unit 101 outputs the control signal to the all configuration information holding unit as described above, the clock path control unit 101 asserts the clock generation start instruction signal 172 to the clock control unit 102.

  As described above, it is possible to set the clock path for propagating the clock in the direction opposite to the data transfer direction.

  Step 603 is a clock output process, and the clock generation unit 102 generates a clock pulse based on the number of bits of the transfer data transmitted from the data transfer control unit 107 to the clock control unit 102 in step 602.

  When the clock generation start instruction signal 172 output from the clock control unit 101 is asserted, the clock control unit 102 sends the value of the total number of bits “20” of the transfer data transmitted from the data transfer control unit 107 to the counter 301. set. The counter 301 decrements every clock until the value becomes zero, and stops the counter when the value becomes zero after 20 clocks. Since the clock valid signal generation OR circuit 302 ORs all the bits of the counter 301, it generates a clock valid signal for 20 clock cycles. Therefore, the clock 180 output from the clock generator 102 transmits a clock by 20 pulses.

  With the above processing, following the change of the data transfer path of the serial transfer bus, the clock path is changed so that the clock propagation path is in the opposite direction to the data transfer path, and clock pulse transmission control is performed as many times as necessary for data transfer. Is possible. As a result, it is possible to reduce the risk of occurrence of a hold timing violation due to a change in the data transfer path of the serial transfer bus, and to reduce the number of hold buffers inserted.

[Second Embodiment]
In the second embodiment, in the array-type arithmetic unit, even when a power shut-off area (unusable area) exists on the configuration information setting path, and the setting path needs to be detoured, it is in the opposite direction to the setting path. A clock configuration that enables clock propagation and a clock control method will be described.

<Device configuration (FIG. 7)>
FIG. 7 is a block diagram showing a characteristic configuration of the present embodiment, and the configuration of the display device to which the second embodiment is applied will be described with reference to FIG. In addition, the same number is attached | subjected to the block equivalent to the block diagram shown in 1st Embodiment, and description is abbreviate | omitted.

  Reference numerals 710, 711, 712, 713, 714, 715, 716, 717, 718, 719, 720, and 721 in the figure are configuration information holding units that internally hold the configuration information transmitted from the data transfer control unit 107. To do. In addition, the configuration information holding unit has a serial transfer bus, and there are two serial transfer buses with different transfer directions for each adjacent configuration information holding unit, and both directions can be changed by changing the serial transfer path. Data transfer is possible. The configuration information held in the configuration information holding unit has information for determining at least the calculation contents of the calculation element unit and the data exchange path between the calculation element units.

  Reference numerals 740, 741, 742, 743, 744, 745, 746, 747, 748, 749, 750, 751, 752, 753, 754, 755, and 756 are serial transfer buses that connect the configuration information holding units. The serial transfer bus connecting the configuration information holding units is composed of a 2-bit data line having a different transfer direction and a 2-bit clock line having a different propagation direction. In other words, two serial transfer buses indicated by 1-bit data transfer and 1-bit clock line are provided.

  The transfer direction of all serial transfer buses will be described below.

  The serial transfer bus 740 is a serial transfer bus that connects the configuration information holding units 710 and 711, and the data line includes one bit output from the configuration information holding unit 710 to the configuration information holding unit 711 and a configuration information holding unit 711. It consists of 1 bit output to the information holding unit 710. The clock is composed of a clock that propagates the clock from the configuration information holding unit 711 to the configuration information holding unit 710, and the clock is a clock that propagates the clock from the configuration information holding unit 710 to the configuration information holding unit 711.

  The serial transfer bus 741 is a serial transfer bus that connects the configuration information holding units 711 and 712, and the data line includes one bit output from the configuration information holding unit 711 to the configuration information holding unit 712 and a configuration information holding unit 712. It consists of 1 bit output to the information holding unit 711. The clock is composed of a clock that propagates the clock from the configuration information holding unit 712 to the configuration information holding unit 711, and the clock is a clock that propagates the clock from the configuration information holding unit 711 to the configuration information holding unit 712.

  The serial transfer bus 742 is a serial transfer bus that connects the configuration information holding units 710 and 713, and the data line includes one bit output from the configuration information holding unit 710 to the configuration information holding unit 713 and a configuration information holding unit 713. It consists of 1 bit output to the information holding unit 710. The clock is composed of a clock that propagates the clock from the configuration information holding unit 713 to the configuration information holding unit 710, and the clock is a clock that propagates the clock from the configuration information holding unit 710 to the configuration information holding unit 713.

  The serial transfer bus 743 is a serial transfer bus that connects the configuration information holding units 711 and 714, and the data line includes one bit output from the configuration information holding unit 711 to the configuration information holding unit 714 and a configuration information holding unit 714. It consists of 1 bit output to the information holding unit 711. The clock is composed of a clock that propagates the clock from the configuration information holding unit 714 to the configuration information holding unit 711, and the clock is a clock that propagates the clock from the configuration information holding unit 711 to the configuration information holding unit 714.

  The serial transfer bus 744 is a serial transfer bus that connects the configuration information holding units 712 and 715, and the data line includes one bit output from the configuration information holding unit 712 to the configuration information holding unit 715 and a configuration information holding unit 715. It consists of 1 bit output to the information holding unit 712. The clock is composed of a clock that propagates the clock from the configuration information holding unit 715 to the configuration information holding unit 712, and the clock is a clock that propagates the clock from the configuration information holding unit 715 to the configuration information holding unit 712.

  The serial transfer bus 745 is a serial transfer bus that connects the configuration information holding units 713 and 714, and the data line includes one bit output from the configuration information holding unit 713 to the configuration information holding unit 714 and a configuration information holding unit 714. It consists of 1 bit output to the information holding unit 713. The clock is composed of a clock that propagates the clock from the configuration information holding unit 714 to the configuration information holding unit 713, and the clock is a clock that propagates the clock from the configuration information holding unit 713 to the configuration information holding unit 714.

  The serial transfer bus 746 is a serial transfer bus that connects the configuration information holding units 714 and 715, and the data line includes one bit output from the configuration information holding unit 714 to the configuration information holding unit 715 and the configuration information holding unit 715. It consists of 1 bit output to the information holding unit 714. The clock is composed of a clock that propagates the clock from the configuration information holding unit 715 to the configuration information holding unit 714, and the clock is a clock that propagates the clock from the configuration information holding unit 714 to the configuration information holding unit 715.

  The serial transfer bus 747 is a serial transfer bus that connects the configuration information holding units 713 and 716, and the data line includes one bit output from the configuration information holding unit 713 to the configuration information holding unit 716 and a configuration information holding unit 716. It consists of 1 bit output to the information holding unit 713. The clock is composed of a clock that propagates the clock from the configuration information holding unit 716 to the configuration information holding unit 713, and the clock is a clock that propagates the clock from the configuration information holding unit 713 to the configuration information holding unit 716.

  The serial transfer bus 748 is a serial transfer bus that connects the configuration information holding units 714 and 717, and the data line includes one bit output from the configuration information holding unit 714 to the configuration information holding unit 717 and the configuration information holding unit 717. It consists of 1 bit output to the information holding unit 714. The clock is composed of a clock that propagates the clock from the configuration information holding unit 717 to the configuration information holding unit 714, and the clock is a clock that propagates the clock from the configuration information holding unit 714 to the configuration information holding unit 717.

  The serial transfer bus 749 is a serial transfer bus that connects the configuration information holding units 715 and 718, and the data line includes one bit output from the configuration information holding unit 715 to the configuration information holding unit 718 and a configuration information holding unit 718. It consists of 1 bit output to the information holding unit 715. The clock is composed of a clock that propagates the clock from the configuration information holding unit 718 to the configuration information holding unit 715, and the clock is a clock that propagates the clock from the configuration information holding unit 715 to the configuration information holding unit 718.

  The serial transfer bus 750 is a serial transfer bus that connects the configuration information holding units 716 and 717, and the data line includes one bit output from the configuration information holding unit 716 to the configuration information holding unit 717 and the configuration information holding unit 717. It consists of 1 bit output to the information holding unit 716. The clock is composed of a clock that propagates the clock from the configuration information holding unit 717 to the configuration information holding unit 716, and the clock is a clock that propagates the clock from the configuration information holding unit 716 to the configuration information holding unit 717.

  The serial transfer bus 751 is a serial transfer bus that connects the configuration information holding units 717 and 718, and the data line includes one bit output from the configuration information holding unit 717 to the configuration information holding unit 718 and a configuration information holding unit 718. It consists of 1 bit output to the information holding unit 717. The clock is composed of a clock that propagates the clock from the configuration information holding unit 718 to the configuration information holding unit 717, and the clock is a clock that propagates the clock from the configuration information holding unit 717 to the configuration information holding unit 718.

  The serial transfer bus 752 is a serial transfer bus that connects the configuration information holding units 716 and 719, and the data line includes one bit output from the configuration information holding unit 716 to the configuration information holding unit 719 and a configuration information holding unit 719. It consists of 1 bit output to the information holding unit 716. The clock is composed of a clock that propagates the clock from the configuration information holding unit 719 to the configuration information holding unit 716, and the clock is a clock that propagates the clock from the configuration information holding unit 716 to the configuration information holding unit 719.

  The serial transfer bus 753 is a serial transfer bus that connects the configuration information holding units 717 and 720, and the data line includes one bit output from the configuration information holding unit 717 to the configuration information holding unit 720 and a configuration information holding unit 720. It consists of 1 bit output to the information holding unit 717. The clock is composed of a clock that propagates the clock from the configuration information holding unit 720 to the configuration information holding unit 717, and the clock is a clock that propagates the clock from the configuration information holding unit 717 to the configuration information holding unit 720.

  The serial transfer bus 754 is a serial transfer bus that connects the configuration information holding units 718 and 721, and the data line includes one bit output from the configuration information holding unit 718 to the configuration information holding unit 721 and a configuration information holding unit 721. It consists of 1 bit output to the information holding unit 718. The clock is composed of a clock that propagates the clock from the configuration information holding unit 721 to the configuration information holding unit 718, and the clock is a clock that propagates the clock from the configuration information holding unit 718 to the configuration information holding unit 721.

  The serial transfer bus 755 is a serial transfer bus that connects the configuration information holding units 719 and 720, and the data line includes one bit output from the configuration information holding unit 719 to the configuration information holding unit 720 and a configuration information holding unit 720. It consists of 1 bit output to the information holding unit 719. The clock is composed of a clock that propagates the clock from the configuration information holding unit 720 to the configuration information holding unit 719, and the clock is a clock that propagates the clock from the configuration information holding unit 719 to the configuration information holding unit 720.

  The serial transfer bus 756 is a serial transfer bus that connects the configuration information holding units 720 and 721, and the data line includes one bit output from the configuration information holding unit 720 to the configuration information holding unit 721 and a configuration information holding unit 721. It consists of 1 bit output to the information holding unit 720. The clock is composed of a clock that propagates the clock from the configuration information holding unit 721 to the configuration information holding unit 720, and the clock is a clock that propagates the clock from the configuration information holding unit 720 to the configuration information holding unit 721.

  The serial transfer bus 760 is a serial transfer bus that connects the data transfer control unit 107 and the configuration information holding unit 710. The serial transfer bus 760 includes a 1-bit data line and a clock line. The data transfer direction of the data line is output from the data transfer control unit 107 to the configuration information holding unit 710, and the clock is output from the configuration information holding unit 710. To the data transfer control unit 107.

  Reference numeral 780 denotes a serial data transfer clock, and configuration information holding units 710, 711, 712, 713, 715, 716, 718, 719, 720, 721 arranged from the clock control unit 102 to the outer edge of the data processing device. Is output.

<Configuration of Configuration Information Holding Unit (FIG. 8)>
FIG. 8 is a block diagram showing the configuration of the configuration information holding unit in the second embodiment, and the configuration of the configuration information holding unit will be described with reference to FIG. In addition, the same number is attached | subjected to the block equivalent to the block diagram shown in 1st Embodiment, and description is abbreviate | omitted.

  In the case of the second embodiment, one configuration information holding unit can input data from the other four configuration information holding units, and the other four configuration information holding units can be output targets. Please be careful.

  Reference numerals 810, 811, 812, and 813 in the figure are data lines of the serial transfer bus input from the other configuration information holding unit, and reference numerals 820, 821, 823, and 824 are assigned to the data lines 810, 811, 812, and 813, respectively. The corresponding clock line is shown.

  Reference numerals 830, 831, 832, and 833 are data lines of the serial transfer bus output to the other configuration information holding unit, and reference numerals 840, 841, 843, and 844 correspond to the data lines of the data lines 830, 831, 832, and 833, respectively. Shows the clock line.

  Further, the data line 810 and the data data 830 are different data lines in the same serial transfer bus direction. Similarly, the data line 811 and the data line 831 are different data lines in the same serial transfer bus direction. Similarly, the data lines 812 and 832 are different data lines in the same serial transfer bus direction. The data line 813 and the clock line 833 are different data lines in the same serial transfer bus direction.

  Reference numeral 802 denotes a multiplexer that selects the data lines 810, 811, 812, and 813 of the serial transfer bus, and selects the serial transfer bus according to the data transfer control signal 161 transmitted from the data transfer control unit.

  Reference numeral 804 denotes a multiplexer for bypassing the configuration information storage unit. When there is no need to rewrite the data in the configuration information storage unit, the multiplexer 802 receives the data transfer control signal 161 transmitted from the data transfer control unit. Select the data to be output. Data output from the multiplexer 804 is transmitted to the data lines 830, 831, 832, and 833 of the serial transfer bus.

  Reference numeral 806 denotes a multiplexer that selects the clock lines of the clocks 840, 841, 842, and 843 of the serial transfer bus, and performs clock selection according to the clock control signal 170 transmitted from the clock path control unit 101.

  Reference numeral 805 denotes a clock gating circuit that performs gating of a clock used in the configuration information storage unit 201 in accordance with a clock control signal 170 transmitted from the clock control unit.

  Reference numeral 803 denotes a multiplexer for bypassing the clock. When there is no need to set data in the configuration information storage unit 201, the multiplexer 806 outputs the multiplexer 806 in response to the clock control signal 170 transmitted from the clock path control unit. Select the clock. The clock output from the multiplexer 803 is transmitted to the clocks 820, 821, 822, and 823 of the serial transfer bus.

  The correspondence relationship between the data line and clock line of the serial transfer bus included in the configuration information holding unit in FIG. 8 and the serial transfer bus in FIG. 7 will be described below.

  One configuration information holding unit in FIG. 7 has serial transfer buses on the top, bottom, left and right, and the data lines of the serial transfer bus connected to the right side of the configuration information holding unit are 810 and 830, respectively. Are 820 and 840. Similarly, the data lines of the serial transfer bus connected to the upper side of the configuration information holding unit are 811 and 831, and the corresponding clock lines are 821 and 841, respectively. Similarly, the data lines of the serial transfer bus connected to the left side of the configuration information holding unit are 812 and 832, and the corresponding clock lines are 822 and 842, respectively. Similarly, the data lines of the serial transfer bus connected to the lower side of the configuration information holding unit are 813 and 833, and the corresponding clock lines are 823 and 843, respectively.

  Also, in the configuration information holding unit located at the end in FIG. 7, when there is no adjacent configuration information holding unit and no serial transfer bus, the output side data line and the clock line are open, and the input side data line is Fixed to ground. However, the input clock line is connected to the serial transfer clock signal 780.

  Also, the serial transfer bus 760 in the figure is composed of a 1-bit data line and a 1-bit clock line. The data line 812 and the clock line 822 in FIG. Shall be connected.

  As an example, the connection relationship of the serial transfer bus will be described below using the configuration information holding unit 710 as an example.

  The serial transfer bus 740 connected to the right side of the configuration information holding unit 710 is connected to the data lines 810 and 830 and is connected to the clock lines 820 and 840. Since there is no serial transfer bus connected to the upper side of the configuration information holding unit 710, 811 is connected to the ground, and 831 and 821 are open. However, a serial data transfer clock 780 is connected to 841. Since the serial transfer bus connected to the left side of the configuration information holding unit 710 is 760, 812 is connected to the data line of the serial transfer bus 760 and 822 is connected to the clock line. Further, the data line 832 is output open, and the clock line 842 is fixed to the ground. The serial transfer bus 742 connected to the lower side of the configuration information holding unit 710 is connected to the data lines 813 and 833 and connected to the clock lines 833 and 843. Regarding the configuration information holding units other than the configuration information holding unit 710, the connection relationship of the serial transfer bus is clear depending on the arrangement position of the configuration information holding unit, and thus description thereof is omitted.

<Clock path change processing (FIGS. 6 and 9)>
The flow of processing for changing the clock path following the change of the path of the serial transfer bus will be described with reference to FIGS.

  FIG. 9 shows configuration information stored in the memory 106 in the second embodiment. The configuration information 901 includes an ID “1” and setting data “0101010101”. The configuration information 902 includes an ID “2” and setting data “1111100000”. The configuration information 903 includes an ID “5” and setting data “1111100000”.

  As in the first embodiment, the ID of the calculation element unit 130 is “0”, the ID of the calculation element unit 131 is “1”, the ID of the calculation element unit 132 is “2”, and the ID of the calculation element unit 133 is “3”. It is assumed that the ID of the calculation element unit 134 is “4” and the ID of the calculation element unit 135 is “5”.

  In the second embodiment, the configuration information holding unit 714 will be described as being in a state where the power is shut down for some reason and cannot be used as a data transmission path for the configuration information.

  The flow of processing for changing the clock path following the change of the path of the serial transfer bus will be described below with reference to FIG.

  In step 601, the data transfer control unit 107 reads the configuration information 901, 902, and 903 from the memory 106, and the configuration information holding unit that needs to be set based on the ID information of the read configuration information is the configuration information holding unit 711, 713, 717 is determined.

  Since the configuration information holding unit 714 cannot be included in the data transfer path, the data transfer control unit 107 uses the detour path search algorithm to change the configuration information holding unit 710 → 711 → 712 → 715 → 718 → 717 → 716 → 713. The transfer route to be determined is determined.

  In the second embodiment, as a bypass route search algorithm, a method of performing a route search by the Dijkstra method in a state where a restriction that some of the routes cannot be selected is imposed. Note that the detour route search algorithm is not limited to the above method, and a detour route may be searched using another algorithm.

  When the transfer path is determined, the data transfer control unit 107 transmits the transfer path information to the clock path control unit 101 and outputs a data transfer control signal 161 for each configuration information holding unit. The data transfer control signal 161 output by the data transfer control unit 107 for each configuration information holding unit is a control signal for the serial bus selection multiplexer 802 and a control signal for the configuration information storage unit bypass multiplexer 804.

  Details of the data transfer control signal 161 output from the data transfer control unit 107 to each configuration information holding unit will be described below.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 760 as a control signal for the multiplexer 802 of the configuration information holding unit 710, and a control signal for selecting the signal output from the multiplexer 802 to the multiplexer 804. Output.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 740 as a control signal of the multiplexer 802 of the configuration information holding unit 711, and is output from the storage unit 201 of the configuration information holding unit 711 to the multiplexer 804. A control signal for selecting a signal is output.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 741 as a control signal for the multiplexer 802 of the configuration information holding unit 712, and a control signal for selecting the signal output from the multiplexer 802 to the multiplexer 804. Output.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 744 as a control signal for the multiplexer 802 of the configuration information holding unit 715, and a control signal for selecting the signal output from the multiplexer 802 to the multiplexer 804. Output.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 749 as a control signal for the multiplexer 802 of the configuration information holding unit 718, and outputs a control signal for selecting the signal output from the multiplexer 802 to the multiplexer 804. Output.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 751 as a control signal of the multiplexer 802 of the configuration information holding unit 717, and is output from the storage unit 201 of the configuration information holding unit 717 to the multiplexer 804. A control signal for selecting a signal is output.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 750 as a control signal for the multiplexer 802 of the configuration information holding unit 716, and outputs a control signal for selecting the signal output from the multiplexer 802 to the multiplexer 804. Output.

  The data transfer control unit 107 outputs a control signal for selecting the serial transfer bus 747 as a control signal of the multiplexer 802 of the configuration information holding unit 713, and is output from the storage unit 201 of the configuration information holding unit 713 to the multiplexer 804. A control signal for selecting a signal is output.

  Next, the data transfer control unit 107 generates transfer data corresponding to the determined transfer path. The transfer data is generated in the order of transfer on the transfer path of the configuration information holding unit. In this embodiment, an example in which the transfer order of the configuration information holding unit is performed in the order of the configuration information holding unit 710 → 711 → 712 → 715 → 718 → 717 → 716 → 713 has been described. Therefore, the data transfer control unit 107 generates a configuration information holding unit 713 as serial transfer data, and then a configuration information holding unit 717 and a configuration information holding unit 717 followed by a bit string that becomes setting data of the configuration information holding unit 711. That is, the bit string generated by the data transfer control unit 107 is 30 bits “001100110011111100001010101” from FIG. The generated transfer data is transmitted to the data line of the serial transfer bus 760 in order from the leftmost bit when a clock for serial transfer is transmitted from the clock generator 102.

  Next, the data transfer control unit 107 transmits the total number of bits “30” of the serial transfer data to the clock generation unit 102.

  In step 602, when the clock path control unit 101 receives a data transfer path from the data transfer control unit 107, the clock path generated by the clock control unit 102 determines a clock path in the opposite direction to the data transfer path. Therefore, in the second embodiment, the clock path control unit 101 and the clock path are configured so that the clock information is transmitted in the order of the configuration information holding unit 713 → 716 → 717 → 718 → 715 → 712 → 711 → 710. decide.

  When the clock path is determined, the clock path control unit 101 outputs a clock control signal 170 to the all configuration information holding unit so that the clock propagates along the clock path. The control signals output from the clock path control unit 101 for each configuration information holding unit are a control signal for the clock selection multiplexer 806, a control signal for the clock bypass multiplexer 803, and a control signal for the clock gating circuit 805.

  Details of the clock control signal 170 output from the clock path control unit 101 to each configuration information holding unit will be described below.

  The clock path control unit 101 outputs a control signal for selecting the clock 780 to the multiplexer 806 of the configuration information holding unit 713, and outputs a control signal for selecting a path from the configuration information storage unit to the multiplexer 803. In addition, a control signal for enabling the clock supplied to the storage unit 201 of the configuration information holding unit 713 is output to the clock gating circuit 805.

  The clock path control unit 101 outputs a control signal for selecting the clock line of the serial transfer bus 747 to the multiplexer 806 of the configuration information holding unit 716, and outputs a control signal for selecting the clock output from the 806 to the multiplexer 803. In addition, a control signal for stopping the clock supplied to the storage unit 201 of the configuration information holding unit 716 is output to the clock gating circuit 805.

  The clock path control unit 101 outputs a control signal for selecting the clock line of the serial transfer bus 750 to the multiplexer 806 of the configuration information holding unit 717, and outputs a control signal for selecting a path from the configuration information storage unit to the multiplexer 803. . In addition, a control signal for enabling a clock supplied to the storage unit 201 of the configuration information holding unit 717 is output to the clock gating circuit 805.

  The clock path control unit 101 outputs a control signal for selecting the clock line of the serial transfer bus 751 to the multiplexer 806 of the configuration information holding unit 718, and outputs a control signal for selecting the clock output from the 806 to the multiplexer 803. In addition, a control signal for stopping the clock supplied to the storage unit 201 of the configuration information holding unit 718 is output to the clock gating circuit 805.

  The clock path control unit 101 outputs a control signal for selecting the clock line of the serial transfer bus 749 to the multiplexer 806 of the configuration information holding unit 715, and outputs a control signal for selecting the clock output from the 806 to the multiplexer 803. In addition, a control signal for stopping the clock supplied to the storage unit 201 of the configuration information holding unit 715 is output to the clock gating circuit 805.

  The clock path control unit 101 outputs a control signal for selecting the clock line of the serial transfer bus 744 to the multiplexer 806 of the configuration information holding unit 712, and outputs a control signal for selecting the clock output from the 806 to the multiplexer 803. In addition, a control signal for stopping the clock supplied to the storage unit 201 of the configuration information holding unit 712 is output to the clock gating circuit 805.

  The clock path control unit 101 outputs a control signal for selecting the clock line of the serial transfer bus 741 to the multiplexer 806 of the configuration information holding unit 711, and outputs a control signal for selecting a path from the configuration information storage unit to the multiplexer 803. . In addition, a control signal for enabling the clock supplied to the storage unit 201 of the configuration information holding unit 711 is output to the clock gating circuit 805.

  The clock path control unit 101 outputs a control signal for selecting the clock line of the serial transfer bus 740 to the multiplexer 806 of the configuration information holding unit 710, and outputs a control signal for selecting the clock output from the 806 to the multiplexer 803. In addition, a control signal for stopping the clock supplied to the storage unit 201 of the configuration information holding unit 710 is output to the clock gating circuit 805.

  Further, the clock path control unit 101 controls to stop the clock supplied to the storage unit 201 of another configuration information holding unit (719, 720, 721 in the second embodiment) that is off the data or clock transfer path. The signal is output to the clock gating circuit 805.

  As described above, when the clock path control unit 101 outputs a control signal to the all configuration information holding unit, the clock generation start instruction signal 172 is asserted to the clock generation unit 102.

  As described above, it is possible to set the clock path for propagating the clock in the direction opposite to the data transfer direction.

  In step 602, when the clock generation start instruction signal 172 output from the clock control unit 101 is asserted, the clock generation unit 102 has a value of the total number of bits “30” of transfer data transmitted from the data transfer control unit 107. Is set in the counter 301.

  The counter 301 decrements every clock until the value becomes zero, and stops the counter when the value becomes zero after 30 clocks. Since the clock valid signal generation OR circuit 302 ORs all the bits of the counter 301, it generates a clock valid signal for 30 clock cycles. Therefore, the clock 180 output from the clock generation unit 102 transmits a clock by 30 pulses.

  As described above, according to the second embodiment, in the array type arithmetic unit, even when the power shut-off area exists on the configuration information setting path and it is necessary to bypass the setting path, it is opposite to the setting path. The clock can be propagated in the direction. As a result, it is possible to reduce the risk of occurrence of a hold timing violation due to a change in the data transfer path of the serial transfer bus, and to reduce the number of hold buffers inserted.

  The present invention is not limited to the above-described embodiment, and can be widely applied when the data transfer path change of the serial transfer bus can be changed.

DESCRIPTION OF SYMBOLS 100 ... Data processing part, 101 ... Clock path control part, 102 ... Clock control part, 106 ... Memory, 107 ... Data transfer control part, 110 thru | or 121 ... Configuration information holding part, 130 thru | or 135 ... Calculation element part (PE), 140 to 156 ... Serial transfer bus

Claims (6)

Configuration information for determining a plurality of arithmetic elements, processing contents of each arithmetic element and a data transfer path connecting the arithmetic elements can be stored, arranged in a matrix, and connected to each other via a serial transfer bus A control device for an array type arithmetic unit configured with a plurality of configuration information holding units,
When one or more new configuration information to be changed is given, a transfer path for transferring the new configuration information is determined and transferred based on the position of the configuration information holding unit to be updated with the new configuration information Data transfer control means for determining the arrangement of the new configuration information at the time,
New configuration information that is determined by the data transfer control means is determined in reverse to the transfer path of the new configuration information, and the configuration information holding unit to be updated on the reverse path is transferred in synchronization with the clock. And a clock path control means for setting the configuration information holding unit other than the configuration information holding unit to be updated to bypass the clock,
A clock control means for supplying a number of clocks corresponding to the length of information indicated by the new configuration information to a configuration information holding unit serving as a starting end on the reverse path; Control device.   The array data processing device control device according to claim 1, wherein the data transfer control unit determines a transfer path based on an ID of a calculation element included in the new configuration information.   The data transfer control unit transfers the sequence of bits representing the configuration information in the new configuration information earlier in the configuration information holding unit to be updated as it is closer to the end of the transfer path. Item 3. The control device for the array type arithmetic device according to Item 1 or 2. The serial transfer bus that connects two adjacent configuration information holding units includes two serial transfer buses whose transfer directions are opposite to each other,
2. The data transfer control unit, when there is an unusable configuration information storage unit, determines a transfer path for transferring the new configuration information that bypasses the unusable configuration information storage unit. Control device of array type arithmetic unit as described in 2.   5. The control device for an array type arithmetic unit according to claim 1, wherein the clock control means generates a number of clocks corresponding to all bits indicated by the new configuration information to be transferred. Configuration information for determining a plurality of arithmetic elements, processing contents of each arithmetic element and a data transfer path connecting the arithmetic elements can be stored, arranged in a matrix, and connected to each other via a serial transfer bus A control method of an array type arithmetic unit configured with a plurality of configuration information holding units,
When the data transfer control means is given one or more new configuration information to be changed, a transfer path for transferring the new configuration information based on the position of the configuration information holding unit to be updated with the new configuration information. And a data transfer control step for determining the arrangement of the new configuration information when transferring, and
The clock path control means determines a path reverse to the transfer path of the new configuration information determined in the data transfer control step, and the configuration information holding unit to be updated on the reverse path is synchronized with the clock. A clock path control step for storing and updating the new configuration information to be transferred, and setting the configuration information holding unit other than the configuration information holding unit to be updated to bypass the clock; and
A clock control step for supplying a number of clocks corresponding to a length of information indicated by the new configuration information to a configuration information holding unit serving as a starting end on the reverse path; Control method for array type arithmetic unit.

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