JP2010109869A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce latency on a network or to improve throughput in a semiconductor device with NoC (network on chip). <P>SOLUTION: The semiconductor device includes: a plurality of components IP0-IP7 for performing predetermined processing; a plurality of router circuits R0-R7 connected to the components, respectively; a plurality of wirings connecting the router circuits; and a router management unit SOC_NAVI for monitoring in real time whether the plurality of router circuits are enabled or not. For example, R0 holds, for each of R1-R7, single or plural route information determined on a stage of design beforehand, starting from R0 up to R1-R7. When transferring a request to a predetermined component, R0 searches for an optimal route while reflecting information from SOC_NAVI in the route information. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as a SoC (system on chip) having a NoC (network on chip) that connects a number of master components and slave components via a network interface. Related to effective technology.

  FIG. 2 shows a route search method generally known on the Internet and its advantages and disadvantages. As shown in FIG. 2, in the Internet, a static routing method in which a route is fixed and a dynamic routing method in which a route is dynamically changed are known. For example, the dynamic routing method can avoid routes that cannot be used due to failures, etc., but if incorrect route information is announced due to a setting error or device failure, the entire network is spread and the worst network goes down. There is.

For example, Patent Document 1 discloses a data processing apparatus including a traffic monitoring unit that monitors the traffic state of each bus between two buses to which a plurality of initiators and targets are connected. The traffic monitoring unit determines which bus is congested by integrating the generation period of the bus grant signal for each bus transmitted to each initiator, and one of the buses based on the determination result. Various types of switching are performed so that data transfer from the initiator to the target is performed via.
JP 2007-026284 A

  In recent years, with the increase in the number of IPs (intellectual properties) installed in SoCs, the number of router circuits that are constituent elements of NoC connecting these IPs also increases, and the connection relationship between router circuits is also complicated. It has become. Here, the problem lies in which router circuit is used to exchange data. Depending on the route selection, latency increases and throughput decreases.

  In order to solve such a problem, for example, it is conceivable to apply the technique of Patent Document 1. That is, the technology of Patent Document 1 is a method of monitoring the past access frequency in each bus and selecting the optimum bus, but applying this, the past access frequency to the router circuit is monitored, Based on this, a method of selecting a route through a router circuit with low access frequency is conceivable. However, in this method, route selection is performed based on the past access frequency, so depending on the processing contents (that is, applications) performed by the SoC, the route is not necessarily the optimum route, and there is a possibility that latency is increased. In other words, for example, when the SoC is used as a general-purpose processing device, the optimum access path varies depending on the application, and thus the past access frequency cannot always be effectively utilized. Furthermore, in the technique of Patent Document 1, there is no need to consider connection between buses. However, in SoC with NoC, it is necessary to select the optimum route in consideration of the connection relationship between router circuits. A new mechanism to achieve it efficiently is required.

  The present invention has been made in view of the above, and one of its purposes is to realize a reduction in latency on a network or an improvement in throughput in a semiconductor device provided with a NoC. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows.

  The semiconductor device according to the present embodiment includes a master component that issues a request, a slave component that receives the request, a plurality of router circuits that exist on a plurality of paths between the master component and the slave component, and the plurality of routers. And a router management unit that monitors the valid / invalid state of the circuit in real time. When the router circuit connected to the master component sends a request to the router circuit connected to the slave component, it obtains the valid / invalid state of the plurality of router circuits from the router management unit, and based on this, the router circuit One route is selected from among the routes.

  In this way, the router circuit can perform optimal route search based on the real-time validity / invalidity information of the router circuit on each route, thereby reducing the latency on the network connecting the router circuits or improving the throughput. Becomes feasible. Here, the signal indicating the valid / invalid state of each router circuit includes a buffer status signal indicating whether or not the buffer circuit in each router circuit is empty. Each router circuit has a function of stopping supply of its own operation clock signal according to the conditions. In addition to the buffer status signal, this operation clock signal is used as a signal indicating the valid / invalid state of each router circuit. A clock status signal indicating whether or not the supply is stopped. The router management unit holds a signal indicating the valid / invalid state of each router circuit in the internal storage unit, and updates them in real time (every clock cycle).

  In addition, each router circuit holds one or more route information for each destination in the internal storage unit, starting from itself as a destination other than the router circuit as a destination, and reaching each destination. . Each router circuit searches the optimum route by reflecting the above-described valid / invalid state of each router circuit in this route information. Since this route information can be determined in advance at the design stage of the semiconductor device, although the dynamic routing method is adopted, incorrect route information is never announced. This also makes it possible to reduce the latency on the network or improve the throughput.

  The effects obtained by the representative embodiments of the invention disclosed in this application will be briefly described. In the semiconductor device including the NoC, it is possible to reduce the latency on the network or improve the throughput.

  In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant, and one is the other. Some or all of the modifications, details, supplementary explanations, and the like are related. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing an example of the configuration of the semiconductor device according to the first embodiment of the present invention. The semiconductor device SOC shown in FIG. 1 includes a plurality (eight here) of components IP0 to IP7, a plurality (eight here) of router circuits R0 to R7 corresponding to the respective components, and a router management unit (SoC navigator). ) SOC_NAVI is provided. Each of the components IP0 to IP7 is a master component that can make a transfer request, a slave component that can respond to the transfer request, or both.

  The router circuit R0 is connected to IP0 and is connected to some or all of the other router circuits R1 to R7. Here, in order to easily form the wiring between the router circuits in the semiconductor device, each router circuit is connected to only a part of the router circuits arranged relatively near itself. For example, R0 is connected to R2, R1, and R4 arranged in the vicinity thereof. Similarly, the router circuits R1 to R7 are connected to the corresponding components IP1 to IP7, respectively, and are connected to a plurality of router circuits arranged in the vicinity. The router management unit SOC_NAVI is connected to all the router circuits R0 to R7 and manages the usage status of each router circuit. As will be described in detail later, each of the router circuits R0 to R7 has a first function for selecting a route in real time using communication information with the SOC_NAVI, and a priority order of transfer requests from the components IP0 to IP7. A second function for performing arbitration based on the above is provided.

  FIG. 3 is an explanatory view showing a basic structure example of packet data (interface signal) passing through each router circuit in the semiconductor device of FIG. The packet data (interface signal) shown in FIG. 3 includes a header (HD) and data (DAT) each having an arbitrary bit width. The header (HD) is a packet ID (PKT_ID), a source ID (SRC_ID) of a transfer source, a middle ID (MID_ID) indicating a router circuit that has passed through the previous time, a destination ID (DST_ID) of a transfer destination, and the total size of the header and data Packet size (PKT_SIZE), priority (PRI), opcode (OPC), and optional extension header (EXT).

  SRC_ID, DST_ID, and MID_ID are determined to have a predetermined bit width depending on how many component IPs and router circuits R are provided in the semiconductor device. Further, PKT_SIZE, PRI, and OPC are set to a predetermined bit width according to the specifications of the semiconductor device. Although details will be described later, MID_ID is used to determine the presence or absence of a self-loop, and PRI gives priority to a router circuit when a transfer request or the like is simultaneously received from different components or router circuits. Used to determine Also, PKT_SIZE is used, for example, to identify how many cycles packet data is transferred, and OPC is an instruction code issued to a transfer destination component. The EXT is not necessarily provided, and the PRI can be omitted if the priority order is fixedly determined in advance.

  4 schematically shows an example of a communication method between a master component and a slave component in the semiconductor device of FIG. 1, wherein (a) is a schematic diagram when a transfer request is made, and (b) is (a). It is a schematic diagram at the time of making a response to the transfer request. In practice, as shown in FIG. 1, communication may be performed between a master component and a slave component via a plurality of router circuits. Here, for simplification, the communication is performed via one router circuit. It shall be. When passing through a plurality of router circuits, a router circuit is further inserted after the router circuit R in FIGS. 4 (a) and 4 (b). However, even in this case, as will be described later, the packet data structure and its transmission / reception procedure are fixed regardless of the component and the router circuit. Therefore, the router circuit inserted in the subsequent stage is shown in FIGS. The signal flow is the same as that of each router circuit R.

  In FIG. 4A, the master component IP_M is directed to the router circuit R together with the transfer request signal (REQ), the packet ID (PKT_ID), the source ID of the transfer source (SRC_ID), and the middle representing the router circuit that has passed through the previous time. ID (MID_ID), destination ID (DST_ID) of the transfer destination, total size of header and data (PKT_SIZE), data (DAT), priority (PRI) indicating priority, and operation code (OPC) are transmitted. When permitting this transfer request, the router circuit R transmits a transfer permission signal (GNT) to IP_M, and packet data (PKT_ID, SRC_ID, MID_ID, DST_ID, PKT_SIZE, DAT, PRI, OPC) is held inside. Next, the router circuit R transmits to the slave component IP_S, together with the transfer request signal (REQ), the packet data held by the transfer from the IP_M described above. Note that when performing transmission toward the IP_S, the router circuit R performs transmission by rewriting MID_ID with its own ID. When IP_S permits a transfer request from the router circuit R, the IP_S transmits a transfer permission signal (GNT) to the router circuit R, and an operation code (OPC) or data (DAT) in the transferred packet data. Perform processing according to.

  When the slave component IP_S finishes the predetermined processing according to the request from the IP_M described above, the packet ID (PKT_ID) is transmitted to the router circuit R together with the transfer response signal (RES) as shown in FIG. ), Source ID (SRC_ID) of the transfer source, middle ID (MID_ID) indicating the router circuit that passed through the previous time, destination ID (DST_ID) of the transfer destination, total size of header and data (PKT_SIZE), response data (R_DAT), A priority (PRI) and a response opcode (R_OPC) are transmitted. When permitting this transfer response, the router circuit R transmits a transfer response permission signal (R_GNT) to IP_S, and packet data (PKT_ID, SRC_ID, MID_ID, DST_ID, PKT_SIZE, R_DAT, R_OPC) transferred from this IP_S. ) Is held inside. Thereafter, the same communication is performed between the router circuit R and the IP_M with the signal flow opposite to that in the case of FIG.

  FIG. 5 shows an example of a schematic configuration of each router circuit in the semiconductor device of FIG. 1. FIG. 5A is a schematic diagram of a router circuit corresponding to a component having a master function and a slave function, and FIG. It is the schematic of the router circuit corresponding to the component provided with the slave function. The router circuit R0 shown in FIG. 5A includes a request processing circuit RTCTL_REQ0 and a response processing circuit RTCTL_RES0, assuming that the corresponding component IP0 has a master function and a slave function. The router circuit R4 shown in FIG. 5B includes a request processing circuit RTCTL_REQ4 and a response processing circuit RTCTL_RES4, assuming that the corresponding component IP4 has only a slave function.

  In FIG. 5 (a), RTCTL_REQ0 has four input ports and four output ports. Component IP0 and router circuits R1, R2, and R4 are connected to each input port, and each output port is also connected. , IP0 and R1, R2, and R4 are connected to each other. The request type packet data described in FIG. 4 is input to each of the four input ports. RTCTL_REQ0 selects one of the packet data and selects one of the four output ports. The selected packet data is output from the selected output port. Similarly, RTCTL_RES0 includes four input ports and four output ports, and IP0 and R1, R2, and R4 are connected to each input port, and each output port also has IP0 and R1, respectively. R2 and R4 are connected. The response-related packet data described in FIG. 4 is input to each of the four input ports. RTCTL_RES0 selects one of the packet data and selects one of the four output ports. The selected packet data is output from the selected output port.

  On the other hand, in FIG. 5B, RTCTL_REQ4 includes three input ports and four output ports, and router circuits R0, R3, and R5 are connected to the input ports, respectively. , Component IP4 and R0, R3, R5 are connected. The request-type packet data described in FIG. 4 is input to each of the three input ports. RTCTL_REQ4 selects one of the packet data and selects one of the four output ports. The selected packet data is output from the selected output port. RTCTL_RES4 includes four input ports and three output ports. IP4 and R0, R3, and R5 are connected to each input port, and R0, R3, and R5 are respectively connected to each output port. Connected. The response-related packet data described in FIG. 4 is input to each of the four input ports, and RTCTL_RES4 selects one of the packet data and selects one of the three output ports. The selected packet data is output from the selected output port.

  The configuration in which the request processing circuit (RTCTL_REQ) and the response processing circuit (RTCTL_RES) are separated as shown in FIG. 4 and FIGS. 5A and 5B is called a split transaction. It becomes possible to increase the processing efficiency. If high processing efficiency is not required, a router configuration that is shared by one processing circuit without distinguishing between a request and a response (for example, regarding a transfer response signal (RES) as a transfer request signal (REQ)) It is also possible to do.

  FIG. 6 is a block diagram showing a detailed configuration example of the request processing circuit RTCTL_REQ in the router circuit of FIG. The request processing circuit RTCTL_REQ shown in FIG. 6 includes an input selector SEL_I, an input buffer BUF_I, a request arbitration circuit ARB, an output buffer BUF_O, an output selector SEL_O, a path information holding / calculating circuit RTCAL, a local buffer management unit BUF_CTL, and a clock control circuit CK_CTL. I have. As shown in FIGS. 5A and 5B, SEL_I receives packet data (PKT_ID, SRC_ID, MID_ID, DST_ID, PKT_SIZE, DAT, PRI, OPC) and, in addition, packet data from the component IP is input. Any one of the plurality of packet data is selected by an instruction from BUF_CTL and transferred to the input buffer BUF_I.

  The packet data transferred to the input buffer BUF_I is transferred to the output buffer BUF_O based on the instruction of BUF_CTL. The output selector SEL_O selects the output port 615 based on an instruction from the path information holding / calculating circuit RTCAL, and outputs the packet data transferred to the BUF_O from the selected output port. As shown in FIGS. 5A and 5B, the component port and a plurality of router circuits R are connected to the output port, and one of these is selected.

  The local buffer management unit BUF_CTL receives a transfer request signal (REQ) from a plurality of router circuits R (that is, a REQ from a component IP other than itself) and a REQ from a component IP corresponding to the local buffer management unit BUF_CTL. Either one is allowed. At this time, the priority PRI corresponding to each REQ is referred to, the arbitration circuit ARB is used to determine the REQ having the highest priority, and the presence / absence of BUF_I or BUF_O is checked, and this highest priority is determined. Allow a high REQ. Then, a transfer permission signal (GNT) is transmitted to the router circuit R or component IP corresponding to the permitted REQ.

  In addition, BUF_CTL is a counter with an internal period when, for example, all REQs directed to itself are not issued and packet data does not stay in the input buffer BUF_I and the output buffer BUF_O. Count. Then, BUF_CTL compares the count value with a predetermined threshold value and outputs a standby instruction signal 613 toward the clock control circuit CK_CTL when the threshold value is reached. CK_CTL supplies an operation clock to BUF_I, BUF_O, BUF_CTL, RTCAL, and the like (hereinafter, this state is referred to as clock on). When this standby instruction signal 613 is received, Supply is stopped (hereinafter, this state is called clock-off). Thereby, the router circuit enters a power saving mode. Further, when the power saving mode is set, CK_CTL notifies the SOC_NAVI that the power saving mode is set using the clock-off signal 612a. For example, CK_CTL resumes the supply of the operation clock when receiving the clock-on signal 612b from the SOC_NAVI.

  Further, the BUF_CTL monitors whether the buffer status in the router circuit is “empty” or “full”, and notifies the SOC_NAVI of the monitoring result using the buffer status signal 617. Here, the buffer state of the router circuit being “empty” indicates that the input buffer BUF_I is in a state of accepting packet data. For example, even if the packet data is clogged in the BUF_I, the output buffer BUF_O in the subsequent stage is not in the packet state. If the data can be received, it is “empty”. On the other hand, the buffer state of the router circuit being “full” is a state in which BUF_I cannot accept packet data.

  Note that the above-described function of supplying or stopping the operation clock is not necessarily required, but the more the number of IPs included in the semiconductor device SOC, the more conspicuous the problem of power consumption becomes. Is desirable. The method for supplying or stopping the operation clock is not limited to the method described above, and can be changed as appropriate. For example, the SOC_NAVI monitors the 617 from the local buffer management unit BUF_CTL, and instructs the clock control circuit CK_CTL to stop supplying the operation clock when the state of “empty” continues for a certain period of time. Any method may be used.

  The route information holding / calculating circuit RTCAL holds one or more pieces of route information from the router circuit as a starting point until reaching the destination component in a storage unit (for example, a register) provided therein. As will be described in detail later, RTCAL indicates the status (“empty” or “full”) of the router circuit in all the router circuits other than the router and the supply or stop status of the operation clock via the other router monitoring signal 616 from SOC_NAVI. The optimum route is determined by comparing the received information with the route information described above. The output selector SEL_O selects the output port 615 based on this determination.

  As described above, FIG. 6 illustrates the configuration example of the request processing circuit RTCTL_REQ, but the response processing circuit RTCTL_RES in FIGS. 5A and 5B also has the same configuration. However, in the case of the response processing circuit RTCTL_RES, the local buffer management unit BUF_CTL receives the transfer response signal (RES) and outputs the transfer response permission signal (R_GNT). Further, response data (R_DAT) and response opcode (R_OPC) are input to the input port 610 instead of data (DAT) and opcode (OPC). Note that the clock control circuit CK_CTL can be provided separately for RTCTL_REQ and RTCTL_RES, or in some cases, can be provided in common.

  FIGS. 7A and 7B are schematic diagrams showing an example of the structure of the route table held in the route information holding / calculating circuit RTCAL in each different router circuit in the request processing circuit RTCTL_REQ in FIG. . FIG. 7A is a path table provided in the request processing circuit RTCTL_REQ0 in the router circuit R0, and FIG. 7B is a path table provided in the request processing circuit (RTCTL_REQ1) in the router circuit R1. This route table is an example of the semiconductor device SOC of FIG.

  As shown in FIG. 7A, the route information holding / calculating circuit RTCAL in the router circuit R0 has a route from each router REG0 to the other router circuits R1 to R7 in each register REG. ing. For example, the register REG01_xx holds a path from R0 to R1, and similarly, the register REG06_xx holds a path from R0 to R6. Further, for example, in the register REG06_xx, the register REG06_RT1 in which “xx” is RT1 holds the first candidate path, and the register REG06_RT2 that is RT2 holds the second candidate path, and RT3 and Register REG06_RT3 holds the third candidate path.

  Further, each of the registers REG06_RT1 to REG06_RT3 holds the number of times the router circuit passes through to the destination (that is, the path length). Here, the path length becomes shorter in the order of the first path ≦ the second path ≦ the third path. Further, in this route table, it is assumed that three or less candidates are provided for a route to a certain destination, and at least the first route and the second route have different router circuits that pass first. The router circuit that passes through first is, for example, R2 in REG06_RT1, and R1 in REG06_RT2. Further, as shown in FIG. 7B, the route information holding / calculating circuit RTCAL in the router circuit R1 is also started from the router circuit R1 as in the case of FIG. Each register REG has a path to reach R2 to R7. Although not shown, the RTCALs in the router circuits R2 to R7 are similarly provided with their own registers in their respective registers.

  Here, as shown in FIGS. 7A and 7B, the path information held in the storage unit (for example, register) of the path information holding / calculating circuit RTCAL is determined in advance when the semiconductor device SOC is designed. be able to. As will be described later, the semiconductor device according to the first embodiment employs a dynamic routing method that switches a route according to a situation, but a route that reliably reaches a destination can be determined in advance at the design stage. As in the case of the Internet shown in FIG. 2, incorrect route information is never announced.

  FIG. 8 is a schematic diagram showing an example of a management table held by the router management unit SOC_NAVI in the semiconductor device of FIG. As shown in FIG. 8, the SOC_NAVI includes, for example, registers R0_CTRL to R7_CTRL corresponding to the router circuits R0 to R7, and each of the R0 to R7 is “empty” or Monitor "full" and clock on or off. As described in FIG. 6, this is realized by receiving the buffer status signal 617 and the clock-off signal 612a from the local buffer management unit BUF_CTL and the clock control circuit CK_CTL in each router circuit. FIG. 8 shows an example in which R4 is in the “full” state and R2 is clock off. Here, although not particularly limited, the SOC-NAVI is the same as the clock-on state shown in FIG. 6 with respect to the router circuit in which the clock is off if, for example, more than half of the router circuits in FIG. The signal 612b is issued and an instruction is given to resume the supply of the operation clock.

  Further, as described in FIG. 6, the route information holding / calculating circuit RTCAL of each router circuit can obtain the information of the management table as shown in FIG. 8 in real time via the other router monitoring signal 616. It has become. The RTCAL sequentially determines whether each route as shown in FIGS. 7A and 7B is valid or invalid in real time with reference to the information in the management table. Therefore, instead of selecting a route based on the past access frequency as in the above-mentioned Patent Document 1, it is possible to select a route by judging the status of each router circuit in real time. Therefore, it is possible to select an optimum route that always has a low latency and a high throughput.

  FIG. 9 is a flowchart showing an example of a route search method performed by the route information holding / calculating circuit RTCAL in the request processing circuit RTCTL_REQ of FIG. When the route search is started (901), RTCAL first refers to the route table shown in FIG. 7 and the destination ID (DST_ID) included in the packet data to be transferred in 902 and 903. A determination is made for the first route until the router circuit corresponding to the component IP is reached. In 902, the number of times the first route passes through the router is set to n, and in 903, it is determined whether the next router circuit is valid (“empty” and clock-on) for this first route. If it is valid, the route search ends (910). On the other hand, if it is invalid (“full” or clock off), the process proceeds to 904.

  In 904, the RTCAL determines whether there is a second route with reference to the route table shown in FIG. If there is no second path, the process returns to 902, and the first path is determined again after one cycle. On the other hand, if there is a second route, m is the number of times the second route passes through the router (905), and all the router circuits up to (mn + 1) ahead are valid for this second route. It is determined whether or not there is (906). If it is valid, the route search ends (910). On the other hand, if at least one of them is invalid, the process proceeds to 907.

  In 907, the RTCAL determines whether there is a third route with reference to the route table shown in FIG. If there is no third route, the process returns to 902, and the first route is determined again after one cycle. On the other hand, if there is a third route, j is the number of times the third route passes through the router (908), and all the router circuits up to (j−n + 1) ahead are valid for this third route. It is determined whether or not there is (909). If it is valid, the route search ends (910). On the other hand, when at least one of them is invalid, the process returns to 902, and the first path is determined again after one cycle. When the route search ends (910), RTCAL issues an instruction to the output selector SEL_O so that the packet data is output toward the route.

  The flow in FIG. 9 will be described by way of a specific example. For example, when the router circuit R0 in FIG. 1 receives packet data with IP6 (R6) as a request transfer destination, RTCAL is registered in the register REG06_RT1 in FIG. And n = 2 and determine whether the next router circuit R2 is valid. If it is valid, the route search ends. That is, as shown in FIG. 10, a route of R0 → R2 → R6 is selected, and packet data is output toward R2 in the cycle.

  On the other hand, if R2 is invalid, RTCAL determines whether the register REG06_RT2 exists in the route table of FIG. 7A, and if it exists, determines this. In FIG. 7A, since REG06_RT2 exists, RTCAL determines m = 3 from the information of REG06_RT2, and determines whether the first router circuit R1 and the second router circuit R3 are valid. If it is valid, the route search ends. That is, as shown in FIG. 11, a route of R0 → R1 → R3 → R6 is selected, and packet data is output toward R1 in the cycle. On the other hand, if R1 or R3 is invalid, RTCAL similarly determines the register REG06_RT3, sets j = 3, and determines whether the first router circuit R4 and the second router circuit R5 are valid. Determine.

  FIG. 12 shows an operation example for each clock cycle in the semiconductor device of FIG. 1, and shows state transitions of the input buffer BUF_I and the output buffer BUF_O of each router circuit. For example, it is assumed that at time (clock cycle) t = T0, the router circuit R0 receives a data transfer request signal (REQ) for one cycle issued from IP0 to IP5. In this case, R0 latches the packet data (shown as PD0 on FIG. 12) from IP0 in the input buffer BUF_I. Furthermore, it is assumed that at t = T0, the router circuit R4 receives a data transfer request signal (REQ) for two cycles issued from IP4 to IP7. In this case, R4 latches the packet data (shown as PD4 on FIG. 12) from IP4 in the input buffer BUF_I.

  Next, at t = T1, R0 latches the packet data PD0 with BUF_O and performs route determination for this. On the other hand, R4 latches the packet data PD4 in the first cycle with BUF_O and determines the path for this, and latches the packet data PD4 in the second cycle with BUF_I. Here, FIG. 16 is an explanatory diagram showing an example of a transition state of the input buffer BUF_I and the output buffer BUF_O in the request processing circuit RTCTL_REQ of FIG.

  In FIG. 16, BUF_I latches packet data PD [1] at time (clock cycle) t = T1 ′ and outputs it to BUF_O, and latches packet data PD [2] of the next cycle at t = T2 ′. Output to BUF_O. On the other hand, BUF_O latches PD [1] at t = T2 ′ and outputs it to the output selector SEL_O in FIG. 6, and latches PD [2] at t = T3 ′ and outputs it to SEL_O. In this case, at t = T1 ′, the packet data of BUF_I can be surely swept out to BUF_O in the next cycle, and since BUF_I can be input, it becomes “empty”. At t = T3 ′, BUF_I can be input Therefore, it is “empty”. On the other hand, at t = T2 ', BUF_I and BUF_O are buried, and the packet data of BUF_O is not necessarily swept out in the next cycle, and is “full”. Accordingly, in FIG. 12, R4 becomes “full” at t = T1.

  FIG. 13 is an explanatory diagram showing a state of the semiconductor device of FIG. 1 at t = T1 of FIG. In FIG. 13, in addition to the router circuit R4 being “full” as described above, the router circuit R2 is assumed to be clocked off. In this case, R0 cannot select the route that passes through R4 that is the first route (shortest route) nor the route that passes through R2 that is the second route in the above-described route search. The route R1 → R3 → R6 → R5 is selected, and the packet data PD0 is output to R1. On the other hand, R4 selects the route of R5 → R7 which is the first route in the route search described above, and outputs the packet data PD4 of the first cycle toward R5.

  Next, at t = T2, R1 latches the packet data PD0 with BUF_I. R4 latches packet data PD4 in the second cycle with BUF_O and outputs PD4 in the second cycle toward R5. R5 latches the packet data PD4 in the first cycle with BUF_I. Subsequently, at t = T3, R1 latches the packet data PD0 with BUF_O and determines the path for this. R5 latches the packet data PD4 in the first cycle with BUF_O, determines the path for this, and latches the packet data PD4 in the second cycle with BUF_I. Accordingly, R5 becomes “full”.

  FIG. 14 is an explanatory diagram showing a state of the semiconductor device of FIG. 1 at t = T3 of FIG. In FIG. 14, R5 is “full” and R2 is clock-off as described above. Here, in the route table of R1, it is assumed that the first route (shortest route) toward IP5 (R5) is R3 → R4 → R5, and R1 selects this first route for the route search described above. Therefore, the packet data PD0 is output to R3. On the other hand, R5 selects the route of R7 which becomes the first route in the above route determination, and outputs the packet data PD4 of the first cycle toward R7.

  Subsequently, at t = T4, R3 latches the packet data PD0 with BUF_I. R5 latches the packet data PD4 of the second cycle with BUF_O and outputs the PD4 of the second cycle toward R7. R7 latches the packet data PD4 in the first cycle with BUF_I. Next, at t = T5, R3 latches the packet data PD0 with BUF_O and determines the path for this. R7 latches packet data PD4 in the first cycle with BUF_O, and latches packet data PD4 in the second cycle with BUF_I. Accordingly, R7 becomes “full”.

  FIG. 15 is an explanatory diagram showing a state of the semiconductor device of FIG. 1 at t = T5 of FIG. In FIG. 15, R7 is “full” and R2 is clock-off as described above. Here, in the route table of R3, it is assumed that the first route (shortest route) toward IP5 (R5) is R4 → R5, and R3 can select this first route in the route search described above. , R4, packet data PD0 is output. On the other hand, R7 outputs the packet data PD4 in the first cycle latched by BUF_O to IP7. Hereinafter, although detailed description is omitted, as shown in FIG. 12, the packet data is sequentially transferred, and the request from IP0 to IP5 and the request from IP4 to IP7 are completed.

  In FIG. 12, for ease of explanation, after the local buffer management unit BUF_CTL shown in FIG. 6 detects “full”, the SOC_NAVI is notified via the buffer status signal 617, and the other router monitoring signal is sent from the SOC_NAVI. The clock latency until notification to another router circuit via 616 is omitted. If multiple cycles are required for this, the router circuit (referred to as [1]) actually outputs packet data to the router circuit (referred to as [1]) that is already “full”. I am concerned about such a situation. However, in this case, since the router circuit [2] waits without obtaining the transfer permission signal (GNT) from the router circuit [1], this causes a time loss. It does not happen that the packet data of [2] is lost. The same applies to a case where transfer request signals (REQ) from a plurality of router circuits compete with one router circuit.

  As described above, by using the semiconductor device provided with the network on chip (NoC) according to the first embodiment, it is possible to typically determine the optimum route via the router circuit in real time. It is possible to reduce the latency or improve the throughput. In the description of FIGS. 7 to 16 described above, various explanations have been made assuming the signal path on the request side. However, as described in FIG. 5, the signal path on the response side is additionally provided independently. In the configuration, the operations described with reference to FIGS. 7 to 16 are performed in parallel in the signal path on the response side independently of the request side.

(Embodiment 2)
In the second embodiment, an operation example in which the semiconductor device described in the first embodiment is used and packet data is transferred using priority (PRI) included in the packet data (interface signal) will be described. The priority (PRI) is, for example, a signal that notifies the router circuit that it is urgent when it is desired to perform transfer within a certain limited latency.

  FIG. 17 is a schematic diagram of a portion of the semiconductor device of FIG. 1 extracted from the semiconductor device according to the second embodiment of the present invention. In FIG. 17, the router circuit R0 that has received the transfer request signal (REQ) from the master component IP0 in the previous cycle and the master component IP1 simultaneously transfer the transfer request signal (REQ) to the router circuit R1 in a certain cycle. An example of issuing is shown. The PRI included in the packet data PD0 from IP0 is “7”, and the PRI included in the packet data PD1 from IP1 is “5”. Here, it is assumed that the higher the PRI number, the higher the priority.

  In this case, since R1 cannot accept these two transfer request signals (REQ) at the same time, the local buffer management unit BUF_CTL shown in FIG. 6 compares the sizes of both PRIs using the arbitration circuit ARB. As a result, the transfer permission signal (GNT) is transmitted to R0 by adopting PD0. At the same time, it instructs the input selector SEL_I to transfer PD0 to the input buffer BUF_I. On the other hand, since the transfer permission signal (GNT) is not obtained, IP1 waits for several cycles until it is obtained.

  If IP1 is a router circuit ([3]) that receives a transfer request from a certain component, and there are a plurality of paths, transfer to this router circuit [3] in a certain cycle. When the permission signal (GNT) is not obtained, it is preferable to provide a function for performing a route search again as shown in FIG. 9 in the next cycle. Accordingly, in FIG. 17, for example, if the router circuit R1 maintains the “full” state for the time being with the transfer of PD0, this route can be avoided, and for the router circuit [3], When the route via R1 is not the first route (shortest route), there is a possibility that the route can be changed to the shortest route. That is, a reduction in latency and an improvement in throughput can be expected.

  As described above, by using the semiconductor device of the second embodiment, in addition to the various effects described in the first embodiment, typically, urgent information can be transferred quickly, and the semiconductor device as a whole can be transferred. Processing efficiency can be increased.

(Embodiment 3)
In the third embodiment, an example of a route search method different from that in FIG. 9 described in the first embodiment will be described. The route search method in FIG. 9 determines whether or not to select a route to be determined based on the difference value between the route length of the route and the route length of the first route (shortest route). In principle, the determination was made from the viewpoint of proceeding ahead of the first route. That is, for example, if the route length of the first route is 3 and the route length of the second route is 4, even if the first route cannot pass, if the router circuit is advanced by 2 in the second route, The remaining path length is 2. On the other hand, in the third embodiment, the determination is made based on the difference value of the path length as in the case of FIG. 9, and the determination is made from the viewpoint of proceeding in the same way as the first path in principle. That is, for example, if the route length of the first route is 3 and the route length of the second route is 4, even if the first route cannot pass, the router circuit can be advanced by one on the second route. The remaining path length is 3.

  FIG. 18 is a flowchart showing an example of a route search method performed by the route information holding / calculating circuit RTCAL of the request processing circuit RTCTL_REQ in FIG. 6 in the semiconductor device according to the third embodiment of the present invention. When the route search is started (1801), RTCAL first refers to the route table shown in FIG. 7 and the destination ID (DST_ID) included in the packet data to be transferred in 1802, 1803, and 1810a. Then, a determination is made for the first route until the router circuit corresponding to the component IP is reached. In 1802, the number of times that the first route passes through the router is n, and in 1803, it is determined whether the next router circuit is valid (“empty” and clock-on) for this first route. If it is valid, the process proceeds to 1810a self-loop determination (details will be described later with reference to FIG. 19). If this is passed, the route search ends (1811). On the other hand, if it is invalid (“full” or clock off), or if the self-loop determination of 1810a fails, the process proceeds to 1804.

  In step 1804, the RTCAL determines whether there is a second route with reference to the route table shown in FIG. If there is no second path, the process returns to 1802, and the first path is determined again after one cycle. On the other hand, if there is a second route, the number of times that the second route passes through the router is set to m (1805). It is determined whether it is valid. If m> n, it is determined whether all router circuits up to (mn) are valid (1806). If it is valid, the process shifts to the self-loop determination of 1810b. If this is passed, the route search ends (1811). On the other hand, if any one of them is invalid, or if the self-loop determination of 1810b fails, the process proceeds to 1807.

  In 1807, the RTCAL determines whether there is a third route with reference to the route table shown in FIG. If there is no third route, the process returns to 1802, and the first route is determined again after one cycle. On the other hand, if there is a third route, j is the number of times the third route passes through the router (1808). It is determined whether it is valid. If j> n, it is determined whether all the router circuits up to (jn) ahead are valid (1809). If it is valid, the process shifts to the self-loop determination of 1810c, and when this is passed, the route search ends (1811). On the other hand, if any one of them is invalid, or if the self-loop determination of 1810c is unsuccessful, the process returns to 1802, and the determination for the first path is performed again after one cycle. When the route search ends (1811), RTCAL issues an instruction to the output selector SEL_O so that the packet data is output toward the route.

  The flow of FIG. 18 will be described using a specific example. For example, as shown in FIG. 20, when the router circuit R0 receives packet data having IP4 (R4) as a request transfer destination, first, the path length is set to 1. The shortest path (R0 → R4) is determined, n = 1 is set, and it is determined whether the next router circuit R4 is valid. If it is valid and the self-loop determination is also passed, the route search ends, and packet data is output toward R4 in this cycle. On the other hand, if R4 is invalid or the self-loop determination is unsuccessful, for example, as shown in FIG. 21, RTCAL determines the second route. Here, it is assumed that the second route is a route of R0 → R1 → R3 → R4 having a route length of 3, and if m = 3, the first router circuit R1 and the second router circuit R3 are Determine if it is valid. If it is valid and the self-loop determination is also passed, the route search ends, and packet data is output toward R1 in the cycle.

  FIG. 19 is a flowchart showing an example of the self-loop determination processing 1810a to 1810c in the flow of FIG. In FIG. 19, when the self-loop determination is started (1901), the RTCAL first refers to the source ID (SRC_ID) included in the packet data to be transferred in 1902 and becomes the evaluation target in FIG. It is determined whether a router circuit corresponding to the component IP having the SRC_ID is not included on the existing route. If it is included, a self-loop is performed, so that the self-loop determination fails (1905), and if it is not included, the process proceeds to 1903. In 1903, the middle ID (MID_ID) included in the packet data to be transferred is referred to, and it is determined whether or not a router circuit having this MID_ID is included in the path to be evaluated in FIG. . If it is included, the route that has passed is returned, so the self-loop determination fails (1905), and if it is not included, the self-loop determination passes (1904).

  Compared with the route search flow of FIG. 9, the route search flow of FIG. 18 described above is more likely to enter a self-loop, although the choices of routes that can be actually taken are widened. That is, for example, as shown in FIG. 21, in the cycle in which the packet data is transferred to R1, the remaining path length is temporarily increased (the path is moved away). Then, after making a detour, the possibility of returning to the same route again cannot be denied. In particular, when there are a large number of component IPs in the semiconductor device SOC and their connection paths are complicated, the possibility of this self-loop increases. Therefore, in the flow of FIG. 18, the possibility of self-loop is reduced by performing self-loop determination as shown in FIG. 19, and in the flow of FIG. 9 described above, the possibility of self-loop is reduced in terms of the algorithm. is doing. Furthermore, in the route table of FIG. 7 described above, the number of route options for each destination is set to 3 or less in the order of shorter route length, thereby reducing the possibility of self-looping in terms of the number of options. ing.

  As described above, by using the semiconductor device according to the third embodiment, in addition to the various effects described in the first embodiment, typically, the width of a path that can be practically selected can be increased.

(Embodiment 4)
In this fourth embodiment, an example of a semiconductor device in which the semiconductor devices described in the first to third embodiments are three-dimensionally stacked will be described. FIG. 22 is a schematic diagram showing an example of the configuration of the semiconductor device according to the third embodiment of the present invention. The semiconductor device shown in FIG. 22 is configured by stacking three layers of the semiconductor device SOC shown in the first embodiment or the second embodiment. The lowest layer is a semiconductor device SOC1 having a logic function, the middle layer is a semiconductor device SOC2 having a first memory function (for example, DRAM), and the uppermost layer is a second memory function (for example, DRAM). The semiconductor device SOC3 is provided with an SRAM.

  FIG. 23 is a diagram showing a more detailed configuration example of FIG. Here, an example is shown in which transfer is performed from the semiconductor device SOC1 in the lowest layer to the semiconductor device SOC2 in the middle layer. The SOC 1 includes a plurality of components (for example, arithmetic units) and router circuits corresponding thereto, and similarly, the SOC 2 includes a plurality of components (memory units) and router circuits corresponding thereto. A part (three in this case) of router circuits R10, R11, and R12 in the plurality of router circuits in the SOC1 is a part (three in this case) in the plurality of router circuits in the SOC2, respectively. Are three-dimensionally connected to the router circuits R20, R21, and R22.

  The SOC1, SOC2 and SOC3 are respectively provided with router management units SOC_NAVI1, SOC_NAVI2 and SOC_NAVI3, which are three-dimensionally connected to each other. For example, SOC_NAVI1 monitors the status of each router circuit in the SOC1 as shown in FIG. 8, and similarly, SOC_NAVI2 monitors the status of each router circuit in the SOC2. Furthermore, for example, SOC_NAVI1 can also monitor the status of R20, R21, and R22 in SOC2 by communicating with SOC_NAVI2. In addition, each router circuit in the SOC 1 includes R20, R21, and R22 as destinations in its route table as shown in FIG.

  Therefore, as shown in FIG. 23, for example, when it is desired to transfer the packet data PD from the router circuit R13 in the SOC1 to the SOC2, the R13 refers to its own route table and considers the status of each router circuit from the SOC_NAVI1. Thus, the optimum route can be selected. In other words, in addition to the router circuits in the SOC1, the status of R20, R21, and R22 is also taken into consideration, the packet data PD13a is transferred from R10 to R20, the packet data PD13b is transferred from R11 to R21, and R12 The packet data PD13c can be transferred from R to R22. As a result, the cost can be reduced compared to the case where all router circuits are connected between the respective layers, and the path length can be shortened and the doorway can be expanded as compared with the case where any one of the circuits is connected. In addition, it is possible to reduce latency and improve throughput in communication between semiconductor chips at a low cost.

  As described above, by using the semiconductor device of the fourth embodiment, in addition to the various effects described in the first to third embodiments, typically, a high-performance semiconductor device can be realized at low cost.

  As mentioned above, although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  The semiconductor device according to the present embodiment is useful when applied to a semiconductor device provided with a NoC (network on chip), and is not limited to a single semiconductor chip but a semiconductor device including a plurality of semiconductor chips. Is also applicable.

1 is a block diagram showing an example of the configuration of a semiconductor device according to a first embodiment of the present invention. It is a diagram showing a route search method generally known in the Internet as a prior art and its advantages and disadvantages. FIG. 2 is an explanatory diagram illustrating an example of a basic structure of packet data (interface signal) passing through each router circuit in the semiconductor device of FIG. 1. FIG. 1 schematically shows an example of a communication method between a master component and a slave component in the semiconductor device of FIG. 1, wherein (a) is a schematic diagram when a transfer request is made, and (b) is a transfer request of (a). It is a schematic diagram at the time of responding with respect to it. FIG. 1 shows a schematic configuration example of each router circuit in the semiconductor device of FIG. 1, (a) is a schematic diagram of a router circuit corresponding to a component having a master function and a slave function, and (b) is provided with a slave function. FIG. 6 is a schematic diagram of a router circuit corresponding to the components. FIG. 6 is a block diagram illustrating a detailed configuration example of the request processing circuit in the router circuit of FIG. 5. (A), (b) is the schematic which showed the structural example of the path | route table which the path | route information holding | maintenance / calculation circuit in a different router circuit respectively hold | maintains in the request processing circuit of FIG. FIG. 2 is a schematic diagram illustrating an example of a management table held by the router management unit in the semiconductor device of FIG. 1. FIG. 7 is a flowchart showing an example of a route search method performed by the route information holding / calculating circuit in the request processing circuit of FIG. 6. FIG. 10 is a supplementary diagram of FIG. 9. FIG. 10 is another supplementary diagram of FIG. 9. In the semiconductor device of FIG. 1, an operation example for each clock cycle is shown, and state transitions of the input buffer and the output buffer of each router circuit are shown. FIG. 13 is an explanatory diagram showing a state of the semiconductor device of FIG. 1 at T1 of FIG. It is explanatory drawing which shows the condition of the semiconductor device of FIG. 1 in T3 of FIG. It is explanatory drawing which shows the condition of the semiconductor device of FIG. 1 in T5 of FIG. FIG. 7 is an explanatory diagram illustrating an example of transition states of an input buffer and an output buffer in the request processing circuit of FIG. 6. FIG. 5 is a schematic diagram illustrating a part of the semiconductor device of FIG. 1 in the semiconductor device according to the second embodiment of the present invention. FIG. 7 is a flowchart showing an example of a route search method performed by the route information holding / calculating circuit of the request processing circuit of FIG. 6 in the semiconductor device according to the third embodiment of the present invention. FIG. 19 is a flowchart showing an example of the self-loop determination process in the flow of FIG. 18. It is a supplementary figure of FIG. FIG. 19 is another supplementary diagram of FIG. 18. FIG. 10 is a schematic diagram showing an example of the configuration of a semiconductor device according to a fourth embodiment of the present invention. It is the figure which showed the more detailed structural example of FIG.

Explanation of symbols

610 Input port 612a Clock off signal 612b Clock on signal 613 Standby instruction signal 615 Output port 616 Other router monitoring signal 617 Buffer status signal ARB Arbitration circuit BUF buffer BUF_CTL Local buffer management unit CK_CTL Clock control circuit DAT data DST_ID Destination ID
EXT extension header GNT transfer permission signal HD header IP component MID_ID Middle ID
OPC opcode PD packet data PKT_ID Packet ID
PKT_SIZE packet size PRI priority R router circuit R_DAT response data R_GNT transfer response permission signal R_OPC response opcode REQ transfer request signal RES transfer response signal RTCAL path information holding / calculating circuit RTCTL_REQ request processing circuit RTCTL_RES response processing circuit SEL selector SOC semiconductor control SOC selector Unit SRC_ID Source ID

Claims (13)

Realized with one semiconductor chip,
A plurality of router circuits including a first router circuit and a second router circuit;
A first component connected to the first router circuit for performing predetermined processing;
A second component connected to the second router circuit for performing predetermined processing;
A first wiring path connecting between the first router circuit and the second router circuit via a part of the plurality of router circuits;
A second wiring path connecting the first router circuit and the second router circuit via another part of the plurality of router circuits;
A router management unit connected to the plurality of router circuits, and monitoring a valid / invalid state of the plurality of router circuits for each instruction cycle;
The first router circuit obtains valid / invalid states of the plurality of router circuits from the router management unit when receiving an instruction from the first component to the second component, and based on the obtained status, A semiconductor device comprising: selecting a first wiring path or the second wiring path, and transferring a signal group accompanying the command to the selected wiring path. The semiconductor device according to claim 1,
Each of the plurality of router circuits includes a buffer circuit for temporarily holding a signal group accompanying the instruction,
The router management unit holds a buffer status signal indicating whether each of the buffer circuits in the plurality of router circuits is available or not in the first storage unit as the valid / invalid status of the plurality of router circuits. A semiconductor device characterized by the above. The semiconductor device according to claim 2,
Each of the plurality of router circuits further includes a clock control unit that supplies a clock signal to the buffer circuit for each instruction cycle,
The clock control unit includes a first function for stopping the supply of the clock signal when a predetermined condition is satisfied,
The router management unit, as a valid / invalid state of the plurality of router circuits, further includes a clock status signal indicating whether or not the supply of the clock signal is stopped by the first function in the plurality of router circuits. The semiconductor device is held in the first storage unit. The semiconductor device according to claim 3.
The router management unit determines an empty ratio of the buffer circuit in the plurality of router circuits based on the buffer status signal, and accordingly, the clock signal toward the first function in the plurality of router circuits. A semiconductor device comprising a second function of generating an output for resuming the supply of. The semiconductor device according to claim 1,
Each of the plurality of router circuits starts with a router circuit other than itself as a destination and sets a single or a plurality of wiring routes for each destination until reaching the destination determined in advance in the design stage. 2. A semiconductor device which is held in a storage unit. The semiconductor device according to claim 5.
The second storage unit holds the number of router circuits through which the route reaches the destination as a route length for each wiring route along with one or a plurality of wiring routes for each destination. A semiconductor device characterized by the above. The semiconductor device according to claim 6.
When the path length of the first wiring path is shorter than the path length of the second wiring path,
The first router circuit selects the first wiring path when the router circuit that passes first on the first wiring path is valid, and the router that passes first on the first wiring path. When the circuit is invalid, a number of router circuits that sequentially pass on the second wiring path and reflect the difference value between the path length of the first wiring path and the path length of the second wiring path The semiconductor device is characterized in that the second wiring path is selected when all of the above are valid. The semiconductor device according to claim 6.
The second storage unit holds, for each destination, a number of routes that are equal to or less than a predetermined maximum value, and the number of routes that are equal to or less than the maximum value is determined in the order of shorter route length. A semiconductor device characterized by that. The semiconductor device according to claim 1,
Each of the plurality of router circuits includes an arbitration circuit that determines which is preferentially received when the command is received from two or more router circuits other than itself in the same command cycle. Semiconductor device. The semiconductor device according to claim 1,
A first semiconductor chip comprising the semiconductor chip;
A second semiconductor chip comprising the semiconductor chip and stacked and mounted on the first semiconductor chip;
At least one of the plurality of router circuits included in the first semiconductor chip is connected to at least one of the plurality of router circuits included in the second semiconductor chip;
The first router management unit serving as the router management unit included in the first semiconductor chip is connected to the second router management unit serving as the router management unit included in the second semiconductor chip, and the second router A semiconductor device, wherein a valid / invalid state of at least one of the plurality of router circuits included in the second semiconductor chip is monitored via a management unit. A first router circuit and a second router circuit;
N (n ≧ 1) router circuits provided on a first wiring path connecting the first router circuit and the second router circuit;
M (m ≧ n) router circuits provided on a second wiring path connecting the first router circuit and the second router circuit,
When transferring data from the first router circuit to the second router circuit, the first router circuit is effective when the router circuit that passes first on the first wiring path is effective. When the first wiring path is selected and the router circuit that first passes on the first wiring path is invalid, the number reflecting the value of (mn) that sequentially passes on the second wiring path The second wiring path is selected when all of the router circuits are effective. The semiconductor device according to claim 11.
When the first router circuit that passes through the first wiring path is invalid, all the router circuits that pass through the (m−n + 1) th path on the second wiring path are valid. In some cases, the second wiring path is selected. The semiconductor device according to claim 11.
The first router circuit passes first on the second wiring path when (mn) = 1 when the first router circuit passing on the first wiring path is invalid. When the router circuit is valid, the second wiring path is selected. When (mn)> 1, all the router circuits passing through the second wiring path up to (mn) are valid. In this case, the second wiring path is selected.

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