JP2015191393A - timing constraint setting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a timing constraint setting method capable of reducing the amount of low threshold cells used.SOLUTION: The timing constraint setting method of an embodiment includes: performing provisional placement using only the high threshold cells of a cell library 12 on the basis of the clock skew distribution set forth in an inputted timing constraint 11, with a value derived by subtracting an improvement in speed due to low threshold cells as a margin 13 from an original clock cycle being a layout clock cycle (step S1); verifying the timing of a signal propagation path on the basis of the result of provisional placement (step S2); extracting a path for which timing violation was detected by the timing verification (step S3); analyzing details of delay propagation relating to the detected path (step S4); and calculating a clock skew amount distributed to a signal propagation path relating to the detected path and updating the timing constraint 11 on the basis of the analysis result and outputting a timing constraint 21 for definite placement (step S5).

Description

  Embodiments described herein relate generally to a timing constraint setting method.

  In the layout process of a semiconductor integrated circuit, automatic placement of cells, generation of a clock tree, and automatic wiring are executed based on timing constraints estimated at the logic synthesis stage. At this time, if the layout satisfying the given timing constraint is performed, the timing violation does not occur in the timing verification after the layout.

  However, since the accuracy of estimation at the logic synthesis stage is not high, timing violation may occur in timing verification after layout. When a timing violation occurs, as one of countermeasures, a high threshold cell is replaced with a low threshold cell. Since the low threshold cell is composed of a low threshold transistor, the operation speed of the cell is improved.

  However, since a low threshold transistor has a large leakage current, when a large number of low threshold cells are used, there is a problem that the current consumption of the semiconductor integrated circuit increases.

JP 2003-16130 A

  The problem to be solved by the present invention is to provide a timing constraint setting method capable of reducing the amount of low threshold cell usage.

  In the timing constraint setting method according to the embodiment, the value obtained by subtracting from the original clock cycle with the speed improvement due to the low threshold cell as a margin is used as the clock cycle for layout, and the high threshold is set based on the clock skew distribution described in the input timing constraint. Temporary placement is performed using only cells. Based on the result of the temporary arrangement, the timing of the signal propagation path is verified. A path where a timing violation is detected by the timing verification is extracted. The details of delay propagation related to the extracted path are analyzed. Based on the result of the analysis, the amount of clock skew to be distributed to the signal propagation path related to the extracted path is calculated, the timing constraint is updated, and the actual placement timing constraint is output.

5 is a flowchart illustrating an example of a processing procedure of a timing constraint setting method according to the first embodiment. The figure for demonstrating the margin in the timing constraint setting method of 1st Embodiment. FIG. 5 is a diagram illustrating an example of clock skew adjustment in the timing constraint setting method according to the first embodiment. The figure for demonstrating the timing constraint setting method of 2nd Embodiment. The figure for demonstrating the timing constraint setting method of 2nd Embodiment. The figure for demonstrating the timing constraint setting method of 3rd Embodiment. The figure for demonstrating the timing constraint setting method of 4th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

(First embodiment)
The outline of the timing constraint setting method of this embodiment will be described. First, for example, based on the timing constraint estimated in the logic synthesis stage, provisional placement is performed only with high threshold cells, and the timing constraint violation is found from the provisional placement result. The generated signal propagation path is extracted. Thereafter, the clock skew amount distributed to the signal propagation path is calculated so as to eliminate the violation as much as possible, the timing constraint is updated, and the timing constraint for the actual placement is generated.

  Details of the timing constraint setting method of the present embodiment will be described with reference to FIGS. FIG. 1 is a flowchart showing an example of a processing procedure of the timing constraint setting method of the present embodiment, and FIG. 2 is a diagram for explaining a margin used in the temporary arrangement of the present embodiment.

  In the flowchart shown in FIG. 1, first, provisional placement is performed using only the high threshold cells among the cells registered in the cell library 12 based on the clock skew distribution described in the input timing constraint 11 ( Step S1).

  At this time, in this embodiment, the speed improvement expected when the high threshold cell is replaced with the low threshold cell is calculated in advance as the margin 13, and a value obtained by subtracting the margin 13 from the original clock cycle is used as the layout cycle. Used as

  FIG. 2 shows an example of a method for calculating the margin 13.

As shown in FIG. 2A, when the delay time between the input and output of the high threshold cell HTC1 is dT1, and the delay time between the input and output of the low threshold cell LTC1 is dT2, the high threshold cell HTC1 is changed to the low threshold cell LTC1. The speed improvement rate SP at the time of replacement is
SP = (dT1-dT2) / dT1
It is expressed.

For example, when dT1 = 100 ps and dT2 = 80 ps,
SP = (100-80) /100=20/100=0.2
That is, the speed improvement rate SP is 20%.

Therefore, in this embodiment, a value obtained by multiplying the original clock cycle T0 of the semiconductor integrated circuit by the speed improvement rate SP is calculated as the margin 13. If the value of this margin 13 is M,
M = SP × T0
It is expressed.

  In the temporary arrangement in step S1, a value obtained by subtracting the margin 13 from the original clock period T0 is used as the layout period T.

FIG. 2B shows the relationship between the original clock period T0 and the layout period T. The layout cycle T has a margin 13 value of M,
T = T0-M
It is expressed.

  That is, for the layout apparatus that performs the placement process, the provisional placement in step S1 in which only the high threshold cell is used is the placement process under the strictest condition in terms of timing. Therefore, the layout apparatus performs a cell arrangement optimization process that maximizes the driving capability of the high threshold cell.

  Returning to the flow of FIG. 1, next, the timing of the signal propagation path is verified based on the result of the temporary arrangement in step S1 (step S2), and the path where the timing violation is detected is extracted (step S3).

  As described above, in the temporary placement in step S1, placement is performed so as to maximize the drive capability of the high threshold cell. Therefore, the route extracted in step S3 is a route that cannot satisfy the timing specification only by the high threshold cell. In the present embodiment, all such routes can be extracted by one temporary arrangement.

  Next, details of delay propagation related to the path extracted in step S3 are analyzed (step S4).

  As described above, the route extracted in step S3 is a route that cannot satisfy the timing specification only with the high threshold cell, but there may be a route with sufficient timing before and after the route. In that case, the timing violation can be eliminated or the amount of timing violation can be reduced by adjusting the clock timing including the paths before and after the path where the timing violation is detected.

  Therefore, in step S4, the propagation state of the delay of the route extracted in step S3 and the route before and after the route is analyzed in detail.

  Next, based on the result of the analysis in step S4, the clock skew amount to be distributed to the signal propagation path related to the path extracted in step S3 is calculated, the timing constraint 12 is updated, and the actual placement timing constraint 21 is obtained. Is output (step S5).

  The actual placement timing constraint 21 describes a timing constraint in which the clock skew amount of the path where the timing violation is detected in the temporary placement is adjusted. Therefore, by using the main arrangement timing constraint 21, the occurrence of timing violations in the main arrangement can be reduced.

  Next, taking the circuit shown in FIG. 3A as an example, an example of clock skew adjustment by the timing constraint setting method of this embodiment will be described.

  In the circuit shown in FIG. 3A, a cell CT1 such as a logic circuit or a memory is connected between the register cell REG1 and the register cell REG2 to form a signal propagation path path1, and the register cell REG2 and the register cell REG3 Between these, a cell CT2 such as a logic circuit or a memory is connected to form a signal propagation path path2.

  Clock signals CK1, CK2, and CK3 are input to the register cells REG1, REG2, and REG3, respectively. Here, it is assumed that clock skews skew1, skew2, and skew3 are set as timing constraints 11 for the clock signals CK1, CK2, and CK3, respectively.

  FIGS. 3B to 3D show examples of clock skew adjustment when the flow of FIG. 1 is executed on the circuit shown in FIG.

  The example shown in FIG. 3B is an example in which the timing violation is detected in the path path1 in the previous stage of the register cell REG2 by the extraction of the timing violation path in step S3 of the flow of FIG.

  In this case, in the detailed analysis in step S4, the margin of timing is analyzed including the subsequent path path2 in which there is no timing violation. As a result, it is found that the path path1 has a margin of -s1, and the path path2 has a margin of + s2. Here, the negative sign (−) of the margin indicates that the timing is insufficient.

  Based on the analysis result, in step S5, the skew amount of the clock signal CK2 of the register cell REG2 is adjusted. At this time, in the process of step S5, the skew amount to be adjusted is changed according to the size of the margin s2 at the subsequent stage of the register cell REG2 and the margin s1 (insufficient amount) at the preceding stage.

  That is, when s2 ≧ s1, the skew amount of the clock signal CK2 is adjusted to skew2 + s1. As a result, the margin of the previous stage is increased by s1, and the timing violation of the path path1 of the previous stage is solved. At this time, the margin of the subsequent stage is decreased by s1, but the path path2 of the subsequent stage still has a margin of (s2-s1).

  On the other hand, when s2 <s1, the skew amount of the clock signal CK2 is adjusted to skew2 + s2. In this case, the timing violation of the previous path path1 remains, but the amount of violation decreases to (s1-s2). Further, the path path2 in the subsequent stage has a margin of 0, but no timing violation occurs.

  The example shown in FIG. 3C is an example in which a timing violation is detected in the path path2 subsequent to the register cell REG2.

  In this case, assuming that the margin of the path path1 is + s1 and the margin of the path path2 is -s2, the skew amount is adjusted in step S5 as follows.

  That is, when s1 ≧ s2, the skew amount of the clock signal CK2 is adjusted to skew2-s2, and when s1 <s2, the skew amount of the clock signal CK2 is adjusted to skew2-s1.

  When s1 ≧ s2, the skew of the clock signal CK2 is adjusted to skew2-s2, thereby eliminating the timing violation of the path path2, and when s1 <s2, the skew of the clock signal CK2 is adjusted to skew2-s1. As a result, the timing violation amount of the path path2 is reduced to (s2-s1).

  The example shown in FIG. 3D is an example in which a timing violation is detected in both the path path1 in the preceding stage and the path path2 in the subsequent stage of the register cell REG2.

  In this case, neither timing violation is eliminated even if the skew amount of the clock signal CK2 is adjusted. Therefore, in this case, the process in step S5 adjusts the skew amount of the clock signal CK2 so that the timing violation amounts of the path path1 and the path path2 are equal.

  At this time, assuming that the margin of the path path1 is −s1 and the margin of the path path2 is −s2, the adjustment of the skew amount in step S5 is performed as follows.

  That is, when s2 ≧ s1, the skew amount of the clock signal CK2 is adjusted to skew2- (s2-s1) / 2, and when s1 <s2, the skew amount of the clock signal CK2 is skew2 + (s1-s2) / Adjust to 2.

For example, when s1 = 1 and s2 = 3, that is, the timing violation amount of the path path1 is 1 and the timing violation amount of the path path2 is 3, the skew amount of the clock signal CK2 is
skew2- (3-1) / 2 = skew2-1
And the clock signal CK2 is advanced by 1. As a result, the timing violation amounts of the path path1 and the path path2 are both 2.

Conversely, when s1 = 3 and s2 = 1, the skew amount of the clock signal CK2 is
skew2 + (3-1) / 2 = skew2 + 1
And the clock signal CK2 is delayed by 1. As a result, the timing violation amounts of the path path1 and the path path2 are both 2.

  By equalizing the timing violation amounts of the two routes in this way, it is possible to reduce routes having a large timing violation amount, and it becomes easy to take a countermeasure against timing violation after execution of this arrangement.

  According to the present embodiment as described above, the temporary placement is performed only in the high threshold cell using the layout clock cycle that is subtracted from the original clock cycle with the speed improvement by the low threshold cell as a margin. Therefore, the driving capability of the high threshold cell is maximized, and all the paths that cannot satisfy the timing specifications with only the high threshold cell can be extracted in one temporary arrangement.

  In addition, for the timing violation path, it is possible to generate a main arrangement timing constraint in which the skew amount of the clock signal is adjusted so that the timing violation is eliminated or the amount of violation is reduced. By using this real placement timing constraint, the amount of low threshold cells used in the real placement can be reduced.

(Second Embodiment)
In the present embodiment, an example of a timing constraint establishment method effective for improving timing violation of a cell having a large number of input pins and a large number of output pins such as an SRAM is shown.

  FIG. 4 is a diagram for explaining a timing constraint establishment method according to the second embodiment.

  The high threshold cell HTC11 shown in FIG. 4A is a cell having a large number of input pins and a large number of output pins, and a clock signal CK11 is input as a clock signal. It is assumed that the skew amount skew11 is described in the timing constraint 11 for the clock signal CK11.

  FIG. 4B is a bar graph showing the propagation delay value to the input pin and the propagation delay value of the output pin after provisional placement (before adjusting the skew amount). In this graph, the range between the input side timing specification spec1 and the output side timing specification spec2 is a range satisfying the timing specification.

  In the example shown in FIG. 4B, there are one path on the input side and five paths on the output side that violate this timing specification.

  Therefore, in this embodiment, in order to reduce the number of timing violation paths on the output side, the clock signal CK11 is advanced by the minimum margin Δt1 of the input side path. Therefore, the skew amount of the clock signal CK11 due to timing constraints is changed from skew 11 to (skew 11−Δt 1).

  FIG. 4C is a diagram illustrating the effect of adjusting the skew amount of the clock signal CK11. When the skew amount of the clock signal CK11 is adjusted to (skew11−Δt1), the timing violation path on the output side is reduced from five in this example to one.

  On the other hand, the number of timing violation paths on the input side remains the same as before the skew amount adjustment.

  FIG. 5A is an example in which there are five paths that violate the timing specifications on the input side and one path on the output side. In this case, in order to reduce the timing violation path on the input side, the clock signal CK11 is delayed by the minimum margin Δt2 of the output side path. Therefore, the skew amount of the clock signal CK11 due to timing constraints is changed from skew 11 to (skew 11 + Δt 2).

  FIG. 5B is a diagram illustrating the effect of adjusting the skew amount of the clock signal CK11. When the skew amount of the clock signal CK11 is adjusted to (skew11 + Δt2), the timing violation path on the input side is reduced from five to one in this example.

  On the other hand, the number of timing violation paths on the output side remains the same as before the skew amount adjustment.

  According to the present embodiment as described above, the timing violation of a large number of paths can be improved at the same time by adjusting the skew of the clock signal so that the number of timing violation paths is minimized. In addition, since the number of timing violation paths can be minimized, the number of low threshold cells used in this arrangement can be reduced.

(Third embodiment)
One index for evaluating timing violation is TNS (Total Negative Slack) that represents the total amount of timing violations of all violation paths. In the present embodiment, an example of a timing constraint setting method for adjusting the skew amount of the clock signal so that the TNS is minimized will be described.

  FIG. 6 is a diagram for explaining a timing constraint establishment method according to the third embodiment.

  FIG. 6A is a diagram illustrating the TNS after provisional arrangement (before adjusting the skew amount). The area of the hatched portion in this figure represents TNS. Also, TNS on the front stage side of the clock input is TNS1, and TNS on the rear stage side is TNS2. In this example, TNS is biased between the front side and the rear side, and TNS2 >> TNS1.

  Therefore, in this case, the skew amount of the clock signal is adjusted so that the TNS on the rear stage side is reduced.

  As shown in FIG. 6B, when the skew amount is adjusted, the TNS on the front stage of the clock input changes to TNS11 and the TNS on the rear stage changes to TNS12. In this case, the TNS on the front stage side increases slightly, but the TNS on the rear stage side significantly decreases.

  According to the present embodiment as described above, the timing violation amount reduced by adjusting the skew amount of the clock signal becomes the reduction amount of the low threshold cell in this arrangement as it is, so that the usage rate of the low threshold cell is reduced. Can do.

(Fourth embodiment)
In this embodiment, an example of a timing constraint setting method that adjusts the amount of skew of a clock signal based on the setup time and access time values specified for the high threshold cell, regardless of the timing verification analysis result after provisional placement. Show. The method of this embodiment is effective when there is a difference of several times between the setup time and the access time.

  FIG. 7 is a diagram for explaining a timing constraint establishment method according to the fourth embodiment.

  In the high threshold cell HTC21 shown in FIG. 7A, the setup time of the input signal Din with respect to the clock signal CK21 is defined as tsu, and the access time of the output signal Dout with respect to the clock signal CK21 is defined as tas.

  The example shown in FIG. 7B is an example in which the access time tas is several times longer than the setup time tsu (tas >> tsu).

In this case, the skew amount skew21 set in the clock signal CK21 is set to skew21 =-(tas-tsu) / 2.
And That is, the clock signal CK21 is advanced by skew21.

  By setting the skew amount, the timing margin for the subsequent stage of the high threshold cell HTC 21 is increased, and the probability of occurrence of a timing violation can be reduced even when the access time is large.

  The example shown in FIG. 7C is an example in which the setup time tsu is several times longer than the access time tas (tsu >> tas).

In this case, the skew amount skew21 set in the clock signal CK21 is set to skew21 = + (tsu-tas) / 2.
And That is, the clock signal CK21 is delayed by skew21.

  By setting the skew amount, the timing margin with respect to the previous stage of the high threshold cell HTC21 is increased, and the probability of occurrence of a timing violation can be reduced even if the setup time is specified.

  According to the present embodiment as described above, it is possible to set timing constraints without analyzing timing verification after provisional placement.

  According to the timing constraint setting method of at least one embodiment described above, the usage amount of the low threshold cell can be reduced.

  Moreover, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

11 Timing constraint 12 Cell library 13 Margin 21 Timing constraint for placement HTC1, HTC11, HTC21 High threshold cell LTC1 Low threshold cell REG1 to REG3 Register cell CT1, CT2 cell

Claims (5)

Temporary placement using only the high threshold cell based on the clock skew distribution described in the input timing constraint, using the value obtained by subtracting the speed improvement due to the low threshold cell as the margin and the clock cycle for layout. Steps to do,
Performing timing verification of the signal propagation path based on the result of the temporary placement;
Extracting a path in which a timing violation is detected by the timing verification;
Analyzing details of delay propagation related to the extracted path;
Calculating a clock skew amount to be distributed to a signal propagation path related to the extracted path based on a result of the analysis, updating the timing constraint, and outputting a timing constraint for actual placement. A characteristic timing constraint setting method. 2. The timing constraint setting method according to claim 1, wherein the margin is a value obtained by multiplying the original clock cycle by a speed improvement rate of the low threshold cell with respect to the high threshold cell. Updating the timing constraint comprises:
The timing constraint setting method according to claim 1, wherein the clock skew amount is calculated so that the number of paths in which the timing violation occurs is minimized. Updating the timing constraint comprises:
3. The timing constraint setting method according to claim 1, wherein the clock skew amount is calculated such that a total amount of violations of the timing violation is minimized. Updating the timing constraint comprises:
3. The timing constraint setting method according to claim 1, wherein the clock skew amount is calculated based on an access time and a setup time set in the high threshold cell regardless of the analysis result. 4.