JP2015184910A - process controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability with a simple structure by using a non-volatile memory.SOLUTION: A process controller 3 comprises: a MRAM 330 which is a non-volatile memory in which there is limitation of error correction of bits; and a control part for writing data to the MRAM and reading out the data from the MRAM. The process controller 3 further comprises an error determination part for comparing pieces of data which are read out from a same set of MRAMs, in which the plural MRAMs writing same data are divided into sets of two, and when the pieces of data do not match, outputting an error signal MBE. The control part designates a data writing area to the all MRAMs when writing the data to the MRAMs, writes same data to the MRAMs for same set, designates a data reading out area to the all MRAMs and reads out the data from each of the MRAMs when reading out the data from the MRAMs.

Description

  The present invention relates to a process controller.

  In a factory that manages a production process, a large number of devices (for example, devices such as sensor devices and valve positioners) are arranged in the plant to manage the process. Devices in the plant are controlled by a process controller that controls the process. The process controller described in Patent Document 1 below uses a DRAM (Dynamic Random Access Memory) as a memory for storing a control program and control data.

JP 2006-3929 A

  DRAMs and SRAMs (Static Random Access Memory) are equipped with an ECC (Error Correction Code) circuit that detects and repairs memory errors because memory errors occur due to cosmic rays such as alpha rays. However, since the ECC circuit has a complicated function, it becomes a factor for increasing the failure rate of the process controller. Also, since DRAM and SRAM are volatile, it is necessary to save data to a nonvolatile memory or the like provided separately when the process controller is powered off.

  The present invention has been made to solve the above-described problems caused by the prior art, and an object of the present invention is to provide a process controller that uses a nonvolatile memory and can improve reliability with a simple configuration. .

  The process controller according to the present invention is a process controller comprising: a nonvolatile memory having a limit in error correctable bits; and a control unit that writes data to the nonvolatile memory and reads data from the nonvolatile memory, When the data read from the non-volatile memory of the same set is compared for two or more non-volatile memories that are distinguished into two sets for writing the same data, An error determination unit that outputs an error signal is further provided, and when the control unit writes data to the non-volatile memory, it designates a data write area for all the non-volatile memories, and the same set for each set When writing data to the non-volatile memory and reading data from the non-volatile memory, all non-volatile Specifies the data read region with respect to the memory, reads the data from the respective said nonvolatile memory.

  By adopting such a configuration, when data is written to the nonvolatile memory, the same data can be written to two nonvolatile memories belonging to the same group, and when data is read from the nonvolatile memory, two data belonging to the same group can be written. The data read from the two nonvolatile memories are compared with each other, and if they do not match, an error signal can be output. As a result, in the nonvolatile memory, even when a memory error occurs exceeding the number of bits that can be corrected, an error signal can be output and when the process controller power is shut off, the nonvolatile memory It is also possible to omit a configuration for saving the data in another memory.

  ADVANTAGE OF THE INVENTION According to this invention, the process controller which can improve reliability with a simple structure using a non-volatile memory can be provided.

It is a figure which illustrates the structure of the process management system in embodiment. It is a figure which illustrates the circuit structure of the process controller shown in FIG. It is a figure which illustrates the function structure of the process controller shown in FIG.

  Embodiments according to the present invention will be described below with reference to the drawings. However, the embodiment described below is merely an example, and does not exclude application of various modifications and techniques not explicitly described below. That is, the present invention can be implemented with various modifications without departing from the spirit of the present invention.

  FIG. 1 is a diagram illustrating a configuration of a process management system including a process controller according to an embodiment of the present invention. As shown in FIG. 1, the process management system 10 includes a device management apparatus 1 and an operation monitoring apparatus 2 that are upper management apparatuses, a process controller 3, an IO (input / output) unit 4, and a device 5. .

  The device 5 is a device arranged in the plant. For example, a device corresponding to the foundation fieldbus technology, a device equipped with a HART (Highway Addressable Remote Transducer) communication function, a device compatible with the Profibus technology. Can be used. Examples of the device 5 include various sensor devices that detect flow rate, pressure, temperature, and the like, valve positioners that control various valves such as flow rate control valves and pressure control valves, and various actuators that operate pumps and fans. Applicable.

  The process controller 3 is a device that controls the execution state of the production process. Illustratively, the process controller 3 controls the valve positioner based on measured values such as flow rate and pressure acquired from the transmitter, thereby adjusting the opening of the valve provided in the pipe.

  The process controller 3 is configured to be redundant, and is constructed so that the system can continue to operate even if one of them fails and stops. For redundancy, a parallel redundancy system in which a plurality of process controllers 3 are duplicated may be employed, or a standby redundancy system in which the plurality of process controllers 3 function as an active system and a standby system may be employed.

  The IO unit 4 is a device that mediates between the process controller 3 and the device 5. For example, the IO unit 4 converts a protocol on the process controller 3 side and a protocol on the device 5 side.

  The device management apparatus 1 is an apparatus for managing the device 5, and performs centralized management of parameters, management of alert information, and the like. The operation monitoring device 2 is a device for displaying the operation contents of the device 5 collected via the process controller 3 on a monitor and operating the operation state of the device 5 in accordance with an operator's instruction.

  An example of the hardware configuration of the process controller 3 will be described with reference to FIG. The process controller 3 physically includes, for example, a CPU (Central Processing Unit) 310, a CPLD (Complex Programmable Logic Device) 320, and MRAMs (Magnetoresistive Random Access Memory c) 330A to MRAM 330H. CPU 310, CPLD 320, and MRAM 330A to MRAM 330H are connected to each other by a bus. Note that MRAM 330A to MRAM 330H will be referred to as MRAM 330 in the following unless it is necessary to distinguish between them.

  The CPU 310 illustratively has a bus width of 32 bits, and the MRAM 330 illustratively has a 512K × 8 bit configuration. Further, in the MRAM 330, for example, it is assumed that the number of bits that can be error-corrected is 1 bit. Note that the memory is not limited to the MRAM 330 exemplified here, and can be applied to the present invention as long as it is a non-volatile memory having a limit in bits that can be corrected.

  The MRAM 330 is distinguished into two sets for writing the same data. In FIG. 2, there are four sets, a set of MRAM 330A and MRAM 330B, a set of MRAM 330C and MRAM 330D, a set of MRAM 330E and MRAM 330F, and a set of MRAM 330G and MRAM 330H.

  The 32-bit data exchanged between the CPU 310 and the MRAM 330 is divided into four 8-bit data groups, each of which is exchanged with an MRAM belonging to one of the four groups. This will be specifically described below.

  Of the 32-bit data, the 1st to 7th bit data is exchanged with the set of MRAM 330A and MRAM 330B, and the 8th to 16th bit data is exchanged with the set of MRAM 330C and MRAM 330D. Similarly, the 17th to 24th bits of data are exchanged with the set of MRAM 330E and MRAM 330F, and the 25th to 32nd bits of data are exchanged with the set of MRAM 330G and MRAM 330H.

  The CPLD 320 controls data writing to the MRAM 330 and data reading from the MRAM 330 according to the control signal received from the CPU 310.

  The CPLD 320 further includes XOR (Exclusive OR) circuits 321A to 321D and an OR circuit 322. Note that the XOR circuits 321A to 321D are hereinafter referred to as XOR circuits 321 when there is no need to distinguish between them.

  The XOR circuit 321 compares the data read from the two MRAMs 330 belonging to the corresponding MRAM set, and outputs “1” as an error signal to the OR circuit 322 if they do not match. On the other hand, the XOR circuit 321 outputs “0” to the OR circuit 322 when the compared data match.

  The OR circuit 322 outputs “1” as the error signal MBE when “1” is output from any of the XOR circuits 321. This error signal MBE is transmitted to the operation monitoring device 2. On the other hand, the OR circuit 322 outputs “0” when “0” is output from all the XOR circuits 321.

  When the driver 331A to the driver 331D output “OE (Output Enable)” indicating that reading from the MRAM is permitted from the CPLD 320, the driver 331A to the driver 331D do not pass data, and when “OE” is not output. , The data is passed. Thus, when reading data from the MRAM 330, by outputting “OE”, the driver 331A to the driver 331D do not pass the data, so that the data can be individually read from each MRAM 330. Note that the drivers 331 </ b> A to 331 </ b> D are referred to as drivers 331 in the following unless there is no need to distinguish them.

  Next, an operation when the CPU 310 of the process controller 3 writes data to each MRAM 330 will be described with reference to FIG.

  First, the CPU 310 outputs “CS (Chip Select)” indicating selection as a write target to the CPLD 320 as a control signal.

  Subsequently, the CPLD 320 outputs “CS” to all the MRAMs 330. As a result, all the MRAMs 330 are selected as data write targets.

  Subsequently, the CPU 310 designates a data write area for all the MRAMs 330 via the address bus AB.

  Subsequently, the CPU 310 outputs data to be written in each MRAM 330 via the data bus DB.

  Subsequently, the CPU 310 outputs “WE (Write Enable) x” [x = 0 to 3] indicating that writing is permitted to the CPLD 320 as a control signal.

  Subsequently, the CPLD 320 outputs “WEx” to all the MRAMs 330. As a result, data is written in all the MRAMs 330.

  Subsequently, the CPU 310 and the CPLD 320 cancel all control signals.

  Next, an operation when the CPU 310 of the process controller 3 reads data from each MRAM 330 will be described with reference to FIG.

  First, the CPU 310 outputs “CS (Chip Select)” indicating selection as a reading target to the CPLD 320 as a control signal.

  Subsequently, the CPLD 320 outputs “CS” to all the MRAMs 330. As a result, all the MRAMs 330 are selected as data reading targets.

  Subsequently, the CPU 310 designates a data read area for all the MRAMs 330 via the address bus AB.

  Subsequently, the CPU 310 outputs “OE (Output Enable)” indicating that reading is permitted to the CPLD 320 as a control signal.

  Subsequently, the CPLD 320 outputs “OE” to all the MRAMs 330 and the drivers 331. As a result, all the drivers 331 pass data, and data is read from all the MRAMs 330, respectively.

  Subsequently, the XOR circuit 321A to XOR circuit 321D of the CPLD 320 compares the data read from the corresponding two MRAMs 330 and outputs “1” to the OR circuit 322 if they do not match. In this case, “0” is output to the OR circuit 322.

  Subsequently, when “1” is output from any XOR circuit 321, the OR circuit 322 outputs “1” as the error signal MBE, and “0” is output from all the XOR circuits 321. "0" is output.

  Subsequently, the CPU 310 and the CPLD 320 cancel all control signals.

  Next, an example of a functional configuration of the process controller 3 will be described with reference to FIG. Functionally, the process controller 3 includes a control unit 31 and a determination unit 32, for example.

  When writing data to the MRAM 330, the control unit 31 designates a data writing area for all the MRAMs 330 and writes the same data to the MRAM 330 for each same set.

  When reading data from the MRAM 330, the control unit 31 designates a data read area for all the MRAMs 330 and reads data from each MRAM 330.

  The determination unit 32 compares the data read from the same set of MRAMs 330 and outputs an error signal MBE if they do not match.

  The error signal MBE is transmitted to the operation monitoring device 2, and a message that an error has occurred in the process controller 3 is displayed on the monitor of the operation monitoring device 2. Therefore, the operator who confirms the message can stop the process controller 3 in which the error has occurred and perform confirmation and inspection. Since the process controller 3 has a redundant configuration, the system can continue to operate even if one process controller 3 is stopped.

  As described above, according to the process controller 3 in the embodiment, when data is written to the MRAM 330, the same data can be written to two MRAMs 330 belonging to the same group, and when data is read from the MRAM 330, the same group is used. The data read from the two MRAMs 330 to which they belong are compared with each other, and if they do not match, an error signal can be output.

  As a result, even when a memory error occurs in the MRAM 330 exceeding the number of bits that can be corrected, the error signal MBE can be transmitted to the operation monitoring device 2 and the process controller 3 is turned off. In addition, the configuration for saving the data in the MRAM 330 to another memory can be omitted.

  Therefore, according to the process controller 3 in the embodiment, the reliability can be improved with a simple configuration using the MRAM 330 which is a nonvolatile memory.

DESCRIPTION OF SYMBOLS 1 ... Device management apparatus 2 ... Operation monitoring apparatus 3 ... Process controller 4 ... IO unit 5 ... Device 10 ... Process management system 31 ... Control part 32 ... Determination part 310 ... CPU
320 ... CPLD
330 ... MRAM (nonvolatile memory)

Claims (3)

Non-volatile memory with limited bits for error correction,
A controller that writes data to the nonvolatile memory and reads data from the nonvolatile memory,
When the data read from the non-volatile memory of the same set is compared for two or more non-volatile memories that are distinguished into two sets for writing the same data, An error determination unit that outputs an error signal is further provided,
The controller is
When writing data to the non-volatile memory, specify a data write area for all the non-volatile memory, write the same data to the non-volatile memory for each same set,
When reading data from the non-volatile memory, specify a data read area for all the non-volatile memories, and read data from each of the non-volatile memories,
Process controller characterized by that.   2. The process controller according to claim 1, wherein the nonvolatile memory is an MRAM (Magnetoresistive Random Access Memory).   3. The process controller according to claim 1, wherein the process controller is configured to be redundant.

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