JP2015173180A - Solid-state image pickup device and manufacturing method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique which is effective to reduction of color mixing without degradation of the charge transfer characteristic.SOLUTION: Each pixel of a solid-state image pickup device has a photoelectric converter having a first conduction type charge accumulation part, and a gate electrode for forming a channel through which charges of the charge accumulation part are transferred to floating diffusion. The solid-state image pickup device contains separation parts constructed by semiconductor areas having a second conduction type opposite to the first conduction type so as to separate adjacent pixels mutually. A method of manufacturing the solid-state image pickup device contains a doping step of doping impurities into a substrate to form the separation parts. The doping step contains an oblique doping step of doping impurities into the substrate along a direction which is parallel to the width direction of the channel and inclined with respect to the normal line of the surface of the substrate under the state that a mask containing a portion located on an area where the channel will be formed exists on the substrate.

Description

  The present invention relates to a solid-state imaging device and a manufacturing method thereof.

  Patent Document 1 describes a technique for reducing color mixing in a solid-state imaging device mounted on a camera such as a digital video camera or a digital still camera. Specifically, Patent Document 1 describes a configuration in which a semiconductor region having a conductivity type opposite to the conductivity type of the charge storage region is disposed under the gate electrode of the transfer transistor (for example, FIG. 5).

JP 2004-193547 A

  As a method of forming a semiconductor region for separation between pixels under the gate electrode of the transfer transistor, a method of forming the gate electrode after forming the semiconductor region can be considered. In this method, generally, a photoresist mask having an opening is formed in a region where a semiconductor region for isolation between pixels is to be formed, and impurities are implanted into the substrate through the opening. In this case, impurities will be implanted into the substrate with the region where the gate electrode of the transfer transistor is to be formed exposed.

  The present inventors evaluated a solid-state imaging device in which a semiconductor region for separation between pixels was formed by such a method. As a result, a portion immediately below the gate electrode of the transfer transistor, that is, a channel for transferring charges. It was discovered that an unintended impurity was introduced into the region where the film was formed. In the implantation process for forming the semiconductor region for separating the pixels, the present inventors have found that the impurity recoiled on the side surface of the photoresist mask loses energy and the substrate has an intended depth. I came to the conclusion that it was caused by not being able to reach it. When an unintended impurity is introduced into a region where a channel for transferring charges is formed, the charge transfer characteristics are affected.

  An object of the present invention is to provide an advantageous technique for reducing color mixing without deteriorating charge transfer characteristics.

  One aspect of the present invention relates to a method of manufacturing a solid-state imaging device having a plurality of pixels. Each pixel includes a photoelectric conversion unit having a first conductivity type charge storage unit, and floating diffusion in the charge storage unit. The solid-state imaging device is composed of a semiconductor region of a second conductivity type opposite to the first conductivity type so as to separate adjacent pixels from each other. The manufacturing method includes an implantation step of forming the separation portion by implanting impurities into the substrate, and the implantation step is a portion located on a region where the channel is to be formed. Inclining implantation for injecting impurities into the substrate along a direction that is parallel to the width direction of the channel and inclined with respect to the normal of the surface of the substrate, in a state where a mask including Including the degree.

  According to the present invention, an advantageous technique is provided for reducing color mixing without deteriorating charge transfer characteristics.

The figure which shows the solid-state imaging device (a) of 1 embodiment of this invention, and the structure (b) of a pixel. The figure which shows the layout (a) of a part of pixel array, the cross section (b) of A-A 'line, and the cross section of B-B' line. The figure which shows the manufacturing method of 1st Embodiment. The figure which shows the manufacturing method of 1st Embodiment. The figure which illustrates the mask used at the implantation process of the impurity in 1st Embodiment. The figure which shows the manufacturing method of 2nd Embodiment. The figure which shows the manufacturing method of 2nd Embodiment. The figure which illustrates the mask used at the implantation process of the impurity in 2nd Embodiment. The figure which illustrates the impurity concentration distribution of a separation part. The figure which illustrates the impurity concentration distribution of a separation part.

  Hereinafter, a solid-state imaging device and a manufacturing method thereof according to the present invention will be described through exemplary embodiments with reference to the accompanying drawings.

  FIG. 1A shows a schematic configuration of a solid-state imaging device 50 according to one embodiment of the present invention. The solid-state imaging device 50 includes a pixel array 51, a row selection circuit 52, a readout circuit 53, a signal holding unit 54, a column selection circuit 55, and an output unit 56. The pixel array 51 has a plurality of pixels arranged so that a plurality of rows and a plurality of columns are formed. The row selection circuit 52 selects a row in the pixel array 51. The readout circuit 53 includes a plurality of column amplifiers respectively corresponding to the plurality of columns in the pixel array 51. Each column amplifier reads a signal output to the corresponding column signal line of the pixel array 51. The signal holding unit 54 holds a plurality of columns of signals read by the reading circuit 53. The column selection circuit 55 selects a plurality of columns of signals held in the signal holding unit 54 in a predetermined order. The output unit 56 amplifies and outputs the signal of the column selected by the column selection circuit 55.

  FIG. 1B shows a configuration example of one pixel PIX constituting the pixel array 51. The pixel PIX includes a photoelectric conversion unit 011 and a transfer transistor 012. The photoelectric conversion unit 011 can be, for example, a photodiode. The photoelectric conversion unit 011 has a charge accumulation region for accumulating charges generated by photoelectric conversion. In addition, the pixel PIX may include a floating diffusion 013, a reset transistor 014, an amplification transistor 015, and a selection transistor 016. The floating diffusion 013, the reset transistor 014, the amplification transistor 015, and the selection transistor 016 may be shared by a plurality of photoelectric conversion units 011 (in other words, a plurality of pixels PIX). The selection transistor 016 can be omitted. When the selection transistor 016 is omitted, the pixel PIX can be selected by the reset potential of the floating diffusion 013.

  In the example shown in FIG. 1B, the pixel PIX accumulates electrons among electrons and holes generated by photoelectric conversion, and outputs a signal corresponding to the amount of the electrons as a signal of the pixel PIX. However, the pixel PIX may be configured to accumulate holes and output a signal corresponding to the amount of the holes as a pixel signal. The transfer transistor 012 transfers the charge in the charge storage unit of the photoelectric conversion unit 011 to the floating diffusion 013. The transfer transistor 012 has a MOS transistor structure including a gate electrode. When the transfer signal TX is activated by the row selection circuit 52, the gate electrode forms a channel in the semiconductor substrate for transferring the charge in the charge storage portion of the photoelectric conversion portion 011 to the floating diffusion 013.

  The amplification transistor 015 outputs a signal corresponding to the amount of charge transferred to the floating diffusion 013 to the column signal line 020. In one example, one end of a current source 021 is connected to the column signal line 020, and a source follower circuit can be configured by the amplification transistor 015 and the current source 021. The reset transistor 014 resets the potential of the floating diffusion 013 when the reset signal RES is activated by the row selection circuit 52. The selection transistor 016 connects the amplification transistor 015 and the column signal line 020 when the selection signal SEL is activated by the row selection circuit 52.

  FIG. 2A illustrates a layout of a part of the pixel array 51. 2A shows a plurality of layers in and on the semiconductor substrate SB. FIG. 2B is a cross-sectional view taken along the line A-A ′ of FIG. FIG. 2C is a cross-sectional view taken along line B-B ′ of FIG. In FIGS. 2A, 2B, and 2C, the reset transistor 014, the amplification transistor 015, and the selection transistor 016 are omitted.

  The semiconductor substrate SB includes a first conductivity type semiconductor region 101 and a second conductivity type semiconductor region (well) 102 disposed on the semiconductor region 101. Here, the first conductivity type and the second conductivity type are opposite to each other. When the first conductivity type is n-type, the second conductivity type is p-type. Conversely, when the first conductivity type is p-type, the second conductivity type is n-type. According to the example described in FIG. 1B, the first conductivity type is n-type and the second conductivity type is p-type.

  The pixel array 51 has an element isolation region 103. The element isolation region 103 can be, for example, an element isolation region made of an insulator (typically silicon oxide), for example, STI (shallow trench isolation). Alternatively, the element isolation region 103 may be a second conductivity type semiconductor region.

  The photoelectric conversion unit 011 can be configured by the first conductivity type charge storage unit 107 and the second conductivity type semiconductor region 102. The charge storage unit 107 is disposed in the active region 110. The photoelectric conversion unit 011 may further include a second conductivity type semiconductor region (surface region) 120 disposed on the charge storage unit 107. The floating diffusion 013 can be constituted by the first conductivity type semiconductor region 105 disposed in the second conductivity type semiconductor region 102.

  The gate electrode 106 of the transfer transistor 012 can be made of, for example, polysilicon. The gate electrode 106 is disposed on the surface of the semiconductor substrate SB via the gate insulating film 112. When the transfer signal TX is activated, the gate electrode 106 forms a channel in the channel formation region RCH that transfers the charge of the charge storage unit 107 to the floating diffusion 013 (semiconductor region 105).

  In the semiconductor region 102, the isolation part 104 comprised by the semiconductor region of the 2nd conductivity type is arrange | positioned. The separation unit 104 is arranged so as to surround each photoelectric conversion unit 011 (charge storage unit 107), in other words, to separate adjacent photoelectric conversion units 011 from each other. As illustrated in FIGS. 2A, 2 </ b> B, and 2 </ b> C, the separation unit 104 includes a portion disposed below the gate electrode 106 of the transfer transistor 012. For example, the separation unit 104 may have a lattice configuration. By providing the separation unit 104, a potential barrier is formed against electric charges (electrons in the example shown in FIG. 1B) read out as signals. As a result, it is possible to reduce color mixing due to the movement of charges between adjacent photoelectric conversion units 011.

  In general, each pixel has a microlens that collects light. In many cases, the center of the orthogonal projection of the microlens on the light receiving surface coincides with the center of the photoelectric conversion unit 011. However, there is a case where the centers of the orthogonal projections onto the light receiving surface of the microlens are shifted in the upward direction of FIG. 2A, that is, in the direction opposite to the semiconductor region 105 without matching. In such a case, the amount of color mixing differs depending on the adjacent direction in each pixel, and asymmetric shading may occur. In such a case, it is possible to suppress asymmetric shading by disposing a part of the separation unit 104 below the gate electrode 106 of the transfer transistor 012. The separation unit 104 can include a plurality of stages of second-conductivity-type semiconductor regions 104a, 104b, and 104c formed by a plurality of implantation steps having different implantation energies. The plurality of stages of the second conductivity type semiconductor regions 104a, 104b, and 104c are disposed at different depths.

  Here, the “width direction” of the “channel” used below will be described. By applying an active voltage to the gate electrode 106 of the transfer transistor 012, a channel is formed in the channel formation region RCH. The “width direction” of the channel is a direction parallel to the A-A ′ line in FIG. 2A, and the direction illustrated as the “channel width direction” in FIG. 2B.

  Hereinafter, the manufacturing method of the first embodiment of the solid-state imaging device 50 will be described with reference to FIGS. Here, FIGS. 3 and 4 are cross-sectional views corresponding to the cross section taken along the line A-A ′ of FIG. In the following description, the first conductivity type is n-type and the second conductivity type is p-type.

  In step S310, the second conductivity type semiconductor region 102 is formed by implanting boron as the second conductivity type impurity into the semiconductor substrate SB having the semiconductor region 101. In step S310, the element isolation region 103 is formed in the semiconductor substrate SB. The element isolation region 103 can be configured by, for example, STI (shallow trench isolation). Alternatively, the element isolation region 103 can be formed of a high-concentration second conductivity type semiconductor region.

  In step S320, an insulating film is formed on the surface of the semiconductor substrate SB. In step S320, a photoresist mask is formed by a lithography process, and arsenic is implanted as an impurity of the first conductivity type into the semiconductor substrate SB through the opening of the photoresist mask, thereby forming the charge storage portion 107. In step S320, a polysilicon film is formed on the insulating film and patterned to form the gate electrode 106 of the transfer transistor 012. At this time, gate electrodes of other transistors can also be formed. A gate insulating film 112 is formed under the gate electrode 106.

  In step S330, a mask 109 is formed on the semiconductor substrate SB. The mask 109 is made of, for example, a photoresist. FIG. 5 illustrates a plan view of the mask 109. The mask 109 has an opening 108. Mask 109 includes a portion 1091 located on channel formation region RCH, which is a region where the channel of transfer transistor 012 is to be formed.

In steps S340 to S360, an injection process is performed. In the implantation step, the isolation part 104 is formed by implanting impurities into the semiconductor substrate SB. The implantation process can include an oblique ion implantation process. The oblique ion implantation process may include a first process (S340) and a second process (S350). The implantation step may further include a third step (S360) in which the tilt angle of impurity implantation is smaller than that in the first step and the second step. Here, the tilt angle θ1 of the impurity implantation in the first step (S340) may be, for example, not less than 10 degrees and not more than 50 degrees. Further, the tilt angle θ2 of the impurity implantation in (S340) can be, for example, not less than 10 degrees and not more than 50 degrees. The implantation energy in the first step (S340) and the second step (S350) is not less than 100 keV and not more than 2500 keV, and the dose can be not less than 1 × 10 ^{11 and not} more than 1 × 10 ¹⁴ (cm ⁻² ).

  In the oblique ion implantation process (S340, S350), in a state in which the mask 109 including the portion 1091 is present, it is parallel to the channel width direction of the transfer transistor 012 and inclined with respect to the normal line NL of the surface SS of the semiconductor substrate SB. Along this, impurities are implanted into the semiconductor substrate SB. Here, in the oblique ion implantation process, in the first process (S340) and the second process (S350), the directions in which the impurity implantation directions for the semiconductor substrate SB are projected onto the surface SS of the semiconductor substrate SB are opposite to each other. . As a result, the separation portion 104 is also formed below the portion 1091 or the gate electrode 106, that is, below the channel formation region RCH. Such a separation unit 104 is advantageous for improving separation performance between adjacent photoelectric conversion units 011 and reducing color mixing.

  The first step (S340) preferably includes a plurality of injection steps with different injection energies, and similarly, the second step (S350) preferably includes a plurality of injection steps with different injection energies. . Thereby, a plurality of stages of second conductivity type semiconductor regions 104a, 104b, 104c are formed. That is, the dimension of the separation part 104 in the depth direction can be increased.

  Here, if an impurity is implanted into the semiconductor substrate SB with the gate electrode 106 exposed, the impurity may also be implanted into the gate electrode 106 and transfer performance may deteriorate. Therefore, the mask 109 (part 1091) preferably covers the gate electrode 106 of the transfer transistor 012. That is, the mask 109 is preferably formed so that the gate electrode 106 is not exposed in the opening 108.

  The cross-sectional shape of the mask 109 may be an overhang shape in which the width in the width direction of the channel of the transfer transistor 012 increases as the distance from the surface SS of the semiconductor substrate SB increases. In this case, the amount of impurities that penetrate through the mask 109 and are implanted into the channel formation region RCH can be reduced.

  As in the first embodiment, when the separation part 104 is formed after the gate electrode including the gate electrode 106 of the transfer transistor 012 is formed, the separation part 104 is not affected by the heat treatment for forming the gate electrode. Therefore, the amount of diffusion of impurities for forming the separation portion 104 by heat treatment can be reduced. This is advantageous for reducing the pixel size.

  Here, unlike the first embodiment, consider a case where the implantation step for forming the separation portion 104 is performed without covering the channel formation region RCH with the mask 109. In this case, since the impurity that recoils on the side surface of the mask and enters the semiconductor substrate SB loses energy during the recoil, it reaches the desired depth of the semiconductor substrate SB (the depth at which the separation portion 104 is to be formed). It cannot reach and can remain on the surface portion of the semiconductor substrate SB. Then, an unintended impurity is implanted into the channel formation region RCH of the transfer transistor 012. As a result, the charge transfer characteristics of the transfer transistor 012 are affected, and unintended transfer characteristics can be obtained.

  Therefore, it is preferable to form the separation part 104 in a state where the channel formation region RCH is covered with the mask 109. For this purpose, the oblique ion implantation process (S340, S350) is performed. In the oblique ion implantation process, an impurity region 111 can be formed by implanting an impurity into a region near the surface of the semiconductor substrate SB (that is, a shallow region) in a portion not covered with the mask 109.

  The tilt angle of impurity implantation in the third step (S360) is smaller than the tilt angle of impurity implantation in the first step and the second step. The tilt angle of the impurity implantation in the third step (S360) can be, for example, 0 degrees. Also in the third step (S360), for the portion not covered with the mask 109, an impurity is implanted into a region near the surface of the semiconductor substrate SB (ie, a shallow region), and an impurity region 111 can be formed. The third step (S360) may be performed by forming another mask instead of the mask 109 and using the other mask.

  In the case where the injection process for forming the separation unit 104 includes the first process, the second process, and the third process, the order in which they are performed is arbitrary. A heat treatment process may be performed after or during the implantation process for forming the separation portion 104.

  Subsequent to the implantation step for forming the separation portion 104, a new mask is formed instead of the mask 109, and the floating diffusion 013 is implanted by injecting the first conductivity type impurity into the semiconductor substrate SB through the opening of the new mask. Can be formed.

  9 and 10 exemplify the impurity concentration distribution of the separation portion 104 at a predetermined depth in a cross section passing through the channel parallel to the channel width direction of the transfer transistor 012. In the example of the impurity concentration distribution of the separation portion 104 shown in FIG. 9, the impurity concentration in the region below the gate electrode 106 is lower than the impurity concentration in the region around the region. In the example of the impurity concentration distribution of the separation portion 104 shown in FIG. 10, the impurity concentration in the region below the gate electrode 106 is higher than the impurity concentration in the region around the region. Thus, the impurity concentration in the region below the gate electrode 106 can be different from the impurity concentration in the region around the region. This is because the impurity concentration in the region below the gate electrode 106 is determined through the impurity implantation in the first step and the impurity implantation in the second step.

  Hereinafter, a manufacturing method of the second embodiment of the solid-state imaging device 50 will be described with reference to FIGS. Note that matters not mentioned in the second embodiment can follow the first embodiment. In the second embodiment, the isolation part 104 is formed before the gate electrode 106 of the transfer transistor 012 is formed. This is advantageous for preventing impurities for forming the isolation portion 104 from being injected into the gate electrode 106 and the gate insulating film 112 and preventing the threshold value of the transfer transistor 012 from fluctuating.

  In step S610, the second conductive type semiconductor region 102 is formed by implanting boron as a second conductive type impurity into the semiconductor substrate SB having the semiconductor region 101. In step 610, the element isolation region 103 is formed in the semiconductor substrate SB. The element isolation region 103 can be configured by, for example, STI (shallow trench isolation). Alternatively, the element isolation region 103 can be formed of a high-concentration second conductivity type semiconductor region.

  In step S620, a mask 109 is formed on the semiconductor substrate SB. The mask 109 is made of, for example, a photoresist. FIG. 8 illustrates a plan view of the mask 109. The mask 109 has an opening 108. Mask 109 includes a portion 1091 located on channel formation region RCH.

  In steps S630 to S650, an injection process is performed. In the implantation step, the isolation part 104 is formed by implanting impurities into the semiconductor substrate SB. The implantation process can include an oblique ion implantation process. The oblique ion implantation process may include an oblique ion implantation process including a first process (S630) and a second process (S640). The implantation step may further include a third step (S650) in which the tilt angle of impurity implantation is smaller than that in the first step and the second step. Here, the first step (S630), the second step (S640), and the third step (S650) in the second embodiment are the first step (S340), the second step (S350), and the second step in the first embodiment. Each of the three steps (S360) may be the same.

  In step S660, an insulating film is formed on the surface of the semiconductor substrate SB. In step S660, a photoresist mask is formed by a lithography process, and arsenic is implanted as an impurity of the first conductivity type into the semiconductor substrate SB through the opening of the photoresist mask, thereby forming the charge storage portion 107. In step S660, a polysilicon film is formed on the insulating film, and the gate electrode 106 of the transfer transistor 012 is formed by patterning the polysilicon film. At this time, gate electrodes of other transistors can also be formed. A gate insulating film 112 is formed under the gate electrode 106.

Claims (13)

A method of manufacturing a solid-state imaging device having a plurality of pixels,
Each pixel includes a photoelectric conversion unit having a charge storage unit of a first conductivity type, and a gate electrode for forming a channel for transferring the charge of the charge storage unit to a floating diffusion. A separation unit configured by a semiconductor region of a second conductivity type opposite to the first conductivity type so as to separate pixels to be separated from each other;
The manufacturing method includes an injection step of forming the separation portion by injecting impurities into the substrate,
In the implantation step, a mask including a portion located on a region where the channel is to be formed exists on the substrate, and is parallel to the width direction of the channel with respect to a normal line of the surface of the substrate. Including an oblique implantation step of implanting impurities into the substrate along the inclined direction,
A method of manufacturing a solid-state imaging device. The oblique implantation step includes a first step of injecting impurities into the substrate and a second step of injecting impurities into the substrate, and the direction in which the impurity implantation direction with respect to the substrate is projected onto the surface of the substrate is The first step and the second step are opposite to each other.
The method for manufacturing a solid-state imaging device according to claim 1. The first step includes a plurality of implantation steps with different implantation energies, and the second step includes a plurality of implantation steps with different implantation energies.
The method for manufacturing a solid-state imaging device according to claim 2. The implantation step further includes a third step of injecting impurities into the substrate, and the tilt angle of the impurity implantation is smaller in the third step than in the first step and the second step.
The method for manufacturing a solid-state imaging device according to claim 2, wherein: The implantation step is performed after forming the gate electrode.
The method for manufacturing a solid-state imaging device according to claim 1, wherein: The mask is made of a photoresist.
The method for manufacturing a solid-state imaging device according to claim 1, wherein: The mask is made of a photoresist,
The mask is formed so that the gate electrode is not exposed in the opening of the photoresist.
The method for manufacturing a solid-state imaging device according to claim 1, wherein: The implantation step is performed before forming the gate electrode.
The method for manufacturing a solid-state imaging device according to claim 1, wherein: In the implantation step, the separation portion is formed so as to surround each pixel.
The method for manufacturing a solid-state imaging device according to claim 1, wherein: The tilt angle of the impurity implantation in the oblique implantation step is not less than 10 degrees and not more than 50 degrees.
The method for manufacturing a solid-state imaging device according to claim 1, wherein: A solid-state imaging device having a plurality of pixels,
Each pixel includes a photoelectric conversion unit having a charge storage unit of a first conductivity type, and a gate electrode for forming a channel for transferring the charge of the charge storage unit to a floating diffusion,
The solid-state imaging device includes a separation unit configured by a semiconductor region of a second conductivity type opposite to the first conductivity type so as to separate adjacent pixels from each other,
The impurity concentration distribution of the separation part at a predetermined depth in a cross section passing through the channel parallel to the width direction of the channel is such that the impurity concentration in the region below the gate electrode is different from the impurity concentration in the region around the region Is,
A solid-state imaging device. An impurity concentration in a region below the gate electrode is lower than an impurity concentration in a region around the region;
The solid-state imaging device according to claim 11. An impurity concentration in a region below the gate electrode is higher than an impurity concentration in a region around the region;
The solid-state imaging device according to claim 11.