JP2015170199A - communication system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication system capable of making a signal line for transmitting a slave select signal common without reducing the number of transmittable bits of data.SOLUTION: A microcomputer 10 outputs slave select data corresponding to an IC which should be selected as a communication object by a slave select signal transmitted via a slave select signal line 23 made common to ICs 11-13. The slave select data is binary data which changes in different patterns from each other while a prescribed number of clock signals Clock are output. The slave select data allows a communication object IC to be reliably selected.

Description

  The present invention relates to a communication system that performs clock synchronous serial communication between one host device and a plurality of slave devices.

  Conventionally, a clock synchronous serial data communication system represented by SPI (Serial Peripheral Interface) or the like is known as a communication system for performing serial communication between one host device and a plurality of slave devices. A general communication procedure in this communication method will be described. First, a host device outputs a slave select signal of an active level (usually, a low level) to a slave device to be a communication target, and selects it as a communication target. . Next, the host device outputs transmission data to be transmitted to the selected slave device at the timing synchronized with the rising edge or falling edge of the clock signal while transmitting the clock signal. On the other hand, the selected slave device also outputs received data to be received by the host device at a timing synchronized with the clock signal. In this manner, data transmission / reception is executed in synchronization with the clock between the host device and the slave device. When transmission / reception of all data is completed, the host device sets the slave select signal to an inactive level and terminates communication.

  As described above, conventionally, the slave device to be communicated is selected by setting the slave select signal to the active level. Therefore, it is necessary to connect the host device and the plurality of slave devices by independent signal lines. As a result, the host device needs to have a large number of slave select terminals (SS terminals), and an increase in the number of SS terminals has been one problem.

  Further, due to having a large number of SS terminals, there is a possibility that an erroneous connection between the SS terminals and each slave device, a short circuit between the SS terminals, or a short circuit to a potential corresponding to the active level may occur. If any of these events actually occurs, communication with a slave device that is not the target of communication is established, and the slave device may behave unintentionally. It was.

  A communication system capable of solving such a problem is disclosed in Patent Document 1, for example. In the communication system of Patent Document 1, a signal line for transmitting a slave select signal is shared by each slave device, and information indicating a slave device to be communicated is added to transmission data from a host device. .

Japanese Patent Laid-Open No. 2004-362067

  However, when information indicating a communication target is added to the transmission data from the host device as in the communication system of Patent Document 1, there is a problem that the number of bits of data that can be transmitted is reduced accordingly.

  Furthermore, in the communication system of Patent Document 1, information indicating a communication target is added using 3 bits in transmission data. However, when connecting more than the upper limit number of slave devices that can be distinguished by the number of bits, the number of signal lines for transmitting slave select signals is increased. In this case, there is a possibility that communication with a slave device that is not a communication target may be established due to an erroneous connection or a short circuit as described above.

  The present invention has been made in view of the above points, and provides a communication system capable of sharing a signal line for transmitting a slave select signal without reducing the number of bits of transmittable data. For the purpose.

In order to achieve the above object, a communication system according to the present invention is one in which one host device (10) and a plurality of slave devices (11, 12, 13) perform clock synchronous serial communication,
Between the host device and multiple slave devices,
A common clock signal line (20) for transmitting a clock signal from the host device to a plurality of slave devices;
A common first communication line (21) for transmitting data from the host device to the plurality of slave devices in synchronization with the clock signal;
A common second communication line (22) for transmitting data from the plurality of slave devices to the host device in synchronization with the clock signal;
The host device is connected to a slave select signal line (23) for transmitting a slave select signal for selecting a slave device as a communication partner,
The slave select signal line is shared by multiple slave devices.
A plurality of slave devices are pre-assigned binary data that changes in different patterns while a predetermined number of clock signals are output.
The host device outputs binary data corresponding to the slave device to be selected in response to the slave select signal.

  As described above, in the communication system according to the present invention, the host device does not add information indicating the slave device to be communicated to the transmission data, but corresponds to the slave device to be selected by the slave select signal. Output binary data. Therefore, unlike the prior art, the number of bits of data that can be transmitted does not decrease by the amount of information indicating the communication target. Furthermore, even if the slave select signal line is shared by a plurality of slave devices, the slave device to be communicated can be reliably selected by the binary data.

  In the above-described configuration, it is preferable that the host device uses a pattern other than the pattern that becomes the active level of the slave select signal as binary data. In this way, for example, when the slave select signal line is short-circuited to a potential corresponding to the active level, it is possible to easily detect the occurrence of such an abnormality and take necessary measures. .

  For example, the plurality of slave devices may end the communication operation when receiving binary data having a pattern that is all in an active level as binary data. In this case, even if the above-described abnormality occurs, it is possible to prevent the host device from erroneously communicating with a slave device that is not a communication target.

  Furthermore, when data transmission / reception is performed simultaneously between the host device and the slave device, the host device should detect that a failure has occurred based on not receiving data from the slave device. May be. As a result, the host device can easily detect the failure when the slave select signal line is short-circuited to a potential corresponding to the active level.

  The reference numerals in the parentheses merely show an example of a correspondence relationship with a specific configuration in an embodiment described later in order to facilitate understanding of the present invention, and are intended to limit the scope of the present invention. Not intended.

  Further, the technical features described in the claims of the claims other than the features described above will become apparent from the description of embodiments and the accompanying drawings described later.

It is a block diagram which shows the structure of an example of the communication system which concerns on embodiment. It is the timing chart which showed the various signals in case the microcomputer 10 performs clock synchronous serial communication with each IC11-13. It is a figure which shows an example of allocation of the slave select data to each IC. It is the timing chart which showed the various signals communicated between the microcomputer 10 and IC-A, when the microcomputer 10 selects IC-A11 as a communication object. 4 is a flowchart showing communication processing executed in the microcomputer 10. It is a flowchart which shows all the slave communication processes performed in each IC until a to-be-selected IC is determined. It is a flowchart which shows the selected slave communication process performed by selected IC. 10 is a flowchart showing the contents of Modification 1; 10 is a flowchart showing the contents of Modification 2.

  Hereinafter, a communication system according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram illustrating a configuration example of a communication system according to the present embodiment.

  As shown in FIG. 1, the communication system according to the present embodiment includes a microcomputer 10 as a host device and a plurality of ICs (IC-A11, IC-B12, IC-C13, etc.) as slave devices. Clock synchronous serial communication is performed between the microcomputer 10 and a plurality of ICs (IC-A11, IC-B12, IC-C13, etc.).

  The microcomputer 10 is a clock output terminal that outputs a clock signal Clock, a transmission data output terminal that outputs transmission data Tx to be transmitted to the ICs 11 to 13, and reception data that is output from the ICs 11 to 13 and received by the microcomputer 10. A reception data input terminal for inputting Rx, and a slave select signal output terminal for outputting a slave select signal SS including slave select data for selecting an IC to be a communication partner.

  The clock output terminal of the microcomputer 10 is connected to the clock signal line 20. The clock signal line 20 is connected to the clock signal input terminals of the ICs 11 to 13. That is, a common clock signal line 20 is provided for each of the ICs 11 to 13, and the clock signal Clock from the microcomputer 10 is given to each of the ICs 11 to 13 via the common clock signal line 20.

  A transmission data output terminal of the microcomputer 10 is connected to the first communication line 21. The first communication line 21 is connected to the data input terminals of the ICs 11 to 13. The reception data input terminal of the microcomputer 10 is connected to the second communication line 22. The second communication line 22 is connected to the data output terminals of the ICs 11 to 13. Further, the slave select signal output terminal of the microcomputer 10 is connected to the slave select signal line 23. The slave select signal line 23 is connected to the slave select signal input terminals of the ICs 11 to 13. As shown in FIG. 1, the first communication line 21, the second communication line 22, and the slave select signal line 23 are also shared by the respective ICs 11 to 13, as in the case of the clock signal line 20. .

  In the serial communication performed in the communication system according to the present embodiment, the microcomputer 10 always has the initiative of communication. That is, when the microcomputer 10 performs serial communication with each of the ICs 11 to 13, as shown in FIG. 2, first, the slave select signal SS is set to the active level (low level in the present embodiment) so that the ICs 11 to 13 can perform serial communication. Put it in a state. The active level may be a high level.

  Next, the microcomputer 10 starts outputting the transmission data Tx as shown in FIG. The transmission data Tx includes various commands, data, addresses (addresses of memories and registers in the communication target IC), and the like. For example, as a command, the microcomputer 10 outputs a read command as a command when reading data held by the communication target IC, and outputs a write command when writing data into the communication target IC. Further, the microcomputer 10 outputs, for example, a command for executing a function included in the communication target IC as a command.

  In synchronization with the output start of the transmission data Tx described above, the microcomputer 10 selects an IC (any one of IC-A11, IC-B12, IC-C13, etc.) to be selected as a communication partner from the slave select signal output terminal. Starts to output binary data (slave select data) corresponding to.

  The microcomputer 10 outputs a clock signal Clock to each of the ICs 11 to 13 after outputting the transmission data Tx and the slave select data. Then, each of the ICs 11 to 13 takes in the transmission data Tx and the slave select data at the timing when the clock signal Clock falls. However, the data capture timing in each of the ICs 11 to 13 may be when the clock signal Clock rises. The slave select data will be described in detail below.

  In the communication system according to the present embodiment, slave select data that changes in different patterns is assigned in advance to each of the ICs 11 to 13 while a predetermined number of clock signals Clock are output. When each IC receives the same data as the slave select data assigned to itself in the slave select data transmission period defined by the predetermined number of clock signals Clock, it is selected that the IC is selected as the communication target of the microcomputer 10. recognize.

  An example of the assignment of the slave select data is shown in FIG. In the example shown in FIG. 3, the number of ICs to which the slave select data is assigned is 7, and an example is shown in which 3-bit data is used as the slave select data. Therefore, in the example shown in FIG. 3, the transmission period of the slave select data corresponds to three clock signals Clock.

  In the example illustrated in FIG. 3, slave select data “001” is assigned to the IC-A 11. Therefore, if the slave select data is fetched at three consecutive data fetch timings when the clock signal Clock falls, and the value is “001”, the IC-A 11 is selected as a communication target. . In this case, the IC-A 11 continues the communication operation even after the elapse of the slave select data transmission period, and exchanges the transmission data Tx and the reception data Rx with the microcomputer 10.

  Similarly, in the example shown in FIG. 3, slave select data “010” is assigned to IC-B12, slave select data “011” is assigned to IC-C13, and IC-D14 is assigned. “100” slave select data is assigned, “101” slave select data is assigned to IC-E15, “110” slave select data is assigned to IC-F16, and IC-G17 is assigned. Slave select data of “111” is assigned.

  Thus, since unique slave select data is assigned to each of the ICs 11 to 17, the microcomputer 10 transmits the slave select data corresponding to the desired IC by the slave select signal SS, thereby enabling communication. An IC to be a target can be arbitrarily selected.

  Here, in this embodiment, data of “000” in which all bits are at the active level of the slave select signal SS is not used as slave select data. For this reason, if the slave select signal line is short-circuited to the ground potential corresponding to the active level, communication with any of the ICs 11 to 17 is not continued. Therefore, it is possible to reliably prevent at least communication with an IC that is not a communication target from being established and the IC to behave unintentionally.

  Next, as shown in FIG. 4, the case where the microcomputer 10 selects the IC-A 11 as a communication target is taken as an example. The processing in the microcomputer 10, the processing in each of the ICs 11 to 17, and the IC- selected as the communication target The processing in A11 will be described using the flowcharts of FIGS.

First, processing in the microcomputer 10 will be described based on the flowchart of FIG.
When starting communication with the IC-A 11, the microcomputer 10 first sets the slave select signal SS to an active level in step S100. Thereby, all the ICs 11 to 17 including the IC-A 11 are in a communicable state.

  Next, in step S110, the microcomputer 10 starts outputting the transmission data Tx and starts outputting slave select data for selecting the IC-A11. Since the slave select data of the IC-A11 is “001”, immediately after the start of the output of the slave select data, the slave select signal SS is maintained at the low level as shown in FIG. After the transmission data Tx and slave select data are output, the microcomputer 10 lowers the clock signal Clock in step S120 after the time necessary for the levels of these data to stabilize has elapsed. Then, all the slave communication processing shown in step S130 is executed by each of the ICs 11 to 17, and the transmission data Tx and the slave select data are captured.

  This all-slave communication process will be described with reference to the flowchart of FIG. In the all slave communication processing, first, in step S300, it is determined whether or not the slave select signal SS is activated. If it is determined that it has not been activated, the process proceeds to step S370, and the communication process with the microcomputer 10 is terminated. On the other hand, if it is determined that the slave select signal SS is activated, the process proceeds to step S310.

  In step S310, each of the ICs 11 to 17 determines whether or not the clock signal Clock applied to each clock signal input terminal has fallen. At this time, when it is determined that the clock signal Clock has not fallen, the process of S310 is repeatedly executed to wait for the fall of the clock signal Clock. On the other hand, if it is determined that the clock signal Clock has fallen, the process proceeds to step S320. In step S320, reception processing of transmission data Tx and slave select data is performed in each IC 11-17. In this reception process, data for one bit of transmission data Tx and slave select data is captured.

  In step S330, reception data Rx to be received by the microcomputer 10 is output. As the reception data Rx, each of the ICs 11 to 17 transmits data responding to the command included in the transmission data Tx, or transmits dummy data when there is no response data to be transmitted.

  During the slave select data transmission period, the communication processing operation is performed in all the ICs 11 to 17. Therefore, the reception data Rx is output from all the ICs 11 to 17. In this case, if the ICs 11 to 17 output different received data Rx, the received data Rx received by the microcomputer 10 may become unstable. For this reason, the same reception data Rx is output from each of the ICs 11 to 17 during the transmission period of the slave select data, that is, during the period when all the ICs 11 to 17 perform the communication processing operation.

  In the subsequent step S340, it is determined whether or not the reception of the slave select data is completed by each of the ICs 11 to 17 depending on whether or not the slave select data has been fetched by a predetermined number of clocks. . At this time, if it is determined that the reception of slave select data has not been completed, the processing from step S310 is repeated. In this case, each of the ICs 11 to 17 cannot yet determine which IC has been selected as a communication target. However, it is possible to stop communication processing when it becomes clear that it is not selected in the process of receiving slave select data bit by bit without waiting for reception of all slave select data. It is. On the other hand, if it is determined that the reception of the slave select data is completed, the process proceeds to step S350.

  In step S350, each IC 11-17 determines whether it has been selected as a communication target based on whether the received slave select data matches the slave select data assigned to each IC 11-17. To do. At this time, if it is determined that it has been selected, the process proceeds to step S360 to wait for the next falling of the clock signal Clock in order to continue communication with the microcomputer 10. On the other hand, if it is determined that it has not been selected, the process proceeds to step S370, and the communication process with the microcomputer 10 is terminated.

  In step S370, the IC that has completed the communication process is prohibited from resuming the communication process even if the slave select signal SS becomes active after the slave select data transmission period ends. This prohibition of resuming communication processing is canceled when the microcomputer 10 completes communication with the selected IC-A 11 and deactivates the slave select signal SS. Accordingly, the microcomputer 10 can communicate only with the selected communication target IC-A 11 after the slave select data transmission period has elapsed.

  Returning to the flowchart of FIG. 5 again, the description will be continued. The microcomputer 10 waits for a predetermined time for all the slave communication processes described above, and then raises the clock signal Clock in step S140. At this time, the reception data Rx output from each of the ICs 11 to 17 is stable. Therefore, the microcomputer 10 performs reception processing of the reception data Rx in step S150 with the rise of the clock signal Clock. In this reception process, one bit of data of the reception data Rx is captured.

  In a succeeding step S160, it is determined whether or not the transmission of the slave select data is completed. At this time, if it is determined that the transmission of slave select data has not been completed, the processing from step S110 is repeated. On the other hand, if it is determined that the transmission of the slave select data is completed, the process proceeds to step S170. At this point, IC-A11 has already been selected as a communication target. Further, the ICs 12 to 17 other than the IC-A 11 are in a state where the history processing is stopped.

  In step S170, the microcomputer 10 holds the slave select signal SS at an active level in order to continue communication with the IC-A11. In the following step S180, 1-bit transmission data Tx is output, and in step S190, the clock signal is lowered. Then, the selected slave communication process shown in step S200 is executed by the selected IC-A11, so that the reception process of the transmission data Tx is performed by the IC-A11.

  This non-selected slave communication process will be described with reference to the flowchart of FIG. In the selected slave communication process, first, in step S400, it is determined whether or not the slave select signal SS is activated. If it is determined that it is not activated, the process proceeds to step S450, and the communication process with the microcomputer 10 is terminated. On the other hand, if it is determined that the slave select signal SS is activated, the process proceeds to step S410.

  In step S410, the selected IC-A 11 determines whether or not the clock signal Clock applied to the clock signal input terminal has fallen. At this time, when it is determined that the clock signal Clock has not fallen, the process of S410 is repeatedly executed to wait for the fall of the clock signal Clock. On the other hand, if it is determined that the clock signal Clock has fallen, the process proceeds to step S420. In step S420, reception processing of transmission data Tx is performed in IC-A11. By this reception processing, data for one bit of transmission data Tx is captured.

  In step S430, the IC-A 11 outputs reception data Rx to be received by the microcomputer 10. In subsequent step S440, the IC-A 11 determines whether or not the transmission of all the reception data Rx has been completed. In this determination process, if it is determined that transmission of all received data Rx has not been completed, the process from step S410 is repeated. On the other hand, if it is determined that the transmission of all the received data Rx is completed, the process proceeds to step S450, and the communication process with the microcomputer 10 is terminated.

  Returning to the flowchart of FIG. 5 again, the description will be continued. The microcomputer 10 waits for a predetermined time for the selected slave communication process described above, and then raises the clock signal Clock in step S210. At this time, the reception data Rx output from the selected IC-A 11 is stable. Therefore, the microcomputer 10 performs reception processing of the reception data Rx in step S220 with the rise of the clock signal Clock. In this reception process, one bit of data of the reception data Rx is captured.

  In the subsequent step S230, it is determined whether or not all data communication processing, that is, transmission data Tx transmission processing and reception data Rx reception processing has been completed. At this time, if it is determined that the communication processing of all data has not been completed yet, the processing from step S180 is repeated. On the other hand, if it is determined that the communication process for all data has been completed, the process proceeds to step S240. In step S240, the slave select signal SS is set to an inactive level. As a result, the prohibition of restart of communication processing of each IC 12 to 17 that has not been selected is cancelled.

  In subsequent step S250, it is determined whether or not there is an IC that should be the next communication target. If it is determined that there is an IC that should be the communication target, the processing from step S100 is repeated. On the other hand, if it is determined that there is no IC to be communicated, the microcomputer 10 ends the process shown in the flowchart of FIG.

  According to the above-described communication system according to the present embodiment, the microcomputer 10 should be selected as a communication target by the slave select signal SS instead of adding information indicating the communication target IC to the transmission data Tx. Outputs slave select data corresponding to the IC. Therefore, unlike the prior art, the number of bits of data that can be transmitted does not decrease by the amount of information indicating the communication target. Furthermore, even if the slave select signal line 23 is made common to a plurality of ICs 11 to 17, it is possible to reliably select an IC to be communicated by the slave select data.

  Further, in the communication system described above, a pattern other than the pattern that is all in the active level is used as slave select data. For this reason, for example, even if the slave select signal line 23 is short-circuited to a potential corresponding to the active level, none of the ICs 11 to 17 is selected as a communication target, so the microcomputer 10 erroneously communicates with an IC that is not a communication target. Can be prevented.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. .

(Modification 1)
For example, the communication processing of the microcomputer 10 shown in the flowchart of FIG. 5 may be modified as shown in FIG. That is, the step of determining whether or not the reception data Rx cannot be received between the reception processing of the reception data Rx in step S220 and the communication completion determination processing of all data in step S230 in the flowchart of FIG. S222 may be provided. If it is determined in step S222 that the received data Rx cannot be received, the process may proceed to step S224 to detect that a failure has occurred.

  As described above, in the communication system according to the present embodiment, data is transmitted and received between the microcomputer 10 and the plurality of ICs 11 to 17 or the ICs selected as communication targets at the same time. Nevertheless, if the microcomputer 10 cannot receive the received data Rx, a failure occurs in which the slave select signal line 23 is shorted to a potential corresponding to the active level, and none of the ICs 11 to 17 is selected as a communication target. Alternatively, there is a high possibility that some failure occurs in the IC selected as the communication target and the reception data Rx cannot be output. As described above, the microcomputer 10 can detect that a failure has occurred in the communication system based on the fact that the reception data Rx cannot be received.

(Modification 2)
Further, the all slave communication process shown in the flowchart of FIG. 6 may be modified as shown in FIG. That is, step S342 for determining whether or not there is an abnormality in the received slave select data between the slave selection data reception completion determination process in step S340 and the selected determination process in step S350 in the flowchart of FIG. May be added. If it is determined in step S342 that there is an abnormality in the slave select data, the process proceeds to step S370, and the communication processing in each of the ICs 11 to 17 is terminated.

  As described above, in this embodiment, data in which all bits are at the active level of the slave select signal SS is not used as slave select data. Accordingly, in the event that each IC 11-17 receives slave select data in which all bits are at an active level, this can be clearly regarded as abnormal, so the communication processing in each IC 11-17 is terminated.

  However, also in the all slave communication processing shown in FIG. 6, when the device itself is not selected as a communication target, the communication processing is terminated via step S350 → step S370. For this reason, also in the all-slave communication process of FIG. 6, when the slave select data in which all the bits are at the active level is received, the communication process is finished in each of the ICs 11 to 17. The example shown in FIG. 9 is for more reliably ending the communication processing of each of the ICs 11 to 17 when the slave select data is abnormal.

(Modification 3)
Further, in the above-described embodiment, the reception process in each of the ICs 11 to 17 is performed at the falling timing of the clock signal Clock, and the reception process in the microcomputer 10 is performed at the rising timing of the clock signal Clock. However, the reception processing of the microcomputer 10 and each of the ICs 11 to 17 can be performed at exactly the same timing in conjunction with the falling or rising of the clock signal.

10 Microcomputer (host device)
11 IC-A (slave device)
12 IC-B (slave device)
13 IC-C (slave device)
20 clock signal line 21 first communication line 22 second communication line 23 slave select signal line

Claims (9)

A communication system in which one host device (10) and a plurality of slave devices (11, 12, 13) perform clock synchronous serial communication,
Between the host device and the plurality of slave devices,
A common clock signal line (20) for transmitting a clock signal from the host device to the plurality of slave devices;
A common first communication line (21) for transmitting data from the host device to the plurality of slave devices in synchronization with the clock signal;
A common second communication line (22) for transmitting data from the plurality of slave devices to the host device in synchronization with the clock signal;
The host device is connected to a slave select signal line (23) for transmitting a slave select signal for selecting a slave device as a communication partner;
The slave select signal line is shared by the plurality of slave devices,
The plurality of slave devices are pre-assigned binary data that changes in different patterns while a predetermined number of clock signals are output,
The communication system, wherein the host device outputs the binary data corresponding to the slave device to be selected in response to the slave select signal.   2. The communication system according to claim 1, wherein the host device uses a pattern other than a pattern that becomes an active level of the slave select signal as the binary data.   3. The communication system according to claim 2, wherein the plurality of slave devices end communication operation when receiving binary data having a pattern that is all at the active level as the binary data. 4.   When data transmission / reception is performed between the host device and the slave device at the same time, the host device indicates that a failure has occurred based on not receiving data from the slave device. The communication system according to claim 2, wherein the communication system is detected.   When the host device communicates with any of the plurality of slave devices, first, the level of the slave select signal is set to an active level of either High or Low at which the plurality of slave devices start communication operations. 5. The binary data is output as the slave select signal, and the level of the slave select signal is set to the active level after the binary data is output. The communication system according to claim 1.   The plurality of slave devices stop communication operation even when the slave select signal is at the active level when it is determined that the slave device is not selected by the binary data as the slave select signal. The communication system according to claim 5.   6. The communication system according to claim 5, wherein the slave device selected by the binary data stops communication operation when communication of all data to be communicated is completed.   8. The host device according to claim 5, wherein when the communication with the slave device selected by the binary data is completed, the level of the slave select signal is set to an inactive level. The communication system described. The host device and the plurality of slave devices transmit and receive data at the same time in synchronization with the clock signal,
The plurality of slave devices each transmit the same data to the host device via the second communication line until the output of the binary data from the host device is completed. The communication system according to any one of 8.

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