JP2015170081A - simulation device and simulation program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a SW model and a HW model to be operated in cooperation with each other with good timing accuracy without requiring special modification to the SW model and the HW model of a verification object system.SOLUTION: An ISS model 10 executes instructions defined in a SW model. An execution number counting unit 20 counts the number of execution times of operation caused by other instructions executed before a HW instruction issued to a HW model among executed instructions. An execution time calculation unit 30 calculates an execution time for the other instructions on the basis of the counted number of execution times. A timing adjusting unit 40 delays timing for an interface unit to relay the HW instruction to the HW model depending on the calculated execution time. A function/pin interface conversion unit 50 relays communication between the SW model and the HW model according to control of the timing adjusting unit 40.

Description

  The present invention relates to a simulation apparatus that operates a software (hereinafter referred to as SW) model having no time concept and a hardware (hereinafter referred to as HW) model having a time concept in cooperation with each other.

  There is a system composed of an HW including a processor and an SW operating on the HW. There is a simulation apparatus that verifies the operation of this system by operating in parallel a HW model in which the HW constituting this system is described in a system-level design language of a C-based language and a SW that operates on the processor of this system.

  Patent Documents 1 and 2 and Non-Patent Document 1 describe techniques for co-simulating an SW model having no time concept and an HW model having a time concept.

  Patent Documents 1 and 2 include means for performing SW model execution scheduling (pseudo-OS), means for performing HW model execution scheduling, and means for communicating between the HW model and the SW model to calculate a pseudo-OS. It describes that the start of the next simulation process is delayed according to the processing time. As a result, a time concept (processing delay) is given to the execution of the SW model so that the SW model and the HW model can perform a cooperative operation in the same timing and execution order as the actual machine.

  Non-Patent Document 1 describes that in order to consider the SW processing time, a certain block of SW parts is recognized, control points are inserted at certain intervals, and the time between control points is entered. Thereby, the concept of time is given to the simulation of the SW model so that the cooperative operation with the HW model can be performed.

JP 2009-26113 A JP 2012-27952 A

"STARC developed on the basis of SystemC, a high-speed hardware-software collaborative verification technology," Nikkei Microdevices, January 2005, p. 106-107

  However, in the techniques described in Patent Documents 1 and 2 and Non-Patent Document 1, the processing time of the software SW is calculated from the performance difference between the system to be verified and the simulation device as time (delay) information given to the SW model. Use things. For this reason, there is a problem that an error becomes large in consideration of processing time caused by internal operation of the CPU such as cache operation and access time to an external memory.

  In addition, since the techniques described in Patent Documents 1 and 2 use a pseudo OS, they cannot be used for debugging the entire system including the OS. Furthermore, since the technique described in Non-Patent Document 1 requires modification of the SW model, there is a problem that it cannot be used for debugging of the SW model although it can be operated in cooperation.

  An object of the present invention is to operate the SW model and the HW model in a coordinated manner with high timing accuracy without requiring any special correction of the SW model and the HW model of the system to be verified.

The simulation apparatus according to the present invention is
A simulation device that operates a SW model (software model) having no time concept and a HW model (hardware model) having a time concept in cooperation with each other,
An SW model execution unit for executing an instruction defined in the SW model;
A counting unit that counts the number of executions of operations generated by other commands executed before the HW command issued to the HW model among the commands executed by the SW model execution unit;
An execution time calculation unit that calculates an execution time of the other instruction based on the number of executions counted by the counting unit;
An IF unit that relays communication between the SW model and the HW model;
And a timing adjustment unit that delays the timing at which the IF unit relays the HW instruction to the HW model according to the execution time calculated by the execution time calculation unit.

  The simulation apparatus according to the present invention calculates the execution time of an instruction based on the number of executions of the instruction executed by the SW model execution unit, and delays the issue of the instruction to the HW model according to the calculated execution time. Therefore, the SW model and the HW model can be operated in a coordinated manner with high timing accuracy without requiring any special correction to the SW model and the HW model.

1 is a configuration diagram of a simulation apparatus 100 according to Embodiment 1. FIG. The figure which shows the classification | category of the mounting language of each model shown in FIG. The figure which shows an example of an operation | movement flow. The figure which shows the timing chart in case a real machine operate | moves under a precondition. The figure which shows operation | movement of the execution frequency counting part 20 from the start of simulation until an external IO access is performed. The figure which shows operation | movement of the execution time calculation part 30. The figure which shows operation | movement of the timing adjustment part 40 and the function / pin IF conversion part 50 when the access request with respect to the HW model 70A is made from the external IO model 15. The figure which shows a series of operation | movement demonstrated based on FIGS. FIG. 3 is a configuration diagram of a simulation apparatus 100 according to a second embodiment. The figure which shows the relationship between the additional timing information calculation part 80 and another function part. The figure which shows the operation example in case there exists 1 step | paragraph bus buffer in the external IO part of a real machine. The figure which shows that the simulation apparatus 100 can perform the simulation equivalent to FIG. FIG. 3 is a diagram showing an example of a hardware configuration of the simulation apparatus 100 shown in the first and second embodiments.

Embodiment 1 FIG.
FIG. 1 is a configuration diagram of a simulation apparatus 100 according to the first embodiment.
The simulation apparatus 100 includes an ISS (Instruction Set Simulator) model 10 (SW model execution unit), an execution count counting unit 20 (counting unit), an execution time calculation unit 30, a reference value storage unit 31, a timing adjustment unit 40, and a function / pin. An IF conversion unit 50 (IF unit), a SW model 60, and a HW model 70 (HW models 70A to 70Z) are provided.

The ISS model 10 operates the SW model 60 of the system to be verified. The ISS model 10 simulates the execution of the SW model 60 in the same manner as the actual machine of the system to be verified. The ISS model 10 includes a CPU core model 11, a CPU bus model 12, an internal memory / peripheral device model 13, a cache model 14, and an external IO model 15 simulating each component of an actual machine.
The function models 11 to 15 included in the ISS model 10 and the SW model 60 are modeled using a high-level language such as C language, and have no time concept in the simulation.

The execution count counting unit 20 monitors the behavior of each model included in the ISS model 10 and counts the number of executions of operations generated by the instructions of the SW model 60 executed by the ISS model 10.
The execution frequency counting unit 20 includes, for example, the CPU core model access count 21 for the internal memory / peripheral device model 13, the cache hit / miss count 22 generated in the cache model, and the execution count 23 of each instruction executed in the CPU core model. The number of executions of operations that require processing time in the actual CPU, such as the number of accesses 24 of the CPU core model to the external IO model, is counted.
The number of executions 21 to 24 is counted by subtracting what is hidden when pipeline execution is performed in consideration of an instruction execution sequence, cache hit / miss, and the like. Further, the counted number of executions 21 to 24 is reset to 0 by a counted value reset instruction 51 output from a function / pin IF conversion unit 50 described later.

The execution time calculation unit 30 applies a reference value stored in a reference value storage unit 31 to be described later to the execution number of each execution number 21 to 24 counted by the execution number counting unit 20, and the actual CPU The execution time 32 is calculated.
The reference value storage unit 31 is a storage device that stores the execution time per time in the actual CPU for each type of operation counted by the execution count counting unit 20.

  Based on the execution time 32, the timing adjustment unit 40 controls the timing at which the function / pin IF conversion unit 50 issues an instruction to the HW model 70.

The function / pin IF conversion unit 50 converts an access request (execution of a function such as C language) from the ISS model 10 to the HW model 70 into an operation of a pin capable of IF (interface) with the HW model 70.
The function / pin IF conversion unit 50 is modeled in a language that can describe both the SW model 60 and the HW model 70, such as SystemC.

  The SW model 60 is a SW model to be verified. The SW model 60 is modeled including the OS. As described above, the SW model 60 is modeled using a high-level language such as C language, and has no time concept in the simulation.

  The HW model 70 is a HW model to be verified. The HW model 70 is modeled by HDL (Hardware Description Language), and has a time concept in the simulation.

FIG. 2 is a diagram showing the classification of the implementation language of each model shown in FIG.
Here, the ISS model 10 (including internal models), the execution count counting unit 20, the execution time calculation unit 30, the reference value storage unit 31, and the timing adjustment unit 40 are described in C language. The function / pin IF conversion unit 50 is described in SystemC. The HW model 70 is described in Verilog, which is one of HDL.
This classification is shown to simplify the following description, and does not limit the implementation language of each model.

How the SW model 60 and the HW model 70 cooperate in the simulation apparatus 100 will be described.
First, after explaining the preconditions, a state in which the SW model 60 and the HW model 70 operate in cooperation between the real machine and the simulation apparatus 100 under the preconditions will be described.

<Prerequisites>
(Condition 1) It is assumed that the SW model 60 is stored in the internal memory of the ISS model 10 / the internal memory of the peripheral device model 13, and the CPU core model 11 reads and executes an instruction from the internal memory.
(Condition 2) The reference value storage unit 31 has a uniform execution time of each instruction executed by the CPU core model 11, 5 an internal memory access time, 1 a cache hit access time, and an external IO model is an ISS model. The time until the access is issued to the outside of 10 is 2, and the time from when the access request is issued from the function / pin IF conversion unit 50 until the HW model 70 returns a response is 10 (unit: ns).
(Condition 3) In order to simplify the explanation of the operation of the SW model 60, the CPU core model 11 executes the nine external instructions after executing nine instructions (instructions A to I) as shown in the operation flow shown in FIG. Assume a situation in which the model 15 is accessed and one instruction (instruction J) is subsequently executed after the access to the external IO model 15 is completed. It is assumed that there are 9 cache accesses (hits) and 1 internal memory access when executing a total of 10 instructions (instructions A to J).
Note that these preconditions are defined for convenience in order to simplify the description, and are not limited to these contents.

<Operation on actual machine>
FIG. 4 is a diagram showing a timing chart when the actual machine operates under the preconditions.
In FIG. 4, the number written above represents time [ns]. Also, Ca represents “cache access” shown in FIG. 3, Ma is “internal memory access”, A to J are “execution of instructions A to J”, external IO is “external IO access”, and HW is “ HW operation ".
As a result, the actual machine takes 28 [ns] to execute the precondition.

<Operation in Simulation Device 100>
FIG. 5 is a diagram illustrating the operation of the execution count counting unit 20 from the start of the simulation until the external IO access is executed.
In the ISS model 10, instruction execution and memory access to be simulated do not have a time concept and are only executed in order. The execution count counting unit 20 counts the number of executions of these operations (instruction execution and memory access). However, by monitoring the execution order (sequence) of each operation, it is concealed as a result of the pipeline operation in the actual machine. The movement is deducted and counted. As a result, as shown in FIG. 5, the cache access is counted 8 times, internal memory access 1 time, instruction execution 1 time, and external IO access 1 time.

FIG. 6 is a diagram illustrating the operation of the execution time calculation unit 30.
The execution time calculation unit 30 inputs the number of executions of each operation counted by the execution count counting unit 20 and subtracts the execution time per operation stored in the reference value storage unit 31 while counting all the counted operations. The execution time on the actual machine is calculated. In this example, the cache access is 8 times × 1 [ns], the internal memory access is 1 time × 5 [ns], the instruction execution is 1 time × 1 [ns], and the external IO access is 1 time × 2 [ns]. ] To 15 [ns].

FIG. 7 is a diagram illustrating operations of the timing adjustment unit 40 and the function / pin IF conversion unit 50 when an access request is made from the external IO model 15 to the HW model 70A.
An access request (HW instruction) from the external IO model 15 is first issued to the function / pin IF conversion unit 50 (1). When the access request is issued, the function / pin IF conversion unit 50 issues a timing adjustment start instruction to the timing adjustment unit 40 (2).

  The timing adjustment unit 40 controls the timing at which the function / pin IF conversion unit 50 issues an access request to the HW model 70A. When the timing adjustment unit 40 receives the timing adjustment start instruction, the execution time (here, 15 [ns]) calculated by the execution time calculation unit 30 has elapsed using an internal time measurement timer (counter). Make sure. When the execution time elapses, the timing adjustment unit 40 issues an operation start instruction to the function / pin IF conversion unit 50 (3).

Receiving the operation start instruction, the function / pin IF conversion unit 50 starts converting the access request (function operation) from the external IO model 15 into a pin operation capable of IF with the HW model 70A (4).
Here, the function operation is an operation of a function defined in C language such as read (HW_A), for example. The argument HW_A of the read () function is a special identifier (for example, address information) assigned to the HW model 70A. On the other hand, the pin operation is an input / output pin operation necessary for the operation of the HW model 70A. For example, an access enable signal indicating an access request issue state, a read / write signal indicating read / write control, It consists of an address signal indicating an address to be accessed, a data signal for exchanging read / write data, and the like.

The function / pin IF conversion unit 50 converts the function operation into a pin operation and performs the IF with the HW model 70A (5).
When the function / pin IF conversion unit 50 obtains, for example, a data value of 0xABCD as a result obtained by the pin operation, it returns this as a response to the function operation (read (HW_A)) of the external IO model 15 (6). . At the same time, the function / pin IF conversion unit 50 issues a count value reset instruction 51 to the execution count counting unit 20 to reset the count value to 0 (7).

FIG. 8 is a diagram illustrating a series of operations described based on FIGS. 5 to 7.
The upper part of FIG. 8 shows the operation in the actual machine (the same as that shown in FIG. 4), and the lower part of FIG. 8 shows the operation in the simulation apparatus 100.
The ISS model 10 executes up to “external IO access” in the operation flow shown in FIG. In parallel, the execution count counting unit 20 counts the number of instruction executions of the ISS model 10 and the like. When the operation of the ISS model 10 reaches “external IO access”, the external IO model 15 of the ISS model 10 issues an access request (read (HW_A)) to the function / pin IF conversion unit 50. After the access request is issued, the operation of the ISS model 10 (external IO model 15) is in a response waiting state (stopped) until there is a response from the function / pin IF conversion unit 50. On the other hand, the execution time calculation unit 30 calculates the execution time based on the number of executions counted by the execution number counting unit 20 (here, calculated as 15 [ns]). The series of operations up to this point are executed with zero time elapsed in the simulation.

  Subsequently, the function / pin IF conversion unit 50 issues a timing adjustment start instruction to the timing adjustment unit 40. When the timing adjustment unit 40 receives the timing adjustment start instruction, the timing adjustment unit 40 waits for the execution time (15 [ns] in this case) calculated by the execution time calculation unit 30 to elapse, and then operates the function / pin IF conversion unit 50. Issue start instructions. When the operation start instruction is issued, the function / pin IF conversion unit 50 converts the function operation (read (HW_A)) into a pin operation and performs IF with the HW model 70A.

The HW model 70A returns a response to the access request after 10 [ns] as a result of the pin operation converted by the function / pin IF conversion unit 50. When the access response is returned, the ISS model 10 (external IO model 15) that has been stopped waiting for the access response resumes its operation. At the same time, the function / pin IF conversion unit 50 issues a count value reset instruction 51 to the execution count counting unit 20. As a result, the number of executions of all operations counted by the execution number counting unit 20 is reset to zero.
Thereafter, the same operation is repeated every time an external IO access occurs.

  By operating as described above, as shown in FIG. 8, the concept of time passage is given to the operation of the SW model 60 without the concept of time passage, and the simulation is executed. Therefore, the simulation can be executed by coordinating the SW70 model and the HW model 70 at the same operation timing as the actual machine.

  In particular, it is possible to operate the SW model 60 and the HW model 70 in a coordinated manner with good timing accuracy without specially modifying the SW model 60 and the HW model 70.

Embodiment 2. FIG.
In the second embodiment, a description will be given of simulating the operation of a bus buffer mounted on an external IO of a real machine.
In the second embodiment, description of the same parts as those of the first embodiment will be omitted, and different parts from the first embodiment will be described.

FIG. 9 is a configuration diagram of the simulation apparatus 100 according to the second embodiment.
The simulation apparatus 100 shown in FIG. 9 is different from the simulation apparatus 100 according to the first embodiment shown in FIG. 1 in that an additional timing information calculation unit 80 (additional timing adjustment unit) is provided. The additional timing information calculation unit 80 simulates the operation of the bus buffer mounted on the external IO of the actual machine.

FIG. 10 is a diagram illustrating a relationship between the additional timing information calculation unit 80 and other functional units.
The additional timing information calculation unit 80 receives the HW operation information from the function / pin IF conversion unit 50 (1). The HW operation information is information indicating whether or not the HW model 70 connected to the tip of the function / pin IF conversion unit 50 is performing an access response process. The additional timing information calculation unit 80 has a buffer model 81 (buffer unit) that simulates a buffer included in an external IO portion of an actual machine to be simulated by the simulation apparatus. The additional timing information calculation unit 80 calculates additional timing information from the HW operation information and the buffer model 81, and outputs the additional timing information to the function / pin IF conversion unit 50 (2). The completion of the operation of the function / pin IF conversion unit 50 is extended by the additional timing information, and the timing for returning a response to the external IO model 15 is extended.

FIG. 11 is a diagram showing an operation example when there is a one-stage bus buffer in the external IO portion of the actual machine.
FIG. 11 shows a case where the external IO issues two write requests (W1 and W2) to the HW. As a precondition for explanation, the external IO write request can be issued in a minimum of one cycle. . It is assumed that the HW takes 5 cycles to return a response to the write request from the external IO.

Details of the operation of FIG. 11 will be described.
At time 1, the external IO issues a write request (W1) to the HW. At time 2, the HW model 70 starts an operation for the write request (W1). This operation continues until time 6, and the HW cannot accept a new request. On the other hand, since the external IO has one stage of bus buffer, the next operation can be started without waiting for a response to the write request (W1) after issuing the write request (W1). That is, in the first embodiment, when a request is issued from the external IO to the HW, the external ID cannot execute the next operation until there is a response to the request. However, since one bus buffer is provided here, even if one request is issued, the next operation can be started without waiting for a response.
As a result of the external IO starting the next operation, a write request (W2) is issued at time 5. However, since the HW is processing the write request (W1), the start of the write request (W2) is waited until time 7. In other words, a new request has been issued, but the external IO buffer has been used up at time 6, and the next write request cannot be processed. Therefore, the write request (W2) cannot be completed at time 6, and the start of the write request (W2) is extended until time 7.
Subsequently, since the HW has completed the processing of the write request (W1) at the time 7 and the next write request can be accepted, the processing of the write request (W2) that has been waiting to start is started. At the same time, the external IO starts the next process.

FIG. 12 is a diagram showing that the simulation apparatus 100 can perform a simulation equivalent to FIG.
In FIG. 12, the key-shaped arrow represents an operation equivalent to “waiting for 15 [ns] elapsed by the timing adjustment unit 40” described in FIG. Further, the hexagons shaded with diagonal lines are “execution of instructions by the ISS model 10”, “counting of execution times by the execution number counting unit 20”, and “execution time calculation by the execution time calculating unit 30” described in FIG. Represents the equivalent operation.

At time 1, a write request (W 1) is issued to the HW model 70 by the operation of the function / pin IF conversion unit 50.
At time 2, the additional timing information calculation unit 80 takes into account the remaining buffer capacity (the write remaining request (W 1) at time 1, so the remaining buffer capacity is 0 at time 2) and the operation status of the HW model 70. Calculate whether additional timing information is needed. In the case of FIG. 12, since the write request (W1) is entered into the buffer at the time 2 and the ISS model 10 is ready to start the next operation, no additional timing information is output.

  Since additional timing information is not output at time 2, the function / pin IF conversion unit 50 returns a response to the external IO model 15 of the ISS model 10. When the response is returned, the ISS model 10 resumes operation and executes some instruction. As a result of the execution, a write request (W2) is issued. In the case of FIG. 12, the operation time for 3 cycles (time 2 to 4) is counted until the write request (W2) is issued. The adjustment unit 40 adds a delay. At time 5, W2 is issued to the HW model 70.

  At time 6, since there is no remaining buffer capacity and the write request (W1) is still being processed, additional timing information is output. By outputting the additional timing information, the function / pin IF conversion unit 50 extends the completion of the operation until there is no additional timing information, and does not return a response to the external IO model 15 until there is no additional timing information.

  At time 7, processing for the write request (W1) of the HW model 70 is completed, and additional timing information is lost. As a result, the function / pin IF conversion unit 50 returns a response to the write request (W2) to the external IO model 15 of the ISS model 10, and the operation of the ISS model 10 is resumed.

  Thereafter, by repeating these operations, when the external IO model 15 has a buffer, it is possible to perform a co-simulation at the same timing as the actual machine.

FIG. 13 is a diagram illustrating an example of a hardware configuration of the simulation apparatus 100 illustrated in the first and second embodiments.
The simulation apparatus 100 is a computer. Each element of the simulation apparatus 100 can be realized by a program.
As a hardware configuration of the simulation apparatus 100, an arithmetic device 901, an external storage device 902, a main storage device 903, a communication device 904, and an input / output device 905 are connected to the bus.

  The arithmetic device 901 is a CPU (Central Processing Unit) that executes a program. The external storage device 902 is, for example, a ROM (Read Only Memory), a flash memory, a hard disk device, or the like. The main storage device 903 is, for example, a RAM (Random Access Memory). The communication device 904 is, for example, a communication board. The input / output device 905 is, for example, a mouse, a keyboard, a display device, or the like.

The program is normally stored in the external storage device 902, and is loaded into the main storage device 903 and sequentially read into the arithmetic device 901 and executed.
The program is a program that realizes the functions described as the ISS model 10, the execution count counting unit 20, the execution time calculation unit 30, the timing adjustment unit 40, the function / pin IF conversion unit 50, the SW model 60, and the HW model 70. is there.
Furthermore, an operating system (OS) is also stored in the external storage device 902. At least a part of the OS is loaded into the main storage device 903, and the arithmetic device 901 executes the above program while executing the OS.
In the description of the first and second embodiments, the information that the reference value storage unit 31 stores, the ISS model 10, the execution count counting unit 20, the execution time calculation unit 30, the timing adjustment unit 40, the function / pin IF Information described as being output from the conversion unit 50, the SW model 60, and the HW model 70 is stored in the main storage device 903 as a file.

  Note that the configuration of FIG. 13 is merely an example of the hardware configuration of the simulation apparatus 100, and the hardware configuration of the simulation apparatus 100 is not limited to the configuration illustrated in FIG. 13 and may be other configurations. .

  10 ISS model, 20 execution count counting unit, 30 execution time calculation unit, 31 reference value storage unit, 40 timing adjustment unit, 50 function / pin IF conversion unit, 60 SW model, 70 HW model, 80 additional timing information calculation unit, 81 Buffer model, 100 Simulation device.

Claims (5)

A simulation device that operates a SW model (software model) having no time concept and a HW model (hardware model) having a time concept in cooperation with each other,
An SW model execution unit for executing an instruction defined in the SW model;
A counting unit that counts the number of executions of operations generated by other commands executed before the HW command issued to the HW model among the commands executed by the SW model execution unit;
An execution time calculation unit that calculates an execution time of the other instruction based on the number of executions counted by the counting unit;
An IF unit that relays communication between the SW model and the HW model;
A simulation apparatus comprising: a timing adjustment unit that delays the timing at which the IF unit relays the HW instruction to the HW model according to the execution time calculated by the execution time calculation unit. When the operation of the HW model for the relayed HW command is completed, the IF unit returns a response to the SW model execution unit,
The simulation apparatus according to claim 1, wherein the SW model execution unit executes an instruction subsequent to the HW instruction when a response is returned from the IF unit. The simulation apparatus further includes:
A reference value storage unit that stores a reference value of execution time for each type of operation,
The counting unit counts the number of executions of the operation for each type of the operation,
The execution time calculation unit calculates the execution time of the other instruction based on the number of executions for each type of operation counted by the counting unit and the reference value stored by the reference value storage unit. The simulation apparatus according to claim 1 or 2. The simulation apparatus further includes:
A buffer unit that stores the executed HW instruction until the operation of the HW model is completed when the HW instruction is executed;
The IF unit sends a response to the SW model execution unit before the completion of the operation of the HW model in response to the executed HW instruction when the HW instruction is executed when the buffer is empty. Return,
4. The simulation apparatus according to claim 1, wherein the SW model execution unit executes an instruction subsequent to the HW instruction when a response is returned from the IF unit. 5. A simulation program for operating a SW model (software model) having no time concept and a HW model (hardware model) having a time concept in cooperation with each other,
SW model execution processing for executing an instruction defined in the SW model;
A counting process for counting the number of executions of operations generated by other instructions executed before the HW instruction issued to the HW model among the instructions executed in the SW model execution process;
An execution time calculation process for calculating an execution time of the other instruction based on the number of executions counted in the counting process;
IF processing for relaying communication between the SW model and the HW model;
A simulation program for causing a computer to execute a timing adjustment process for delaying a timing for relaying the HW instruction to the HW model in the IF process according to the execution time calculated in the execution time calculation process.

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