JP2015169631A - resolver error correction structure, resolver and resolver error correction method - Google Patents
resolver error correction structure, resolver and resolver error correction method Download PDFInfo
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本発明はレゾルバ誤差補正構造、レゾルバおよびレゾルバ誤差補正方法に係り、特に、使用時における誤差の変化にも十分対応でき、また、事前の誤差測定・記録作業がなくてコスト低減することのできる、レゾルバ誤差補正構造等に関するものである。 The present invention relates to a resolver error correction structure, a resolver, and a resolver error correction method, and in particular, can sufficiently cope with a change in error at the time of use, and can reduce costs without a prior error measurement / recording work. The present invention relates to a resolver error correction structure and the like.
図３は、従来のレゾルバ誤差方正方法を示すブロック図である。図示するように、従来のレゾルバの誤差補正方法は、事前にレゾルバ５１の誤差を測定し、測定した誤差をＲＯＭ等に誤差補正テーブル５９として記録しておき、レゾルバ５１のＣＯＳ出力電圧ＥＳ１−Ｓ３とＳＩＮ出力電圧ＥＳ２−Ｓ４をＲＤ変換器５５に入力してデジタル角度データθ’に返還し、θ’に対応した補正値を誤差補正テーブル５９から読み出し、θ’を補正（５８）して、補正済みデジタル角度データθを得る、というものである。 FIG. 3 is a block diagram showing a conventional resolver error correction method. As shown in the figure, in the conventional resolver error correction method, the error of the resolver 51 is measured in advance, and the measured error is recorded as an error correction table 59 in a ROM or the like, and the COS output voltage E S1-of the resolver 51 is recorded. S3 and the SIN output voltage ES2-S4 are input to the RD converter 55 and returned to the digital angle data θ ', the correction value corresponding to θ' is read from the error correction table 59, and θ 'is corrected (58). Thus, the corrected digital angle data θ is obtained.
なお、レゾルバ等角度検出装置における誤差補正に関しては、従来複数の技術的提案がなされている。たとえば後掲特許文献１には、位置センサの出力信号に含まれるオフセットや振幅差や位相差のバラツキによって生じる周期性の位置検出誤差の低減できるとする位置検出装置が開示されている。すなわち、位置センサの数値をデジタル化、平均化処理した数値を、乗算器と積算器により移動量で積分した値に比例した数値とし、除算器により平均値をとり、当該平均値の周期整数倍の周期変化後における信号の立ち上がり変化をオフセット成分として記憶する、という構成の位置検出装置である。 In addition, regarding the error correction in the resolver equal angle detection device, a plurality of technical proposals have been conventionally made. For example, Patent Document 1 listed below discloses a position detection device that can reduce periodic position detection errors caused by variations in offset, amplitude difference, and phase difference included in an output signal of a position sensor. That is, the numerical value of the position sensor is digitized and averaged, and the value is proportional to the value integrated by the amount of movement by the multiplier and integrator. The average value is taken by the divider, and the average multiple of the average value is multiplied by the period. This is a position detection device configured to store the rise change of the signal after the period change as an offset component.
また特許文献２には、調整者の負担を軽減しつつ、誤差の小さいロータ回転角度を得られるとするレゾルバが開示されている。すなわち、誤差算出部が複数の回転角度測定値の各々に含まれる誤差を算出し、周波数成分取得部が複数の誤差から誤差の周波数成分の位相および振幅を求め、これにより誤差周波数成分取得装置が回転角度測定値に含まれる誤差の周波数成分の位相および振幅を自動的に算出し、当該位相および振幅を用いて回転角度測定値に対する補正を行う、という構成である。 Patent Document 2 discloses a resolver capable of obtaining a rotor rotation angle with a small error while reducing the burden on the adjuster. That is, the error calculation unit calculates an error included in each of the plurality of rotation angle measurement values, and the frequency component acquisition unit obtains the phase and amplitude of the frequency component of the error from the plurality of errors, whereby the error frequency component acquisition device In this configuration, the phase and amplitude of the frequency component of the error included in the rotation angle measurement value are automatically calculated, and the rotation angle measurement value is corrected using the phase and amplitude.
また特許文献３には、レゾルバの励磁周波数またはモータ通電制御の制御周波数が変動した場合や、ＡＤ変換器が故障した場合に故障検出できる回路構成の角度検出装置として、ＡＤ変換器に、第１ＣＰＵがコントロールするアナログ電圧信号を入力してＡＤ変換した値を第１ＣＰＵのコントロール値と比較する機能を付加し、また、励磁信号の元となるクロック源と異なるクロック源で動作する回路により、励磁周波数を監視する機能を付加した装置構成が開示されている。 Further, Patent Document 3 discloses that an angle converter with a circuit configuration that can detect a failure when the excitation frequency of the resolver or the control frequency of the motor energization control fluctuates, or when the AD converter breaks down, includes a first CPU in the AD converter. The function to compare the analog voltage signal controlled by AD and the AD converted value with the control value of the first CPU, and the circuit that operates with a clock source different from the clock source that is the source of the excitation signal, An apparatus configuration to which a function for monitoring the above is added is disclosed.
さて、図３に示した従来のレゾルバ誤差方正方法は、事前に測定したレゾルバ誤差に基づいて行うものであるため、レゾルバ使用時に誤差が変化した場合には、十分な補正を行うことができないという問題があった。また、事前にレゾルバの誤差を測定し、測定した誤差をＲＯＭ等に誤差補正テーブルとして記録しておくことが必要であるため、それらの作業が発生し、コストアップの要因ともなっていた。 Since the conventional resolver error correction method shown in FIG. 3 is based on the resolver error measured in advance, if the error changes when the resolver is used, sufficient correction cannot be performed. There was a problem. Further, since it is necessary to measure the error of the resolver in advance and record the measured error as an error correction table in a ROM or the like, such work has occurred and has been a factor in increasing costs.
したがって、使用時における誤差の変化に対しその時点で可能な補正、しかも高精度の補正を行うことができ、しかもコストアップとならない方法が求められる。かかる要求は、上記各文献開示技術においても十分に解決されるものではない。 Therefore, there is a need for a method capable of performing correction that can be performed at that time with respect to a change in error at the time of use and high-precision correction and that does not increase the cost. Such a request is not sufficiently solved even by the above-described document disclosure techniques.
そこで本発明が解決しようとする課題は、かかる従来技術の問題点を踏まえ、簡易な構成によって、使用時における誤差の変化に対してその都度十分な補正を行うことができ、しかも事前の誤差測定・記録作業が発生することもなく、コスト低減することのできる、レゾルバ誤差補正構造、レゾルバおよびレゾルバ誤差補正方法を提供することである。 Accordingly, the problem to be solved by the present invention is that, based on the problems of the prior art, with a simple configuration, sufficient correction can be performed each time for changes in error during use, and prior error measurement is possible. To provide a resolver error correction structure, a resolver, and a resolver error correction method that can reduce costs without causing a recording operation.
本願発明者は上記課題について検討した結果、レゾルバのＣＯＳ出力電圧とＳＩＮ出力電圧の２乗和を求め、その２乗和が角度により変動したことを検知し、その変動が無くなるようにＣＯＳ出力電圧とＳＩＮ出力電圧を補正することによって、レゾルバの誤差を容易に補正できることを見出し、これに基づいて本発明を完成するに至った。すなわち、上記課題を解決するための手段として本願で特許請求される発明、もしくは少なくとも開示される発明は、以下の通りである。 As a result of examining the above problems, the inventor of the present application obtains the square sum of the COS output voltage and the SIN output voltage of the resolver, detects that the square sum fluctuates depending on the angle, and detects the COS output voltage so that the fluctuation is eliminated. It was found that by correcting the SIN output voltage, the resolver error can be easily corrected. Based on this, the present invention has been completed. That is, the invention claimed in the present application, or at least the disclosed invention, as means for solving the above-described problems is as follows.
〔１〕 レゾルバの電気誤差または角度検出誤差(以下、「誤差」と称する。)を補正するための構造であって、レゾルバのＣＯＳ出力電圧とＳＩＮ出力電圧からそれらの振幅の２乗和を得る２乗和生成部と、該２乗和生成部により得られた２乗和が１か非１かを判定する判定部と、該判定部による判定結果が非１である場合にこれが１となるようＣＯＳ出力電圧またはＳＩＮ出力電圧の少なくとも一方の電圧値を加減修正する出力電圧補正部とを備えていることを特徴とする、レゾルバ誤差補正構造。
〔２〕 前記出力電圧補正部は、修正した電圧値を前記２乗和生成部に供することを特徴とする、〔１〕に記載のレゾルバ誤差補正構造。
〔３〕 前記判定部は、判定が非１である場合に、１との差分の数値を含む補正指示信号を前記出力電圧補正部に対して送信することを特徴とする、〔１〕または〔２〕に記載のレゾルバ誤差補正構造。
[1] A structure for correcting an electrical error or an angle detection error (hereinafter referred to as “error”) of a resolver, and obtaining a sum of squares of the amplitudes from the COS output voltage and the SIN output voltage of the resolver. This is 1 when the square sum generation unit, the determination unit that determines whether the square sum obtained by the square sum generation unit is 1 or non-1, and the determination result by the determination unit is non-1 And a resolver error correction structure comprising: an output voltage correction unit for adjusting and correcting at least one of the COS output voltage and the SIN output voltage.
[2] The resolver error correction structure according to [1], wherein the output voltage correction unit supplies the corrected voltage value to the square sum generation unit.
[3] The determination unit transmits a correction instruction signal including a numerical value of a difference from 1 to the output voltage correction unit when the determination is non-one, [1] or [ 2]. The resolver error correction structure according to [2].
〔４〕 前記判定部は、判定が１である場合に、当該電圧値を補正済みＣＯＳ出力電圧および補正済みＳＩＮ出力電圧としてＲ／Ｄ変換部に供することを特徴とする、〔１〕ないし〔３〕のいずれかに記載のレゾルバ誤差補正構造。
〔５〕 出力電圧補正部が下記（ａ）〜（ｄ）のいずれかであることを特徴とする、〔１〕ないし〔４〕のいずれかに記載のレゾルバ誤差補正構造。
（ａ）アナログの交流電圧であるレゾルバ出力信号を補正するアナログ電子回路
（ｂ）レゾルバ出力信号がＡ／Ｄ変換されたデジタル信号を補正するデジタルの信号処理回路
（ｃ）レゾルバ出力信号がＡ／Ｄ変換されたデジタル信号をＣＰＵまたはＤＳＰを用いた信号処理により補正するソフトウェア
（ｄ）上記（ａ）〜（ｃ）の中から２以上を用いた複合的補正手段
〔６〕 前記２乗和生成部としてＡ／Ｄ変換器が用いられることを特徴とする、〔１〕ないし〔５〕のいずれかに記載のレゾルバ誤差補正構造。
[4] When the determination is 1, the determination unit supplies the voltage value to the R / D conversion unit as a corrected COS output voltage and a corrected SIN output voltage. [3] The resolver error correction structure according to any one of [3].
[5] The resolver error correction structure according to any one of [1] to [4], wherein the output voltage correction unit is any one of the following (a) to (d).
(A) An analog electronic circuit for correcting a resolver output signal which is an analog AC voltage (b) A digital signal processing circuit for correcting a digital signal obtained by A / D converting the resolver output signal (c) A resolver output signal is A / Software for correcting D-converted digital signal by signal processing using CPU or DSP (d) Complex correction means using two or more of the above (a) to (c) [6] The square sum generation The resolver error correction structure according to any one of [1] to [5], wherein an A / D converter is used as the unit.
〔７〕 〔１〕ないし〔６〕のいずれかに記載のレゾルバ誤差補正構造を備えた、レゾルバ。
〔８〕 レゾルバの電気誤差または角度検出誤差(以下、「誤差」と称する。)を補正するための方法であって、レゾルバのＣＯＳ出力電圧とＳＩＮ出力電圧からそれらの振幅の２乗和を得る２乗和生成過程と、該２乗和生成過程により得られた２乗和が１か非１かを判定する判定過程と、該判定過程による判定結果が非１である場合にこれが１となるようＣＯＳ出力電圧またはＳＩＮ出力電圧の少なくとも一方の電圧値を加減修正する出力電圧補正過程とを備えていることを特徴とする、レゾルバ誤差補正方法。
〔９〕 前記出力電圧補正過程が下記（ａ）〜（ｄ）のいずれかであることを特徴とする、〔８〕に記載のレゾルバ誤差補正方法。
（Ａ）アナログの交流電圧であるレゾルバ出力信号をアナログ電子回路で補正する過程
（Ｂ）レゾルバ出力信号がＡ／Ｄ変換されたデジタル信号をデジタルの信号処理回路で補正する過程
（Ｃ）レゾルバ出力信号がＡ／Ｄ変換されたデジタル信号をＣＰＵまたはＤＳＰを用いた信号処理によりソフトウェア的に補正する過程
（Ｄ）上記（ａ）〜（ｃ）の中から２以上を併用する複合的過程
[7] A resolver comprising the resolver error correction structure according to any one of [1] to [6].
[8] A method for correcting an electrical error or angle detection error (hereinafter referred to as “error”) of a resolver, and obtaining a sum of squares of the amplitudes from the COS output voltage and the SIN output voltage of the resolver. This is 1 when the square sum generation process, the determination process for determining whether the square sum obtained by the square sum generation process is 1 or non-1, and the determination result by the determination process is non-1 A resolver error correction method comprising: an output voltage correction process for adjusting and correcting at least one of the COS output voltage and the SIN output voltage.
[9] The resolver error correction method according to [8], wherein the output voltage correction process is any of the following (a) to (d).
(A) Process of correcting resolver output signal which is analog AC voltage by analog electronic circuit (B) Process of correcting digital signal obtained by A / D conversion of resolver output signal by digital signal processing circuit (C) Resolver output A process of correcting a digital signal obtained by A / D conversion of a signal by software by signal processing using a CPU or DSP. (D) A combined process of using two or more of the above (a) to (c).
本発明のレゾルバ誤差補正構造、レゾルバおよびレゾルバ誤差補正方法は上述のように構成されるため、これによれば、事前にレゾルバの誤差を測定しなくても、使用時にレゾルバのＣＯＳ出力電圧とＳＩＮ出力電圧の２乗和を得、レゾルバの角度により２乗和の変動が無くなるようにＣＯＳ出力電圧とＳＩＮ出力電圧を補正することによって、容易にかつ高精度にレゾルバの誤差を補正することができる。 Since the resolver error correction structure, the resolver, and the resolver error correction method of the present invention are configured as described above, according to this, the COS output voltage and SIN of the resolver can be used at the time of use without measuring the resolver error in advance. By obtaining the sum of squares of the output voltage and correcting the COS output voltage and the SIN output voltage so that the fluctuation of the sum of squares is eliminated depending on the resolver angle, the error of the resolver can be easily and accurately corrected. .
つまり本発明のレゾルバ誤差補正構造等によれば、簡易な構成によって、使用時における誤差の変化に対してその都度十分な補正を行うことができ、事前の誤差測定・記録作業が発生することもなく、コスト低減することができる。 That is, according to the resolver error correction structure and the like of the present invention, it is possible to perform sufficient correction each time for a change in error during use with a simple configuration, and an error measurement / recording work in advance may occur. And cost can be reduced.
以下、図面により本発明を詳細に説明する。
図１は、本発明のレゾルバ誤差補正構造の基本構成を示す概念図である。図示するように本レゾルバ誤差補正構造１０は、レゾルバ１の電気誤差または角度検出誤差(以下、「誤差」と称する。)を補正するための構造であって、レゾルバ１のＣＯＳ出力電圧とＳＩＮ出力電圧からそれらの振幅の２乗和を得る２乗和生成部２と、２乗和生成部２により得られた２乗和が「１」か「非１」かを判定する判定部３と、判定部３による判定結果が「非１」である場合にこれが「１」となるようＣＯＳ出力電圧またはＳＩＮ出力電圧の少なくとも一方の電圧値を加減修正する出力電圧補正部（図中では「補正部」。以下の説明でも両用語を併用する。）４とを備えていることを、主たる構成とする。２乗和生成部２としては、Ａ／Ｄ変換器を好適に用いることができる。
Hereinafter, the present invention will be described in detail with reference to the drawings.
FIG. 1 is a conceptual diagram showing a basic configuration of a resolver error correction structure of the present invention. As shown in the figure, the resolver error correction structure 10 is a structure for correcting an electrical error or an angle detection error (hereinafter referred to as “error”) of the resolver 1, and includes a COS output voltage and a SIN output of the resolver 1. A sum-of-squares generation unit 2 that obtains the sum of squares of their amplitudes from the voltage, a determination unit 3 that determines whether the sum of squares obtained by the square-sum generation unit 2 is “1” or “non-1”; When the determination result by the determination unit 3 is “non-1”, an output voltage correction unit (in the drawing, “correction unit”) adjusts and corrects at least one of the COS output voltage and the SIN output voltage so that it becomes “1”. In the following description, both terms are used together.) 4 is a main configuration. As the square sum generation unit 2, an A / D converter can be preferably used.
かかる構成により本レゾルバ誤差補正構造１０では、レゾルバ１から出力されたＣＯＳ出力電圧およびＳＩＮ出力電圧は、２乗和生成部２においてそれらの振幅の２乗和が得られ、判定部３において得られた２乗和が「１」か「非１」かの判定がなされ、判定部３による判定結果が「非１」である場合には、出力電圧補正部４において、２乗和が「１」となるようにＣＯＳ出力電圧またはＳＩＮ出力電圧の少なくとも一方の電圧値が加減修正処理される。 With this configuration, in the present resolver error correction structure 10, the COS output voltage and the SIN output voltage output from the resolver 1 are obtained in the square sum of their amplitudes in the square sum generation unit 2 and obtained in the determination unit 3. If the sum of the squares is “1” or “non-1” and the determination result by the determination unit 3 is “non-1”, the output voltage correction unit 4 sets the square sum to “1”. The voltage value of at least one of the COS output voltage and the SIN output voltage is adjusted / corrected so that
さて、図示するように出力電圧補正部４は、修正した電圧値を２乗和生成部２に供する構成であるため、修正処理された電圧値は再度２乗和生成部２に送られて、再度、２乗和が生成される。生成された２乗和は再度判定部３に送られ、判定部３による再判定結果が「１」である場合には補正完了となる。 Now, as shown in the figure, the output voltage correction unit 4 is configured to provide the corrected voltage value to the square sum generation unit 2, so that the corrected voltage value is sent to the square sum generation unit 2 again, Again, a sum of squares is generated. The generated sum of squares is sent to the determination unit 3 again, and when the redetermination result by the determination unit 3 is “1”, the correction is completed.
図示するように、補正完了した電圧値は、補正済みＣＯＳ出力電圧および補正済みＳＩＮ出力電圧としてＲ／Ｄ変換部５に供される構成であり、デジタル角度データθに変換される。他方、再度の２乗和生成によっても判定部３による再判定結果が「非１」の場合は、補正部４へと送られ、その後２乗和生成部２へ送られ、以後、判定結果が「１」となるまでその循環が続行される。このようにして、最終的にレゾルバ１の誤差が補正される。 As shown in the drawing, the corrected voltage value is provided to the R / D converter 5 as a corrected COS output voltage and a corrected SIN output voltage, and is converted into digital angle data θ. On the other hand, if the re-determination result by the determination unit 3 is “non-1” also by the generation of the second sum of squares, it is sent to the correction unit 4 and then sent to the square sum generation unit 2, and thereafter the determination result is The circulation continues until it becomes “1”. In this way, the error of the resolver 1 is finally corrected.
すなわち本レゾルバ誤差補正構造１０によって、レゾルバのＣＯＳ出力電圧とＳＩＮ出力電圧からそれらの振幅の２乗和を得る２乗和生成過程、２乗和生成過程により得られた２乗和が「１」か「非１」かを判定する判定過程、判定過程による判定結果が「非１」である場合にこれが「１」となるようＣＯＳ出力電圧またはＳＩＮ出力電圧の少なくとも一方の電圧値を加減修正する出力電圧補正過程が実行されて、レゾルバ誤差が補正される。 That is, by the resolver error correction structure 10, the sum of squares obtained by the square sum generation process for obtaining the square sum of the amplitudes from the COS output voltage and the SIN output voltage of the resolver and the square sum generation process is “1”. Or “non-1” is determined, and when the determination result of the determination process is “non-1”, at least one of the COS output voltage and the SIN output voltage is adjusted so as to be “1”. An output voltage correction process is performed to correct the resolver error.
詳述すれば、２乗和生成部２において得られるレゾルバ１のＣＯＳ出力電圧とＳＩＮ出力電圧の２乗和は、判定部３において、その２乗和のレゾルバの角度による変動の有無および変動した場合にはその程度が検知、判断され、補正部４ではその変動が無くなるようにＣＯＳ出力電圧とＳＩＮ出力電圧を補正処理がなされることにより、レゾルバの誤差が補正される。 More specifically, the sum of the squares of the COS output voltage and the SIN output voltage of the resolver 1 obtained in the square sum generation unit 2 is changed in the determination unit 3 depending on whether the square sum resolver angle is changed or not. In such a case, the degree is detected and judged, and the correction unit 4 corrects the COS output voltage and the SIN output voltage so as to eliminate the fluctuation, thereby correcting the error of the resolver.
たとえば、生成した振幅２乗和における変動（「非１」の程度）が検出されると、それに基づきＣＯＳ出力電圧またはＳＩＮ出力電圧の振幅の変動が判断され、ＣＯＳ出力電圧またはＳＩＮ出力電圧の振幅が変動分に応じて加減補正される。 For example, when a variation (a degree of “non-1”) in the generated amplitude sum of squares is detected, a variation in the amplitude of the COS output voltage or the SIN output voltage is determined based on the detected variation, and the amplitude of the COS output voltage or the SIN output voltage is determined. Is corrected according to the variation.
なお、数学的に ＣＯＳ２θ＋ＳＩＮ２θ＝１ であるから、レゾルバのＣＯＳ出力電圧とＳＩＮ出力電圧の２乗和は理想的には一定の値となり、レゾルバの角度により変動することはない。したがって、レゾルバのＣＯＳ出力電圧とＳＩＮ出力電圧の２乗和がレゾルバの角度によらず一定値となれば、レゾルバの誤差は補正された（補正完了した）ものとなっている。 Since COS 2 θ + SIN 2 θ = 1 mathematically, the square sum of the COS output voltage and the SIN output voltage of the resolver is ideally a constant value and does not vary with the angle of the resolver. Therefore, if the square sum of the COS output voltage and the SIN output voltage of the resolver becomes a constant value regardless of the resolver angle, the resolver error is corrected (correction completed).
図２は、本発明のレゾルバ誤差補正構造の構成例を示すブロック図である。本構成例では、ＣＯＳ出力電圧、ＳＩＮ出力電圧の２乗和の生成機能およびその判定機能を、一つのブロックで「振幅２乗和判定」部２３として示している。 なお判定部３２は、判定が「非１」である場合に、補正指示信号（補正制御信号）を出力電圧補正部２４に対して送信する構成である。補正指示信号は、「１」との差分の数値を含むものとすることができる。 FIG. 2 is a block diagram showing a configuration example of the resolver error correction structure of the present invention. In this configuration example, the function of generating the square sum of the COS output voltage and the SIN output voltage and the determination function thereof are shown as an “amplitude square sum determination” unit 23 in one block. The determination unit 32 is configured to transmit a correction instruction signal (correction control signal) to the output voltage correction unit 24 when the determination is “non-1”. The correction instruction signal may include a numerical value that is a difference from “1”.
なお図中の表示の語義は、次のとおりである。
ＥＲ１−Ｒ２：励磁電圧 ＥＳ１−Ｓ３：ＣＯＳ出力電圧 ＥＳ２−Ｓ４：ＳＩＮ出力電圧 Ｋ：変圧比 θ：ロータ角度 Ｈｃ（θ）：ＣＯＳ出力電圧の誤差成分 Ｈｓ（θ）ＳＩＮ出力電圧の誤差成分
In addition, the meaning of the display in a figure is as follows.
E R1-R2 : Excitation voltage E S1-S3 : COS output voltage E S2-S 4: SIN output voltage K: Transform ratio θ: Rotor angle Hc (θ): Error component of COS output voltage Hs (θ) SIN output voltage Error component of
図２では、レゾルバ誤差補正構造２１０を「レゾルバ誤差補正回路」として示している。しかしながら本レゾルバ誤差補正構造は、回路であることに限定されない。すなわち、たとえば（ａ）アナログの交流電圧であるレゾルバ出力信号を補正するアナログ電子回路でも、（ｂ）レゾルバ出力信号がＡ／Ｄ変換されたデジタル信号を補正するデジタルの信号処理回路でも、（ｃ）レゾルバ出力信号がＡ／Ｄ変換されたデジタル信号をＣＰＵまたはＤＳＰを用いた信号処理により補正するソフトウェアでも、（ｄ）これらの中から２以上を用いた複合的補正手段でも、あるいはその他の従来公知の方式・構成でもよい。 In FIG. 2, the resolver error correction structure 210 is shown as a “resolver error correction circuit”. However, the present resolver error correction structure is not limited to being a circuit. That is, for example, (a) an analog electronic circuit that corrects a resolver output signal that is an analog AC voltage, or (b) a digital signal processing circuit that corrects a digital signal obtained by A / D conversion of the resolver output signal (c) ) Software that corrects a digital signal obtained by A / D conversion of the resolver output signal by signal processing using a CPU or DSP, (d) Complex correction means that uses two or more of these, or other conventional methods A known system / configuration may be used.
なお、具体的な補正の内容としては、振幅補正、オフセット補正、位相補正、さらに、これらでは補正不可能な要因による誤差を個別の角度ごとに行う補正（いわば、個別補正）がある。レゾルバ誤差補正構造におけるこれら具体的な補正事項の採否や順序は、限定されない。 Specific contents of the correction include amplitude correction, offset correction, phase correction, and correction (in other words, individual correction) in which errors due to factors that cannot be corrected by these are performed for each individual angle. The adoption or order of these specific correction items in the resolver error correction structure is not limited.
以上説明したレゾルバ誤差補正構造１０等を備えたレゾルバ１等自体もまた、本発明の範囲内である。 The resolver 1 itself including the resolver error correction structure 10 described above is also within the scope of the present invention.
本発明のレゾルバ誤差補正構造、レゾルバおよびレゾルバ誤差補正方法によれば、簡易な構成によって、使用時における誤差の変化に対してその都度十分な補正を行うことができ、事前の誤差測定・記録作業が発生することもなく、コスト低減することができる。したがって、センサ分野および関連する全分野において、産業上利用性が高い発明である。 According to the resolver error correction structure, the resolver, and the resolver error correction method of the present invention, it is possible to perform sufficient correction each time with respect to a change in error during use with a simple configuration, and prior error measurement / recording work. Therefore, the cost can be reduced. Therefore, the invention is highly industrially applicable in the sensor field and all related fields.
１０、２１０…レゾルバ誤差補正構造
１、２１…レゾルバ
２…２乗和生成部
３、２３…判定部
４、３５…出力電圧補正部（補正部）
５、２５…Ｒ／Ｄ変換部（ＲＤ変換器）
５１０…従来のレゾルバ誤差補正構造
５１…レゾルバ
５５…ＲＤ変換器
５８…角度誤差補正
５９…誤差補正テーブル
DESCRIPTION OF SYMBOLS 10, 210 ... Resolver error correction structure 1, 21 ... Resolver 2 ... Square sum generation part 3, 23 ... Determination part 4, 35 ... Output voltage correction part (correction part)
5, 25 ... R / D converter (RD converter)
510 ... Conventional resolver error correction structure 51 ... Resolver 55 ... RD converter 58 ... Angular error correction 59 ... Error correction table
Claims (9)
（ａ）アナログの交流電圧であるレゾルバ出力信号を補正するアナログ電子回路
（ｂ）レゾルバ出力信号がＡ／Ｄ変換されたデジタル信号を補正するデジタルの信号処理回路
（ｃ）レゾルバ出力信号がＡ／Ｄ変換されたデジタル信号をＣＰＵまたはＤＳＰを用いた信号処理により補正するソフトウェア
（ｄ）上記（ａ）〜（ｃ）の中から２以上を用いた複合的補正手段 5. The resolver error correction structure according to claim 1, wherein the output voltage correction unit is any one of the following (a) to (d).
(A) An analog electronic circuit that corrects a resolver output signal that is an analog AC voltage (b) A digital signal processing circuit that corrects a digital signal obtained by A / D-converting the resolver output signal (c) A resolver output signal is A / D Software for correcting a D-converted digital signal by signal processing using a CPU or DSP (d) Complex correction means using two or more of the above (a) to (c)
（Ａ）アナログの交流電圧であるレゾルバ出力信号をアナログ電子回路で補正する過程
（Ｂ）レゾルバ出力信号がＡ／Ｄ変換されたデジタル信号をデジタルの信号処理回路で補正する過程
（Ｃ）レゾルバ出力信号がＡ／Ｄ変換されたデジタル信号をＣＰＵまたはＤＳＰを用いた信号処理によりソフトウェア的に補正する過程
（Ｄ）上記（ａ）〜（ｃ）の中から２以上を併用する複合的過程
9. The resolver error correction method according to claim 8, wherein the output voltage correction process is any of the following (a) to (d).
(A) A process of correcting a resolver output signal, which is an analog AC voltage, by an analog electronic circuit (B) A process of correcting a digital signal obtained by A / D conversion of the resolver output signal by a digital signal processing circuit (C) A resolver output A process of correcting a digital signal obtained by A / D conversion of a signal by software by signal processing using a CPU or DSP (D) A combined process of using two or more of the above (a) to (c)
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