JP2015162866A - clock delay generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock delay generation circuit capable of accurately generating an expected clock signal and also dealing with even the case where an input clock signal is fast.SOLUTION: N pieces (N is an integer equal to or greater than 2) of delay element parts 1-1, ..., 1-N generate delay clock signals D1-DN for which a reference clock signal CLK is successively delayed. An inversion part 2 generates a clock signal CLKN for which the reference clock signal CLK is inverted. N pieces of flip-flops 3-1, ..., 3-N sample and output the delay clock signals D1-DN outputted from the N pieces of delay element parts 1-1, ..., 1-N in accordance with the reference clock signal CLK. On the basis of a control signal SEL, a selection circuit 4 selectively performs output from among the delay clock signals D1-DN. A control signal generation circuit 5 generates the control signal SEL.

Description

  The present invention relates to a clock delay generation circuit, and more particularly to a clock delay generation circuit that digitally delays a clock. In particular, it can be applied to an automatic delay adjustment circuit.

  In general, a clock signal delayed by a predetermined amount from a reference clock supplied from the outside may be used as a clock signal supplied to operate a circuit. In order for the circuit to generate the internal clock signal, it will go through a predetermined delay process after receiving the external clock signal. For example, the external clock signal is analogly delayed to generate a clock signal delayed by a predetermined amount. A circuit to generate is known.

  However, since the delay process has a certain limit, the accuracy of the delay amount is limited. For example, the time until the external clock signal is input and the data stored in the memory is output, that is, the clock access time. There will be a certain limit to reducing this. Therefore, various circuits have been proposed as a circuit for generating a clock signal obtained by delaying an external clock signal by a predetermined amount.

  For example, the one described in Patent Document 1 relates to a clock signal modeling circuit capable of generating an internal clock signal from an external clock signal in a short time without using a PLL (Phase Locked Loop) and a DLL (Delay Locked Loop). It is. In this Patent Document 1, a delay unit that receives an external clock signal and outputs a delayed clock signal, a sampling unit that receives a delayed clock signal, samples and outputs it according to the external clock signal, A comparator that receives the output of the sampling unit and sequentially compares it, and a delayed clock signal that is output from the delay unit, and receives an output signal of the comparator and an internal clock signal in accordance with an externally input switching signal A clock signal modeling circuit including an output unit is disclosed.

  Further, for example, the one described in Patent Document 2 relates to a clock delay amount automatic detection circuit that automatically detects and controls a delay difference between a clock inside the circuit and a clock that is input from the outside. The adjustment clock generator that creates an adjustment clock that is N (N is a positive integer greater than or equal to 2) times, and the operation timing between the adjustment clock and the regression clock are compared, and the delay amount of this regression clock is detected. A configuration having a delay amount detection unit is disclosed.

Japanese Patent Laid-Open No. 9-238058 JP 2005-32157 A

However, the prior art described in each of the above-mentioned patent documents is insufficient in that it can generate a clock signal that is expected with high accuracy and can cope with a case where the input clock signal is fast (high frequency).
The present invention has been made in view of such a problem, and an object of the present invention is to provide a clock delay generation circuit that can generate a clock signal that can be expected with high accuracy and can cope with a case where the input clock signal is fast. It is to provide.

  The present invention has been made to achieve such an object, and the invention according to claim 1 generates N delayed clock signals (D1 to DN) in which a reference clock signal (CLK) is sequentially delayed. (N is an integer of 2 or more) delay element units (1-1,..., 1-N), and outputs from the delay element units of the delay element units (1-1,..., 1-N) N flip-flops (3-1,..., 3-N) that sample and output each delayed clock signal (D1 to DN) according to the reference clock signal (CLK), and a control signal ( SEL), a selection circuit (4) that selectively outputs from each of the delayed clock signals (D1 to DN), and a control signal generation circuit (5) that generates the control signal (SEL), The control signal generation circuit (5) is provided for each of the flip-flops. A clock delay generation circuit and generates the control signal (SEL) based on the force (Q1 through QN). (FIGS. 1 and 4; Embodiments 1 and 2)

  According to a second aspect of the present invention, the reference clock signal (CLK) generates N delay clock signals (D1 to DN) that are delayed in sequence (N is an integer of 2 or more). Element unit (1-1,... 1-N) and each delay clock signal (D1 to DN) output from each delay element unit of the delay element unit (1-1,... 1-N). N flip-flops (3-1,..., 3-N) that sample and output in accordance with the reference clock signal (CLK) and a control signal (SEL) are input. Based on the selection circuit (4) that selectively outputs from the delayed clock signals (D1 to DN) and the outputs (Q1 to QN) of the flip-flops (3-1,..., 3-N), A control signal generation circuit (SEL) for outputting a control signal (SEL) to the selection circuit (4) ) And is a clock delay generation circuit, characterized in that it comprises. (FIGS. 1 and 4; Embodiments 1 and 2)

  The invention according to claim 3 is the invention according to claim 1 or 2, wherein the K-th flip-flop (1 ≦ K ≦ N) is the K-th delay of the K-th delay element unit (1-K). A clock signal (DK) is input, and sampling is performed according to the reference clock signal (CLK) to output a Kth output signal (QK (1 ≦ K ≦ N)). The control signal generation circuit (5) The control signal (SEL) is output based on N output signals (Q1 to QN).

  According to a fourth aspect of the present invention, in the invention according to any one of the first to third aspects, the control signal generation circuit (5) outputs the N output signals from Q1 in order from the lower bid. When QN is set (Q [N: 1]), Q1 to QL (2 ≦ L ≦ N−1) are data A, and QL + 1 is data B obtained by inverting data A. A control signal is generated so as to select a clock signal.

  The invention according to claim 5 is the invention according to any one of claims 1 to 4, wherein the control signal generation circuit (5) outputs the N output signals from Q1 in order from the lower bid. When QN (Q [N: 1]), Q1 to QL (2 ≦ L ≦ N−1) are data A, and when QL + 1 is data B obtained by inverting data A, L / 2 or The control signal is generated so as to select the delay clock signal of the (L + 1) / 2nd delay element unit.

  The invention according to claim 6 is the invention according to any one of claims 1 to 5, wherein the N flip-flops (3-1,... Each delayed clock signal (D1 to DN) output from the element unit is input, and the reference clock signal (CLK) is sampled and output according to the clock signal (CLKN) inverted by the inverting unit (2). Features.

  The invention according to claim 7 is the invention according to any one of claims 1 to 6, wherein the delay element sections from the first to the N / 2nd or (N + 1) / 2 are: Each of the two delay elements (1-1A, 1-1B,... 1-NA, 1-NB) is connected in series, and the selection circuit (4) includes the two delay elements (1 -1A, 1-1B,... 1-NA, 1-NB), and the control signal from the delayed clock signals (DH1 to DHN / 2) and the delayed clock signals (D1 to DN). (SEL) is selectively output. (FIG. 4; Embodiment 2)

  The invention according to claim 8 is the invention according to claim 7, wherein the control signal generation circuit (5) sets the N output signals from Q1 to QN in order from the lower bid (Q [N: 1]), Q1 to QL (2 ≦ L ≦ N / 2) are data A, and when QL + 1 is data B obtained by inverting data A, and L is an even number, L / 2 The delay clock signal of the first delay element unit is selected, and when L is an odd number, a control signal is generated so as to select a delay clock signal between two delay elements of (L + 1) / 2nd delay element unit It is characterized by.

  The invention according to claim 9 is the invention according to claim 7 or 8, wherein the control signal generation circuit (5) sets the N output signals from Q1 to QN in order from the lower bid. (Q [N: 1]), Q1 to QL (2 ≦ L ≦ N / 2) are data A, and when QL + 1 is data B obtained by inverting data A, the delay after the N / 2nd The input of the element portion is fixed to a high level or a low level.

  The invention according to claim 10 is the invention according to any one of claims 7 to 9, wherein the power supply voltage or ground is provided between the delay element units and to the Mth delay element unit. It further includes a switching circuit (6) for generating a switching signal for switching whether to input a voltage or to input the output of the M-1st delay element unit.

According to the present invention, it is possible to realize a clock delay generation circuit that can generate an expected clock signal with high accuracy and can cope with a case where the input clock signal is fast.
Compared to the case where the delay amount is generated in an analog manner, the expected clock can be generated with high accuracy, and even when the input clock is fast, the comparison can be made sequentially and compared with the circuit that generates the delay amount. Thus, it is possible to output a clock signal having a predetermined delay amount quickly.

  In addition, a more accurate clock delay can be generated, and by setting the delay element portion to a fine delay amount, only the first half of the Nth delay element portion may be used, and it is appropriate for the delay amount to be used. Can be set.

1 is a circuit configuration diagram for explaining a first embodiment of a clock delay generation circuit according to the present invention; FIG. FIG. 2 is a timing chart illustrating input / output of each unit illustrated in FIG. 1. It is a figure which shows the truth table of the control signal generation circuit shown in FIG. FIG. 6 is a circuit configuration diagram for explaining a second embodiment of the clock delay generation circuit according to the present invention; FIG. 5 is a diagram illustrating a truth table of the control signal generation circuit illustrated in FIG. 4.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
<Embodiment 1>
FIG. 1 is a circuit configuration diagram for explaining a clock delay generation circuit according to a first embodiment of the present invention. In the figure, reference numerals 1-1,..., 1-N are first to Nth delay element units, 2 is an inverting unit, 3-1,..., 3-N are first to Nth flip-flops (FF), Reference numeral 4 denotes a selection circuit, and 5 denotes a control signal generation circuit.

The clock delay generation circuit according to the first embodiment includes an Nth delay element unit (N is an integer of 1 or more) 1-1,... 1-N, an inverting unit 2, and an Nth flip-flop (N is 1 or more). ,..., 3-N, a selection circuit 4 and a control signal generation circuit 5.
N delay elements 1-1,... 1-N generate delayed clock signals D1 to DN in which the reference clock signal CLK is sequentially delayed. The inverting unit 2 generates a clock signal CLKN obtained by inverting the reference clock signal CLK.

N flip-flops 3-1,... 3-N have delay clock signals D 1 to D 1 output from the delay element units N of the delay element units 1-1,. DN is sampled and output according to the reference clock signal CLK.
The selection circuit 4 selectively outputs from the delayed clock signals D1 to DN based on the control signal SEL. The control signal generation circuit 5 generates the control signal SEL, that is, generates the control signal SEL based on the outputs Q1 to QN of the flip-flops.

  Further, the clock delay generation circuit according to the first embodiment includes N delay element units 1 that generate N (N is an integer of 2 or more) delayed clock signals D1 to DN in which the reference clock signal CLK is sequentially delayed. −1,..., 1-N and the delay clock signals D1 to DN output from the N delay element units 1-1,. N flip-flops 3-1,..., 3-N that sample and output in accordance with the signal CLK, and a control circuit that receives the control signal SEL and selectively outputs from each of the delayed clock signals D1 to DN 4 and a control signal generation circuit 5 that outputs a control signal SEL to the selection circuit 4 based on outputs Q1 to QN of the flip-flops 3-1,.

The Kth flip-flop (1 ≦ K ≦ N) receives the Kth delayed clock signal DK of the Kth delay element section 1-K, samples it according to the reference clock signal CLK, and samples the Kth output signal QK. (1 ≦ K ≦ N) is output, and the control signal generation circuit 5 outputs the control signal SEL based on the N output signals Q1 to QN.
Further, when the N output signals are changed from Q1 to QN in order from the lower bid (Q [N: 1]), the control signal generation circuit 5 represents the data A from Q1 to QL (2 ≦ L ≦ N−1). When QL + 1 is data B obtained by inverting data A, a control signal is generated so as to select a predetermined delayed clock signal.

Further, when the N output signals are changed from Q1 to QN in order from the lower bid (Q [N: 1]), the control signal generation circuit 5 is data from Q1 to QL (2 ≦ L ≦ N−1). When A is Q and QL + 1 is data B obtained by inverting data A, a control signal is generated so as to select the delay clock signal of the L / 2 or (L + 1) / 2nd delay element section.
The N flip-flops 3-1 to 3 -N receive the delayed clock signals D <b> 1 to DN output from the respective delay element units, and the reference clock signal CLK is inverted by the inverting unit 2. The signal is sampled and output in accordance with the signal CLKN.

That is, the Nth delay element unit 1-N generates a delay with respect to the input clock, and each delay element unit is connected in series. In other words, the (K-1) th delay element unit 1-K receives the (K-1) th output clock of the (K-1) th delay element unit, delays it, and outputs it to the (K + 1) th delay element unit. The input clock CLK is input to the first delay element unit 1-1.
Further, the output data of the Nth delay element unit 1-N is input to the input D in synchronization with the clock CLKN obtained by inverting the input clock to the Nth flip-flop (hereinafter referred to as NFF) 3-N. The output Q of each NFF is input to the control signal generation circuit 5.

Further, the control signal generation circuit 5 receives the output Q of each NFF (Q [N: 1]), and switches the selection circuit 4 to be described later based on the stored data held in the control signal generation circuit 5. A control signal SEL to be controlled is generated.
The selection circuit 4 receives the outputs D1 to DN of the Nth delay element units, and selects which output signal among the outputs of the Nth delay element unit 1-N based on the control signal SEL. Select whether to output.

Hereinafter, the case of generating a delayed clock signal delayed by ¼ period with respect to the input clock will be described with reference to FIGS. In the case of generating a delayed clock signal delayed by ¼ period, the signal input to the selection circuit may be up to D (N / 2).
FIG. 2 is a timing chart showing input / output of each unit shown in FIG. 1, and FIG. 3 is a diagram showing a truth table of the control signal generation circuit shown in FIG. 1, showing stored data. .

Each of the Nth delay element units generates signals D1 to DN delayed from the input CLK. At this time, it is assumed that the delay amounts by the Nth delay element units are uniform.
Each NFF operates in synchronization with the inverted CLKN obtained by inverting the input CLK. In FIG. 2, each NFF operates at the rising edge of CLKN. As a result, Q <b> 1 to Q <b> 6 in FIG. 2 are input to the control signal generation circuit 5.

  Here, Q [N: 1] is input to the control signal generation circuit 5, but when there is a signal QK (K is 1 to N) delayed by a half cycle or more with respect to the input clock CLK, QK = Low. Therefore, QL (L <k) = High. For example, in the timing chart of FIG. 2, since D6 is delayed by more than a half cycle with respect to the input CLK, Q6 synchronized with the rising edge of the inverted clock CLKN becomes Low. And Q1-Q5 becomes High.

For the input Q [N: 1], a signal to be selected by the selection circuit 4 is calculated based on the stored data shown in FIG. In the case of FIG. 2, since Q [N: 1] is 01111, the control signal SEL for selecting D3 is output to the selection circuit 4 from the truth table of FIG.
That is, in the first embodiment, the delay amount by each Nth delay element unit is synchronized with the inverted CLKN in the NFF, and the predetermined delay amount is based on the output Q [N: 1] of each NFF and the stored data. Select and output a clock with In particular, before and after the output Q [N: 1] of each NFF differs from the lower bid, the stored data corresponding to the predetermined delay amount is obtained by utilizing the fact that the delay amount of the input clock corresponds to about a half cycle delay. Can be used to generate a delay.

  As a result, the expected clock can be generated with higher accuracy than when the delay amount is generated in an analog manner, and the case where the input clock is fast can also be handled. In addition, it is possible to output a clock signal having a predetermined delay amount earlier than a circuit that generates a delay amount by comparing sequentially.

<Embodiment 2>
FIG. 4 is a circuit configuration diagram for explaining a clock delay generation circuit according to the second embodiment of the present invention. In the figure, reference numerals 1-1A, 1-1B... 1-NA and 1-NB denote first to Nth delay element units, and 6 denotes a switching circuit. In addition, the same code | symbol is attached | subjected to the component which has the same function as FIG.

  In the clock delay generation circuit according to the second embodiment, the delay elements from the first to the N / 2nd or (N + 1) / 2 have two delay elements 1-1A, 1-1B,. 1-NA and 1-NB are connected in series, and the selection circuit 4 is output from between two delay elements 1-1A, 1-1B, ... 1-NA, 1-NB. Based on the control signal SEL, the delayed clock signals DH1 to DHN / 2 and the delayed clock signals D1 to DN are selectively output.

  Further, the control signal generation circuit 5, when N output signals are changed from Q1 to QN in order from the lower bid (Q [N: 1]), Q1 to QL (2 ≦ L ≦ N / 2) are data A When QL + 1 is data B obtained by inverting data A, when L is an even number, the delayed clock signal of the L / 2nd delay element unit is selected, and when L is an odd number, (L + 1) / A control signal is generated so as to select a delayed clock signal between two delay elements of the second delay element unit.

Further, the control signal generation circuit 5, when N output signals are changed from Q1 to QN in order from the lower bid (Q [N: 1]), Q1 to QL (2 ≦ L ≦ N / 2) are data A When QL + 1 is data B obtained by inverting data A, the input of the N / 2nd and subsequent delay element sections is fixed at a high level or a low level.
In addition, a switching signal is provided between the delay element units and switches whether to input a power supply voltage or a ground voltage or an output of the M-1th delay element unit to the Mth delay element unit. A switching circuit 6 is further provided.

That is, the second embodiment further includes a switching circuit 6 in addition to the first embodiment. In each Nth delay element unit, the NAth delay element 1-NA and the NB delay element 1-NB are connected in series, and a delay clock signal between them is further input to the selection circuit 4. It is a form.
The Nth delay element unit includes an NAth delay element 1-NA and an NB delay element 1-NB, and a clock signal that is delayed by a delay amount that is half of the delay amount generated by each Nth delay element unit. DHN can be generated.

As a result, a more accurate clock delay can be generated. It should be noted that the delay element unit may be set to a fine delay amount as described above only in the first half of the Nth delay element unit, and can be appropriately set according to the delay amount to be used.
Further, as described above, the control signal generation circuit 5 outputs a switching signal (Half Mode) in addition to the control signal based on the stored data.

  The switching circuit 6 switches whether to input the power supply voltage or the ground voltage or the output of the M-1st delay element unit to the Mth delay element unit based on the switching signal. For example, if the sampling delay (Q value) is Low in the first half of the delay element with a small amount of delay, the second half of the delay element is not operated and is fixed at the power supply voltage or the ground voltage. Current can be reduced.

  FIG. 5 is a diagram showing a truth table of the control signal generation circuit shown in FIG. As shown in the truth table shown in FIG. 5, when the value of Q is different in the lower bid as shown in the upper part, Half Mode is set to High, that is, the delay element part in the latter half is fixed at the power supply voltage or the ground voltage. On the other hand, when the value of Q is different in the upper bid, Half Mode is set to Low, that is, each output of the delay element unit is input as usual.

As described above, the Nth delay element unit may be configured to be able to finely control the delay amount around a specific delay amount, and the delay element unit in the latter half portion may be controlled based on the output of the delay element unit. It may be configured to reduce current consumption by fixing without operating.
In addition to the above-described form, a form in which a plurality of stored data is held and the stored data is switched and logically operated according to a desired delay amount may be used.

1-1,... 1-N, 1-1A, 1-1B... 1-NA, 1-NB 1st to Nth delay element units 2 Inversion units 3-1,. 1st to Nth flip-flops (FF)
4 selection circuit 5 control signal generation circuit 6 switching circuit

Claims (10)

N delay element units (N is an integer of 2 or more) for generating a delayed clock signal in which the reference clock signal is sequentially delayed,
N flip-flops that sample and output each delayed clock signal output from each delay element of the delay element according to the reference clock signal;
A selection circuit that selectively outputs from each of the delayed clock signals based on a control signal;
A control signal generation circuit for generating the control signal;
With
The clock signal generation circuit, wherein the control signal generation circuit generates the control signal based on the output of each flip-flop. N delay element units for generating N delay clock signals in which the reference clock signal is sequentially delayed (N is an integer of 2 or more);
Each of the delay clock signals output from each delay element unit of the delay element unit is input, N flip-flops that sample and output according to the reference clock signal,
A selection circuit that receives a control signal and selectively outputs from each of the delayed clock signals;
A control signal generation circuit that outputs the control signal to the selection circuit based on the output of each of the flip-flops;
A clock delay generation circuit comprising: The Kth flip-flop (1 ≦ K ≦ N) receives the Kth delayed clock signal of the Kth delay element unit, samples it according to the reference clock signal, and samples the Kth output signal QK (1 ≦ K ≦ N). ))
3. The clock delay generation circuit according to claim 1, wherein the control signal generation circuit outputs the control signal based on N output signals.   When the control signal generation circuit sets the N output signals from Q1 to QN in order from the lower bid (Q [N: 1]), Q1 to QL (2 ≦ L ≦ N−1) are data A The control signal is generated so that a predetermined delay clock signal is selected when QL + 1 is data B obtained by inverting data A. 4. Clock delay generation circuit.   When the control signal generation circuit sets the N output signals from Q1 to QN in order from the lower bid (Q [N: 1]), Q1 to QL (2 ≦ L ≦ N−1) are data A And when the QL + 1 is the data B obtained by inverting the data A, the control signal is generated so as to select the delay clock signal of the L / 2 or (L + 1) / 2nd delay element unit. Item 5. The clock delay generation circuit according to any one of Items 1 to 4.   Each of the N flip-flops receives each delayed clock signal output from each delay element unit, and samples and outputs the delayed clock signal according to a clock signal obtained by inverting the reference clock signal by an inverting unit. The clock delay generation circuit according to any one of claims 1 to 5. The delay elements from the first to the N / 2nd or (N + 1) / 2 are each configured by connecting two delay elements in series,
7. The selection circuit according to claim 1, wherein the selection circuit selectively outputs a delay clock signal output from between the two delay elements and each of the delay clock signals based on the control signal. The clock delay generation circuit according to claim 1. When the control signal generation circuit sets the N output signals from Q1 to QN in order from the lower bid (Q [N: 1]), Q1 to QL (2 ≦ L ≦ N / 2) are data A Yes, when QL + 1 is data B which is inverted data A,
When L is an even number, the delay clock signal of the L / 2th delay element unit is selected. When L is an odd number, the delay clock signal between the two delay elements of the (L + 1) / 2nd delay element unit is selected. 8. The clock delay generation circuit according to claim 7, wherein the control signal is generated so as to be selected.   When the control signal generation circuit sets the N output signals from Q1 to QN in order from the lower bid (Q [N: 1]), Q1 to QL (2 ≦ L ≦ N / 2) are data A 9. When QL + 1 is data B obtained by inverting data A, the input of the N / 2nd and subsequent delay element sections is fixed at a high level or a low level. The clock delay generation circuit described in 1.   A switch that is provided between the delay element units and generates a switching signal for switching whether to input a power supply voltage or a ground voltage or an output of the M-1th delay element unit to the Mth delay element unit. The clock delay generation circuit according to claim 7, further comprising a circuit 6.

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