JP2015153853A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which does not cause a major obstacle in via hole processing while supporting reduction in thickness and warpage of the semiconductor device at the same time.SOLUTION: A semiconductor device comprises a rewiring structure and a semiconductor chip on a surface of the rewiring structure, in which the semiconductor chip is coated with a hardened material of prepreg which includes a fiber material. Provided is the semiconductor device in which the prepreg includes a glass fiber material. Provided is the semiconductor device in which the prepreg includes an organic fiber material.

Description

  The present invention relates to a semiconductor device.

  In recent years, mobile devices have become significantly thinner. Naturally, it is desired to reduce the thickness of the semiconductor device used, and semiconductor devices having various structures have been proposed. Among them, a wiring board using a substrate material in which a glass cloth is impregnated with a thermosetting resin occupies a large proportion of the thickness of the semiconductor device, and a semiconductor device without the wiring board has attracted attention.

  FIG. 1 shows a semiconductor device generally called a fan-out type wafer level package. The rewiring structure 3 is provided on the circuit surface 2 side of the semiconductor chip 1, and the semiconductor chip 1 is covered with the sealing material 4. The sealing material 4 is attached to the rewiring structure 3 as necessary. It has a via hole 5 that reaches it. Since the rewiring structure section 3 is not a wiring board but is made by thinly applying or pasting a photosensitive or thermosetting material, a very thin semiconductor device can be provided in principle.

  However, if all the members are made thin, there is a problem that the semiconductor device warps due to the difference in thermal expansion coefficient between the semiconductor chip and the sealing material covering the semiconductor chip.

In order to solve this problem, a commonly used technique is to lower the thermal expansion coefficient of the sealing material. However, since the sealing material must maintain adhesiveness and fluidity, it can be lowered only to about 6 × 10 ⁻⁶ / ° C. even if the thermal expansion is reduced, and there is a limit to suppressing warpage.

  Therefore, it is necessary to suppress the warpage by increasing the thickness of the semiconductor chip to about 150 μm to 400 μm, which is an obstacle to thinning the package.

  In addition, in order to effectively suppress warpage, as shown in FIG. 2, a fan-out type wafer level package having a structure having a highly rigid plate 6 such as metal or silicon on the opposite side of the rewiring structure 3 of the semiconductor device. Has also been proposed (see, for example, Patent Document 1).

JP 2005-167191 A

  Although the warp can be suppressed even if the chip is thinned with the structure shown in Patent Document 1, it is difficult to open a via hole reaching the rewiring structure part 3 as necessary because of the plate part 6. This is a major obstacle to expanding the use of semiconductor devices. For example, with this structure, it is difficult to apply the semiconductor device to a PoP (package on package) bottom package.

  An object of the present invention is to provide a semiconductor device that does not cause a major obstacle to via hole processing while achieving both reduction in thickness of the semiconductor device and reduction in warpage.

  The present invention has been made in view of such a situation, and as a result of intensive studies, the present inventors used a prepreg formed by impregnating a fiber material with an insulating resin before complete curing instead of a sealing material, It has been found that the above object can be achieved by coating a semiconductor chip with a cured product of prepreg, and the present invention has been completed.

That is, the present invention has the following aspects.
(1) A semiconductor device comprising a rewiring structure part and a semiconductor chip on the surface of the rewiring structure part, wherein the semiconductor chip is covered with a cured product of a prepreg containing a fiber material.
(2) The semiconductor device according to (1), wherein the prepreg includes a glass fiber material.
(3) The semiconductor device according to (1) or (2), wherein the prepreg includes an organic fiber material.
(4) The semiconductor device according to any one of (1) to (3), wherein the cured product of the prepreg has a via hole reaching the rewiring structure portion.
(5) In the cured product of prepreg, the thermal expansion coefficient in the planar direction of the portion including the fiber material is 5 × 10 ⁻⁶ / ° C. or less at 25 to 220 ° C., any one of (1) to (4) above Semiconductor device.
(6) The semiconductor device according to any one of (1) to (5), wherein the thickness of the semiconductor chip is 100 μm or less.

  According to the present invention, it is possible to provide a semiconductor device that does not cause a significant obstacle to via hole processing while achieving both reduction in thickness of the semiconductor device and reduction in warpage.

It is a cross-sectional schematic diagram showing a semiconductor device called a conventional fan-out type wafer level package. It is a cross-sectional schematic diagram showing a semiconductor device called a conventional fan-out type wafer level package. It is a cross-sectional schematic diagram which shows the semiconductor device of embodiment of this invention.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings as necessary. However, the present invention is not limited to the following embodiments. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

FIG. 3 shows the semiconductor device of this embodiment. A rewiring structure 3 is provided on the circuit surface 2 side of the semiconductor chip 1, and the semiconductor chip 1 is covered with a cured product 7 of prepreg. The cured product 7 of the prepreg includes a portion 8 containing a fiber material and an insulating resin 9 that exudes from the prepreg before curing. Via holes 5 reaching the rewiring structure 3 are provided as necessary. The diameter of the via hole 5 is usually 10 to 400 μm, and is formed using a CO ₂ laser device that is generally used for making a via hole in a wiring board.

  In the present invention, the rewiring structure means a wiring provided on the circuit surface of the semiconductor chip in order to connect the pad on the circuit surface of the semiconductor chip and the connection terminal to the outside.

  In the present invention, the prepreg is obtained by impregnating a fiber material with an insulating resin before curing, and the production method is not particularly limited. As a prepreg, it is preferable to apply what is generally used as a wiring board material.

  The insulating resin of the prepreg used in the present invention is not particularly limited, but a thermosetting resin composition is preferable. The thermosetting resin composition is not particularly limited, but is preferably a mixture of an epoxy resin and a thermosetting agent in consideration of plating solution resistance, heat resistance, and insulation resistance. As the epoxy resin, for example, bisphenol A type epoxy resin, bisphenol F type epoxy resin, phenol novolac type epoxy resin, biphenol type epoxy resin, naphthalene type epoxy resin, dicyclopentadiene type epoxy resin, biphenyl aralkyl type epoxy resin should be used. Can do. As the thermosetting agent, for example, an amine curing agent, a guanidine curing agent, an imidazole curing agent, a phenol curing agent, or an acid anhydride curing agent can be used.

  The thermosetting resin composition may contain a flame retardant. Moreover, you may use together halogen containing resin, phosphorus containing resin, nitrogen containing resin etc. as a flame retardant. Moreover, you may add inorganic fillers, such as an alumina, a silica, an inorganic hydrate filler aluminosilicate, and aluminum hydroxide as needed.

  It is preferable that the compounding quantity of the thermosetting agent in a thermosetting resin composition shall be 0.5-1.5 equivalent with respect to 1 equivalent of epoxy groups of an epoxy resin, and shall be 0.75-1.25 equivalent. It is more preferable. The blending amount of the inorganic filler in the thermosetting resin composition is preferably 20 to 80% by mass and more preferably 30 to 70% by mass in the total solid content excluding the solvent.

Here, two methods for producing an insulating resin impregnated in the prepreg are exemplified. By using these insulating resins, the thermal expansion coefficient of the prepreg after curing can be effectively reduced.
(Insulating resin 1)
In a reaction vessel with a capacity of 3 liters, which can be heated and cooled, equipped with a thermometer, a stirrer, and a reflux condenser, bisphenol A type cyanate resin (manufactured by Lonza Japan; trade name Arocy B-10): 500 g and the following formula ( I) Siloxane resin (manufactured by Shin-Etsu Chemical Co., Ltd .; trade name X-22-1821, hydroxyl equivalent: 1600): 500 g and toluene: 1000 g were blended, heated with stirring, and reached 120 ° C. before reaching naphthene. 0.01 g of an 8% by mass mineral spirit solution of zinc acid was added and refluxed at about 115 to 125 ° C. for 4 hours, and then cooled to room temperature (25 ° C.) to obtain a thermosetting resin solution.

（式（Ｉ）中のｐは３５〜４０の整数）

(P in the formula (I) is an integer of 35 to 40)

  100 parts by mass (solid content) of the obtained thermosetting resin, 150 parts by mass of fused silica (manufactured by Admatech Co., Ltd .; trade name SO-25R), and methyl ethyl ketone as a diluting solvent were mixed and the resin content was 60 masses. % Uniform thermosetting resin composition (insulating resin 1) varnish was obtained.

(Insulating resin 2)
A siloxane resin (manufactured by Shin-Etsu Chemical Co., Ltd .; trade name X-22-161A, amino group equivalent) was added to a reaction vessel with a volume of 2 liters that can be heated and cooled, equipped with a thermometer, a stirrer, and a moisture meter with a reflux condenser. 800): 99.2 g, bis (4-maleimidophenyl) methane: 164.3 g, m-aminophenol: 4.5 g, and dimethylacetamide: 250 g, reacted at 100 ° C. for 3 hours, A solution of curable resin was obtained.
50 parts by mass (solid content) of the obtained thermosetting resin, 50 parts by mass of biphenyl aralkyl type epoxy resin (manufactured by Nippon Kayaku Co., Ltd., trade name: NC-3000-H), fused silica (manufactured by Admatech Co., Ltd .; trade name) (SO-25R) 150 parts by mass, isocyanate mask imidazole (manufactured by Daiichi Kogyo Seiyaku Co., Ltd., trade name: G-8809L) as a curing accelerator, and methyl ethyl ketone as a diluent solvent, mixed and mixed to a resin content of 65% by mass A uniform thermosetting resin composition (insulating resin 2) varnish was obtained.

  A sheet-like material obtained by impregnating the above-described insulating resins 1 and 2 into a fiber material and heating and semi-curing the insulating resin is taken as an example of a prepreg.

  Although the kind of fiber material is not specifically limited, Aluminosilicate glass generally used widely for glass cloth for FRP is suitable. Among them, it is preferable to use so-called S glass in which the silica component is increased to reduce the thermal expansion coefficient, so that the thermal expansion coefficient of the cured prepreg can be effectively reduced. As a silica component in glass cloth, 60-70 mass% is preferable, and 64-66 mass% is more preferable. If the silica component is less than 60% by mass, the effect of reducing the coefficient of thermal expansion is reduced, and if it exceeds 70% by mass, the glass cloth tends to break and the prepreg tends to become brittle.

  An organic fiber material can be used as the fiber material. The type of organic fiber material is not particularly limited. For example, Technora (trade name, manufactured by Teijin Limited, “Technola” is a registered trademark), Zyron (trade name, manufactured by Toyobo Co., Ltd., “Zylon” is registered) Trademarks), Zexion (trade name, “Zexion” is a registered trademark) manufactured by KB Seiren Co., Ltd.) and the like are preferable and can effectively reduce the thermal expansion coefficient of the cured prepreg.

  Moreover, as content of the insulating resin of the prepreg to be used, the insulating resin exuded from the prepreg (9 in FIG. 3) is 100% by mass or more and 120% by mass of the amount capable of filling the mounting components such as the mounted semiconductor chip. Or less, more preferably 100% by mass or more and 110% by mass or less. When the amount is less than 100% by mass, the amount of the insulating resin that oozes out from the prepreg is insufficient, and a void is generated in the semiconductor device. Moreover, when it exceeds 120 mass%, since the thermal expansion coefficient of the plane direction after hardening of a prepreg rises, it is unpreferable.

In the semiconductor device of the present embodiment, a portion including the cured prepreg fiber material (8 in FIG. 3) is formed on the upper portion of the semiconductor chip, and the portion is formed as a result of the insulating resin of the prepreg exuding. Since the proportion of the insulating resin having a relatively high thermal expansion coefficient compared to the fiber material is extremely small, the thermal expansion coefficient is extremely low. Therefore, the thermal expansion coefficient in the planar direction after curing of the applied prepreg is not particularly limited, but the thermal expansion coefficient of the portion containing the fiber material of the cured prepreg is 5 × 10 ⁻⁶ / ° C. at 25 to 220 ° C. ^Or less, more preferably 4.5 × 10 ⁻⁶ / ° C. or less, and further preferably 4 × 10 ⁻⁶ / ° C. or less. If it exceeds 5 × 10 ⁻⁶ / ° C., the warp cannot be effectively reduced, which is not preferable.

  The thickness of the semiconductor chip is preferably 100 μm or less, more preferably 100 μm or less and 30 μm or more, and further preferably 80 μm or less and 30 μm or more. If the thickness of the semiconductor chip exceeds 100 μm, it is not preferable because it goes against the thinning, and the amount of the insulating resin that oozes out from the prepreg is likely to be insufficient, and a void may be generated in the semiconductor device. Further, when the semiconductor element is less than 30 μm, the warp reduction effect tends to be small. When a plurality of semiconductor chips are stacked in the vertical direction, the total thickness of the semiconductor chip stack including the adhesive layer used for stacking is defined as the thickness of the semiconductor chip.

EXAMPLES Next, although an Example demonstrates this invention, the scope of the present invention is not limited to these Examples.
The materials and structures of the semiconductor devices used in the examples and comparative examples will be described below.
Example 1
The first embodiment will be described with reference to FIG. In Example 1, prepreg GEA-705GL1078N72 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was used as a material for covering the semiconductor chip 1. The semiconductor chip 1 used was a test chip having a silicon oxide layer on the surface instead of the circuit surface 2. In the rewiring structure 3, a photosensitive insulating material AH-1170T (manufactured by Hitachi Chemical Co., Ltd., trade name) was used as an insulating material, and copper was used as a conductive material.

  The size of the entire semiconductor device is a plate shape of 10 mm long × 10 mm wide × 175 μm thick. The rewiring structure portion 3 has a total thickness of 25 μm, and has a structure in which a 10 μm copper layer is sandwiched between insulating layers, and the copper layer is provided with a dummy pattern so that the remaining copper ratio is about 50%. Yes. The size of the semiconductor chip 1 is a plate shape of 8 mm × 8 mm × 60 μm including the circuit surface 2 (silicon oxide layer). The semiconductor chip 1 is arranged in contact with the rewiring structure portion 3 at the center position of the package. The thickness of the portion 8 including the fiber material of the cured product 7 of the prepreg that covers the semiconductor chip 1 is 90 μm, and the insulating resin 9 that exudes from the prepreg before curing completely covers the side surface of the semiconductor chip 1. The via hole 5 has a diameter of approximately 200 μm and is formed at several locations around the semiconductor chip 1. The portion 8 including the fiber material of the prepreg cured product 7 covering the semiconductor chip 1 is represented as a semiconductor chip upper member (see Table 1).

(Comparative Examples 1-2)
Comparative examples 1 and 2 will be described with reference to FIG. In Comparative Examples 1 and 2, CEL-400ZHF40 (trade name, manufactured by Hitachi Chemical Co., Ltd.) was used as the sealing material 4 as a material for covering the semiconductor chip 1. Other than that, the same material as in Example 1 was used.

  In Comparative Example 1, the size of the entire semiconductor device is a plate shape having a length of 10 mm × width of 10 mm × thickness of 375 μm. The size of the semiconductor chip 1 is a plate shape of 8 mm long × 8 mm wide × 250 μm thick including the circuit surface 2 (silicon oxide layer). The thickness of the sealing material 4 covering the semiconductor chip 1 is 100 μm on the semiconductor chip, and completely covers the side surface of the semiconductor chip 1. The rest is the same as in Example 1. A portion of the sealing material 4 covering the semiconductor chip 1 on the semiconductor chip is represented as a semiconductor chip upper member (see Table 1).

  In Comparative Example 2, the size of the semiconductor chip 1 is a plate shape of 8 mm long × 8 mm wide × 60 μm thick including the circuit surface 2 (silicon oxide layer). Other than that is the same as Comparative Example 1.

(Comparative Example 3)
Comparative Example 3 will be described with reference to FIG. In Comparative Example 3, as a material for covering the semiconductor chip 1, a silicon wafer was used for the plate portion 6, and ABF-GX13 (trade name, manufactured by Ajinomoto Fine Techno Co., Ltd.) was used for the filler 10. Other than that, the same material as in Example 1 was used.

  The size of the entire semiconductor device is a plate shape of 10 mm long × 10 mm wide × 315 μm thick. The filler 10 covering the semiconductor chip 1 and the thickness of the plate portion 6 on the chip are 20 μm filler and 200 μm plate portion (silicon plate), and the filler 10 completely covers the side surface of the semiconductor chip. There are no via holes. The rest is the same as in Example 1. Part of the filler 10 and the plate portion 6 (silicon plate) correspond to a semiconductor chip upper member (see Table 1).

In Table 1 below, in Example 1 and Comparative Examples 1 to 3, the semiconductor chip covering member, the thermal expansion coefficient of the semiconductor chip upper member, the semiconductor device size, the semiconductor chip size, the rewiring structure thickness, the semiconductor chip thickness, The semiconductor chip upper member thickness, semiconductor device thickness, semiconductor device warp, and laser via hole availability are shown. The semiconductor chip covering member is a material for covering the surface and side surfaces of the semiconductor chip.
For the laser via drilling, a CO ₂ laser device (LC-2F21B / 1C, manufactured by Hitachi Via Mechanics Co., Ltd.) generally used for via drilling of the wiring board was used.
Further, the warpage of the semiconductor device was measured by using a shadow moire device (Thermo Ray PS-200, manufactured by AKROMETRIX). The measurement condition of the warp is a warp in the range of 25 to 220 ° C., and the temperature raising time from 25 ° C. to 220 ° C. is 20 minutes.
The coefficient of thermal expansion was calculated from the result of measuring the strain in the planar direction of the upper part of the semiconductor device chip in the range of 25 to 220 ° C. using a DIC device (Thermolay AXP, manufactured by AKMROMTRIX).

  As is clear from Table 1, in Example 1, laser vias can be drilled as compared with Comparative Examples 1 to 3, the thickness of the semiconductor device can be kept low, and the warp of the semiconductor device is small. Can be suppressed.

  In Comparative Example 1, since a thick semiconductor chip is used in order to suppress warpage of the semiconductor device, the thickness of the semiconductor device is large. In Comparative Example 2, the thickness of the semiconductor device is reduced, and as a result of using a thin semiconductor chip, the warp of the semiconductor device is large. In Comparative Example 3, since the silicon plate is used, the warp of the semiconductor device is small, but laser via drilling is impossible and the semiconductor device is thick.

  As described above, in the semiconductor device of the present invention, by using a prepreg instead of the sealing material, a portion having a thermal expansion coefficient equal to or lower than that of the sealing material can be obtained on the top of the semiconductor chip. In addition, since the via hole processing is easy, the industrial utility value is very large.

1: semiconductor chip, 2: circuit surface, 3: rewiring structure part, 4: sealing material, 5: via hole, 6: plate part, 7: cured product of prepreg, 8: part containing fiber material, 9: Insulating resin exuded from prepreg before curing, 10: filler.

Claims (6)

  A semiconductor device comprising: a rewiring structure portion; and a semiconductor chip on a surface of the rewiring structure portion, wherein the semiconductor chip is covered with a cured product of a prepreg containing a fiber material.   The semiconductor device according to claim 1, wherein the prepreg includes a glass fiber material.   The semiconductor device according to claim 1, wherein the prepreg includes an organic fiber material.   The semiconductor device according to claim 1, wherein the cured product of the prepreg has a via hole reaching the rewiring structure portion. 5. The semiconductor device according to claim 1, wherein, in a cured product of the prepreg, a thermal expansion coefficient in a planar direction of a portion including the fiber material is 5 × 10 ⁻⁶ / ° C. or less at 25 to 220 ° C. ⁶ .   The semiconductor device according to claim 1, wherein the semiconductor chip has a thickness of 100 μm or less.

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