JP2015142847A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of saving the capacity of a processing program.SOLUTION: A microcomputer for game control executes, by the same processing routine: a first variation pattern selection processing for selecting a variation pattern including variable display time from the start of variable display to the end of the variable display of first variable display in a first variable display means in which a first start condition is established; and a second variation pattern selection processing for selecting a variation pattern including the variable display time from the start of the variable display to the end of the variable display of second variable display in a second variable display means in which a second start condition is established. The microcomputer selects, in the first variable display means and the second variable display means, from a plurality of variation patterns, a variation pattern including a variable display time of a variable display in the variable display means in which a start condition of the variable display is established.

Description

  In the present invention, after the game ball has won the first starting area, the first start condition that enables the start of the variable display based on the winning is established, and each of the first starting conditions can be identified. First variation display means for starting the first variation display by the identification information and deriving and displaying the display result, and after the game ball has won the second starting area, the variation display based on the winning can be started. And a second variation display means for starting the second variation display based on the second identification information that can identify each of the two variation conditions and deriving and displaying the display result. The present invention relates to a gaming machine such as a pachinko gaming machine that controls a specific gaming state advantageous to the player when a predetermined specific display result is derived and displayed on the display means or the second variation display means.

  As a gaming machine such as a pachinko machine, a variable display is performed by updating and displaying predetermined identification information (for example, a symbol) on an image display device such as a liquid crystal display (LCD), and a stop symbol (display) There is a game that enhances the game interest by executing a so-called variable display game that informs whether or not to give a predetermined game value depending on the result.

  The variable display game is a game in which when the “big hit” occurs, the stop symbol form when the symbol update display is completely stopped is changed to a specific display form. When it is a “hit”, it is very easy to win a game ball in the big prize opening by opening a special electric accessory called a big prize opening. Then, the player is provided with a state in which the winning of the game ball is extremely easy for a certain period of time.

  Hereinafter, a state in which the prize winning opening is in an open state and the winning of a game ball is extremely easy is referred to as a specific game state. When entering the specific gaming state, for example, the stop symbol pattern of the display symbol displayed on the image display device becomes a predetermined specific display mode (generally, the stop symbols are aligned in the same symbol).

  In the variable display game, the player pays attention to whether or not the mode of the stop symbol becomes the specific display mode and becomes a “hit”. For this reason, various effects are displayed to enhance the game entertainment, such as changing the variation of the symbols, until the symbol is finalized (final stop) so that it can be determined whether or not it will be a “big hit”. Is called.

  As such an effect, for example, in the image display device, a symbol other than the symbol that becomes the final stop symbol (for example, the middle symbol of the left and right middle symbols) continues for a predetermined time and matches a specific display result. Before the final result is displayed, such as when it is stopped, swinging, enlarged or reduced or deformed, or when multiple symbols change synchronously with the same symbol, or the position of the displayed symbol is switched. There is a reach effect performed in a state where the possibility of occurrence of big hits is continuing (hereinafter, these states are referred to as reach states). Further, the reach state and its state are referred to as a reach mode. Furthermore, variable display including reach production is called reach variable display.

  Among such gaming machines, there are gaming machines provided with two variable display devices (for example, see Patent Documents 1 and 2).

Japanese Patent Laid-Open No. 08-084807 JP 2005-312813 A

  In a gaming machine equipped with two variable display devices, it is necessary to control each variable display device, so that the capacity of the processing program increases.

  Therefore, an object of the present invention is to provide a gaming machine that can reduce the capacity of a processing program.

The gaming machine according to the present invention can identify each of the game balls based on the fact that the first start condition that enables the start of the variable display based on the winning is established after the game ball has won the first starting area. The first variation display means for starting the first variation display by the first identification information and deriving and displaying the display result, and after the game ball has won the second starting area, the variation display based on the winning can be started. Second variation display means for starting the second variation display by the second identification information that can identify each of the second variation display means based on the fact that the second start condition is established and deriving and displaying the display result, A gaming machine that controls a specific gaming state advantageous to a player when a predetermined specific display result is derived and displayed on the first fluctuation display means or the second fluctuation display means, and controls the progress of the game. , First variation display means And a game control means for controlling the change display in the second change display means, and an effect control means for controlling the effect parts provided in the gaming machine, wherein the effect parts are the first change display or the second change display. Including an effect display device that performs a variation display of the effect identification information corresponding to the second variation display, and the game control means is provided that neither the first variation display nor the second variation display is executed. When the second start condition is satisfied, the second change display start means for starting the second change display by the second change display means, and the first change display means in which the first start condition is satisfied The first variation pattern selection process for selecting a variation pattern including the variation display time from the beginning of variation display to the end of variation display, and the second variation display means in the second variation display means that satisfies the second start condition. 2 fluctuations The second variation pattern selection process for selecting the variation pattern including the variation display time from the start of the variation display to the end of the variation display is executed by the same processing routine, and the first variation display means and the second variation display means Among the variation display means, the variation pattern selection means for selecting the variation pattern including the variation display time of the variation display in the variation display means satisfying the variation display start condition from the plurality of variation patterns, and selected by the variation pattern selection means Based on the variation pattern, the first data indicating the variation display time of the variation display executed by the first variation display means when the first start condition is satisfied, and the second data when the second start condition is satisfied. Fluctuation display time storage means for storing second data indicating the fluctuation display time of the fluctuation display executed in the fluctuation display means in the same storage area; When the dynamic display is started, the fluctuation display means specifying command that can specify which of the first fluctuation display means and the second fluctuation display means starts the fluctuation display, and the fluctuation selected by the fluctuation pattern selection means Including a variation start command transmission means for transmitting a variation pattern command capable of specifying a pattern, and the effect control means restores the power supply when the fluctuation display is executed when the power supply to the gaming machine is stopped. The variation display of the effect identification information in the effect display device is performed in a mode different from the mode before the power supply is stopped.
As such, the capacity of the processing program can be saved.

The drawing processor reads the image data from the image data storage means in a state where the bus width of the data bus is set to a predetermined bus width (for example, 64 bits), and when a predetermined condition is satisfied (for example, a super reach effect) The bus width of the data bus may be changed to a specific bus width (for example, 32 bits) different from the predetermined bus width, and the image data may be read from the image data storage means.
In such a configuration, the bus width of the data bus is set to a wide bus width as the ROM of the image data storage means from which image data is read when the bus width of the data bus is changed to a narrow bus width. Therefore, it is possible to use a ROM capable of inputting / outputting data with fewer bits than a ROM from which image data is read out, and the cost of the image data storage means can be reduced.

The image data storage means stores image data including moving image data in a compressed state, and a specific bus width (for example, 32 bits) is narrower than a predetermined bus width (for example, 64 bits), and is used for drawing. The processor determines that a predetermined condition is satisfied when moving image data is read from the image data storage means (for example, executes the processing of step S842E and step S868), and determines the bus width of the data bus from the predetermined bus width. The moving image data may be read from the image data storage means by changing to a specific bus width.
In such a configuration, when reading moving image data, the bus width of the data bus is narrowed, but since moving image control in the rendering processor takes more time than still image control, Even if the bus width is narrowed, the image processing performance can be prevented from deteriorating.

In the image data storage means, as image data, first image data having a first pixel number (for example, 640 × 480) and a second pixel number having a second pixel number (for example, 800 × 600) larger than the first pixel number are stored. The image data is stored, and the drawing processor performs the process of displaying an image on the image display device based on the first image data or the second image data stored in the image data storage means. The number of pixels of the data or the second image data is increased to the number of pixels corresponding to the image display device according to a predetermined enlargement ratio, and an image is displayed, and the control information output means satisfies a predetermined switching condition Sometimes, the image data to be used is switched between the first image data (for example, moving image image data) and the second image data (for example, still image data) for the drawing processor. Is output (for example, the processes of steps S980, S981, and S985 are performed), and information indicating that the enlargement ratio is switched (for example, the processes of steps S842F and S842G and the processes of steps S869 and S870). Execute processing) Even if it is configured to include an enlargement rate control means (for example, in the production control microcomputer 100, the portion that executes the processing of steps S980, S981, and S985 and the processing of steps S869 and S870). Good.
When configured in this way, all image data has a large number of pixels, preventing an increase in the amount of data, and realizing display according to the number of pixels on the screen of the image display device. And the player is not discomforted with respect to the display effect when the identification information for effect is variably displayed.

The game control means is a prior decision means (for example, in the game control microcomputer 560) that determines whether or not to shift to the specific game state before the display result is derived and displayed on the first variable display section or the second variable display section. , A portion for executing the processing of steps S61 and S62) and reach determination means for determining whether or not to execute the reach effect in the image display device when it is determined by the pre-decision means not to shift to the specific game state ( For example, in the game control microcomputer 560, the reach determination means includes the number of established first conditions and the number of established second start conditions. When the number is larger than the predetermined number (for example, the total number is 4 or more), the established number counted by the first counting means and the second counting means are used. It is determined that the reach effect is executed at a smaller rate than when the total number with the counted number is smaller than the predetermined number (for example, the reach determination table shown in FIGS. 12B and 12D is used). (The process of step S99 may be executed).
In such a configuration, when the total number of established conditions of the first start condition and established condition of the second start condition is large, the frequency of executing the reach effect during the variable display display of the identification information is reduced. can do. As a result, the operating rate of the gaming machine can be improved.

When the game control means starts the variable display of the identification information on the first variable display unit or the second variable display unit, the game control unit displays the variable display of the identification information on either the first variable display unit or the second variable display unit. A variable display part specifying command (for example, symbol variation designation command) that can specify whether to start, and a variable display command (for example, a variation pattern) that can specify to start variable display of the effect identification information on the image display device The command may be configured to include start command transmission means (for example, a part for executing the processing of steps S105 and S106 in the game control microcomputer 560).
In such a configuration, the variable display command can be commonly used for variable display of the identification information on the first variable display unit and variable display of the identification information on the second variable display unit.

The game control means includes a number-of-establishment display means (for example, a total hold storage display unit 18c) that displays information that can identify the number of established first start conditions and information that can identify the number of established second start conditions. Based on the increase in the number of established first start conditions or the number of established second start conditions, an increase in established number that can specify that the number of established first start conditions or the number of established second start conditions has increased. Start that transmits a specific command (for example, total pending storage number designation command) and a number-of-establishment identification command (for example, first start prize designation command or second start prize designation command) that indicates which number has been established A condition establishment number specifying command transmission means (for example, a part for executing the processing of steps S216, S218, S226, and S228 in the game control microcomputer 560) and control The information output means performs control to display the established number of the first start condition and the established number of the second start condition on the established number display means based on the established number increase specifying command and the established number identification command. The established number display control means to be performed (for example, in the production control microcomputer 100, the part that executes the processing of steps S909, S911, S921, and S923) and the established number identification command transmission means without receiving the established number identification command. In a special mode (for example, a blue circle) that is different from the display mode in which the number of established first condition and the number of established second start condition can be specified on the number-of-establishment display means when the number-of-established increase specification is received. Number-of-establishment display mode change control means for performing display (for example, the processing of steps S909, S921, and S931 in the production control microcomputer 100) Portions for performing) and may be configured to include.
In the case of such a configuration, it is possible to easily grasp that an abnormality has occurred regarding the transmission / reception of a command, and it is possible to grasp the number of established start conditions itself even if an abnormality has occurred regarding the transmission / reception of a command.

The game control means performs a process from when the first start condition is established until the display result of the first identification information is derived and displayed, and after the second start condition is established until the display result of the second identification information is derived and displayed. The above processing may be executed by a common processing routine (for example, one special symbol process).
In such a configuration, there is no need to repeatedly program an instruction to execute the same process when the first start condition is satisfied and when the second start condition is satisfied, and the variable display section Even if a plurality of programs are provided, the program capacity required for game control can be prevented from increasing.

It is the front view which looked at the pachinko game machine from the front. It is a block diagram which shows an example of the circuit structure in a main board | substrate (game control board). It is a block diagram which shows the circuit structural example of a relay board | substrate, an effect control board | substrate, a lamp driver board | substrate, and an audio | voice output board | substrate. It is a block diagram which shows the circuit structure of a drawing processor. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows a 2 ms timer interruption process. It is explanatory drawing which shows each random number. It is explanatory drawing which shows a jackpot determination table. It is explanatory drawing which shows a game state determination table. It is explanatory drawing which shows an example of a fluctuation pattern. It is explanatory drawing which shows a fluctuation pattern and fluctuation time. It is explanatory drawing which shows a reach determination table. It is explanatory drawing which shows an example of the content of an effect control command. It is explanatory drawing which shows the example of the transmission timing of an effect control command. It is explanatory drawing which shows the example of the transmission timing of an effect control command. It is a flowchart which shows a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is explanatory drawing which shows the structural example of a pending | holding storage specific information storage area (holding specific area) and a pending | holding buffer. It is explanatory drawing which shows the structural example of the common pending | holding memory number buffer with which a 1st pending memory number and a 2nd pending memory number are provided in common. It is a flowchart which shows a special symbol normal process. It is a flowchart which shows a special symbol normal process. It is a flowchart which shows a fluctuation pattern setting process. It is a flowchart which shows a display result specific command transmission process. It is a flowchart which shows the special symbol change process. It is a flowchart which shows a special symbol stop process. It is a flowchart which shows a big hit end process. It is a flowchart which shows a small hit end process. It is explanatory drawing which shows the example of the display effect in an image display apparatus. It is explanatory drawing which shows an example of the usage method of a frame buffer. It is explanatory drawing which shows an example of the usage method of VRAM. It is explanatory drawing which shows an example of the address map of a frame memory. It is explanatory drawing for demonstrating the method of expansion | deployment of the image data from CGROM to a frame memory. It is explanatory drawing which shows the mode of the transfer of the image data from a frame memory to an image display apparatus. It is explanatory drawing which shows the data bus in the CG bus between a drawing control part and CGROM. It is a block diagram which shows the specific wiring of the data bus in the CG bus between a drawing control part and CGROM. It is explanatory drawing for demonstrating an example of each register in a drawing control register. It is explanatory drawing which shows the data structure of moving image data among the image data of the components image memorize | stored in CGROM. It is explanatory drawing for demonstrating the decoding method of the moving image data (compressed data) by which the moving image expansion part compressed the data. It is a flowchart which shows the main process which the microcomputer for production control performs. It is explanatory drawing which shows the example of the data table stored in ROM. It is a flowchart which shows a 2nd data transfer process. It is a flowchart which shows a fixed area | region data transfer control process. It is a flowchart which shows a sprite / video data transfer process. It is a flowchart which shows production control process processing. It is a flowchart which shows a fluctuation pattern command reception waiting process. It is a flowchart which shows a decoration design change start process. It is explanatory drawing which shows the structural example of a process table. It is explanatory drawing which shows the structural example of a 2nd process table. It is explanatory drawing which shows the mode of storage of the process table in ROM. It is explanatory drawing for demonstrating the display effect performed according to the content of a process table. It is a flowchart which shows a process during decoration design change. It is explanatory drawing for demonstrating switching from a 2nd process table to a 1st process table. It is a flowchart which shows a decoration design change start process. It is explanatory drawing which shows the structural example of a common 2nd process table. It is a flowchart which shows a process during decoration design change. It is a flowchart which shows a decoration design change stop process. It is a flowchart which shows a big hit display process. It is a flowchart which shows a big hit end process. It is a flowchart which shows V blank interruption processing. It is a flowchart which shows the process which a drawing processor transfers image data from CGROM to the fixed area of VRAM according to the command from CPU for production control. It is a flowchart which shows a data transfer process. 10 is a flowchart showing a modification of processing in which the drawing processor transfers image data from the CGROM to a fixed area of the VRAM in response to a command from the CPU for effect control. It is a flowchart which shows the drawing control processing in V blank interruption processing. It is a flowchart which shows the process which a drawing processor transfers image data from the fixed area | region of VRAM to a frame memory according to the command from CPU for production control. It is a flowchart which shows the process which a drawing processor transfers image data from CGROM to a frame memory according to the command from CPU for production control. It is a flowchart which shows the moving image decoding process which a drawing processor transfers the image data of a moving image from CGROM to a frame memory according to the command from CPU for production control. It is a flowchart which shows the moving image decoding process which a drawing processor transfers the image data of a moving image from CGROM to a frame memory according to the command from CPU for production control. It is explanatory drawing which shows the example of the display state of a total pending storage display part. It is a flowchart which shows a pending | holding memory | storage display control process. It is a flowchart which shows a pending | holding memory | storage display control process. It is a flowchart which shows a pending | holding memory | storage display control process. It is explanatory drawing which shows the example of the data set to a summation pending storage table, and the example of a display of a summation pending storage display part. It is explanatory drawing which shows the example of the data set to a summation pending storage table, and the example of a display of a summation pending storage display part. It is explanatory drawing which shows the example of the data set to a summation pending storage table, and the example of a display of a summation pending storage display part. It is explanatory drawing for demonstrating the expansion process of an image. It is a flowchart which shows a decoration design change start process. It is a flowchart which shows a process during decoration design change. It is a flowchart which shows a decoration design change stop process. It is explanatory drawing which shows the example of a components image required about each variation pattern. It is explanatory drawing which shows the structural example of a component image data transfer area | region data table. It is a flowchart which shows command analysis processing. It is a flowchart which shows a component image data transfer control process.

Embodiment 1 FIG.
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a first embodiment of the invention will be described with reference to the drawings. First, the overall configuration of a pachinko gaming machine 1 that is an example of a gaming machine will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as seen from the front.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) that can be opened and closed with respect to the outer frame, a mechanism plate (not shown) to which mechanism parts and the like are attached, and various parts (games to be described later) attached to them. A structure including the board 6).

  On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, there are provided a surplus ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3, and a hitting operation handle (operation knob) 5 for firing the hitting ball. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. In addition, a game area 7 is formed on the front surface of the game board 6 in which a game ball that has been struck can flow down.

  Near the center of the game area 7, an image display device 9 composed of a liquid crystal display device (LCD) is provided. In the image display device 9, variable display (variation) of effect symbols (decorative symbols) synchronized with variable display of the first special symbol or the second special symbol is performed. Therefore, the image display device 9 corresponds to a variable display device that performs variable display of effect symbols (decorative symbols) as identification information. The image display device 9 is controlled by an effect control microcomputer mounted on the effect control board. When the first special symbol display 8a is executing variable display of the first special symbol, the effect control microcomputer causes the image display device 9 to execute the effect display along with the variable display, and the second special symbol display 8a executes the second special display. When the variable display of the second special symbol is executed on the symbol display 8b, the effect display is executed on the image display device in accordance with the variable display, so that it is possible to easily grasp the progress of the game.

  In addition to the image display device 9, the first decorative symbol display that performs variable display of the first decorative symbol corresponding to the first special symbol during the variable display time of the first special symbol by the first special symbol indicator 8a. And a second decorative symbol display that performs variable display of the second decorative symbol corresponding to the second special symbol during the variable display time of the second special symbol by the second special symbol indicator 8b. Also good. In this case, the first decorative symbol display and the second decorative symbol display are controlled by the production control microcomputer 100, and are constituted by, for example, two LEDs or seven-segment LEDs.

  On the left side of the upper part of the image display device 9 in the game board 6, a first special symbol display (first variable display unit) 8a for variably displaying the first special symbol as identification information is provided. In this embodiment, the first special symbol display 8a is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. In other words, the first special symbol display 8a is configured to variably display numbers (or symbols) from 0 to 9. On the right side of the upper part of the image display device 9 in the game board 6, a second special symbol display (second variable display unit) 8b for variably displaying the second special symbol as identification information is provided. The second special symbol display 8b is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. That is, the second special symbol display 8b is configured to variably display numbers (or symbols) from 0 to 9.

  In this embodiment, the type of the first special symbol and the type of the second special symbol are the same (for example, both 0 to 9). Further, the first special symbol display 8a and the second special symbol display 8b may be configured to variably display numbers (or two-digit symbols) of, for example, 00 to 99, for example.

  Hereinafter, the first special symbol and the second special symbol may be collectively referred to as a special symbol, and the first special symbol indicator 8a and the second special symbol indicator 8b may be collectively referred to as a special symbol indicator.

  In the variable display of the first special symbol or the second special symbol, a first start condition (first execution condition) or a second start condition (second execution condition), which is a variable display execution condition, is satisfied (for example, the game ball is After winning the first start winning opening 13 or the second starting winning opening 14), a variable display start condition (for example, when the number of reserved memories is not 0 and the first special symbol and the second special symbol are It starts based on the fact that the variable display is not executed and the big hit game is not executed). When the variable display time (fluctuation time) elapses, the display result (stop symbol) is derived. indicate. Note that winning means that a game ball has entered a predetermined area such as a winning opening. Deriving and displaying the display result is to finally stop and display a symbol (an example of identification information). Further, in this embodiment, the variable display start condition is established in the order in which the start winnings are generated regardless of the winning at the first starting winning port 13 and the winning at the second starting winning port 14. However, priority may be given to winning in any start winning opening. For example, if the variable display of the first special symbol and the second special symbol is not executed, and if the big hit game is not executed, even if the first reserved memory number is not 0, the second The variable display of the second special symbol may be continuously executed until the number of reserved memories becomes zero.

  The image display device 9 is for decoration (production) during the variable display time of the first special symbol on the first special symbol display 8a and during the variable display time of the second special symbol on the second special symbol display 8b. The display design (decorative design) is variably displayed. The variable display of the first special symbol on the first special symbol display device 8a and the variable display of the effect symbol on the image display device 9 are synchronized. Further, the variable display of the second special symbol on the second special symbol display 8b and the variable display of the effect symbol on the image display device 9 are synchronized. Synchronous means that the start time and end time of variable display are substantially the same (may be exactly the same) and the variable display period is substantially the same (may be exactly the same). Further, when the jackpot symbol is stopped and displayed on the first special symbol display 8a and when the jackpot symbol is stopped and displayed on the second special symbol display 8b, an effect symbol that reminds the jackpot on the image display device 9 The combination of is stopped and displayed. In the example shown in FIG. 1, the left, middle, and right decorative symbols are moved and displayed in the vertical direction (display such that the decorative symbol displayed in the center of each of the left, middle, and right columns changes).

  A winning device having a first start winning opening 13 is provided below the image display device 9. The game ball won in the first start winning opening 13 is guided to the back of the game board 6 and detected by the first start opening switch 13a.

  A variable winning ball device 15 having a second starting winning port 14 through which a game ball can be won is provided below a winning device having a first starting winning port (first starting port) 13. The game ball that has won the second start winning opening (second start opening) 14 is guided to the back of the game board 6 and detected by the second start opening switch 14a. The variable winning ball device 15 is opened by a solenoid 16. When the variable winning ball device 15 is in the open state, the game ball can be awarded to the second starting winning port 14 (it is easier to start winning), which is advantageous for the player. In a state where the variable winning ball device 15 is in the closed state, the game ball does not win the second start winning port 14. In the state where the variable winning ball apparatus 15 is in the closed state, it may be configured that the winning is possible (that is, it is difficult for the gaming ball to win) although it is difficult to win a prize.

  Hereinafter, the first start winning opening 13 and the second start winning opening 14 may be collectively referred to as a start winning opening or a starting opening.

  When the variable winning ball device 15 is controlled to be in the open state, the game ball heading for the variable winning ball device 15 is very likely to win the second start winning port 14. The first start winning opening 13 is provided immediately below the image display device 9, but the interval between the lower end of the image display device 9 and the first start winning opening 13 is further reduced, or the first start winning opening 13 is set. The nail arrangement around the first start winning opening 13 is made difficult to guide the game balls to the first starting winning opening 13 so that the winning rate of the second starting winning opening 14 is increased. It is also possible to make the direction higher than the winning rate of the first start winning opening 13.

  Below the first special symbol display 8a, the number of effective winning balls that have entered the first start winning opening 13, that is, the first reserved memory number (the reserved memory is also referred to as the start memory or the start prize memory) 4 is displayed. There is provided a first special symbol storage memory indicator 18a composed of two indicators (for example, LEDs). The first special symbol storage memory indicator 18a increases the number of indicators to be lit by 1 each time there is an effective start winning. Then, each time the variable display on the first special symbol display 8a is started, the number of indicators to be turned on is reduced by one.

  Below the second special symbol display 8b is a second special symbol hold comprising four indicators (for example, LEDs) for displaying the number of effective winning balls that have entered the second start winning opening 14, that is, the second reserved memory number. A storage indicator 18b is provided. The second special symbol storage memory display 18b increases the number of indicators to be lit by 1 every time there is an effective start winning. Then, each time the variable display on the second special symbol display 8b is started, the number of indicators to be turned on is reduced by one.

  Further, the display screen of the image display device 9 displays an area (hereinafter referred to as a total reserved storage display unit 18c) that displays a total number (total reserved storage number) that is the sum of the first reserved memory number and the second reserved memory number. .) Is provided. Since the total pending storage display unit 18c for displaying the total number is provided, it is possible to easily grasp the total number of execution conditions that are not satisfied with the variable display start condition. Since the total reserved memory display unit 18c is provided, the first special symbol reserved memory display 18a and the second special symbol reserved memory display 18b may not be provided.

  In this embodiment, as shown in FIG. 1, the variable winning ball apparatus 15 that opens and closes only the second start winning opening 14 is provided. Any of the start winning ports 14 may be provided with a variable winning ball device that performs an opening / closing operation.

  Further, as shown in FIG. 1, a special variable winning ball device 20 is provided below the variable winning ball device 15. The special variable winning ball apparatus 20 includes an opening / closing plate, and when the specific display result (big hit symbol) is derived and displayed on the first special symbol display 8a, and the specific display result (big hit symbol) on the second special symbol display 8b. When the open / close plate is controlled to be open by the solenoid 21 in the specific game state (big hit game state) that occurs when the symbol is derived and displayed, the big winning opening serving as the winning area is opened. The game ball that has won the big winning opening is detected by the count switch 23.

  A normal symbol display 10 is provided at the lower right side of the game board 6. The normal symbol display 10 variably displays a plurality of types of identification information (for example, “◯” and “x”) called normal symbols.

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the upper and lower lamps (the symbols can be visually recognized when the lamp is lit). . When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In other words, the state of the variable winning ball apparatus 15 is a state that is advantageous from a disadvantageous state for the player when the normal symbol is a stop symbol (a state in which a game ball can be awarded at the second start winning port 14). To change. In the vicinity of the normal symbol display 10, a normal symbol holding storage display 41 having four indicators (for example, LEDs) for displaying the number of winning balls that have passed through the gate 32 is provided. Each time there is a game ball passing through the gate 32, that is, every time a game ball is detected by the gate switch 32a, the normal symbol storage memory display 41 increases the number of indicators that are turned on by one. Then, each time the variable display on the normal symbol display 10 is started, the number of indicators that are lit is reduced by one. Further, in the probability variation state where the probability of being determined to be a big hit as compared to the normal state is high, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the variable winning ball apparatus 15 The opening time becomes longer and the number of opening times is increased. Further, in this embodiment, even in the short time state (the gaming state in which the special symbol variable display time is shortened), the opening time of the variable winning ball device 15 is lengthened or the number of times of opening is increased.

  On the left and right sides of the game area 7 of the game board 6, there are provided decorative LEDs 25 that are displayed blinking during the game, and at the lower part there is an outlet 26 for taking in a hit ball that has not won. In addition, two speakers 27R and 27L that utter sound effects and sounds as predetermined sound outputs are provided on the left and right upper portions outside the game area 7. A top frame LED 28a, a left frame LED 28b, and a right frame LED 28c provided on the front frame are provided on the outer periphery upper portion, the outer periphery left portion, and the outer periphery right portion of the game area 7. Also, a prize ball LED 51 that is turned on when there is a remaining number of prize balls is provided in the vicinity of the left frame LED 28b, and a ball cut LED 52 that is turned on when the supply ball is cut is provided in the vicinity of the right frame LED 28c. . The top frame LED 28a, the left frame LED 28b, the right frame LED 28c, and the decoration LED 25 are examples of effects light emitters provided in the pachinko gaming machine 1. In addition to the above-described various LEDs for production (decoration), LEDs and lamps for production are installed.

  In the gaming machine, a ball striking device (not shown) that drives a driving motor in response to a player operating the batting operation handle 5 and uses the rotational force of the driving motor to launch a gaming ball to the gaming area 7. ) Is provided. A game ball launched from the ball striking device enters the game area 7 through a ball striking rail formed in a circular shape so as to surround the game area 7, and then descends the game area 7. When the game ball enters the first start winning opening 13 and is detected by the first start opening switch 13a, if the variable display of the first special symbol can be started (for example, the variable display of the special symbol ends, 1), the first special symbol display 8a starts variable display (variation) of the first special symbol, and the image display device 9 starts variable display of the effect symbol (decorative symbol). Is done. That is, the variable display of the first special symbol and the effect symbol corresponds to winning in the first start winning opening 13. If the variable display of the first special symbol cannot be started, the first reserved memory number is increased by 1 on the condition that the first reserved memory number has not reached the upper limit value.

  When the game ball enters the second start winning opening 14 and is detected by the second start opening switch 14a, if the variable display of the second special symbol can be started (for example, the special symbol variable display ends, 2), the second special symbol display 8b starts variable display (variation) of the second special symbol, and the image display device 9 starts variable display of the effect symbol (decorative symbol). Is done. That is, the variable display of the second special symbol and the effect symbol corresponds to winning in the second start winning opening 14. If the variable display of the second special symbol cannot be started, the second reserved memory number is increased by 1 on condition that the second reserved memory number has not reached the upper limit value.

  FIG. 2 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. 2 also shows the payout control board 37, the effect control board 80, and the like. A game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the CPU 56 and the RAM 55, and the ROM 54 may be external or built-in. The I / O port unit 57 may be externally attached. The game control microcomputer 560 further includes a random number circuit 503 that generates hardware random numbers (random numbers generated by the hardware circuit).

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  The random number circuit 503 is a hardware circuit that is used to generate a random number for determination to determine whether or not to win a jackpot based on a display result of variable symbol special display. The random number circuit 503 updates numerical data in accordance with a set update rule within a numerical range in which an initial value (for example, 0) and an upper limit value (for example, 65535) are set, and starts at a random timing Based on the fact that the winning time is the reading (extraction) of the numerical data, it has a random number generation function in which the numerical data to be read becomes a random value.

  The random number circuit 503 includes a numeric data update range selection setting function (initial value selection setting function and upper limit value selection setting function), numeric data update rule selection setting function, and numeric data update rule selection. It has various functions such as a switching function. With such a function, the randomness of the generated random numbers can be improved.

  Further, the game control microcomputer 560 has a function of setting an initial value of numerical data updated by the random number circuit 503. For example, a predetermined calculation is performed using the ID number of the game control microcomputer 560 stored in a predetermined storage area such as the ROM 54 (an ID number assigned with a different value for each product of the game control microcomputer 560). The numerical data obtained by the execution is set as the initial value of the numerical data updated by the random number circuit 503. By performing such processing, the randomness of the random number generated by the random number circuit 503 can be further improved.

  The game control microcomputer 560 reads numerical data as random R from the random number circuit 503 when a start winning to the first start port switch 13a or the second start port switch 14a occurs, and performs a specific display based on the random R. It is determined whether or not to make a jackpot display result as a result, that is, whether or not to make a jackpot. When it is determined that the game is a big hit, the gaming state is shifted to a big hit gaming state as a specific gaming state advantageous to the player.

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power supply created on the power supply board. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data corresponding to the game state, that is, the control state of the game control means (such as the value of the special symbol process flag and the total reserved memory number counter) and the data indicating the number of unpaid winning balls are stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like occurs. Further, data corresponding to the control state and data indicating the number of unpaid winning balls are defined as data indicating the progress state of the game. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  A reset signal (not shown) from the power supply board is input to the reset terminal of the game control microcomputer 560. A reset circuit for generating a reset signal supplied to the game control microcomputer 560 and the like is mounted on the power supply board. When the reset signal becomes high level, the game control microcomputer 560 and the like are in an operable state, and when the reset signal becomes low level, the game control microcomputer 560 and the like are in an operation stop state. Therefore, an allowable signal that allows the operation of the game control microcomputer 560 or the like is output during a period when the reset signal is at a high level, and a game control microcomputer is output when the reset signal is at a low level. An operation stop signal for stopping the operation of 560 or the like is output. Note that the reset circuit may be mounted on each electric component control board (a board on which a microcomputer for controlling the electric parts is mounted).

  Further, a power-off signal indicating that the power supply voltage from the power supply board has dropped below a predetermined value is input to the input port of the game control microcomputer 560. That is, the power supply board monitors the voltage value of a predetermined voltage (for example, DC30V or DC5V) used in the gaming machine, and when the voltage value decreases to a predetermined value (the power supply voltage is reduced). A power supply monitoring circuit that outputs a power-off signal indicating that). A clear signal (not shown) indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port of the game control microcomputer 560.

  Further, an input driver circuit 58 for supplying detection signals from the gate switch 32a, the first start port switch 13a, the second start port switch 14a and the count switch 23 to the game control microcomputer 560 is also mounted on the main board 31. The main board also includes an output circuit 59 for driving the solenoid 16 for opening and closing the variable winning ball device 15 and the solenoid 21 for opening and closing the special variable winning ball device 20 that forms a big winning opening in accordance with a command from the game control microcomputer 560. 31. Further, an information output circuit (not shown) for outputting an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state to an external device such as a hall computer is also mounted on the main board 31.

  In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 instructs the effect contents from the game control microcomputer 560 via the relay board 77. A presentation control command is received, and display control is performed with the image display device 9 that variably displays the presentation symbols.

  FIG. 3 is a block diagram illustrating a circuit configuration example of the relay board 77, the effect control board 80, the lamp driver board 35, and the audio output board 70. In the example shown in FIG. 3, the lamp driver board 35 and the audio output board 70 are not equipped with a microcomputer, but may be equipped with a microcomputer. Further, without providing the lamp driver board 35 and the audio output board 70, only the effect control board 80 may be provided for effect control.

  The effect control board 80 has an effect control microcomputer 100 including an effect control CPU 101 and a RAM. The RAM may be externally attached. In the effect control board 80, the effect control CPU 101 operates in accordance with a program stored in a built-in or external ROM (not shown), and receives a capture signal from the main board 31 input via the relay board 77 ( In response to the (effect control INT signal), an effect control command is received via the input driver 102 and the input port 103a. Further, the effect control CPU 101 inputs a detection signal from the operation button 120 via the input port 103b. Further, the effect control CPU 101 causes the drawing processor (VDP: video display processor) 109 to perform display control of the image display device 9 based on the effect control command.

  In this embodiment, a VDP 109 that performs display control of the image display device 9 in cooperation with the effect control microcomputer 100 is mounted on the effect control board 80. The VDP 109 has an address space independent of the production control microcomputer 100, and maps a VRAM therein. The VRAM is a buffer memory for expanding image data generated by the VDP. Then, the VDP 109 outputs the image data in the VRAM to the image display device 9.

  The VDP 109 reads necessary data from a CGROM (not shown) according to the received effect control command in accordance with the instruction from the effect control CPU 101. The CGROM is for storing character image data displayed on the image display device 9, specifically, a person, a character, a figure, a symbol, etc. (including effect symbols) in advance. The VDP 109 executes display control based on the data read from the CGROM in accordance with the instruction from the effect control CPU 101.

  The effect control command and the effect control INT signal are first input to the input driver 102 on the effect control board 80. The input driver 102 passes the signal input from the relay board 77 only in the direction toward the inside of the effect control board 80 (does not pass the signal in the direction from the inside of the effect control board 80 to the relay board 77). It is also a unidirectional circuit as a regulating means.

  As a signal direction regulating means, the signal inputted from the main board 31 is allowed to pass through the relay board 77 only in the direction toward the effect control board 80 (the signal is not passed in the direction from the effect control board 80 to the relay board 77). The unidirectional circuit 74 is mounted. For example, a diode or a transistor is used as the unidirectional circuit. FIG. 3 illustrates a diode. A unidirectional circuit is provided for each signal. Furthermore, since the effect control command and the effect control INT signal are output from the main board 31 via the output port 571 that is a unidirectional circuit, the signal from the relay board 77 toward the inside of the main board 31 is restricted. That is, the signal from the relay board 77 does not enter the inside of the main board 31 (the game control microcomputer 560 side). The output port 571 is a part of the I / O port unit 57 shown in FIG. Further, a signal driver circuit that is a unidirectional circuit may be further provided outside the output port 571 (on the relay board 77 side).

  Further, the effect control CPU 101 outputs a signal for driving the LED to the lamp driver board 35 via the output port 105. Further, the production control CPU 101 outputs sound number data to the audio output board 70 via the output port 104.

  In the lamp driver board 35, a signal for driving the LED is input to the LED driver 352 via the input driver 351. The LED driver 352 supplies a drive signal to each LED provided on the frame side such as the top frame LED 28a, the left frame LED 28b, and the right frame LED 28c. Further, a drive signal is supplied to the decoration LED 25 provided on the game board side. When a light emitter other than the LED is provided, a drive circuit (driver) for driving the light emitter is mounted on the lamp driver substrate 35.

  In the voice output board 70, the sound number data is input to the voice synthesis IC 703 via the input driver 702. The voice synthesizing IC 703 generates voice or sound effect according to the sound number data, and outputs it to the amplifier circuit 705. The amplifier circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speakers 27R and 27L. The voice data ROM 704 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data showing the output form of the sound effect or sound in a time series in a predetermined period (for example, the changing period of the effect design).

  FIG. 4 is a block diagram showing a circuit configuration of the VDP 109. FIG. 4 also shows a CPU (production control CPU) 101, a ROM 112 for storing production control programs, various production patterns such as symbol display, light emission, and voice output, and a RAM 113 used as a work memory. ing.

  When executing display control of the image display device 6, the effect control CPU 101 gives a command corresponding to the effect control command to the VDP 109. The VDP 109 reads out necessary data from the CGROM 83 or the like according to the command. The CGROM 83 stores, for example, decorative patterns displayed on the image display device 6 and image data (moving image data and still image data) including characters (persons, animals), characters, figures, symbols, and the like. Note that the CGROM 83 may store moving image data or still image data obtained by actual shooting. The VDP 109 generates image data to be displayed on the image display device 9 according to the input data, and outputs R (red), G (green), B (blue) signals and a synchronization signal to the image display device 9. The image display device 9 incorporates a driver circuit that drives a display element, and performs, for example, a screen display by a dot matrix system that drives a large number of pixels.

  Specifically, the VRAM 84 and the frame buffer 85 are realized using SDRAM. In this embodiment, the VRAM 84 and the frame buffer 85 are separately configured. However, the VRAM 84 and the frame buffer 85 may be implemented using a common SDRAM. In this case, the SDRAM is provided with a frame buffer area and a VRAM area.

  The VDP 109 includes a drawing control unit 91 (drawing circuit), a display signal control unit 87 (display circuit) for outputting a signal to the image display device 9, a moving image decompression unit 89 that performs moving image decoding processing, and image data transfer. And a data transfer circuit 94 for performing the above. The drawing control unit 91 includes a VRAM address generation unit and the like.

  In addition, a CG bus interface (CG bus I / F) 93 is provided inside the VDP 109, and the data transfer circuit 94 and the moving image decompression unit 89 read image data from the CGROM 83 via the CG bus I / F 98. . In addition, a CPU I / F 92 is also provided inside the VDP 109, and the effect control CPU 101 can access a portion connected to the CG bus via the CPU I / F 92. Specifically, the effect control CPU 101 can access the drawing control register 95 connected to the CG bus. The drawing control register 95 stores a command from the effect control CPU 101 to the drawing control unit 91.

  In this embodiment, the variable display of the first special symbol by the first special symbol display device 8a is based on the fact that the game ball that has entered the first starting winning port 13 is detected by the first starting port switch 13a. After the start condition is satisfied, the start is made based on the fact that the start condition is satisfied, for example, by the last special symbol variable display, the big hit gaming state, or the small hit gaming state being completed. The variable display of the second special symbol by the second special symbol display 8b is performed after the second starting condition is satisfied, for example, when a game ball that has entered the second starting winning port 14 is detected by the second starting port switch 14a. For example, the game is started on the basis that the start condition is satisfied by, for example, the variable display of the previous special symbol, the big hit gaming state, or the small hit gaming state being ended.

  In the special symbol variable display by the first special symbol display unit 8a or the second special symbol display unit 8b, after a predetermined time has elapsed after the variable symbol special display is started, a fixed special that results in a variable symbol variable display result is obtained. The symbol is stopped and displayed (derived display). At this time, if a specific special symbol (big hit symbol) is stopped and displayed as a confirmed special symbol, it becomes a “big hit” as the specific display result, and a predetermined special symbol (small bonus symbol) different from the big hit symbol is stopped and displayed. Then, “small hit” is obtained as a predetermined display result, and if a special symbol other than the big hit symbol or the small hit symbol is stopped and displayed, “off” is obtained. After the variable display result in the variable display of the special symbol becomes “big hit”, the game is controlled to the big hit gaming state as the specific gaming state. Further, after the variable display result in the variable display of the special symbol becomes “small hit”, the small hit game state different from the big hit game state is controlled. In the pachinko gaming machine 1 in this embodiment, as an example, the numbers indicating “1”, “3”, and “7” are jackpot symbols, the numbers indicating “5” are small hit symbols, and “−” The symbol indicating is a missing symbol.

  In this embodiment, among the special symbols indicating the numbers “1”, “3”, and “7” that are jackpot symbols, the special symbols indicating the numbers “3” and “7” are 15 round jackpot symbols, A special symbol indicating the number “1” is a two-round jackpot symbol. In the big hit gaming state (15 round big hit state) as the first specific gaming state controlled after the 15 round big hit symbol is stopped and displayed as a fixed special symbol in the variable display of the special symbol, the opening / closing plate of the special variable winning ball apparatus 20 However, the special prize-winning ball apparatus 20 is controlled for the player by controlling the big prize opening to be open until a predetermined period (for example, 29 seconds), which is the first period, or until a predetermined number (for example, 10) of winning balls are generated. A round to change to an advantageous first state is performed. The opening / closing plate that opened the grand prize opening during the round receives the game ball falling on the surface of the game board 2. Thereafter, the special winning opening is closed, and the special variable winning ball apparatus 20 is changed to the second state which is disadvantageous for the player, thereby completing one round. In the 15 round big hit state, the number of executions of the round, which is the opening cycle of the big prize opening, is the first number (for example, “15”). A game in the 15-round big hit state in which the number of round executions is “15” is also referred to as a 15-time open game.

  In the big hit gaming state (two round big hit state) as the second specific gaming state controlled after the two round big hit symbol is stopped and displayed as the fixed special symbol in the variable display of the special symbol, the special variable winning ball apparatus 20 in each round The second period (for example, 0.5 seconds) in which the period during which the game is changed to the first state advantageous to the player (the period in which the big winning opening is opened by the opening / closing plate) is shorter than the first period in the 15 round big hit state It is. In the 2 round big hit state, the number of executions of the round is a second number (for example, “2”) smaller than the first number in the 15 round big hit state. In the two-round big hit state, at least one of the period in which the winning prize opening is opened in each round becomes the second period and the number of executions of the round becomes the second number is performed. Control other than that may be performed, and other control may be performed in the same manner as in the 15 round big hit state. A game in a two round big hit state in which the number of round executions is “2” is also referred to as a two-time open game. In the two-round big hit state, the predetermined winning ball apparatus provided separately from the special variable winning ball apparatus 20 in each round is changed from the second state that is disadvantageous to the player to the first state that is advantageous to the player. The second state may be restored after a predetermined period (first period or second period) has elapsed.

  In addition, among the special symbols indicating the numbers “3” and “7”, which are the 15 round big hit symbols, the special symbol indicating the number “3” is stopped and displayed as a fixed special symbol in the variable symbol variable display. After the base 15 round big hit state is over, as a special gaming state, the special symbol variable time (special figure variation time) in the variable display of the special symbol is controlled to a short time state compared to the normal state The The normal state is a special game state such as a big hit game state, a special game state such as a short-time state, or a game state other than the small hit game state, and an initial setting state of the pachinko gaming machine 1 (for example, a system reset is performed). As in the case where the initialization process is performed after the power is turned on, the same control is performed. The time-saving state ends when one of the conditions is established first, that is, the variable display of the special symbol is executed a predetermined number of times (for example, 100 times) and the variable display result is “big hit”. . In addition, after the 15 round big hit state based on the fact that the special symbol showing the number “3” out of the 15 round big hit symbols is stopped and displayed as the fixed special symbol in the variable display of the special symbols, Instead, it may be in a normal state. A 15-round jackpot symbol that is controlled to a short-time state or a normal state after the jackpot gaming state is ended after the jackpot gaming state based on being stopped and displayed as a fixed special symbol in the variable display of the special symbol, such as a special symbol indicating the number “3” Is usually referred to as a big hit symbol (also referred to as a “non-probable variable big hit symbol”).

  15 based on the special symbol indicating the number “7” among the special symbols indicating the numbers “3” and “7”, which are the big hit symbols of 15 rounds, being stopped and displayed as the confirmed special symbol in the variable symbol variable display 15 After the end of the round jackpot state, or after the end of the two round jackpot state based on the special symbol indicating the number of “1” being the two round jackpot symbol being stopped and displayed as a fixed special symbol in the variable display of the special symbol As one of the special gaming states different from the short-time state, for example, the special figure variation time is shortened compared to the normal state and the probability variation state (high probability gaming state) is controlled. In the following, the round two big hit is sometimes referred to as a sudden probability change (surprise) big hit.

  In the probability variation state, in the variable display of each special symbol and the decorative symbol variable display, the probability that the variable display result becomes “big hit” and is further controlled to the big hit gaming state is improved to be higher than in the normal state. The probability change state may be continued until the next variable display result becomes “big hit” regardless of the number of executions of the variable display of the special symbol. In addition, after entering the probability variation state, one of the conditions is established first, that is, the variable display of a special symbol is executed a predetermined number of times (for example, 100 times) and the variable display result is “big hit”. You may make it complete | finish when it does. Like the special symbol indicating the number “7”, the 15 round jackpot symbol that is controlled to the probable change state after the big hit gaming state based on the fact that it is stopped and displayed as the fixed special symbol in the variable display of the special symbol is It is called a jackpot symbol.

  After the small hit symbol is stopped and displayed as the fixed special symbol in the variable display of the special symbol, the small hit game state different from the big hit game state is controlled. In the small winning game state, a variable winning operation for changing the special variable winning ball apparatus 20 to the first state advantageous to the player is performed in the same way as the two round big hit state. That is, in the small hit game state, until the second number of times is reached, the operation of opening the large winning opening over the second period by the opening / closing plate in the special variable winning ball apparatus 20 is repeatedly executed. In the small hit gaming state, as in the two round big hit state, the period during which the big prize opening is opened is the second period, and the number of executions of the operation for opening the big prize opening is the second number. It may be controlled so that at least one of them is performed. After the small hit gaming state ends, the gaming state is not changed, and the game state before the variable display result is “small hit” is continuously controlled. When the winning ball device provided separately from the special variable winning ball device 20 in each round in the two round big hit state is changed to the first state, the same as the two round big hit state in the small hit gaming state. In the aspect, the winning ball apparatus may be changed to the first state.

  In the probability variation state and the short time state, the normal symbol variable display on the normal symbol display unit 10 can be controlled so that the variation time of the normal symbol (ordinary symbol variation time) is shorter than that in the normal state, or the normal symbol can be variably displayed each time. Control for improving the probability that the variable display result of the normal symbol is “per normal symbol” than in the normal state, and the opening time of the variable winning ball apparatus 15 based on the fact that the variable display result is “per normal symbol”. The second start condition is easily established by increasing the possibility that a game ball will enter the second start winning opening 14, such as control that is longer than that in the normal state and control that increases the number of times of opening is greater than that in the normal state. Control is performed. It should be noted that in the probability variation state or the short time state, any one of the respective controls may be performed, or a plurality of controls may be performed in combination. The control to be performed may be different between the probability variation state and the time-short state, or the combination of the controls to be performed (which may or may not include the same control) may be different.

  In the period from the start of variable display of decorative symbols to the end of variable display due to the stop display of the fixed decorative symbols in the “left”, “middle”, and “right” decorative symbol display areas, variable display of decorative symbols The state may become a predetermined reach state. The reach state means a decorative symbol that is not yet stopped and displayed when the decorative symbol that is stopped and displayed in the display area of the image display device 9 constitutes a part of the jackpot combination (also referred to as “reach variation symbol”). Is a display state in which the variation continues, or a display state in which all or part of the decorative symbols change synchronously while constituting all or part of the jackpot combination. Specifically, a part of the “left”, “middle”, and “right” decorative symbol display areas (for example, the “left” and “right” decorative symbol display areas) constitutes a predetermined jackpot combination. Decorative symbols are displayed in the remaining decorative symbol display area (for example, the “decorative” decorative symbol display area) that has not yet been stopped when decorative symbols (for example, decorative symbols indicating “7” alphanumeric characters) are stopped. The display pattern is changing, or the decorative symbols in all or part of the “left”, “middle”, and “right” decorative symbol display areas change synchronously while constituting all or part of the jackpot combination Is in the display state. Further, in response to the reach state, a character image (effect image imitating a person) different from the decorative design is displayed in the display area of the image display device 9, or the display mode of the background image is changed. Or change the variation of the decorative pattern. A change in the display mode of the character image, the display mode of the background image, and a change in the variation mode of the decorative pattern is referred to as reach effect display (or simply reach effect).

  Next, the operation of the gaming machine will be described. FIG. 5 is a flowchart showing main processing executed by the game control microcomputer 560 on the main board 31. When power is supplied to the gaming machine and power supply is started, the input level of the reset terminal to which the reset signal is input becomes high level, and the gaming control microcomputer 560 (specifically, the CPU 56) After executing a security check process, which is a process for confirming whether the contents of the program are valid, the main process after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2), and a stack pointer designation address is set to the stack pointer (step S3). After initialization of the built-in device (CTC (counter / timer) and PIO (parallel input / output port), which are built-in devices (built-in peripheral circuits)) is performed (step S4), the RAM is accessible (Step S5). In the interrupt mode 2, the address synthesized from the value (1 byte) of the specific register (I register) built in the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is This mode indicates an interrupt address.

  Next, the CPU 56 executes a process for providing a delay time. That is, a value (delay time value) corresponding to the delay time is set in a predetermined area of the RAM 55 (step S5A), and the delay time value is set to -1 (step S5B). When the delay time value becomes 0, the process proceeds to step S6 (step S5C). If the delay time value is not 0, the process returns to step S5B. When the power supply is started, the effect control microcomputer 100 executes a process of developing the decorative design image data in the VRAM 84. The process of providing the delay time is executed in order for the effect control microcomputer 100 to complete the process of developing the decorative design image data in the VRAM 84 before the CPU 56 enters the state of executing the game control process. As for the delay time, when the power supply is started, the VDP 109 develops the second data (for example, the image data of the decorative design) stored in the CGROM 83 in the VRAM 84 in accordance with the instruction of the effect control microcomputer 100. It is set to be longer than the time from the start of processing to the completion. Since the game control microcomputer 560 does not transmit a command to the sub-board until the delay time elapses, the process of providing the delay time is the second time when the game control microcomputer 560 can transmit the command. This corresponds to a delay process for delaying after the process of transferring data to the VRAM 84 is completed.

  Next, the CPU 56 checks the state of the output signal of the clear switch (for example, mounted on the power supply board) input via the input port (step S6). When the on-state is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S9 to S15).

  If the clear switch is not on, check whether data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) was performed when power supply to the gaming machine was stopped (Step S7). When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing. Whether there is backup data in the backup RAM area is confirmed, for example, by the state of the backup flag set in the backup RAM area in the power supply stop process.

  When it is confirmed that the power supply stop process has been performed, the CPU 56 performs data check of the backup RAM area (step S8). In this embodiment, a parity check is performed as a data check. Therefore, in step S8, the calculated checksum is compared with the checksum calculated and stored by the same process in the power supply stop process. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, an initialization process that is executed when the power is turned on is not performed when the power supply is stopped.

  If the check result is normal, the CPU 56 restores the game state recovery process (steps S41 to S44) for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Process). Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S41), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S42). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S41 and S42, the saved contents of the work area that should not be initialized remain as they are. The part that should not be initialized is, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, probability variation flag, time reduction flag, etc.), and the area where the output state of the output port is saved (output port buffer) ), A portion in which data indicating the number of unpaid prize balls is set.

  Further, the CPU 56 transmits a power failure recovery designation command as an initialization command at the time of power supply recovery (step S43). In addition, a display result specifying command, a combined pending storage number designation command, and a variation pattern command are transmitted (step S44). Then, the process proceeds to step S14. The variation pattern command is transmitted only when the special symbol and the decorative symbol are variably displayed when the power supply is stopped.

  There are a plurality of types of commands as the display result specifying command. In the process of step S44, the display result specifying command stored in the RAM 55 (the display result specifying command transmitted last when the power supply is stopped) is indicated. Send a command based on the data. Further, the total pending storage number designation command includes data indicating the total pending storage number, but in the process of step S44, the total pending storage number designation command including data indicating the total pending storage number stored in the RAM 55 is provided. Send. Then, a command based on data indicating the variation pattern command stored in the RAM 55 (the variation pattern command transmitted last when the power supply is stopped) is transmitted as the variation pattern command.

  In this embodiment, whether or not the data in the backup RAM area is stored is confirmed using both the backup flag and the check data, but only one of them may be used. That is, either the backup flag or the check data may be used as an opportunity for executing the game state restoration process.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S9). The RAM clear process initializes predetermined data (for example, count value data of a counter for generating a big hit determination random number) to 0, but is initialized to an arbitrary value or a predetermined value. You may make it do. Alternatively, the entire area of the RAM 55 may not be initialized, and predetermined data (for example, count value data of a counter for generating a big hit determination random number) may be left as it is. Further, the initial address of the initialization setting table stored in the ROM 54 is set as a pointer (step S10), and the contents of the initialization setting table are sequentially set in the work area (step S11).

  By the processing of steps S10 and S11, for example, a special symbol buffer, a total number of winning balls storage buffer, a special symbol process flag, a winning ball flag, a ball out flag, a payout stop flag, and the like are selectively processed according to the control state. An initial value is set in the flag for this.

  Further, the CPU 56 is an initialization designation command for initializing a sub board (a board on which a microcomputer other than the main board 31 is mounted) (a command indicating that the game control microcomputer 560 has executed initialization processing). Is transmitted to the sub-board (step S12). For example, when the initialization control microcomputer 100 receives the initialization designation command, the image display device 9 performs screen display for notifying that the control of the gaming machine has been performed, that is, initialization notification.

  In step S <b> 14, the CPU 56 executes a random number circuit setting process for initially setting the random number circuit 503. For example, the CPU 56 performs setting according to the random number circuit setting program to cause the random number circuit 503 to update the value of the random R.

  In step S15, the CPU 56 sets a register of the CTC built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 2 ms). That is, a value corresponding to, for example, 2 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 2 ms.

  When the execution of the initialization process (steps S10 to S15) is completed, the CPU 56 repeatedly executes the display random number update process (step S17) and the initial value random number update process (step S18) in the main process. When executing the display random number update process and the initial value random number update process, the interrupt disabled state is set (step S16). When the display random number update process and the initial value random number update process are finished, the interrupt enabled state is set. Set (step S19). In this embodiment, the display random number is a random number for determining a variation pattern and a random number for determining whether to reach or not, and the display random number update process is for generating a display random number. This is a process for updating the count value of the counter. The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is used to determine the initial value of the count value of a counter for generating a random number for determining whether or not to win the normal symbol display result (normal symbol determination random number generation counter). It is a random number. A game control process for controlling the progress of the game, which will be described later (the game control microcomputer 560 controls game devices such as a variable display device, a variable winning ball device, a ball payout device, etc. provided in the game machine itself. Counter for generating a random number in a process for transmitting a command signal to cause another microcomputer to control, or a game device control process) (a counter for generating a random number) When the value is incremented by the number of values between the minimum value and the maximum value that can be taken, the initial value is set in the counter.

  When the timer interrupt occurs, the CPU 56 executes the timer interrupt process in steps S21 to S35 shown in FIG. In the timer interrupt process, first, a power-off detection process for detecting whether or not a power-off signal is output (whether or not an on-state is turned on) is executed (step S21). The power-off signal is output when, for example, a voltage drop monitoring circuit mounted on the power supply board detects a drop in the voltage of the power supplied to the gaming machine. In the power-off detection process, when detecting that the power-off signal has been output, the CPU 56 executes a power supply stop process for saving necessary data in the backup RAM area. Next, detection signals of the gate switch 32a, the first start port switch 13a, the second start port switch 14a, and the count switch 23 are input via the input driver circuit 58, and the state determination is performed (switch processing: step) S22).

  Next, the CPU 56 has a first special symbol display 8a, a second special symbol display 8b, a normal symbol display 10, a first special symbol hold storage display 18a, a second special symbol hold storage display 18b, a normal symbol. A display control process for controlling the display of the on-hold storage display 41 is executed (step S23). For the first special symbol display 8a, the second special symbol display 8b, and the normal symbol display 10, a drive signal is output to each display according to the contents of the output buffer set in steps S33 and S34. Execute control.

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (determination random number update process: step S24). The CPU 56 further performs a process of updating the count value of the counter for generating the initial value random number and the display random number (initial value random number update process, display random number update process: steps S25 and S26).

FIG. 7 is an explanatory diagram showing each random number. Each random number is used as follows.
(1) Random 2: Determine the variation pattern (variation time) of the first special symbol and the second special symbol (for variation pattern determination)
(2) Random 3: Determines whether or not to generate a hit based on a normal symbol (for normal symbol hit determination)
(3) Random 4: Determine the initial value of random 3 (for determining the random 4 initial value)
(4) Random 5: Decide whether or not to reach if not a big hit (for reach determination)
(5) Random 6: Determine gaming state (probability variation state / normal state) (for gaming state determination)

  In step S24 in the game control process shown in FIG. 6, the game control microcomputer 560 uses a counter for generating (2) a random number for determining per ordinary symbol and (5) a random number for determining the game state. Count up (add 1). That is, they are determination random numbers, and other random numbers are display random numbers or initial value random numbers. In addition, in order to improve a game effect, you may use random numbers other than the random number of said (1)-(5). In this embodiment, the big hit determination random number (random R) is a random number generated by the hardware built in the game control microcomputer 560. The big hit determination random number is generated by the game control microcomputer 560 as the big hit determination random number. Software random numbers generated based on a program may be used.

  Further, the CPU 56 performs special symbol process processing (step S27). In the special symbol process, corresponding processing is executed according to a special symbol process flag for controlling the first special symbol indicator 8a, the second special symbol indicator 8b, and the special winning award in a predetermined order. The CPU 56 updates the value of the special symbol process flag according to the gaming state.

  Next, normal symbol process processing is performed (step S28). In the normal symbol process, the CPU 56 executes a corresponding process according to a normal symbol process flag for controlling the display state of the normal symbol display 10 and the open / close state of the variable winning ball apparatus 15 in a predetermined order. The CPU 56 updates the value of the normal symbol process flag according to the gaming state.

  Further, the CPU 56 performs a process of sending an effect control command to the effect control microcomputer 100 (effect control command control process: step S29).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S30).

  Further, the CPU 56 executes prize ball processing for setting the number of prize balls based on detection signals from the first start port switch 13a, the second start port switch 14a, and the count switch 23 (step S31). Specifically, the payout mounted on the payout control board 37 in response to winning detection based on any one of the first start port switch 13a, the second start port switch 14a, and the count switch 23 being turned on. A payout control command (prize ball number signal) indicating the number of prize balls is output to the control microcomputer. The payout control microcomputer drives the ball payout device 97 in accordance with a payout control command indicating the number of winning balls.

  In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 relates to on / off of the solenoid in the RAM area corresponding to the output state of the output port. The contents are output to the output port (step S32: output processing).

  Further, the CPU 56 performs special symbol display control processing for setting special symbol display control data for effect display of the special symbol in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S33). For example, if the variation speed is 1 frame / 0.2 seconds until the end flag is set when the start flag set in the special symbol process is set, the CPU 56, for example, every 0.2 seconds passes. Then, the value of the display control data set in the output buffer is incremented by one. Further, the CPU 56 outputs a drive signal in step S22 in accordance with the display control data set in the output buffer, whereby the first special symbol display unit 8a and the second special symbol display unit 8b Variable display of the second special symbol is executed.

  Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in an output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S34). For example, when the start flag related to the variation of the normal symbol is set, the CPU 56 switches the display state (“◯” and “×”) for the variation rate of the normal symbol every 0.2 seconds until the end flag is set. With such a speed, the value of the display control data set in the output buffer (for example, 1 indicating “◯” and 0 indicating “x”) is switched every 0.2 seconds. Further, the CPU 56 outputs a normal signal on the normal symbol display 10 by outputting a drive signal in step S22 according to the display control data set in the output buffer.

  Thereafter, the interrupt permission state is set (step S35), and the process is terminated.

  With the above control, in this embodiment, the game control process is started every 2 ms. The game control process corresponds to the processes of steps S21 to S34 (excluding step S30) in the timer interrupt process. In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed.

  FIG. 8 is an explanatory diagram showing a jackpot determination table. The jackpot determination table is a table in which a jackpot determination value to be compared with random R (random number for jackpot determination) is set. The big hit determination table is stored in the ROM 54. The big hit determination table includes a normal big hit determination table (FIG. 8A) used in a normal state (a gaming state that is not a probable change state), and a probable change big hit determination table (FIG. 8B) used in a positive change state. There is. The numerical values described in the left column of FIGS. 8A and 8B are jackpot determination values. The CPU 56 extracts a count value of a counter for generating a random R when an effective start winning occurs, and uses the extracted value as a random number for determining a big hit, and for starting a change in a special symbol, When the random number value matches the jackpot determination value shown in FIG. 8, it is determined that the jackpot or the jackpot is set for the first special symbol and the second special symbol.

  In this embodiment, when the game ball wins the first start winning opening 13 and when the game ball wins the second start winning opening 14, the normal probability / probability big hit / surprise big hit is obtained with the same probability. Although the allocation is made, that is, when the first special symbol is changed and the second special symbol is changed, the normal big hit / probable big hit / surprise big hit is assigned with the same probability. For example, the probability variation big hit / surprise big hit distribution may be changed between when the game ball wins the first start winning opening 13 and when the game ball wins the second start winning opening 14. As an example, when a game ball wins the second start winning opening 14, the probability of winning a big hit is set to 0, and the probability change state (the variable winning ball apparatus 15 having the second start winning opening 14 is likely to be opened, and , The opening time is long.) It may be difficult to make a big hit, and the interest of the game may not be reduced.

  FIG. 9 is an explanatory diagram showing a gaming state determination table. The gaming state determination table is a table in which determination values to be compared with random 6 (random number for determining gaming state) are set for each jackpot type. FIG. 9 shows the number of determination values, not the determination values themselves. The gaming state determination table is stored in the ROM 54. The CPU 56 extracts the count value of the counter for generating the gaming state determination random number when the effective start winning occurs, and uses the extracted value as the gaming state determination random number value, and starts the variation of the special symbol. When the random number value for determining the game state matches the determination value corresponding to each jackpot type, the jackpot type is determined as the jackpot type.

  FIG. 10 is an explanatory diagram illustrating an example of a variation pattern. In the variation pattern of super reach shown in FIG. 10 (A), the decorative symbol fluctuates at high speed for 5 seconds from the start of variation, and after the left symbol stops, the right symbol stops and reaches reach (the left and right symbols all stop together). ) And super reach production is executed. When the fluctuation time from the start of fluctuation elapses, the left middle right symbol is finally stopped. In the normal reach variation pattern shown in FIG. 10B, the decorative symbol fluctuates at a high speed for 5 seconds from the start of variation, and after the left symbol stops, the right symbol stops and reaches (the left and right symbols all stop together). A normal reach effect is executed. When the fluctuation time from the start of fluctuation elapses, the left middle right symbol is finally stopped. It should be noted that, when the decorative symbol is changed by the super reach variation pattern, the big hit is made at a higher rate or at a rate of 100% than when the decorative symbol is changed by the normal reach variation pattern.

  In the deviation variation pattern shown in FIG. 10C, the decorative symbol fluctuates at high speed for 5 seconds from the start of variation, and the middle symbol and the right symbol stop after the left symbol stops. In the variation pattern at the time of accuracy / small hit shown in FIG. 10 (D), the decorative symbol fluctuates at high speed for 2 seconds from the start of variation, and the left middle right symbol stops. The variation pattern at the time of sudden hit / small hit is used when it is decided to make a small hit and when it is decided to suddenly make a big hit suddenly.

  The deviation variation pattern shown in FIG. 10E is a variation pattern used when a deviation is determined in the probability variation state and when a deviation is determined in the time reduction state. The variation pattern and variation time at the time of accuracy / small hit shown in FIG. 10D are the same, but the display effects executed during the variation in the image display device 9 are different.

  FIG. 11 is an explanatory diagram showing a variation pattern and a variation time used in this embodiment. Variation pattern 1, which is a variation pattern of super reach, is used only when it is decided to make a big hit. The fluctuation pattern 2 which is a fluctuation pattern of super reach is used when it is decided to make a big hit, but it is also used at a low rate when it is decided to make a deviation. The fluctuation patterns 3 and 4 which are fluctuation patterns of the normal reach are used when it is decided to make a big hit or not. The fluctuation pattern 5 which is a fluctuation pattern of normal reach is used only when it is decided to make a deviation. The variation patterns 6 to 8 are used when the gaming state is a certain variation state or a short time state. The fluctuation pattern 9 is the fluctuation pattern shown in FIG. 10C, the fluctuation pattern 10 is the fluctuation pattern shown in FIG. 10D, and the fluctuation pattern 11 is shown in FIG. Variation pattern.

  FIG. 12 is an explanatory diagram of a reach determination table. The reach determination table is a table in which a reach determination value to be compared with random 5 (reach determination random number) is set. The reach determination table is stored in the ROM 54. The reach determination table includes a determination table (see FIG. 12A) that is used when the total number of pending storages is 3 or less (less than 4) at the start of fluctuation of the first special symbol, and at the start of fluctuation of the first special symbol. A determination table (see FIG. 12 (B)) used when the total number of pending storages is 4 or more, and a determination table used when the total number of pending storages is 3 or less (less than 4) when the second special symbol starts to change (See FIG. 12 (C)) and a determination table (see FIG. 12 (D)) used when the total number of pending storages is 4 or more at the start of fluctuation of the second special symbol.

  The CPU 56 extracts the count value of the counter for generating the random 5 and uses the extracted value as the reach determination random number value when the effective start winning is generated (at the time of starting the variation of the special symbol). When it is decided not to make a big hit at the start of the fluctuation, it is decided to reach when the reach determination random number value matches the reach determination value shown in FIG.

  As shown in FIG. 12, when the total number of pending storage is large, the ratio determined to reach is low. Also, the reach determination table (see FIGS. 12A and 12B) used when the first special symbol starts to change and the reach determination table used when the second special symbol starts changing (FIGS. 12C and 12D). ))), The number of reach determination values is different. Specifically, the number of reach determination values in the reach determination table used at the start of the variation of the second special symbol is smaller. In this embodiment, the reach determination table to be used is changed depending on whether or not the total pending storage number is 4 or more. However, “4” is an example and is a value for changing the reach determination table to be used. Other values may be used as A plurality of values may be used as values for changing the reach determination table to be used. As an example, the reach determination table used when the total pending storage number is less than 4, the reach determination table used when the total pending storage number is 4 to 6, and the total pending storage number is 7 or more. A reach determination table is used. In this embodiment, the reach determination table used at the start of fluctuation of the first special symbol and the reach determination table used at the start of fluctuation of the second special symbol are separated, but they are common to one table. May be used. In that case, the ratio of reaching / not reaching is the same when the first special symbol is changed and when the second special symbol is changed, when the big hit is not made.

  FIG. 13 is an explanatory diagram showing an example of the contents of the effect control command transmitted by the game control microcomputer 560. In the example shown in FIG. 13, the command 80XX (H) is an effect control command (variation pattern) that specifies a variation pattern of an effect symbol (decoration symbol) that is variably displayed on the image display device 9 in response to variable display of a special symbol. Command) (corresponding to the variation pattern XX, respectively). “(H)” indicates a hexadecimal number. The effect control command for designating the variation pattern is also a command for designating the start of variation. Accordingly, when receiving the command 80XX (H), the effect control microcomputer 100 controls the image display device 9 to start variable display of the effect symbol (decorative symbol).

  The commands 8C01 (H) to 8C05 (H) are effect control commands indicating whether or not to make a big hit and the type of the big hit game. The production control microcomputer 100 determines the display results of the decorative symbols and the production symbols in response to the reception of the commands 8C01 (H) to 8C05 (H), so that the commands 8C01 (H) to 8C05 (H) are specified as the display results. It is called a command.

  Command 8D01 (H) is an effect control command (first symbol variation designation command) indicating that variable display (variation) of the first special symbol is started. Command 8D02 (H) is an effect control command (second symbol variation designation command) indicating that variable display (variation) of the second special symbol is started. The first symbol variation designation command and the second symbol variation designation command may be collectively referred to as a special symbol specifying command (or symbol variation designation command). Note that information indicating whether to start variable display of the first special symbol or variable display of the second special symbol may be included in the variation pattern command.

  Command 8F00 (H) is an effect control command (symbol confirmation designation command) indicating that the variable display (fluctuation) of the effect symbol (decoration symbol) is terminated and the display result (stop symbol) is derived and displayed. When receiving the symbol confirmation designation command, the effect control microcomputer 100 ends the variable display (fluctuation) of the effect symbol (decoration symbol) and derives and displays the display result.

  Command 9000 (H) is an effect control command (initialization designation command: power-on designation command) transmitted when power supply to the gaming machine is started. Command 9200 (H) is an effect control command (power failure recovery designation command) transmitted when power supply to the gaming machine is resumed. When the power supply to the gaming machine is started, the gaming control microcomputer 560 transmits a power failure recovery designation command if data is stored in the backup RAM, and if not, initialization designation is performed. Send a command.

  Command 9F00 (H) is an effect control command (customer waiting demonstration designation command) for designating a customer waiting demonstration.

  The commands A001 to A003 (H) are for displaying a fanfare screen, that is, an effect control command for designating the start of a jackpot game or the start of a jackpot game (a jackpot start designation command or a jackpot start designation command: a fanfare designation command). is there. The big hit start designation command or the small hit start designation command includes a big hit start 1 designation command, a big hit start designation 2 designation command, and a small hit / rush start designation command corresponding to the type or small hit. The command A1XX (H) is an effect control command (special command during opening of a big winning opening) indicating a display during the opening of the big winning opening for the number of times (round) indicated by XX. A2XX (H) is an effect control command (designation command after opening the big winning opening) indicating the closing of the big winning opening for the number of times (round) indicated by XX.

  Command A301 (H) displays a jackpot end screen, that is, specifies the end of the jackpot game and an effect control command (special jackpot end 1 designation command: ending) that specifies that the jackpot game is a non-probable big hit (usually a big hit) 1 designation command). Command A302 (H) is an effect control command for displaying the jackpot end screen, that is, the end of the jackpot game and specifying that it is a probable big hit (big hit end 2 designation command: ending 2 designation command). is there. Command A303 (H) is an effect control command (small hit / probability end designation command: ending 3 designation command) for designating the end of the small hit game or the sudden probability change game.

  The command C000 (H) is an effect control command (first start winning designation command) for designating that there is a first start winning. The command C100 (H) is an effect control command (second start winning designation command) for designating that the second starting win has been won. The first start prize designation command and the second start prize designation command may be collectively referred to as a start prize designation command.

  The command C2XX (H) is an effect control command (total pending storage number designation command) for designating a total number (total pending storage number) that is the sum of the first reserved memory number and the second reserved memory number. “XX” in the command C2XX (H) indicates the total pending storage number. The command C300 (H) is an effect control command (total pending storage count subtraction designation command) that designates that the total pending storage count is decremented by one. In this embodiment, the game control microcomputer 560 transmits a total pending storage number subtraction designation command when subtracting the total pending storage number, but does not use the total pending storage number subtraction designation command, and does not use the total pending storage number subtraction designation command. When the stored number is subtracted, the combined pending storage number after the subtraction may be designated by a combined pending storage number designation command.

  The effect control microcomputer 100 (specifically, the effect control CPU 101) mounted on the effect control board 80 receives the above-described effect control command from the game control microcomputer 560 mounted on the main board 31. Then, the display state of the image display device 9 is changed according to the contents shown in FIG. 13, the display state of the lamp is changed, and the sound number data is output to the audio output board 70.

  In this embodiment, the effect control command has a 2-byte structure, the first byte represents MODE (command classification), and the second byte represents EXT (command type). The first bit (bit 7) of the MODE data is always set to “1”, and the first bit (bit 7) of the EXT data is always set to “0”. Note that such a command form is an example, and other command forms may be used. For example, a control command composed of 1 byte or 3 bytes or more may be used.

  In addition, as the transmission method of the effect control command, the effect control command data is output from the main board 31 to the effect control board 80 via the relay board 77 on the eight parallel signal lines of the effect control signals CD0 to CD7, In addition to the effect control command data, a method of outputting a pulse-like (rectangular wave) capture signal (effect control INT signal) for instructing capture of the effect control command data is used. The 8-bit effect control command data of the effect control command is output in synchronization with the effect control INT signal. The effect control microcomputer 100 mounted on the effect control board 80 detects that the effect control INT signal has risen, and starts a 1-byte data capturing process through an interrupt process.

  In the example shown in FIG. 13, the variable pattern command and the display result specifying command are displayed in a variable display (variation) of the decorative symbol corresponding to the variation of the first special symbol on the first special symbol indicator 8a and the second special symbol indicator. The image display device 9 that can be used in common with the variable display (variation) of the decorative symbol corresponding to the variation of the second special symbol in 8b, and that produces effects in accordance with the variable display of the first special symbol and the second special symbol. When controlling the effect parts, it is possible to prevent an increase in the types of commands transmitted from the game control microcomputer 560 to the effect control microcomputer 100.

  The command 8D01 (H) (first symbol variation designation command) and command 8D02 (H) (second symbol variation designation command) are, for example, during the variable display time of the first special symbol by the first special symbol display 8a. Is provided with a first effect symbol display (display means different from the image display device 9) for variably displaying the first effect symbol as a decorative (effect) symbol, and the second special symbol display 8b provides a second display. (2) A second effect symbol display (display means different from the image display device 9) is provided for performing variable display of the second effect symbol as a decorative (effect) symbol during the variable symbol variable display time. In this case, the production control microcomputer 100 can be used to determine which production symbol display the production symbol should be changed.

  14 and 15 are explanatory diagrams illustrating an example of the transmission timing of the effect control command. FIG. 14A shows an example when a start prize (first start prize or second start prize) occurs. The game control microcomputer 560 transmits the first start prize designation command (or the second start prize designation command), and then continuously transmits the total pending storage number designation command. Specifically, a first start winning designation command (or second start winning designation command) is transmitted in a game control process based on a timer interrupt, and then a combined pending storage number designation command is transmitted.

  As shown in FIG. 14B, the game control microcomputer 560 transmits a variation pattern command, a special symbol identification command, a display result identification command, and a total pending storage number subtraction designation command at the start of variation. When the variable display time (fluctuation time) elapses, a symbol confirmation designation command is transmitted.

  FIG. 15A shows an example when power supply is started (when power is turned on). The game control microcomputer 560 transmits a customer waiting demonstration designation command after transmitting a power-on designation command.

  FIG. 15B shows an example when power supply is resumed (when power failure is restored). The game control microcomputer 560 continuously transmits a power failure recovery designation command, a display result specifying command, and a combined pending storage number designation command. The effect symbol type storage area formed in the RAM 55 is stored for a predetermined period even when the power supply to the gaming machine is stopped. Therefore, when the power supply is resumed, the game control microcomputer 560 displays the effect symbol type storage area. A display result specifying command is transmitted based on the data stored in the type storage area. Further, the value of the total pending storage number counter formed in the RAM 55 is stored for a predetermined period even when the power supply to the gaming machine is stopped. Therefore, when the power supply is resumed, the game control microcomputer 560 is restored. Transmits a total pending storage number designation command based on the stored total pending storage number counter value. Note that “formed in the RAM” means an area in the RAM.

  Next, the special symbol process (step S27) in the main process will be described. FIG. 16 is a flowchart showing an example of a special symbol process processing program executed by the game control microcomputer 560 (specifically, the CPU 56 of the game control microcomputer 560). The game control microcomputer 560 is provided with a first start port switch 13a or a second start for detecting that a game ball has won a first start winning port 13 provided in the game board 6 in the special symbol process. If the second start opening switch 14a for detecting that the game ball has won the winning opening 14 is turned on, that is, the start winning in which the game ball wins the first start winning opening 13 or the second start winning opening 14 is made. If it has occurred (step S311), after performing the start port switch passing process (step S312), any one of steps S300 to S310 is performed according to the internal state. If the first start winning port 13 or the second start port switch 14a is not turned on, any one of steps S300 to S310 is performed according to the internal state.

  In step S311, the game control microcomputer 560 determines whether the bit corresponding to the first start winning port 13 or the second start port switch 14a is on in the input data input from the input port, for example. You may check. Further, for example, in the switch process (see step S21), the flag is set based on the fact that the first start winning port 13 or the second start port switch 14a is turned on twice in succession, and the game control The microcomputer 560 may confirm whether or not the flag is set in step S311.

  Special symbol normal processing (step S300): Executed when the value of the special symbol process flag is zero. When the game control microcomputer 560 is in a state where variable display of a special symbol can be started, the game control microcomputer 560 checks the number of numerical data stored in the reserved storage number buffer (total reserved storage number). The number of numerical data stored in the reserved storage number buffer can be confirmed by the count value of the total reserved storage number counter. If the count value of the total reserved memory number counter is not 0, it is determined whether the display result of the variable display of the first special symbol or the second special symbol is a big hit or a small hit. In case of big hit, set big hit flag. In the case of a small hit, a small hit flag is set. Then, the internal state (special symbol process flag) is updated to a value (1 in this example) according to step S301. The big hit flag and the small hit flag are reset when the big hit game or the small hit game ends.

  Fluctuation pattern setting process (step S301): This process is executed when the value of the special symbol process flag is 1. A variation pattern of variable display of a special symbol (corresponding to the variation time here) is selected from a plurality of types of variation patterns determined in advance according to the value of the variation pattern determination random number (random 2) extracted at the time of start winning. select. Further, control is performed to transmit information for instructing a variation pattern (a variation pattern command, that is, a variable display pattern command) to the production control microcomputer 100. Then, the internal state (special symbol process flag) is updated to a value (2 in this example) according to step S302.

  Display result specifying command transmission process (step S302): executed when the value of the special symbol process flag is 2. Control for transmitting a display result specifying command to the production control microcomputer 100 is performed. Then, the internal state (special symbol process flag) is updated to a value (3 in this example) corresponding to step S303.

  Special symbol changing process (step S303): This process is executed when the value of the special symbol process flag is 3. When the variation time of the variation pattern selected in the variation pattern setting process elapses (the variation time timer set in step S301 times out, that is, the variation time tie value becomes 0), the internal state (special symbol process flag) is stepped. The value is updated to 4 according to S304 (4 in this example).

  Special symbol stop process (step S304): The special symbol in the first special symbol display 8a or the second special symbol display 8b is stopped. Further, control is performed to transmit a symbol confirmation designation command to the production control microcomputer 100. If the stop symbol of the special symbol is a jackpot symbol, the internal state (special symbol process flag) is updated to a value (5 in this example) according to step S305. Otherwise, the internal state (special symbol process flag) is updated to a value (0 in this example) according to step S300.

  Preliminary winning opening opening process (step S305): This is executed when the value of the special symbol process flag is 5. In the pre-opening process for the big prize opening, control for opening the big prize opening is performed. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized, and the solenoid 21 is driven to open the special variable winning ball apparatus 20 to the big prize opening. Is released. Also, the execution time of the special winning opening opening process is set by the process timer, and the internal state (special symbol process flag) is updated to a value (6 in this example) according to step S306. The pre-opening process for the big winning opening is executed for each round, but when the first round is started, the pre-opening process for the big winning opening is also a process for starting the big hit game.

  Large winning opening opening process (step S306): This process is executed when the value of the special symbol process flag is 6. A control for sending an effect control command for a round display during the big hit gaming state to the effect control microcomputer 100, a process for confirming the establishment of the closing condition of the big prize opening, and the like are performed. Further, when the closing condition for the special winning opening is established, the control for closing the special winning opening is performed. Specifically, the solenoid 21 is driven to close the special variable winning ball apparatus 20 to close the special winning opening. If the closing condition for the special prize opening is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. When all the rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S307 (7 in this example).

  Big hit end process (step S307): executed when the value of the special symbol process flag is 7. Control is performed to cause the microcomputer 100 for effect control to perform display control for notifying the player that the big hit gaming state has ended. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) according to step S300.

  Small hit release pre-processing (step S308): This process is executed when the value of the special symbol process flag is 8. In the pre-opening process for small hits, control is performed to open the big prize opening. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized, and the solenoid 21 is driven to open the big prize opening. Also, the execution time of the special prize opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value (9 in this example) corresponding to step S309. It should be noted that although the pre-opening process for small hits is executed for each round, the pre-opening process for small hits is also a process for starting a small hit game when starting the first round.

  Small hit release processing (step S309): executed when the value of the special symbol process flag is 9. A control for transmitting an effect control command for a round display during the small hit gaming state to the effect control microcomputer 100, a process for confirming the completion of the closing condition of the big prize opening, and the like are performed. If the closing condition for the big prize opening is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to a value corresponding to step S308 (8 in this example). When all rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S310 (in this example, 10 (decimal number)).

  Small hit end process (step S310): executed when the value of the special symbol process flag is 10. Control is performed to cause the microcomputer 100 for effect control to perform display control for notifying the player that the small hit gaming state has ended. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  FIG. 17 is a flowchart showing the start port switch passing process in step S312. In the start port switch passing process executed when at least one of the first start port switch 13a and the second start port switch 14a is in the on state, the CPU 56 is turned on by the first start port switch 13a. Whether or not (step S211). If the first start port switch 13a is on, the CPU 56 checks whether or not the value of the first reserved memory number counter for counting the first reserved memory number is 4 (step S212). If the value of the first reserved memory number counter is 4, the process proceeds to step S221.

  If the value of the first reserved memory number counter is not 4, the CPU 56 increments the value of the first reserved memory number counter by 1 (step S213). Further, the CPU 56 corresponds to the value of the total reserved storage number counter in the reserved storage specific information storage area (hold specific area) for storing the winning order to the first start winning opening 13 and the second start winning opening 14. Data indicating “first” is set in the area (step S214).

  In this embodiment, when the first start opening switch 13a is turned on (that is, when a game ball starts and wins the first start winning opening 13), data indicating “first” is set, When the second start port switch 14a is turned on (that is, when a game ball starts and wins the second start winning port 14), data indicating “second” is set. For example, the CPU 56 sets 01 (H) as data indicating “first” when the first start port switch 13 a is turned on in the reserved storage specifying information storage area (holding specified area), and the first 2 When the start port switch 14a is turned on, 02 (H) is set as data indicating “second”. In this case, when there is no corresponding reserved storage, 00 (H) is set in the reserved storage specific information storage area (hold specific area).

  In addition, you may implement | achieve the process of step S213-218 and the process of step S223-228 by one common routine. In that case, the CPU 56 first sets data indicating “first” when detecting that the first start port switch 13a is turned on, and indicates that the second start port switch 14a is turned on. When data is detected, the data indicating “second” is set, and the common storage routine selects the reserved memory number buffer (first reserved memory number buffer or second reserved memory number buffer) according to the set data. Or a start prize designation command (first start prize designation command or second start prize designation command) is selected.

  FIG. 18A is an explanatory diagram showing a configuration example of a reserved storage specifying information storage area (holding specified area). As shown in FIG. 18A, an area corresponding to the maximum value (8 in this example) of the total reserved memory number counter is secured in the reserved specific area. FIG. 18A shows an example in which the value of the total pending storage number counter is 5. As shown in FIG. 18A, an area corresponding to the maximum value (8 in this example) of the total reserved memory number counter is secured in the reserved specific area, and the first start winning opening 13 or the second start is determined. Data indicating “first” or “second” is set in order of winning based on winning in the winning opening 14. Accordingly, in the reserved storage specific information storage area (hold specific area), the winning order to the first start winning opening 13 and the second starting winning opening 14 is stored. Note that the reserved specific area is formed in the RAM 55.

  FIG. 18B is an explanatory diagram showing a configuration example of an area (hold buffer) for storing a random number or the like corresponding to the hold memory. As shown in FIG. 18B, a storage area corresponding to the upper limit value (4 in this example) of the first reserved storage number is secured in the first reserved storage buffer. In addition, a storage area corresponding to the upper limit value of the second reserved storage number (4 in this example) is secured in the second reserved storage buffer. The first reserved storage buffer and the second reserved storage buffer are formed in the RAM 55.

  In the start port switch passing process, the CPU 56 extracts a value from the random number circuit 503 and a counter for generating a software random number, and executes a process of storing them in the storage area in the first reserved storage buffer (step S215). . In the process of step S215, random R (a big hit determination random number) and random numbers 2, 5, and 6 (see FIG. 7) are stored in the storage area.

  Next, the CPU 56 performs control to transmit a first start winning designation command (step S216). Further, the CPU 56 increases the value of the total pending memory number counter indicating the total pending memory number that is the sum of the first reserved memory number and the second reserved memory number by 1 (step S217). Then, the CPU 56 performs control to transmit a total pending storage number designation command indicating the total pending storage number based on the value of the total pending storage number counter (step S218). Note that the total pending storage number designation command may be transmitted before the first start winning designation command.

  When transmitting an effect control command to the effect control microcomputer 100, the CPU 56 sets an address of a command transmission table (preliminarily set for each command in the ROM) corresponding to the effect control command as a pointer. . And the address of the command transmission table according to an effect control command is set to a pointer, and an effect control command is transmitted in an effect control command control process (step S29).

  Next, the CPU 56 checks whether or not the second start port switch 14a is turned on (step S221). If the second start port switch 14a is on, the CPU 56 checks whether or not the value of the second reserved memory number counter for counting the second reserved memory number is 4 (step S222). If the value of the second reserved memory number counter is 4, the process is terminated. If the value of the second reserved memory number counter is 4, the CPU 56 may perform the process of confirming again whether the first start port switch 13a is on (see step S211).

  If the value of the second reserved memory number counter is not 4, the CPU 56 increases the value of the second reserved memory number counter by 1 (step S223). Further, the CPU 56 sets data indicating “second” in an area corresponding to the value of the total reserved storage number counter in the reserved storage specific information storage area (hold specific area) (step S224).

  Next, the CPU 56 extracts values from the random number circuit 503 and a counter for generating software random numbers, and executes a process of storing them in a storage area in the second reserved storage buffer (step S225). In the process of step S225, random R (big hit determination random number) read from the random number circuit 503 and random numbers 2, 5, and 7 (see FIG. 7) that are software random numbers are stored in the storage area.

  Next, the CPU 56 performs control to transmit a second start winning designation command (step S226). Further, the CPU 56 increases the value of the total pending storage number counter by 1 (step S227). Then, the CPU 56 transmits a total pending storage number designation command based on the value of the total pending storage number counter (step S228). Note that the total pending storage number designation command may be transmitted before the second start winning designation command.

  Further, in this embodiment, the case where the first reserved memory number buffer and the second reserved memory number buffer are separately provided is described as an example, but the first reserved memory number and the second reserved memory number are common. A reserved storage number buffer may be provided. FIG. 19 is an explanatory diagram of a configuration example of a common reserved memory number buffer provided in common for the first reserved memory number and the second reserved memory number. As shown in FIG. 18, the common reserved storage number buffer includes eight areas obtained by combining the reserved storage specifying information storage area and the random value storage area. In the common reserved storage number buffer, consecutive addresses are assigned to the reserved storage specific information storage area and the random value storage area.

  20 and 21 are flowcharts showing the special symbol normal process (step S300) in the special symbol process. In the special symbol normal process, the CPU 56 confirms the value of the total pending storage number (step S51). Specifically, the count value of the total pending storage number counter is confirmed. If the total pending storage number is 0, the process is terminated.

  If the total pending storage number is not 0, the CPU 56 checks whether or not the first data among the data set in the pending specific area (see FIG. 18A) is data indicating “first”. (Step S52). If it is data indicating “first”, a special symbol pointer (a flag indicating whether special symbol process processing is being performed for the first special symbol or special symbol process processing is being performed for the second special symbol) is set to “first 1 "is set (step S53). If it is not data indicating “first”, that is, if it is data indicating “second”, data indicating “second” is set in the special symbol pointer (step S54).

  In the RAM 55, the CPU 56 reads out each random number value stored in the storage area corresponding to the reserved storage number = 1 indicated by the special symbol pointer, and stores it in the random number buffer area of the RAM 55 (step S55). Specifically, when the special symbol pointer indicates “first”, the CPU 56 determines each disturbance stored in the storage area corresponding to the first reserved memory number = 1 in the first reserved memory number buffer. The numerical value is read and stored in the random number buffer area of the RAM 55. In addition, when the special symbol pointer indicates “second”, the CPU 56 reads each random number value stored in the storage area corresponding to the second reserved memory number = 1 in the second reserved memory number buffer. And stored in the random number buffer area of the RAM 55.

  Then, the CPU 56 decrements the count value of the reserved storage number counter indicated by the special symbol pointer, and shifts the contents of each storage area (step S56). Specifically, when the special symbol pointer indicates “first”, the CPU 56 decrements the count value of the first reserved memory number counter by 1 and saves each storage area in the first reserved memory number buffer. Shift the contents of. When the special symbol pointer indicates “second”, the count value of the second reserved memory number counter is decremented by 1, and the contents of each storage area in the second reserved memory number buffer are shifted.

  That is, when the special symbol pointer indicates “first”, the CPU 56 saves the first reserved memory number = n (n = 2, 3, 4) in the first reserved memory number buffer of the RAM 55. Are stored in a storage area corresponding to the first reserved memory number = n−1. Further, when the special symbol pointer indicates “second”, it is stored in the storage area corresponding to the second reserved memory number = n (n = 2, 3, 4) in the second reserved memory number buffer of the RAM 55. Each random number value is stored in a storage area corresponding to the second reserved memory number = n−1.

  Therefore, the order in which each random value stored in each storage area corresponding to each first reserved memory number (or each second reserved memory number) is extracted is always the first reserved memory number (or (Second reserved storage number) = 1, 2, 3, 4 in order.

  Then, the CPU 56 stores the count value of the total pending storage number counter in a predetermined area of the RAM 55 (step S57), and then decreases the value of the total pending storage number by one. That is, 1 is subtracted from the count value of the total pending storage number counter (step S58). The CPU 56 stores the value of the total pending storage number counter before the count value is decremented by 1 in a predetermined area of the RAM 55.

  In the special symbol normal process, first, data indicating “first” indicating that the process is executed for the first start winning opening 13, that is, “first” indicating that the process is executed for the first special symbol. ”Or“ second ”indicating that the process is performed on the second special symbol, that is,“ second ”indicating that the process is performed on the second start winning opening 14. Data is set in the special symbol pointer. In the subsequent processing in the special symbol process, processing corresponding to the data set in the special symbol pointer is executed. Therefore, the process of steps S300 to S310 can be made common between the case of targeting the first special symbol and the case of targeting the second special symbol.

  Next, the CPU 56 reads a random R (a jackpot determination random number) from the random number buffer area (step S61), and executes a jackpot determination module (step S62). The jackpot determination module is a program that compares a jackpot determination value (see FIG. 8) determined in advance with a jackpot determination random number, and executes a process of determining whether to hit a jackpot or a small hit if they match.

  Note that when the gaming state is in the probability variation state, the CPU 56 uses the jackpot determination value in the table in which the jackpot determination value as shown in FIG. 8B is set, and the gaming state is in the normal state (non-probability variation state). Is, the jackpot judgment value in the table in which the jackpot judgment value as shown in FIG. 8A is set is used. If it is determined to be a big hit (step S63), the process proceeds to step S64. Note that deciding whether to win or not is to decide whether or not to shift to the big hit gaming state, but to decide whether or not to stop the special symbol display as a big hit symbol. But there is.

  If it is determined to be a small hit (step S72), a small hit flag is set (step S73). Then, the process proceeds to step S75. When not making a small hit, the CPU 56 proceeds to step S75 as it is.

  In step S64, the CPU 56 sets a big hit flag. Then, the game state determination random number is read from the random number buffer area (step S65), and it is determined whether or not to make a probable big hit based on the game state determination random number. When it is determined that the probability variation big hit is to be made, the probability variation big hit flag is set (steps S66 and S67). If it is determined that the sudden probability change big hit is suddenly set, the sudden probability change big hit flag is set (steps S68 and S69).

  Then, data indicating the stop symbol of the special symbol is stored in a predetermined area of the RAM 55 (step S75), and the value of the special symbol process flag is updated to a value corresponding to the variation pattern setting process (step S301) (step S76).

  In this embodiment, the stop symbol of the special symbol is “7” when it is decided to make a probable big hit, and “1” when it is decided to make a probable big hit suddenly. Yes, it is “3” if it is usually decided to make a big hit, and “5” if it is decided to make a big hit. If it is determined to be off, it is “-”. In the process of step S80, data indicating those stopped symbols is stored in the RAM 55. Note that the stop symbol may be determined by lottery using a random number.

  FIG. 22 is a flowchart showing the variation pattern setting process (step S301) in the special symbol process. In the variation pattern setting process, the CPU 56 checks whether or not the big hit flag or the small hit flag is set (step S81). When the big hit flag and the small hit flag are not set, the process proceeds to step S91. When the big hit flag or the small hit flag is set, when it is decided to make a small hit (when the small hit flag is set) or when the sudden probability change big hit flag is set (step) In step S82, the variation pattern is determined as the variation pattern at the time of sudden hit / small hit (step S83), and the process proceeds to step S105. When the small hit flag and the sudden probability change big hit flag are not set, the random number for determining the variation pattern is read from the random number buffer area (step S101).

  Then, the variation pattern is determined. Specifically, when the probability variation flag indicating the probability variation state or the time reduction flag indicating the time reduction state is set, the random number for variation pattern determination matches the value from the variation pattern table shortened at the big hit A variation pattern corresponding to the determination value to be selected is selected (steps S102 and S103). The big hit shortening variation pattern table is a table stored in the ROM 54, and data indicating the variation pattern 6 or the variation pattern 7 (see FIG. 11) is set corresponding to the determination value. When the big hit flag is set, the variation pattern 8 is not selected. When the probability variation flag and the time reduction flag are not set, a variation pattern corresponding to the determination value matching the variation pattern determining random number value is selected from the big hit non-shortened variation pattern table (steps S102 and S104). The big hit non-shortening variation pattern table is a table stored in the ROM 54, and data indicating the variation patterns 1 to 4 is set corresponding to the determination value. If the big hit flag is set, the variation pattern 5 is not selected.

  Then, the CPU 56 performs control to transmit a variation pattern command (see FIG. 13) corresponding to the variation pattern selected in step S100, step S103, or step S104 to the effect control microcomputer 100 (step S105). Note that the special symbol variation time (variable display time) is determined by the processing of steps S101 to S104. Also, when using a different variation pattern between when the variable display of the first special symbol is performed and when the variable display of the second special symbol is performed, for example, in the processing of steps S103 and S104, the special symbol pointer is changed. A variation pattern is selected from the variation pattern table shown.

  Also, control is performed to transmit a symbol variation designation command indicating the variation of the special symbol (step S106). Specifically, when data indicating “first” is set in the special symbol pointer, the CPU 56 transmits a first symbol variation designation command indicating the variation of the first special symbol, and the special symbol pointer is transmitted to the special symbol pointer. When the data indicating “second” is set, a second symbol variation designation command indicating the variation of the second special symbol is transmitted. Then, according to the setting of the special symbol pointer, the first special symbol or the second special symbol starts to change (step S107). For example, a start flag referred to in the special symbol display control process in step S33 is set. Further, a value corresponding to the variation time (see FIG. 11) corresponding to the selected variation pattern is set in the variation time timer formed in the RAM 55 (step S108). Then, the value of the special symbol process flag is updated to a value corresponding to the display result specifying command transmission process (step S302) (step S109). In addition, you may comprise so that the process of step S106 may be performed before the process of step S105. That is, the symbol variation designation command (special symbol specifying command) may be transmitted before transmitting the variation pattern command.

  In step S91, the CPU 56 checks whether or not the time reduction flag is set. If the time reduction flag is set, the value of the time reduction counter indicating the number of times the special symbol can be changed in the time reduction state is decremented by 1 (step S92). When the value of the time reduction counter becomes 0, a time reduction end flag is set in order to shift the gaming state to the non-time reduction state when the variable display ends (steps S93 and S94).

  Next, the reach determination random number is read from the random number buffer area (step S95). Then, it is confirmed whether or not the value of the total pending storage number counter stored in a predetermined area of the RAM 55 (the value before being subtracted in the process of step S58) is equal to or greater than a predetermined value (4 in this example) ( In step S96), if it is equal to or greater than the predetermined value, it is determined whether or not to reach based on the reach determination table used when the value of the special symbol pointer and the value of the total pending storage number counter are equal to or greater than the predetermined value (step S97). . If it is less than the predetermined value, it is determined whether or not to reach based on the reach determination table used when the value of the special symbol pointer and the value of the total pending storage number counter are less than the predetermined value (step S98).

  In the process of step S97, the CPU 56 uses the reach determination table shown in FIG. 12B if the value of the special symbol pointer is a value indicating “first”, and the value of the special symbol pointer is “second”. Is used, the reach determination table shown in FIG. 12D is used. In the process of step S98, if the value of the special symbol pointer indicates “first”, the CPU 56 uses the reach determination table shown in FIG. If the value indicates “2”, the reach determination table shown in FIG.

  If it is decided to reach in the process of step S97 or the process of step S98, the process proceeds to step S101. When it is determined not to reach, the CPU 56 changes the fluctuation pattern to the fluctuation pattern 9 shown in FIG. 11 (when the probability variation flag and the time reduction flag are not set) or the variation pattern 11 (probability variation flag or (When the time reduction flag is set) (step S100). Then, the process proceeds to step S105.

  When reaching in the case of detachment (when “Y” is determined in step S99), the CPU 56 determines a random number value for determining a variation pattern from the variation variation table at the time of detachment in the process of step S103. A variation pattern corresponding to the determination value that matches is selected. The off-time shortening variation pattern table is a table stored in the ROM 54, and data indicating the variation patterns 6 to 8 (see FIG. 11) is set corresponding to the determination value. Further, in the process of step S104, a variation pattern corresponding to the determination value that matches the variation pattern determining random number value is selected from the non-shortened variation pattern table at the time of loss. The off-time non-shortening variation pattern table is a table stored in the ROM 54, and data indicating the variation patterns 2 to 5 is set corresponding to the determination value.

  In this embodiment, the special symbol process is used for both the first special symbol and the second special symbol. That is, the special symbol process is also shared. Therefore, an area for storing the special symbol process processing program in the ROM 54 is also saved. Further, for example, the variable time timer (formed in the RAM 55) set in step S108 is shared by the first special symbol and the second special symbol, which leads to a capacity saving of the RAM 55.

  FIG. 23 is a flowchart showing the display result specifying command transmission process (step S302). In the display result specifying command transmission process, the CPU 56 transmits an effect control command (see FIG. 13) of any one of the display result 1 designation to the display result 5 designation according to the determined type of big hit, small hit, and loss. Control. Specifically, the CPU 56 first checks whether or not the big hit flag is set (step S110). If not set, the process proceeds to step S116. When the big hit flag is set, when the probability variation big hit flag is set, control for transmitting the display result 3 designation command is performed (steps S111 and S112). When the sudden probability big hit flag is set, control for transmitting a display result 4 designation command is performed (steps S113 and S114). When neither the probability variation jackpot flag nor the sudden probability variation jackpot flag is set, control for transmitting a display result 2 designation command is performed (step S115).

  When the CPU 56 confirms that the small hit flag is set in the process of step S116, the CPU 56 performs control to transmit a display result 5 designation command (step S117). When the small hit flag is not set, control for transmitting a display result 1 designation command is performed (step S118).

  Then, a total pending storage number subtraction designation command designating that 1 is subtracted from the total pending storage number is transmitted (step S119). Instead of transmitting the total pending storage number subtraction designation command, a total pending storage number designation command for designating the total pending storage number after subtraction may be transmitted. Further, the CPU 56 stores the transmitted display result specifying command in the effect symbol type storage area in the RAM 55.

  Thereafter, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol changing process (step S303) (step S120).

  FIG. 24 is a flowchart showing the special symbol changing process (step S303) in the special symbol process. In the special symbol changing process, the CPU 56 decrements the variable time timer by 1 (step S121), and when the variable time timer times out (step S122), the value of the special symbol process flag corresponds to the special symbol stop process (step S304). The updated value is updated (step S123). If the variable time timer has not timed out, the process ends.

  FIG. 25 is a flowchart showing the special symbol stop process (step S304) in the special symbol process. In the special symbol stop process, the CPU 56 sets an end flag referred to in the special symbol display control process in step S33 to end the variation of the special symbol, and the first special symbol display unit 8a and the second special symbol display unit 8b. Then, a control for deriving and displaying the stop symbol is performed (step S131). When data indicating “first” is set in the special symbol pointer, the variation of the first special symbol is terminated, and when data indicating “second” is set in the special symbol pointer. The variation of the second special symbol is terminated. Moreover, control which transmits the symbol determination designation | designated command to the microcomputer 100 for production control is performed (step S132). If the big hit is not set, the process proceeds to step S138 (step S133).

  When the big hit flag is set, the CPU 56 resets the probability variation flag and the hourly flag (step S134), and performs control to transmit the big hit start designation command (step S135). Specifically, when the probability variation jackpot flag is set, a jackpot start 2 designation command is transmitted.

  Further, a value corresponding to the big hit display time (time for notifying the occurrence of the big hit in the image display device 9, for example) is set in the big hit display time timer (step S136). Then, the value of the special symbol process flag is updated to a value corresponding to the pre-winner opening pre-processing (step S305) (step S137).

  In step S138, the CPU 56 checks whether or not the time reduction end flag is set. If the time reduction end flag is set, the time reduction end flag is reset (step S139), and the time reduction flag is reset (step S140). Then, it is confirmed whether or not the small hit flag is set (step S140). If the small hit flag is set, control is performed to transmit a small hit / probability start designation command (step S142). In addition, a value corresponding to the small hit display time (time for notifying the occurrence of the small hit in the image display device 9, for example) is set in the small hit display time timer (step S143). Then, the value of the special symbol process flag is updated to a value corresponding to the small hit release pre-processing (step S308) (step S144). If the small hit flag is not set, the value of the special symbol process flag is updated to a value corresponding to the special symbol normal process (step S300) (step S145).

  In the big winning opening opening pre-processing, when the big hit display time timer is set, the CPU 56 controls to open the big winning opening when the big hit display time timer times out, and sets the big winning opening opening time timer. A value corresponding to the opening time (for example, 29 seconds in the case of a normal big hit and a probable big hit) is set, and the value of the special symbol process flag is updated to a value corresponding to the big winning opening opening process (step S306). . The case where the big hit display time timer is set is the case before the start of the first round. When the interval timer (timer for determining the interval time between rounds) is set, when the interval timer times out, control is performed to open the big prize opening and the opening time ( For example, in the case of a normal big hit and a probable big hit, a value corresponding to 29 seconds) is set, and the value of the special symbol process flag is updated to a value corresponding to the big prize opening opening process (step S306).

  In the process during opening of the big prize opening, the CPU 56 does not finish the final round when the big prize opening time timer times out or the number of winning balls to the big prize opening reaches a predetermined number (for example, 10). In this case, control for closing the special winning opening is performed, a value corresponding to the interval time is set in the interval timer, and the value of the special symbol process flag is set to a value corresponding to the pre-opening process for the special winning opening (step S305). Update. When the final round is completed, the value of the special symbol process flag is updated to a value corresponding to the jackpot end process (step S307).

  FIG. 26 is a flowchart showing the jackpot end process (step S307) in the special symbol process. In the jackpot end process, the CPU 56 checks whether or not the jackpot end display timer is set (step S150). If the jackpot end display timer is set, the process proceeds to step S154. If the jackpot end display timer is not set, the jackpot flag is reset (step S151), and control for transmitting a jackpot end designation command is performed (step S152). Here, when the probability variation big hit flag or the sudden probability variation big hit flag is set, the big hit end 2 designation command is transmitted. When neither the probability variation big hit flag nor the sudden probability variation big hit flag is set, the big hit end 1 designation command is sent. Send. Then, a value corresponding to the display time corresponding to the time during which the big hit end display is being performed in the image display device 9 (the big hit end display time) is set in the big hit end display timer (step S153), and the processing is ended.

  In step S154, 1 is subtracted from the value of the big hit end display timer. Then, the CPU 56 checks whether or not the value of the jackpot end display timer is 0, that is, whether or not the jackpot end display time has elapsed (step S155). If not, the process ends. If it has elapsed, it is checked whether the probability variation jackpot flag or the sudden probability variation jackpot flag is set (step S158).

  If the probability variation jackpot flag or the sudden probability variation jackpot flag is set, the set flag (probability variation jackpot flag or sudden probability variation jackpot flag) is reset (step S159), the probability variation flag is set, and the gaming state is the probability variation state. (Step S161). If neither the probability variation big hit flag nor the sudden probability variation big hit flag is set, the time reduction flag is set (step S162), and the value of the special symbol process flag is updated to a value corresponding to the special symbol normal processing (step S300) (step S300). Step S163).

  FIG. 27 is a flowchart showing the small hit end process (step S310) in the special symbol process. In the small hit end process, the CPU 56 checks whether or not the small hit end display timer is set (step S170). If the small hit end display timer is set, the process proceeds to step S174. If the small hit end display timer is not set, the small hit flag is reset (step S171), and a control for transmitting a small hit / coincidence end designation command is performed (step S172). Then, the small hit end display timer sets a value corresponding to the display time corresponding to the time during which the small hit end display is performed in the image display device 9 (small hit end display time) in the small hit end display timer ( Step S173), the process is terminated.

  In step S174, 1 is subtracted from the value of the small hit end display timer. Then, the CPU 56 checks whether or not the value of the small hit end display timer is 0, that is, whether or not the small hit end display time has elapsed (step S175). If not, the process ends. If it has elapsed, the value of the special symbol process flag is updated to a value corresponding to the special symbol normal process (step S300) (step S176).

  Next, the display effect during the variation of the decorative pattern in the image display device 9 will be described. FIG. 28 is an explanatory diagram illustrating an example of a display effect in the image display device 9. In the example shown in FIG. 28, the decorative symbols 9a, 9b, and 9c change so as to move from the right to the left of the screen. Hereinafter, the decorative pattern that fluctuates in the upper part of the screen of the image display device 9 is the first decorative pattern 9a, the decorative pattern that fluctuates in the middle part of the screen of the image display device 9 is the second decorative pattern 9b, and the lower part of the screen of the image display device 9 The decorative pattern that fluctuates in is called a third decorative pattern 9c.

  As shown in FIG. 28A, a background image 9F is displayed on the screen of the image display device 9. In addition, a character image 9D that moves in the direction opposite to the changing direction is displayed in accordance with the change in the first decorative symbol 9a, the second decorative symbol 9b, and the third decorative symbol 9c. Alternatively, a background image (including the character image 9D) that moves in the direction opposite to the changing direction is displayed.

  In the example shown in FIG. 28 (A), the character image 9D, decorative symbols (first decorative symbol 9a, second decorative symbol 9b, and third decorative symbol 9c) and star display portions on the screen of the image display device 9 are displayed. In a portion other than (background portion), in addition to the background image 9F, a background image is displayed. In FIG. 28, a common code 9D is assigned to different character images, but the different character images are treated as different in the production control microcomputer 100 and the VDP 109.

  In the example shown in FIG. 28B, only the variable display of the first decorative symbol 9a, the second decorative symbol 9b, and the third decorative symbol 9c is performed on the screen of the image display device 9. That is, on the screen of the image display device 9, the background image 9F is not displayed, and the character image 9D is not displayed.

  In the example shown in FIG. 28 (B), the area other than the decorative symbol and the moving star (blank symbol) displayed on the screen of the image display device 9 is displayed in black or white. That is, display control is not performed for areas other than decorative symbols and moving stars on the screen of the image display device 9.

  The image data of each character image 9D is stored in the CGROM 83. The image data of the background image is also stored in the CGROM 83. The VDP 109 transfers the image data expanded in the VRAM 84 to the frame buffer 85 and causes the image display device 9 to display an image based on the image data transferred to the frame buffer 85. Then, image data is read from the CGROM 83 and written to the VRAM 84 at a predetermined time. That is, it is expanded in the VRAM 84. When the image data is compressed (encoded), a process for expanding (decoding) the image data read from the CGROM 83 is performed.

  When the decoration pattern is changed, the background and character are also displayed as shown in FIG. 28A. In particular, the character is moved and displayed, the character shape is changed during the moving display, and the background is moved and displayed. In this case, other types of image data (image data of characters having different shapes and image data of backgrounds having different scenes) need to be developed in the VRAM 84. It takes time (for example, about several seconds) to develop necessary image data from the CGROM 83 to the VRAM 84.

  When the power supply to the gaming machine is started, the production control microcomputer 100 and the VDP 109 are reset and the initial setting process is performed. In the initial setting process, the character image data and background image required from the CGROM 83 to the VRAM 84 are performed. The data is expanded. Since it takes a certain amount of time to deploy, if the change starts immediately when the condition for starting the change of the special symbol and decorative design is satisfied immediately after the power supply is started, the background and character Cannot display. Specifically, the background and the character cannot be displayed until the processing for developing the character image data and the background image data necessary for the VRAM 84 is completed. The decorative design image data also needs to be developed in the VRAM 84. However, the time required to develop the decorative design image data is longer than the time required to develop the necessary character image data and background image data. short. In general, the shape of the decorative design does not change, or even if it changes, the degree of change is small compared to the case of changing the character shape or moving the background, and the amount of data of the required decorative design image data is necessary This is because the amount of image data of a simple character and the amount of image data of the background are small.

  Therefore, in this embodiment, when the condition for starting the variation of the special symbol and the decorative symbol is satisfied immediately after the power supply to the gaming machine is started, the effect control microcomputer 100 and the VDP 109 store the image data of the decorative symbol in the VRAM 84. Then, as shown in FIG. 28B, in the image display device 9, control is performed so that only the decoration pattern is changed as a display effect. Then, when power supply to the gaming machine is started, a process of developing the image data of the main character and the background image data into the VRAM 84 is also started, but the image data of the main character and the background image data are transferred to the VRAM 84. When the development is completed, the display effect on the image display device 9 is switched from the display effect as shown in FIG. 28 (B) to the display effect as shown in FIG. 28 (A). That is, the effect control microcomputer 100 and the VDP 109 perform control so as to switch to a display effect accompanied by display of a character or background. Note that the VDP 109 executes control in accordance with a command from the effect control microcomputer 100. The main character image data and background image data are character image data and background image data that are often used throughout all the variation patterns.

  FIG. 29 is an explanatory diagram illustrating an example of a method of using the frame buffer 85. As shown in FIG. 29, in the frame buffer 85, two areas (areas 0 and 1) corresponding to the screen of the image display device 9 are secured. Areas 0 and 1 are called a virtual area or frame memory 84A. In the areas 0 and 1 in the frame memory 84A, a part image such as a character image is expanded from the CGROM 83 via the VRAM 84 as appropriate (for example, when image data is required). If image data exists in the area of the VRAM 84, the image data is expanded from the area to the areas 0 and 1. When the component image is developed in the area 0, an image signal based on the image data of the area 1 is output to the image display device 9, and when the component image is expanded in the area 1, the image based on the image data of the area 0 is output. A signal is output to the image display device 9. When the component image is expanded in the area 0, the area 0 is a drawing area, and when the component image is expanded in the area 1, the area 1 is the drawing area. When image data is read from area 0 and an image signal based on the image data is output to the image display device 9, area 0 is a display area, image data is read from area 1, and the image When an image signal based on the data is output to the image display device 9, area 1 is the display area. Thus, the areas 0 and 1 are used as a double buffer. In this embodiment, a double buffer is used, but the frame memory 84A may be a single buffer.

  FIG. 30 is an explanatory diagram showing an example of how to use the VRAM 84. In the VRAM 84, buffer areas for component images (transfer destination areas from the CGROM 83) 84b1 and 84b2 are secured. The transfer destination area from the CGROM 83 stores a part image (specifically, source data of the part image) that is highly likely to be used at that time, that is, highly likely to be drawn in the drawing area of the frame memory 84A. Is done. The buffer area 84b1 is an area where decorative design image data is stored. The buffer area 84b2 is an area for storing necessary character image data and background image data. The buffer areas 84b1 and 84b2 are referred to as fixed areas 84b in the VRAM 84. The VRAM 84 has a temporary storage area 84c in addition to the fixed area 84b. The fixed area 84b is an area in which the image data of the component image is regularly stored.

  In this embodiment, the frame buffer 85 and the VRAM 84 are provided outside the VDP 109, but the VDP 109 containing the frame buffer 85 and the VRAM 84 may be used.

  FIG. 31 is an explanatory diagram showing an example of an address map of the frame memory 84A. FIG. 31 illustrates a region 0. In the frame memory 84A, the portion corresponding to the upper left of the display screen of the image display device 9 is assigned to the smallest address, the next address is assigned to the portion corresponding to the right on the display screen, and the portion of the row on the display screen is assigned. The address next to the address of the part corresponding to the right is assigned to the part corresponding to the leftmost of the next line. Hereinafter, similarly, the next address of the address corresponding to the rightmost part of a certain row is assigned to the part corresponding to the leftmost position of the next line. The address value shown in FIG. 31 is an example.

  FIG. 32 is an explanatory diagram for explaining a method of developing image data from the CGROM 83 to the frame memory 84A. As shown in FIG. 32A, the image data may be transferred from the fixed area 84b of the VRAM 84 to the frame memory 84A. The transfer of the image data from the fixed area 84b to the frame memory 84A is executed by the VDP 109. The VDP 109 reads the image data word by word from the fixed area 84b and writes the read image data to the frame memory 84A. Instead, the image data is transferred by DMA (Direct Memory Access) transfer. That is, the VDP 109 includes a built-in DMA circuit (data transfer circuit 94) having a DMA transfer function. In the DMA transfer, the data is continuously transferred while the read address and the write address are incremented by one for the output of the read address to the VRAM bus, the read signal output, the output of the write address to the VRAM bus, and the write signal output. This is the transfer method.

  In this embodiment, DMA transfer is used as an example. However, the VDP 109 may read image data word by word from the fixed area 84b and write the read image data to the frame memory 84A. In this case, the read image data is temporarily stored, for example, in a register of the VDP 109, and written from the register to the frame memory 84A.

  As shown in FIG. 32B, the VDP 109 reads image data from the CGROM 83, stores the read image data in the temporary storage area 84c in the VRAM 84, and transfers the read image data from the temporary storage area 84c to the frame memory 84A. Is possible. In that case, the VDP 109 writes the image data read from the CGROM 83 and stored in the temporary storage area 84c into the frame memory 84A by DMA transfer.

  FIG. 33 is an explanatory diagram showing how image data is transferred from the frame memory 84A to the image display device 9 via the display signal control unit 87 (see FIG. 4). The display signal control unit 87 in the VDP 109 reads out the image data from the frame memory 84A at a predetermined timing and outputs it to the image display device 9 (see FIG. 33A).

  When the VDP 109 outputs image data to the image display device 9 and receives an enlargement command from the effect control microcomputer 100, the VDP 109 enlarges the image and outputs it to the image display device 9 (see FIG. 33B). . Note that when enlarging an image, the VDP 109 performs pixel interpolation processing, for example. For example, when enlarging an image twice (twice vertically and twice horizontally), four pixels (two in the vertical direction and two in the horizontal direction (2 × 2)) from the image data (original pixel data) of one pixel ) Image data is generated. That is, new image data of three pixels is generated. In that case, as an example, an average value of the original pixel data and the image data of the adjacent pixels is set as the image data of the new pixel.

  FIG. 34 is an explanatory diagram showing a data bus in the CG bus between the drawing control unit 91 and the CGROM 83 in the VDP 109. In FIG. 34, the CG bus I / F 93 (see FIG. 4) is not shown. As shown in FIG. 34, the data bus physically has 64 bits, but a 64-bit mode in which all 64 bits are used as a data bus, and a 32-bit mode in which lower 32 bits are used as a data bus. Can be switched to.

  In this embodiment, when image data is read from the ROM 83C in which moving image data is stored, the image data is read from ROMs 83A and 83B in which the 32-bit mode is set and still image (sprite image) data is stored. When reading, the 64-bit mode is set. Therefore, the image data of the sprite image is read from the CGROM 83 in 64-bit units, and the moving image data is read from the CGROM 83 in 32-bit units.

  FIG. 35 is a block diagram showing specific wiring of the data bus in the CG bus between the drawing control unit 91 and the CGROM 83 in the VDP 109. As shown in FIG. 35, the lower 32 bits of the 64-bit data bus from the drawing controller 91 are actually branched and wired to the ROM 83A and the ROM 83C, respectively.

  FIG. 36 is an explanatory diagram for describing an example of each register in the drawing control register 95. In the example shown in FIG. 36, the CGROM start address register for designating the start address of the CGROM 83 when reading out the image data, the image data stored in the temporary storage area 84c (see FIG. 30) of the VRAM 84, or the VRAM 84 A VRAM head address register for designating the top address when reading image data from the temporary storage area 84c, a VRAM transfer data size register for designating the size of transfer data when transferring image data to the VRAM 84, and the CGROM 83 to VRAM 84 VRAM fixed area transfer execution instruction register for instructing data transfer to fixed area 84b (see FIG. 30), VRAM for instructing data transfer from CGROM 83 to temporary area 84b of VRAM 84 via temporary storage area 84c of VRAM 84 There is a dynamic transfer execution instruction register.

  Further, a frame memory head address register for designating a head address when developing image data in the frame memory 84A, a frame memory transfer data size register for designating the size of transfer data, and a temporary storage area 84c of the VRAM 84 from the CGROM 83 There is a frame memory transfer execution instruction register for instructing data transfer to the frame memory 84A.

  Furthermore, a fixed area start address register that specifies the start address of the fixed area 84b of the VRAM 84, a fixed area end address register that specifies the final address of the fixed area 84b of the VRAM 84, and an arbitrary address of the fixed area 84b of the VRAM 84 are specified. There is an arbitrary head address register in the fixed area, and a fixed area data transfer execution instruction register for instructing data transfer from the fixed area 84b of the VRAM 84 to the frame memory 84A.

  Further, a data bus mode register for instructing whether the data bus mode is set to the 32-bit mode or the 64-bit mode, moving image data in the CGROM 83 is read out, temporarily stored in the temporary storage area 84c, and the moving image data There is a decoding execution instruction register for instructing data transfer to the frame memory 84A and a display area register indicating the current display area.

  Furthermore, there is an enlargement ratio setting register for setting a vertical enlargement ratio (vertical enlargement ratio) and a horizontal enlargement ratio (horizontal enlargement ratio).

  The values set in the VRAM fixed area transfer execution instruction register, VRAM automatic transfer execution instruction register, frame memory transfer execution instruction register, fixed area data transfer execution instruction register, and decoding execution instruction register may each be 1 bit. The values set in these registers are set to predetermined bits in each register, for example.

  Also, the configuration of the drawing control register 95 as shown in FIG. 36 is an example, and the registers constituting the drawing control register 95 may be configured differently from the configuration shown in FIG. For example, the register classification method for designating the head address may be different from the example shown in FIG.

  FIG. 37 is an explanatory diagram showing a data structure of moving image data among image data of component images stored in the CGROM 83. The moving image data has a configuration in which a file header is set at the first address, and then a frame header and compressed data of each frame are sequentially set. In the stream, frame headers and compressed data of frames 1 to N (frame images 1 to n) are set in order from image 1. The moving image data is encoded by, for example, MPEG2 (Moving Picture Experts Group phase 2) encoding method. Since the amount of image data before encoding is reduced by encoding, the encoded image data is referred to as compressed data.

  FIG. 37 illustrates two pieces of moving image data (super reach moving image data and customer waiting demonstration moving image data), but more moving image data may be stored in the CGROM 83. .

  The compressed data is stored in the CGROM 83 in a ROM having 32 bits as one word. When the VDP 109 reads compressed data from the CGROM 83, the bus width of the CG bus is set to 32 bits. Therefore, the VDP 109 reads the compressed data from the CGROM 83 in units of 32 bits.

  Next, a method of decoding moving image data (compressed data) compressed by the moving image decompression unit 89 will be described with reference to the explanatory diagram of FIG. The frame numbers shown in FIG. 38A are the frame serial numbers in the moving image data shown in FIG. 37 (frames 1 to N). In the moving image data, the compressed data of frames 1 to N are configured by I pictures, B pictures, or P pictures defined by the MPEG2 encoding method in the order shown in FIG. For example, frame 1 is an I picture, frames 2, 3, 5, and 6 are B pictures, and frames 4 and 7 are P pictures. The subscripts attached to I, B, and P are serial numbers for each picture type.

  As described above, frames 1 to N (frame images 1 to n) are stored as moving image data in order from frame 1 (image 1) (see FIG. 37). For example, frame 1 (image 1) in the stream is an I picture, frames 2, 3, 5, and 6 (images 2, 3, 5, and 6) are B pictures, and frames 4 and 7 (images 4 and 7). Is a P picture.

  When decoding an I picture (image 1), the moving picture decompression unit 89 performs a decoding process using only the I picture. In addition, when decoding a B picture, the moving picture decompression unit 89 refers to the I picture or P picture before one or more pictures and the I picture or P picture after one or more pictures together with the B picture. The decryption process is performed. In the example illustrated in FIG. 37, for example, when decoding the image 2, the decoding process is performed with reference to the image 1 that is the previous I picture and the image 4 that is the second P picture. When decoding a P picture, the moving picture decompression unit 89 performs decoding processing with reference to the previous I picture or P picture together with the P picture. In the example illustrated in FIG. 37, for example, when decoding the image 4, the decoding process is performed with reference to the image 1 that is the previous I picture 23.

  Next, the operation of the effect control means will be described. FIG. 39 is a flowchart showing main processing executed by the effect control microcomputer 100 (specifically, the effect control CPU 101) mounted on the effect control board 80. The effect control CPU 101 starts executing the main process when the power is turned on. In the main processing, first, initialization processing is performed for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval (for example, 2 ms) (step S701). . Next, a second data transfer process is performed (step S702). In the second data transfer process, the fixed area 84b (see FIG. 30) is set in the VRAM 84, and the decorative symbol image data (buffer area 84b1: see FIG. 30) stored in the CGROM 83 is stored in the fixed area 84b of the VRAM 84 (see FIG. 30). For example, this is a process for transferring image data obtained by adding a predetermined image to each of numbers 0 to 9 (see FIG. 28). In this case, the VDP 109 sets the bus width of the data bus in the CG bus to 64 bits. The second data transfer process is data including a plurality of pieces of image data used for display presentation when the identification information for presentation is variably displayed, and the second data having a data amount smaller than the data amount of the first data. It is an example of the process which transfers.

  Thereafter, the effect control CPU 101 executes a random number update process for updating the counter value of a counter for generating a predetermined random number (step S703), and executes a sprite / video data transfer process (step S704). The sprite / video data transfer process is a process for transferring the image data of the character image and the background image from the CGROM 83 to the fixed area 84b (buffer area 84b2: see FIG. 30) of the VRAM 84. Then, it is confirmed whether or not the timer interrupt flag is set (step S705). When a timer interrupt occurs, the effect control CPU 101 sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the effect control CPU 101 clears the flag (step S706) and executes the effect control process. Note that the sprite / video data transfer process in step S704 is an example of an initial data transfer process in which the first data is transferred from the image data storage unit to the display storage unit when power supply to the gaming machine is started. Further, the sprite / video data transfer process in step S704 is executed as a process after confirming that the timer interrupt flag is set (for example, as a process executed following the process in step S709). You may comprise. In this embodiment, control is performed so that the decorative design image data is collectively transferred to the VRAM 84 in the second data transfer process of step S702. However, when the data amount of the decorative design image data is small, etc. Instead of transferring in advance when power supply to the gaming machine is started, it is possible to control so that the CGROM 83 is transferred to the VRAM 84 each time the decorative symbols are variably displayed. In that case, the process in which the image data relating to the initial appearance displayed on the image display device 9 when the power supply to the gaming machine is started is temporarily written from the CGROM 83 to the VRAM 84 corresponds to the second data transfer process.

  In the effect control process, the effect control CPU 101 first analyzes the received effect control command and executes a process of setting a flag according to the received effect control command (command analysis process: step S707). Next, the effect control CPU 101 executes effect control process processing (step S708). In the effect control process, the process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the image display device 9 is executed. In addition, a hold storage display control process for controlling the display state of the combined hold storage display unit 18c is executed (step S709). Thereafter, the process proceeds to step S703.

  FIG. 40 is an explanatory diagram showing an example of a data table stored in the ROM 112. FIG. 40 illustrates a second data transfer area data table used in the process of step S702 and a sprite / video data transfer area data table used in the process of step S704.

  The second data transfer area data table is a data table used when image data of decorative symbols is transferred to the VRAM 84. The sprite / video data transfer area data table is a data table used when transferring image data of main character images and background images to the VRAM 84. Note that FIG. 40 shows one sprite / video data transfer area data table, but the character image and background required according to the progress of the game, specifically according to the contents of the display effect. Since the types of images are different, a plurality of types of sprite / video data transfer area data tables may be prepared in order to set necessary image data in the VRAM 84 as appropriate. For example, if the required image data is not set in the VRAM 84, the effect control microcomputer 100 uses the sprite / video data transfer area data table for transferring the required image data to the VRAM 84, and stores it in the VDP 109. A command for transferring the image data is output to the VDP 109.

  It should be noted that the effect control microcomputer 100 causes the VDP 109 to display all character images so that the image data of the character image and the background image to be used exists in the VRAM 84 when any display effect is executed. The command may be output to the VDP 109 so that the image data of the background image is transferred to the VRAM 84. In that case, only one sprite / video data transfer area data table is required.

  FIG. 41 is a flowchart showing the second data transfer process shown in FIG. In the second data transfer process, the effect control CPU 101 sets the start address of the area used as the fixed area 84b in the fixed area start address register (see FIG. 36) in order to secure the fixed area 84b in the VRAM 84. Step S921). Further, the final address of the area used as the fixed area 84b is set in the fixed area final address register (see FIG. 36) (step S922).

  Next, with reference to the second data transfer area data table, the VDP 109 is given a command for transferring the decorative design image data stored in the CGROM 83 to the VRAM 84. In other words, the production control CPU 101 sets the top address of the second data transfer area data table in the ROM 112, for example, in an internal register (step S923), and sets 0 in the address pointer (step S924). Then, the fixed area data transfer control process is executed (step S925).

  The effect control CPU 101 checks whether or not the transfer of the image data is completed (step S926). When it is confirmed that the transfer of the image data is completed, the second data transfer process is terminated. When the transfer of the image data is completed, the VDP 109 resets the corresponding bit in the VRAM fixed area transfer execution instruction register. The effect control CPU 101 can recognize that the transfer of the image data from the CGROM 83 to the VRAM 84 is completed by confirming that the corresponding bit of the VRAM fixed area transfer execution instruction register is reset.

  FIG. 42 is a flowchart showing fixed area data transfer control processing. In the fixed area data transfer control process, the effect control CPU 101 reads data at the address pointed to by the address pointer in the second data transfer area data table (data storage start address (transfer source start address) in the CGROM 83) (step S931). . Since the start address of the second data transfer area data table in the ROM 112 is not 0000, when reading data from the second data transfer area data table, the value of the address pointer is set to the second data transfer area data table. Is added as an offset value. The effect control CPU 101 sets the data read from the second data transfer area data table in the CGROM head address register (see FIG. 36) (step S932). Then, the value of the address pointer is incremented by 1 (step S933).

  Next, the data at the address indicated by the address pointer in the second data transfer area data table (the storage storage start address (transfer destination start address) of the buffer area 84b1 in the VRAM 84) is read (step S934), and the read data is read from the VRAM start. The address register (see FIG. 36) is set (step S935). Then, the value of the address pointer is incremented by 1 (step S936).

  Next, the address data (data length) indicated by the address pointer in the second data transfer area data table is read (step S937), and the read data is set in the VRAM transfer data size register (see FIG. 36) (step 36). S938). Then, the corresponding bit of the VRAM fixed area transfer execution instruction register is set (step S939).

  As described above, the instruction for transferring the decorative design image data stored in the CGROM 83 to the VRAM 84 is given to the VDP 109 from the effect control CPU 101 to the VDP 109.

  The VDP 109 executes data transfer from the CGROM 83 to the VRAM 84 when a command for transferring the image data to the VRAM 84 is given from the effect control CPU 101. Specific data transfer will be described later.

  FIG. 43 is a flowchart showing the sprite / video data transfer process shown in FIG. In the sprite / video data transfer process, the effect control CPU 101 checks whether or not a character transfer completion flag is set (step S941). The character transfer completion flag indicates that the data transfer from the CGROM 83 to the VRAM 84 of the image data of the character image and the background image (main character image and background image) used in the display effect accompanying the variation of the decorative design is completed. It is a flag indicating that. If the character transfer completion flag is set, the sprite / video data transfer process is terminated.

  If the transfer completion flag such as a character is not set, it is confirmed whether or not the transfer start flag is set (step S942). The transfer start flag is a flag indicating that processing for transferring the image data of the main character image and the background image from the CGROM 83 to the VRAM 84 is started.

  When the transfer start flag is not set, the effect control CPU 101 refers to the sprite / video data transfer area data table and sends a command to transfer the decorative design image data stored in the CGROM 83 to the VRAM 84. Is given to VDP109. That is, the effect control CPU 101 sets the start address of the sprite / video data transfer area data table in the ROM 112, for example, in an internal register (step S946), and sets 0 in the address pointer (step S947). Then, the fixed area data transfer control process (see FIG. 42) is executed (step S948). Thereafter, the transfer start flag is set.

  When the fixed area data transfer control process is called from the sprite / video data transfer process, the effect control CPU 101 receives data from the second data transfer area area data table in the processes of steps S931, S934, and S937. Instead of reading, data is read from the sprite / video data transfer area data table.

  If the transfer start flag has already been set, the effect control CPU 101 checks whether or not the transfer of the image data has been completed (step S943). If the image data transfer has not been completed, the sprite / video data transfer process is terminated. When it is confirmed that the transfer of the image data is completed, a character transfer completion flag is set (step S944), and the transfer start flag is reset (step S945). Note that the character transfer completion flag remains in the set state until the power supply is stopped.

  When the transfer of the image data is completed, the VDP 109 resets the corresponding bit in the VRAM fixed area transfer execution instruction register. The effect control CPU 101 can recognize that the transfer of the image data from the CGROM 83 to the VRAM 84 is completed by confirming that the corresponding bit of the VRAM fixed area transfer execution instruction register is reset.

  As described above, the image data of the main character image and the background image is stored in the VRAM 84. It should be noted that when a display effect based on a variation pattern is actually executed, it is possible that image data such as necessary character images is not stored in the VRAM 84 (image data such as necessary character images is the main character). In such a case, the image data is appropriately transferred from the CGROM 83 to the VRAM 84 during the variable display of the decorative design. Since the amount of image data transferred from the CGROM 83 to the VRAM 84 as appropriate is small, there is no hindrance to the display effect. However, when all the character images and background images in the CGROM 83 are transferred to the VRAM 84 in the sprite / video data transfer process when the power supply is started, the image data to the VRAM 84 is used. After the transfer of the image data is completed, the image data such as the necessary character image is not stored in the VRAM 84 (if the decorative pattern change starts before the image data transfer to the VRAM 84 is completed). There may be missing image data.) In the sprite / video data transfer process, the image data of the movie image may be developed in the VRAM 84.

  FIG. 44 is a flowchart showing the effect control process (step S708) in the main process shown in FIG. In the effect control process, the effect control CPU 101 performs one of steps S800 to S806 according to the value of the effect control process flag. In each process, the following process is executed.

  Fluctuation pattern command reception waiting process (step S800): It is confirmed whether a variation pattern command is received from the game control microcomputer 560. Specifically, it is confirmed whether or not the variation pattern command reception flag set in the command analysis process is set. If a variation pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the decorative symbol variation start process (step S801).

  Decoration symbol variation start processing (step S801): Control is performed so that the variation of the ornament symbol is started. Then, the value of the effect control process flag is updated to a value corresponding to the decorative symbol changing process (step S802).

  Decoration symbol variation processing (step S802): Controls the switching timing of each variation state (variation speed) constituting the variation pattern and monitors the end of the variation time. When the variation time ends, the value of the effect control process flag is updated to a value corresponding to the decorative symbol variation stop process (step S803).

  Decoration symbol variation stop process (step S803): Based on the reception of the effect control command (design determination designation command) for instructing all symbols to stop, the variation of the ornament symbol is stopped and the display result (stop symbol) is derived and displayed. Take control. Then, the value of the effect control process flag is updated to a value corresponding to the jackpot display process (step S804) or the variation pattern command reception waiting process (step S800).

  Big hit display process (step S804): After the end of the variation time, control is performed to display a screen for notifying the image display device 9 of the occurrence of the big hit. Then, the value of the effect control process flag is updated to a value corresponding to the big hit game processing (step S805). In this embodiment, the big hit display process is executed even when a small hit has occurred, but when a small hit has occurred, a screen for informing the occurrence of the small hit is displayed. Control.

  Big hit game processing (step S805): Control during big hit game is performed. For example, when an effect control command for display before opening the big winning opening or display when opening the big winning opening is received, display control of the number of rounds in the image display device 9 is performed. Then, the value of the effect control process flag is updated to a value corresponding to the big hit end process (step S806). In this embodiment, the big hit game processing is executed even when a small hit occurs.

  Big hit end process (step S806): In the image display device 9, display control is performed to notify the player that the big hit gaming state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800). In this embodiment, the big hit ending process is executed even when a small hit has occurred. However, when a small hit has occurred, a screen for informing the end of the small hit game is displayed. Control the display.

  FIG. 45 is a flowchart showing a variation pattern command reception waiting process (step S800) in the effect control process shown in FIG. In the variation pattern command reception waiting process, the effect control CPU 101 confirms whether or not the variation pattern command reception flag is set (step S811). If the variation pattern command reception flag is set, the variation pattern command reception flag is reset (step S812). Then, the value of the effect control process flag is updated to a value corresponding to the decorative symbol variation start process (step S801) (step S813). The variation pattern command reception flag is set in the command analysis process when a variation pattern command is received. In the command analysis process, the received fluctuation pattern command or data indicating the received fluctuation pattern command is stored in the fluctuation pattern command storage area of the RAM 113.

  FIG. 46 is a flowchart showing a decorative symbol variation start process (step S802) in the effect control process shown in FIG. In the decorative symbol variation start process, the effect control CPU 101 reads the variation pattern command or data indicating the received variation pattern command from the variation pattern command storage area (step S840).

  Next, the display result (stop symbol) of the decorative symbol is determined according to the data stored in the display result specifying command storage area of the RAM (that is, the received display result specifying command) (step S841). The effect control CPU 101 stores data indicating the display result of the determined decorative symbol in the decorative symbol display result storage area. The display result specifying command storage area stores the display result specifying command received in the command analysis process.

  In step S841, the effect control CPU 101 extracts a predetermined random number and determines a stop symbol based on the extracted random number. At this time, when a display result specifying command (display result 1 designation command) indicating a loss is received, a combination of stop symbols that causes a loss is determined. Specifically, if the fluctuation pattern command with reach effect or the data indicating the received fluctuation pattern command is stored in the fluctuation pattern command storage area, the left and right symbols match but the middle symbol does not match A variation pattern that determines the combination of symbols (or the upper and lower symbols match but does not match the middle symbol, or the two symbols match in any of the diagonal lines), and the fluctuation pattern command storage area does not involve reach effect If the command or data indicating the received variation pattern command is stored, the combination of the stop symbol whose left middle right symbol does not match (or the upper middle, lower and lower symbols do not match, or in any of the diagonal lines Discrepancy).

  If a display result specifying command (display result 2 specifying command, display result 3 specifying command, display result 4 specifying command or display result 5 specifying command) indicating a big hit or a small hit is received, a big hit or a small hit A combination of stop symbols (for example, all symbols match) is determined. When a display result specifying command (display result 3 designation command) indicating a probability variation big hit is received, a combination of stop symbols that recalls a probability variation big hit (for example, “7” “7” “7”) May be determined. However, when a display result specifying command (display result 4 designation command) indicating a sudden probability variation big hit is received, it is a combination of decorative symbols that are irregular in the middle left and right, and a combination of decorative symbols corresponding to the sudden probability big hit. You may make it determine the chance eyes (for example, "1" "2" "3"). Even when a display result specifying command (display result 5 designation command) indicating a small hit is received, a chance item may be determined as a combination of stop symbols. In addition, a combination of decorative symbols that evokes a big hit is sometimes referred to as a big hit symbol, and a combination of decorative symbols that evokes a loss is sometimes referred to as a missed symbol.

  Next, the effect control CPU 101 checks whether or not the character transfer completion flag is set (step S842). If the character transfer completion flag is set, the process table (first process table) corresponding to the variation pattern is selected (step S842A), and the process proceeds to step S843. Note that selecting a process table specifically means, for example, setting the start address of the selected process table as a pointer for effect control, or transferring the contents of the selected process table to a predetermined area of the RAM 113. It is to be. When the start address of the selected process table is set as the pointer, the effect control CPU 101 executes control based on the data in the area pointed to by the pointer while incrementing the pointer value by +1.

  If the character transfer completion flag is not set, the second process table corresponding to the variation pattern is selected (step S842B), the simple variation flag is set (step S842C), and the process proceeds to step S843.

  The fact that the character transfer completion flag is set means that the image data of the main character image and the background image used in the display effect accompanying the variation of the decorative design has already been developed in the VRAM 84. In other words, it means that a changing display effect using the character image and the background image can be executed. Further, when the character transfer completion flag is not set, it means that the changing display effect using the character image and the background image cannot be executed. However, the decorative design image data is developed in the VRAM 84 in the second data transfer process (step S702) shown in FIG.

  Note that the image data of the main character image and background image is controlled to be transferred from the CGROM 83 to the VRAM 84 when the power is turned on (at the start of power supply) in the sprite / video data transfer process (step S704 in FIG. 39). Therefore, although stored in the VRAM 84, the image data of the character image and the background image used in the effect control of the variation pattern starting from now on may not be stored in the VRAM 84. This is a case where the character image or background image to be used is one that is used very little. In that case, the CPU 101 for effect control has the address of the CGROM 83 storing the image data of the necessary character image and the image data of the background image, the transfer destination address of the frame memory 84A, and the transferred image data. Is specified (stored in the ROM 112 in advance), and the VDP 109 is caused to execute the CGROM → frame memory transfer process shown in FIG.

  FIG. 47A is an explanatory diagram showing a configuration example of a process table (first process table). The process table is a table in which process data referred to when the effect control CPU 101 executes control of the effect device is set. That is, the effect control CPU 101 controls effect devices (effect components) such as the image display device 9 in accordance with the data set in the process table. The process table includes data in which a plurality of combinations of process timer set values, display control execution data, lamp control execution data, and sound number data are collected. The display control execution data includes data indicating each variation mode constituting the variation mode during the variable display time (variation time) of the variable display of the decorative symbols. Specifically, data relating to the change of the display screen of the image display device 9 is described. The process timer set value is set with a change time in the form of the change. In the V blank interrupt process, the effect control CPU 101 refers to the process table, and performs control for displaying the decorative pattern in the variation mode set in the display control execution data for the time set in the process timer set value. Do.

  The process table shown in FIG. 47A is stored in the ROM 112 of the effect control board 80 as shown in the explanatory diagram of FIG. A process table is prepared for each variation pattern. Furthermore, different process tables are prepared according to the difference in the notice effect mode (notice type) when the notice effect is executed.

  47B and 47C are explanatory diagrams illustrating an example of display control execution data. FIG. 47B illustrates display control execution data related to a still image, and the display control execution data related to a still image includes a frame memory head indicating the start address of an area in which image data of a component image is expanded in the frame memory 84A. Address, frame memory final address indicating the final address of the image data of the component image in the frame memory 84A, flag indicating that it is a still image, component image specifying data for specifying the component image (the leading address and data in the CGROM 83) Length etc.) is set. FIG. 47B illustrates display control execution data relating to a moving image, and the display control execution data relating to a moving image includes, for example, a frame indicating the start address of an area in which image data of a moving image is expanded in the frame memory 84A. The memory start address, the frame memory final address indicating the final address of the area in which the image data of the moving image is expanded in the frame memory 84A, the flag indicating that it is a moving image, and movie data designation data (such as the start address and data length in the CGROM 83) Is set. Further, when combining a plurality of images, data specifying a plurality of images to be combined is also set in the display control execution data.

  FIG. 48A is an explanatory diagram showing a configuration example of the second process table. As shown in the explanatory diagram of FIG. 49, the second process table is also stored in the ROM 112 of the effect control board 80, and is prepared according to each variation pattern. Regarding the contents of the second process table, the data indicating the variation of the decorative pattern is described with respect to the display control execution data, but the process table (the data of the character image and the background image is not set). The contents of the first process table are different. Others are the same as the contents of the process table (first process table).

  That is, when the effect control is executed in accordance with the contents of the second process table, a display effect (a display effect that does not include a character image or a background image) as illustrated in FIG. 28B is executed. Further, when the effect control is executed according to the contents of the process table (first process table), the display effect (display effect including the character image and the background image) as illustrated in FIG. 28A is executed. The

  When the character transfer completion flag is not set, the second process table is selected, so that a display effect relating to the variation of the decorative pattern that does not include the character image or the background image is executed. When the character transfer completion flag is not set, the image data of the character image and the background image does not exist in the VRAM 84, so the VDP 109 cannot execute the effect control using the character image or the background image. Since the image data exists in the VRAM 84, the decorative pattern variation control can be executed.

  In step S843, the production control CPU 101 starts a process timer corresponding to the production execution data 1 in the selected process table (first process table or second process table) (step S843). Next, the effect control CPU 101 performs the effect device (the effect display device 9 as the effect component, the effect component as the effect component according to the contents of the process data 1 (display control execution data 1, lamp control execution data 1, sound number data 1). Control of the various lamps and the speaker 27 as a production component is executed (step S844). For example, a command is output to the VDP 109 in order to display an image according to the variation pattern on the effect display device 9. In addition, a control signal (lamp control execution data) is output to the lamp driver board 35 in order to perform on / off control of various lamps. In addition, a control signal (sound number data) is output to the sound output board 70 in order to output sound from the speaker 27.

  In this embodiment, when the variation pattern is accompanied by a super reach effect, process data indicating transfer of moving image data is included in the process table corresponding to the variation pattern. Specifically, the display control execution data includes data as exemplified in FIG.

  In this embodiment, the effect control CPU 101 performs control so that the decorative pattern is variably displayed by the change pattern corresponding to the change pattern command on a one-to-one basis. The variation pattern to be used may be selected from a plurality of types of variation patterns corresponding to.

  Then, the value corresponding to the variation time specified by the variation pattern command is set in the variation time timer (step S845), the process data valid flag is set (step S846), and the value of the effect control process flag is changed to the decorative pattern variation. A value corresponding to the intermediate process (step S803) is set (step S847). In this embodiment, the effect control CPU 101 appropriately outputs a command to the VDP 109 on condition that a process data valid flag is set in a V blank interrupt process described later. However, in step S844, if data that requires a command to be output to the VDP 109 has been set, the command is output to the VDP 109 according to the data.

  FIG. 50 is an explanatory diagram for explaining display effects executed in accordance with the contents of the process table (first process table or second process table). When the first process table is used as shown in FIG. 50A (when the character transfer completion flag is set), the effect control CPU 101 and the VDP 109 display the process table (first process) shown in FIG. Since display control is executed in accordance with display control execution data in the table), as shown in FIG. 28A, a display effect with a necessary character image and background image is executed during the variation of the decorative design. . When the second process table is used as shown in FIG. 50B (when the character transfer completion flag is not set), the effect control CPU 101 and the VDP 109 display the second process table shown in FIG. Since display control is executed in accordance with the display control execution data in FIG. 28, a display effect without a character image and a background image is executed while the decorative design is changing, as illustrated in FIG.

  FIG. 51 is a flowchart showing the decorative symbol variation process (step S803) in the effect control process. In the decorative symbol variation processing, the effect control CPU 101 subtracts 1 from the variation time timer value (step S851).

  If the variation time timer has timed out (step S856), the value of the effect control process flag is updated to a value corresponding to the effect symbol variation stop process (step S803) (step S858). Even if the variable time timer has not timed out, if the confirmation command reception flag indicating that the symbol confirmation designation command has been received is set (step S857), the process proceeds to step S858. The effect control CPU 101 sets a confirmation command reception flag when a symbol confirmation designation command is received in the command analysis process (step S707). Even if the variation time timer has not timed out, if the symbol confirmation designation command is received, the process shifts to control to stop variation.For example, a variation pattern command indicating a long variation time due to noise between substrates is received. Even in such a case, it is possible to end the variation of the effect symbol when the regular variation time has elapsed (when the variation of the special symbol ends).

  Further, when a power failure occurs during the change of the decorative symbol and then the power is restored within a predetermined period, the game control microcomputer 560 transmits a variation pattern command (see step S44 in FIG. 5). , The change of the decorative pattern is resumed. Then, when the remaining fluctuation time (fluctuation time—the fluctuation period executed before the power failure) has elapsed, the game control microcomputer 560 transmits a symbol determination command. The effect control CPU 101 operates to control the variation of the decorative symbol over the original variation time corresponding to the variation pattern based on the reception of the variation pattern command. Accordingly, the variation of the decorative design is terminated, so that the game control by the game control microcomputer 560 and the effect control by the effect control microcomputer 100 do not shift. Note that the game control microcomputer 560 may be configured not to transmit the variation pattern command when the power is restored within a predetermined period. In that case, the effect control CPU 101 causes the decoration symbol to be changed at a high speed in response to reception of a command such as a power failure recovery designation command, and when the symbol confirmation command is received, When the symbol confirmation command is received without performing the variation control, control is performed to cause the image display device 9 to display a stop symbol corresponding to the type of the received display result specifying command. In the case where it is configured not to control the variation of the decorative symbols, the image display device 9 can recover from a power failure until, for example, a control time for displaying the stopped symbols on the image display device 9 or for a predetermined period. A screen is displayed.

  When the confirmation command reception flag is not set, the effect control CPU 101 checks whether or not the simple variation flag indicating that the second process table is used is set (step S861). If the simple variation flag is set, it is confirmed whether or not a character transfer completion flag is set (step S862). When the character transfer completion flag is set, the process table to be used is switched. That is, the process table (first process table) corresponding to the currently used second process table is changed to a process table to be used later (step S863). The process table corresponding to the second process table is the first process table corresponding to the variation pattern corresponding to the second process table currently used (see FIG. 49).

  Then, the effect control CPU 101 starts a process timer corresponding to the effect execution data m in the selected process table (first process table) (step S864). Next, the production control CPU 101 performs the production device (the production display device 9 as the production component, the production component as the production component according to the contents of the process data m (display control execution data m, lamp control execution data m, sound number data m)). Control of the various lamps and the speaker 27 as a production component is executed (step S865). Further, the simple fluctuation flag is reset (step S866).

  The process data m is the process data in the second process table used last with reference to the time when the process table was switched (step S863) (in this embodiment, V blank interrupt processing described later). Used: see FIG. 59) is the mth process data, it is the process data in the mth first process table that is the same as that m.

  For example, when there are 100 pieces of process data in the first process table, the same number (100 pieces) of process data is set in the second process table. The value of each process timer in the second process table is set to the same value as the value of each process timer in the first process table.

  By executing the process of step S865, the remaining time of the presentation control using the process table (m-th process in the process table) when the use of the second process table is continued and when the process is switched to the first process table. The sum of the timer values of each process timer after the timer is almost the same, but not exactly the same. This is because the timing at which the m-th process timer is started is different between when the use of the second process table is continued and when the process is switched to the first process table. However, the effect control during the change is terminated when the symbol determination command is received from the game control microcomputer 560, and the final stop symbol of the decorative symbol is derived, so “displacement” does not become a problem.

  In this embodiment, after the production control based on the first process data in the process table is started, the production data is switched based on the process timer in the process table being timed out, and the production control is based on the process data after the switching. Is performed in the V blank interruption process (see FIG. 59), but the effect control CPU 101 switches the process data based on the process timer being timed out in the decorative symbol variation process, and based on the process data after the switching. Production control may be executed.

  FIG. 52 is an explanatory diagram for explaining switching from the second process table to the first process table. If the character transfer completion flag is set during the production control using the second process table, as shown in FIG. 52, each set in the first process table from that time is shown. Display control of the image display device 9 is executed according to the display control execution data.

  When the second process table is used, the display effect with the character image and the background image is not performed, but the variation speed of the decorative design (corresponding to the number of decorative design changes per unit time such as 1 second) is Control is performed in the same manner as when a display effect with a character image and a background image is performed (when a normal display effect that is not simple is performed). For example, when the normal display effect is a display effect accompanied by a reach effect (see FIG. 10), the decorative design fluctuates at a high speed, and then fluctuates according to the reach effect (for example, faster than the fluctuating speed of the high-speed fluctuation). It fluctuates at a slow fluctuation speed, a so-called frame advance, a fluctuation speed faster than the fluctuation speed of the high-speed fluctuation, a pause (speed 0), etc., and the speed is switched during reach production). Even when a simple variation using the second process table is performed, the variation rate of the decorative pattern is similarly controlled.

  However, when performing a simple change, the change speed of the decorative pattern may not be controlled, and the change speed may be constant from the start of change to the end of change (for example, a change speed of high-speed change).

  FIG. 53 is a flowchart showing the decorative symbol variation starting process (step S802) in the effect control process when the decorative symbol variation speed is kept constant when performing simple variation. In this case, if the character transfer completion flag is not set (step S842), the effect control CPU 101 selects the common second process table regardless of the variation pattern (step S842D), and the process proceeds to step S843. Transition. The other processes are the same as those shown in FIG. It should be noted that the effect control during the change is terminated when the symbol confirmation command is received from the game control microcomputer 560, and the final stop symbol of the decorative symbol is derived. This is the same as when the second process table corresponding to each variation pattern is used.

  FIG. 54 is an explanatory diagram of a configuration example of the common second process table. As shown in FIG. 54, the same value (for example, a value corresponding to high-speed fluctuation) is set in each process timer in the common second process table. For example, in the case of a fluctuation rate of 10 symbols / second (when a decorative symbol variation (variable display) is performed such that one decorative symbol moves left and right one frame at a time in the screen), each process timer Is set to a value corresponding to 0.1 seconds, and each display control execution data is set with data for designating the display of a decorative pattern shifted by one. In other words, the process timer is set to respond out in 100 ms.

  In the example shown in FIG. 49, the first process table and the second process table corresponding to each variation pattern are stored in the ROM 112. However, when the common second process table is used, A first process table corresponding to the variation pattern and one common second process table are stored in the ROM 112.

  FIG. 55 is a flowchart showing the decorative symbol variation process (step S803) in the effect control process when the variation rate of the decorative symbol is made constant when performing simple variation (that is, when the common second process table is used). It is. In this case, the effect control CPU 101 does not execute the processing of steps S861 to S866 (see FIG. 51). That is, the process of switching the process table based on the state of the character transfer completion flag is not executed. The processing in steps S851 to S858 is the same as the processing shown in FIG.

  As shown in FIG. 55, when a simple change is made, the process table is not switched from the second process table to the first process table. The background image is not displayed, and only the decorative design is displayed (variable display). Then, the variation of the decorative pattern accompanying the character image or the background image is executed after the next variation. However, the display of the background image on the image display device 9 may be resumed when the decorative symbol stop symbol is displayed (that is, when the symbol confirmation command is received).

  Note that even when the control shown in FIG. 46 is performed (when the decorative symbol variation speed is not always constant), the processing of steps S861 to S866 is not executed in the processing shown in FIG. The variation of the decorative pattern accompanying the image and the background image may be executed after the next variation. That is, the condition for executing the display effect using the first data including the plurality of image data used for the display effect when the effect control microcomputer 100 variably displays the effect identification information is at least: The end of the first variable display after the start of power supply may be included.

  FIG. 56 is a flowchart showing the effect symbol variation stop process (step S803) in the effect control process. In the effect symbol variation stop process, the effect control CPU 101 checks whether or not the confirmed command reception flag is set (step S871). If the confirmed command reception flag is set, the confirmed command reception flag is reset. Then (step S872), control for deriving and displaying the stop symbol is performed according to the data (data indicating the stop symbol) stored in the effect symbol display result storage area (step S873). Further, the process data valid flag is reset (step S874). Then, the effect control CPU 101 checks whether or not it is determined to be a big hit or a small hit (step S875). Whether it is determined to be a big hit or a small hit is confirmed, for example, by a display result specifying command stored in the display result specifying command storage area. In this embodiment, it can be confirmed whether or not it is determined to be a big hit or a small hit according to the determined stop symbol.

  If it is determined to be a big hit or a small hit, the value of the effect control process flag is updated to a value corresponding to the big hit display process (step S804) (step S876).

  When it is determined not to make a big hit or a small hit, the effect control CPU 101 updates the value of the effect control process flag to a value corresponding to the variation pattern command reception waiting process (step S800) (step S877). .

  FIG. 57 is a flowchart showing the jackpot display process (step S804) in the effect control process. In the jackpot display processing, the effect control CPU 101 receives a jackpot start 1 designation command reception flag and a jackpot start 2 designation command reception indicating that a jackpot start 1 designation command, a jackpot start 2 designation command or a small hit / surprise start designation command has been received. It is confirmed whether or not a flag or a small hit / rush start designation command reception flag is set (step S881). If the jackpot start 1 designation command reception flag, jackpot start 2 designation command reception flag, or small hit / cooking start designation command reception flag is set, the set flags (big hit start 1 designation command reception flag, jackpot start 2 designation command reception flag or small hit / attack start designation command reception flag) is reset (step S882), and a control to display a game start screen corresponding to the set flag on the effect display device 9 is performed.

  That is, a process table is selected according to the big hit game effect or the small hit game effect corresponding to the big hit type (step S883). Then, the process timer corresponding to the effect execution data 1 in the selected process table is started (step S884). Next, the effect control CPU 101 performs the effect device (the effect display device 9 as the effect component, the effect component as the effect component according to the contents of the process data 1 (display control execution data 1, lamp control execution data 1, sound number data 1). The control of the various lamps and the speaker 27 as a production component is executed (step S885). For example, a command is output to the VDP 109 in order to display an image according to the variation pattern on the effect display device 9. In addition, a control signal (lamp control execution data) is output to the lamp driver board 35 in order to perform on / off control of various lamps. In addition, a control signal (sound number data) is output to the sound output board 70 in order to output sound from the speaker 27. Then, the process data valid flag is set (step S886), and the value of the effect control process flag is updated to a value corresponding to the big hit game processing (step S805) (step S887).

  FIG. 58 is a flowchart showing the big hit end process (step S806) in the effect control process. In the big hit ending process, the effect control CPU 101 first checks whether or not the ending effect flag is set (step S890). If the ending effect flag is set, the process moves to step S897. When the ending effect flag is not set, the effect control CPU 101 responds to a jackpot end effect (big hit game end notification effect) or a small hit end effect (small hit game end notification effect) according to the type of jackpot. The selected process table is selected (step S891). Then, a process timer corresponding to the production execution data 1 in the selected process table is started (step S892). Next, the effect control CPU 101 performs the effect device (the effect display device 9 as the effect component, the effect component as the effect component according to the contents of the process data 1 (display control execution data 1, lamp control execution data 1, sound number data 1). The control of the various lamps and the speaker 27) as an effect part is executed (step S893). Also, a process data valid flag is set (step S894).

  Further, the effect control CPU 101 sets a value corresponding to the effect time in the effect period measurement timer (step S895), and sets an ending effect flag (step S896).

  In step S897, the effect control CPU 101 subtracts 1 from the effect period measurement timer. And it is confirmed whether the production period measurement timer has timed out (step S898). That is, it is determined whether or not the end timing of the ending effect has come. If the production period measurement timer has timed out, the process data valid flag is reset (step S899), and the value of the production control process flag is updated to a value corresponding to the variation start command reception waiting process (step S800) ( Step S900).

  FIG. 59 is a flowchart showing a V blank interrupt process executed by the effect control CPU 101 in response to a V blank interrupt from the VDP 109. The V blank interrupt is an interrupt generated by the VDP 109 in the same cycle as that of the vertical synchronization signal supplied to the image display device 9. For example, when the screen change frequency (frame frequency) of the image display device 9 is 30 Hz, the generation period of the V blank interrupt is 33.3 ms, and when the frame frequency is 60 Hz, the occurrence of the V blank interrupt is generated. The period is 16.7 ms.

  In this embodiment, the production control CPU 101 outputs a command to the VDP 109 in the V blank interruption process, but the process shown in FIG. 59 may be executed in another process. Other processes are, for example, a timer interrupt based on a timer built in for production control, or a decorative symbol changing process. In other processes, when the process shown in FIG. 59 is executed, for example, it is preferable to periodically execute a process for synchronizing the execution cycle and the V blank interrupt cycle.

  In the V blank interruption process, the effect control CPU 101 refers to the data in the display area register (see FIG. 36) to check whether the current display area is the area 0 or the area 1 (step S821). If the current display area is area 0, data indicating area 1 is set in the display area register to set the display area to area 1 (step S822). If the current display area is area 1, data indicating area 0 is set in the display area register to set the display area to area 0 (step S823).

  Next, when the process data valid flag (flag indicating that the effect control based on the process data is being performed) is set (step S824), the effect control CPU 101 decrements the value of the process timer by −1 (step S824). Step S825). When the value of the process timer becomes 0 (step S826), the value of the process data pointer is incremented by 4 (step S827). Therefore, the process data pointer points to the next process timer set value (see FIG. 47A). The effect control CPU 101 loads the contents of the display control execution data set in the area next to the area pointed to by the process data pointer (area where the process timer set value is set) (step S828). Note that data indicating specific display control contents may be set in the display control execution data area, but an address of a ROM area where data indicating specific display control contents is set is set. It may be.

  When data indicating drawing of a component image, that is, development to a frame memory is set as display control execution data (step S829), a drawing control process is executed (step S830). For example, when a variable display of a decorative symbol is executed such that one decorative symbol moves left and right one frame at a time every 0.1 second (100 ms), the process timer is set to respond out in 100 ms. Is set. If the decorative pattern “5” was displayed before the process timer timed out, the display control execution data used when the time-out occurred should be expanded to the frame memory with the decorative pattern “6”. The data shown is set. In this case, the effect control CPU 101 determines that drawing of a component image is necessary.

  Then, the process timer set value pointed to by the process data pointer is set in the process timer (step S831). That is, the process timer is started.

  In this embodiment, the frame memory has a double buffer configuration with areas 0 and 1, but the frame memory may be configured with a single area. In that case, the VDP 109 writes the image data in a single area. The display signal control unit 87 creates an image signal based on the image data developed in the frame memory and outputs the image signal to the image display device 9, but the frame memory is composed of a single area. In the VDP 109, the display signal control unit 87 performs the reading process after the writing process of the image data to the frame memory is finished so that the writing and reading of the image data to the frame memory do not compete with each other. Run.

  FIG. 60 is a flowchart showing a process in which the VDP 109 (specifically, the drawing control unit 91 in the VDP 109) transfers image data from the CGROM 83 to the fixed area of the VRAM 84 in response to a command from the effect control CPU 101. Note that the instruction from the CPU 101 for effect control is specifically, for example, VRAM fixed area transfer by the process of step S939 in the fixed area data transfer control process (see FIG. 42) executed when power supply is started. The corresponding bit in the execution instruction register is set.

  When the relevant bit of the VRAM fixed area transfer execution instruction register is set (step S1001), the VDP 109 uses the read source counter set in the CGROM start address register as a read address counter (for example, a general-purpose register in the VDP 109 (Internal RAM is used.) (Step S1002). Further, the transfer destination start address set in the VRAM start address register is set in a write address counter (for example, a general-purpose register or built-in RAM in the VDP 109 is used) (step S1003). Further, the data length (transfer data amount) set in the VRAM transfer data size register is set in a transfer data amount storage area (for example, a general-purpose register or built-in RAM in the VDP 109 is used) (step S1004). .

  Then, the data transfer process is executed (step S1005). When the data transfer process is completed, the corresponding bit of the VRAM fixed area transfer execution instruction register is reset (step S1006). The effect control CPU 101 can recognize that the transfer of the image data from the CGROM 83 to the VRAM 84 is completed by confirming that the corresponding bit of the VRAM fixed area transfer execution instruction register is reset (step S926 in FIG. 41, etc.). reference).

  FIG. 61 is a flowchart showing the data transfer process in step S1005. The data transfer process as a subroutine shown in FIG. 61 is also executed in other processes described later.

  In the data transfer process, the VDP 109 sets a process counter (for example, a general-purpose register or a built-in RAM in the VDP 109 is used) to 0 (step S1100). That is, the processing counter is initialized.

  Next, data is read from the address indicated by the read address counter (step S1101). In this case, image data is read from the CGROM 83. Then, the read data is written to the address indicated by the write address counter (step S1102). Next, the values of the read address counter, the write address counter, and the process counter are each incremented by 1 (step S1105). If the value of the processing counter matches the value (transfer data amount) set in the transfer data amount storage area, it means that all image data has been written in the transfer destination area, and the process ends (step S1106). ). If they do not match, the process returns to step S1101.

  In this embodiment, decorative design image data is transferred in advance from the CGROM 83 to the fixed area 84b (buffer area 84b1: see FIG. 30) of the VRAM 84. When the power supply to the gaming machine is started and the VDP 109 becomes operable, the contents of the drawing control register 95 are initialized, but the initial value of the data bus mode register (see FIG. 36) in the drawing control register 95 is “0”. Therefore, when the decorative design image data is pre-transferred to the fixed area of the VRAM 84, the data bus mode register is set to “0”, and the data width of the CG bus is 64 bits.

  When transferring the image data of the moving image from the CGROM 83 to the VRAM 84, the effect control CPU 101 uses the data bus mode register (see FIG. 36) in the drawing control register 95 to make the data width of the CG bus 32 bits. ) Is set to “1”. Then, for example, the start address of the area where the image data of the moving image is stored is set in the CGROM start address register. Further, the start address of the transfer destination area in the VRAM 84 is set in the VRAM start address register. Then, the corresponding bit of the decoding execution instruction register is set. Then, the VDP 109 transfers the decoded moving image data to the VRAM. Thereafter, the CPU 101 for effect control sets “0” in the data bus mode register (see FIG. 36) in the drawing control register 95 in order to return the data width of the CG bus to 64 bits.

  FIG. 62 is a flowchart showing a modified example of processing in which the VDP 109 (specifically, the drawing control unit 91 in the VDP 109) transfers image data from the CGROM 83 to the fixed area of the VRAM 84 in response to a command from the CPU 101 for effect control. It is. Here, the VDP 109 transfers the image data from the CGROM 83 to the fixed area via the temporary storage area 84 c of the VRAM 84.

  When the relevant bit of the VRAM fixed area transfer execution instruction register is set (step S1001), the VDP 109 uses the read source counter set in the CGROM start address register as a read address counter (for example, a general-purpose register in the VDP 109 (Internal RAM is used.) (Step S1002). Further, the head address of the temporary storage area 84c of the VRAM 84 is set in a write address counter (for example, a general-purpose register or built-in RAM in the VDP 109 is used) (step S1003A). Further, the data length (transfer data amount) set in the VRAM transfer data size register is set in a transfer data amount storage area (for example, a general-purpose register or built-in RAM in the VDP 109 is used) (step S1004). .

  Then, the data transfer process is executed (step S1005). When the data transfer process is completed, the start address of the transferred data, that is, the start address of the temporary storage area 84c is set as the transfer source start address in the built-in DMA circuit. (Step S1007) The contents of the VRAM head address register are set as the transfer destination head address (step S1008). Further, the data length (transfer data amount) set in the VRAM transfer data size register is set in the built-in DMA circuit (step S1009A), and the built-in DMA circuit is activated (step S1009B).

  The built-in DMA circuit outputs the read address starting from the transfer source start address to the VRAM bus, the read signal output, the output of the write address starting from the transfer destination start address to the VRAM bus, and the write signal output to the read address and the write signal. The data transfer is performed continuously while adding 1 to the embedded address. When the data transfer for the set data length is completed, for example, an internal interrupt is generated. The VDP 109 recognizes that all data has been transferred to the VRAM 84 due to the occurrence of the internal interrupt (step S10009C), and resets the corresponding bit in the VRAM fixed area transfer execution instruction register (step S1006).

  FIG. 63 is a flowchart showing the drawing control process in the V blank interrupt process (see FIG. 59). The effect control CPU 101 first specifies a component image to be updated (step S961). As an example, when a variable display of a decorative pattern is executed such that one decorative pattern moves up and down or left and right one frame at a time every 0.1 second (100 ms), the process timer is 100 ms out. It is set to be. If the decorative pattern “5” is displayed before the process timer times out, the decorative pattern “6” is expanded in the frame memory 84A as the display control execution data used when the process times out. Is set. In this case, the effect control CPU 101 determines that drawing of a component image is necessary in the process of step 829 in the V blank interrupt process. In step S961, the part image to be updated is identified as a decorative symbol “6”. Also, the process timer is shorter than 100 ms when variable display of a decorative pattern is executed such that one decorative symbol moves up and down or left and right on the screen every 0.1 second (100 ms). If it is set to respond out in time (for example, 50 ms) and only the decorative pattern of “5” is displayed before the process timer times out, the display control execution data used when timed out is Data indicating that a part of the decorative pattern “5” and a part of the decorative pattern “6” are expanded in the frame memory 84A may be set.

  Next, the effect control CPU 101 determines whether or not to switch to the moving image on the condition that the moving image mode flag is not set (step S962). Whether or not to switch to a moving image is determined based on the contents of the process data set in the process table. That is, the determination is made based on whether or not a flag indicating a moving image is set in the display control execution data (see FIG. 47C). When it is determined that switching to the moving image should be performed, “1” is set in the data bus mode register (see FIG. 36) in the drawing control register 95 (step S963). Then, the moving image mode flag is set (step S964).

  Further, the effect control CPU 101 determines whether or not to switch to the still image on the condition that the moving image mode flag is set (step S965). Whether or not to switch to a still image is determined based on the contents of process data set in the process table. That is, it is determined by whether or not a flag indicating a still image is set in the display control execution data (see FIG. 47B). If it is determined that the still image should be switched, “0” is set in the data bus mode register (see FIG. 36) in the drawing control register 95 (step S966). Then, the moving image mode flag is reset (step S967).

  By the processing in step S963, the effect control CPU 101 instructs the bus width of the CG bus between the CGROM 83 and the VDP 109 to be 32 bits when moving image display is performed on the image display device 9. In addition, when no moving image display is performed in the image display device 9, a command is given to set the bus width of the CG bus between the CGROM 83 and the VDP 109 to 64 bits.

  As described above, moving image data (compressed data) is stored in the CGROM 83 in a ROM capable of data input / output of 32 bits. Therefore, even if the bus width of the CG bus is set to 32 bits, the VDP 109 can read image data from the CGROM 83 without error.

  In this embodiment, the bus width of the CG bus is automatically set to 32 bits when “1” is set in the data bus mode register, and automatically when “0” is set in the data bus mode register. In particular, a VDP 109 that sets the bus width of the CG bus to 64 bits is used. However, the VDP 109 (specifically, the drawing control unit 91) validates the upper 32 bits of the 64-bit data bus according to the value set in the data bus mode register (the bus width is set to 64 bits). It is also possible to use a VDP 109 configured to perform control or disable control (the bus width is set to 32 bits). When such a VDP 109 is used, when the value set in the data bus mode register changes, the drawing control unit 91 performs a process of setting the bus width of the CG bus according to the changed value.

  In this embodiment, the VDP 109 sets the bus width to 32 bits and then returns the bus width to 64 bits when the still image data is read from the CGROM 83 next time. However, the process of reading moving image data from the CGROM 83 is performed. When finished, the bus width may be returned to 64 bits.

  Next, the effect control CPU 101 determines whether or not there is a part image to be updated (step S971). The process in step S971 is a process that takes into account that there may be a plurality of component images to be updated. If there is a part image to be updated, it is determined whether or not the part image exists in the fixed area 84b of the VRAM 84 (step S972). In this embodiment, each decorative design is a component image existing in the fixed area 84 b of the VRAM 84.

  If the component image exists in the fixed area, the start address of the area where the image data of the component image in the fixed area 84b exists is set in the fixed area arbitrary address register (see FIG. 36) (step S973). Further, the head address of the area where the image data of the component image is expanded in the frame memory 84A is set in the frame memory head address register (see FIG. 36) (step S974). Further, the transfer data amount (data length) of the image data to be transferred is set in the frame memory transfer data size register (see FIG. 36) (step S975). Then, the corresponding bit of the fixed area data transfer execution instruction register (see FIG. 36) is set (step S976).

  When the component image does not exist in the fixed area 84b, the effect control CPU 101 determines whether or not the component image is a moving image (step S980). If it is not a moving image, the head address of the image data of the component image (still image) in the CGROM 83 is set in the CGROM head address register (see FIG. 36) (step S981). In addition, the head address of the area where the image data of the component image is expanded in the frame memory 84A is set in the frame memory head address register (step S982). Further, the transfer data amount (data length) of the transferred image data is set in the frame memory transfer data size register (step S983). Then, the corresponding bit of the frame memory data transfer execution instruction register (see FIG. 36) is set (step S984).

  If the component image is a moving image, the start address of the image data (movie data) of the component image (moving image) in the CGROM 83 is set in the CGROM start address register (step S985). Further, the head address of the area where the image data of the moving image is expanded in the frame memory 84A is set in the frame memory head address register (step S986). Further, the transfer data amount (data length) of the movie data is set in the frame memory transfer data size register (step S987). Then, the corresponding bit of the decoding execution instruction register (see FIG. 36) is set (step S988).

  FIG. 64 is a flowchart showing processing in which the VDP 109 (specifically, the drawing control unit 91 in the VDP 109) transfers image data from the fixed area of the VRAM 84 to the frame memory 84A in response to a command from the CPU 101 for effect control. is there. The VDP 109 transfers the image data using the area 1 as the drawing area when the area 0 in the frame memory 84A is set as the display area, and the area 0 as the drawing area when the area 1 is set as the display area. The image data is transferred as In order to enable such control, for example, the effect control CPU 101 always instructs the address of the area 0 when instructing the address of the frame memory 84A. When the image data is transferred using the area 1 as the drawing area, the VDP 109 adds the difference between the address of the area 1 and the address of the area 0 to the commanded address to obtain a transfer destination address.

  When the corresponding bit in the fixed area transfer execution instruction register is set (step S1025), the VDP 109 sets the transfer source head address set in the fixed area arbitrary head address register in the processing of step S973 in the read address counter. (Step S1026). Further, the transfer destination start address set in the frame memory start address register is set in the write counter as the transfer destination start address (step S1027). Further, the data length (transfer data amount) set in the frame memory transfer data size register is set in the transfer data amount storage area (step S1028).

  Then, the data transfer process (see FIG. 61) is executed (step S1029). When the data transfer process is completed, the corresponding bit in the fixed area transfer execution instruction register is reset (step S1030). If necessary, the production control CPU 101 confirms that the corresponding bit of the fixed area transfer execution instruction register has been reset, and the transfer of the image data from the fixed area 84b of the VRAM 84 to the frame memory 84A is completed. I can recognize that.

  FIG. 65 is a flowchart showing processing in which the VDP 109 (specifically, the drawing control unit 91 in the VDP 109) transfers image data from the CGROM 83 to the frame memory 84A in response to a command from the effect control CPU 101.

  When the corresponding bit in the frame memory transfer execution instruction register is set (step S1031), the VDP 109 sets the transfer source head address set in the CGROM head address register in the read address counter (step S1032). Further, the start address of the temporary storage area 84c of the VRAM 84 is set in the write counter as the transfer destination start address (step S1033). Further, the data length (transfer data amount) set in the frame memory transfer data size register is set in the transfer data amount storage area (step S1034). Note that the corresponding bit of the frame memory transfer execution instruction register is set, for example, in the process of step S984 (see FIG. 63).

  Then, the data transfer process (see FIG. 61) is executed (step S1035). When the data transfer process is completed, the built-in DMA circuit sends the transferred data start address as the transfer source start address, that is, the temporary storage area 84c. The start address is set (step S1036), the transfer destination start address set in the frame memory start address register is set as the transfer destination start address, and the data length (transfer data set in the frame memory transfer data size register is set) Amount) is set (step S1037), and the built-in DMA circuit is activated (step S1038).

  The built-in DMA circuit outputs the read address starting from the transfer source start address to the VRAM bus, the read signal output, the output of the write address starting from the transfer destination start address to the VRAM bus, and the write signal output to the read address and the write signal. The data transfer is performed continuously while adding 1 to the embedded address. When the data transfer for the set data length is completed, for example, an internal interrupt is generated. The VDP 109 recognizes that all data has been transferred to the frame memory 84A due to the occurrence of the internal interrupt (step S1039), and resets the corresponding bit of the frame memory transfer execution instruction register (step S1040). If necessary, the effect control CPU 101 can recognize that the transfer of the image data from the CGROM 83 to the frame memory 84A has been completed by confirming that the corresponding bit of the frame memory transfer execution instruction register has been reset. .

  When it is necessary to transfer the image data from the CGROM 83 to the frame memory 84A, the presentation control CPU 101 simply designates the start address in the CGROM 83 and the start address in the frame memory 84A with respect to the addresses (see steps S981 and S982). The VDP 109 reads the image data from the frame memory 84A and expands the image data to the frame memory 84A via the temporary storage area 84c of the VRAM 84 (see steps S1032 to S1039). Therefore, even if the VDP 109 that transfers image data from the frame memory 84A to the frame memory 84A via the temporary storage area 84c is used, the effect control CPU 101 does not need to specify an address in the temporary storage area 84c, and the frame is transferred from the CGROM 83 to the frame. The control burden related to the transfer of image data to the memory 84A does not increase.

  66 and 67 show a moving image in which the VDP 109 (specifically, the drawing control unit 91 in the VDP 109) transfers the image data of the moving image from the CGROM 83 to the frame memory 84A in response to a command from the CPU 101 for effect control. It is a flowchart which shows a decoding process. In the moving picture decoding process, when the corresponding bit in the decoding execution instruction register is set (step S1041), the VDP 109 sets the transfer source head address set in the CGROM head address register in the read address counter (step S1042). ). Further, the start address of the temporary storage area 84c of the VRAM 84 is set in the write counter as the transfer destination start address (step S1043). Further, the data length (transfer data amount) set in the frame memory transfer data size register is set in the transfer data amount storage area (step S1044).

  Then, a data transfer process (see FIG. 61) is executed (step S1045). When the data transfer process ends, the moving image decompression unit 89 in the VDP 109 transfers the moving image data (compressed data) transferred to the temporary storage area 84c of the VRAM 84. For example, in units of 32 bits (step S1047).

  In this case, in the data transfer process, the image data is read from the CGROM 83 in units of 32 bits, and the image data is written in the temporary storage area 84c in units of 32 bits. In the case where the VRAM 84 is configured to have 64 bits as one word, when the image data is read twice from the CGROM 83 in units of 32 bits, the two image data are written in the temporary storage area 84c.

  Next, the decoded image data is stored in another area in the temporary storage area. If the moving image data is an I picture, decoding can be performed using only the moving image data transferred to the temporary storage area in step S1045. However, if the moving image data is a B picture or a P picture, it cannot be decoded using only the moving image data transferred to the temporary storage area in the process of step S1045. It is also necessary to use image data of frames that are decoded thereafter. Therefore, the VDP 109 stores image data of previously decoded frames necessary for decoding the P picture in the temporary storage area of the VRAM 84. Further, when decoding a B picture, the compressed data of the B picture is stored in the temporary storage area until the image data of the frame necessary for decoding the B picture is decoded, and is necessary for decoding the B picture. When the frame image data is decoded, the B picture image data is decoded.

  In this embodiment, the frame memory 84A and the VRAM 84 are provided outside the VDP 109. However, when the frame memory 84A and the VRAM 84 are built in the VDP 109, moving image data (compressed data) is The compressed data transferred from the CGROM 83 to the temporary storage area 84c in the internal RAM of the VDP 109 and transferred to the internal RAM is decoded.

  Next, the VDP 109 sets the start address of the temporary storage area 84c where the decoded image data is stored as the transfer source start address in the built-in DMA circuit (step S1048), and the frame memory start as the transfer destination start address. The transfer destination head address set in the address register is set, the data length (transfer data amount) of the decoded image data is set (step S1049), and the built-in DMA circuit is activated (step S1050).

  The built-in DMA circuit outputs the read address starting from the transfer source start address to the VRAM bus, the read signal output, the output of the write address starting from the transfer destination start address to the VRAM bus, and the write signal output to the read address and the write signal. The data transfer is performed continuously while adding 1 to the embedded address. When the data transfer for the set data length is completed, for example, an internal interrupt is generated. The VDP 109 recognizes that all data has been transferred to the frame memory 84A due to the occurrence of the internal interrupt (step S1051), and resets the corresponding bit in the decoding execution instruction register (step S1052). If necessary, the effect control CPU 101 can recognize that the transfer of the image data from the CGROM 83 to the frame memory 84A has been completed by confirming that the corresponding bit of the decoding execution instruction register has been reset.

  In this embodiment, the VDP 109 stores the moving image data (compressed data) of the CGROM 83 in the temporary storage area 84c of the VRAM 84, and the moving image decompression unit 89 targets the compressed data stored in the temporary storage area 84c. Decryption processing is performed. However, while the VDP 109 reads compressed data from the CGROM 83 in units of 32 bits, the moving image decompression unit 89 may perform decoding processing on the read compressed data. Then, the decoded image data is sequentially stored in the temporary storage area 84c.

  As described above, the drawing control to the frame memory 84A based on the display control execution data set in the process data is executed. The display signal control unit 87 creates an image signal based on the image data developed in the frame memory 84A, outputs the image signal to the image display device 9, and realizes image display on the image display device 9. The display signal control unit 87 outputs an image signal based on the image data developed in the area 0 or the area 1 of the frame memory 84A during a V blank interruption occurrence interval (for example, 33.3 ms). The image is output to the image display device 9 in synchronization with the clock signal. The display signal control unit 87 displays an image signal based on the image data developed in the region 1 as the display region when the drawing control unit 91 develops the image data in the region 0 as the drawing region. 9, when the drawing control unit 91 develops image data for the area 1 as the drawing area, an image signal based on the image data developed in the area 0 as the display area is sent to the image display device 9. Output.

  In this embodiment, the moving image data stored in the CGROM 83 is transferred to the frame memory 84A after being decoded. However, before actual display based on the moving image data is performed, the moving image data stored in advance in the CGROM 83 may be decoded and stored in the temporary storage area 84c of the VRAM 84, for example. In that case, for example, in the first display control execution data in the process table, a command (for VDP 109) for decoding the moving image data and expanding it in the temporary storage area is stored. A command for transferring image data from the temporary storage area of the VRAM 84 to the frame memory 84A may be set.

  As described above, in this embodiment, when the power supply to the gaming machine is started, the player can immediately start the variable display of the decorative symbols, and the player feels suspicious about the gaming machine. The possibility of embrace can be reduced. In addition, even when the variable display of the first special symbol is performed and when the variable display of the second special symbol is performed, a common display effect (for example, the direction of variation of the decorative symbols is the same) in the image display device. Since this is done, the player will not feel discomfort regarding the variable display.

  In the above embodiment, the image data expanded in the VRAM 84 is stored (stored) in the CGROM 83 and the image data is expanded in the VRAM 84 by the VDP 109. However, the production control CPU 101 creates the image data. Then, it may be written in the VRAM 84. As an example, the production control CPU 101 may create three-dimensional image data using polygons, and write the created image data into the VRAM 84. When the effect control CPU 101 creates image data and writes it to the VRAM 84, some of the image data used in the display effect is transferred from the CGROM 83 to the VRAM 84 by the VDP 109, and other image data. May be created by the effect control CPU 101 and transferred from the effect control CPU 101 to the VRAM 84.

  For example, when power supply to the gaming machine is started, the effect control CPU 101 determines that the image data of the decorative design (data including a plurality of image data used for display effects, which is larger than the data amount of the first data). An example of second data having a small data amount) is created (or read from the ROM 112 in which image data is stored in advance, or read from the CGROM 83 when the effect control CPU 101 can access the CGROM 83), and then the VRAM 84. Control is performed so as to be transferred to (an example of display storage means). The VDP 109 also stores image data of a character image and a background image (an example of first data including a plurality of image data used for display presentation when the identification information for presentation is variably displayed) as VRAM 84 (display storage means). Control) is performed. The effect control CPU 101 controls to write the decorative design image data directly to the VRAM 84, so that the decorative design image data is set in the VRAM 84 earlier, and as a result, power supply to the gaming machine is started. Sometimes it is possible to start changing the decorative pattern more quickly.

  Conversely, the second data may be transferred from the CGROM 83 to the VRAM 84 by the VDP 109, and the first data may be transferred from the CGROM 83 to the VRAM 84 by the effect control CPU 101. In this case, the initial data transfer means for executing the initial data transfer processing for transferring the first data from the image data storage means to the display storage means is realized by the effect control microcomputer 100. When the first data (or second data) is transferred from the CGROM 83 to the VRAM 84 by the effect control CPU 101 when power supply to the gaming machine is started, the second data (or The first data) may be transferred from the CGROM 83 to the VRAM 84 every time it is necessary for drawing.

Also, some image data (first data or second data in the above example) is transferred from the CGROM 83 to the VRAM 84 by the VDP 109, and other image data (second data or first data in the above example) is Instead of being configured to be transferred from the CGROM 83 to the VRAM 84 by the effect control CPU 101, the first data and the second data are transferred from the CGROM 83 to the VRAM 84 by the effect control CPU 101. May be.

  In this embodiment, the image control microcomputer 100 and the VDP 109 cooperate to realize the development of the image data from the CGROM 83 to the VRAM 84. The function of the VDP 109 (the function of the drawing processor) is controlled by the effect control. It may be realized by a microcomputer other than the microcomputer 100. Control information output means for outputting information for controlling the display state of the image display device may be realized by a drawing processor such as VDP. Further, when the display control microcomputer 100 and the VDP cooperate to perform display control, a plurality of VDPs may be provided.

  Further, when the production control CPU 101 is configured to create image data and write it to the VRAM 84, the created image data may be written to the VRAM 84 by the V blank interruption process shown in FIG. Good.

  FIG. 68 is an explanatory diagram showing an example of the display state of the summation pending storage display unit 18c. As shown in FIGS. 68 (A) and 68 (B), the total pending storage display portion 18c displays a number of circles (up to 8) corresponding to the total pending storage number. The effect control microcomputer 100 causes the VDP 109 to display a circle so that the first reserved memory and the second reserved memory can be distinguished. For example, a circle corresponding to the first reserved memory is displayed in red, and a circle corresponding to the second reserved memory is displayed in green. In FIG. 68, the frame portions are also displayed for those for which no hold has yet occurred (three in the example of FIG. 68 (A)), but the number for which no hold has occurred is completely undisplayed (frame Etc. may not be displayed.

  FIG. 68 (C) shows an example of the display state of the total suspension storage display unit 18c at the time of power failure recovery. As shown in FIG. 68 (C), at the time of power recovery, a number of stars corresponding to the total number of pending storage is displayed on the total pending storage display unit 18c. FIG. 68D shows an example of the display state of the total pending storage display unit 18c when the total pending storage number designation command is received from the game control microcomputer 560 but the start winning designation command cannot be received. ing. As shown in FIG. 68 (C), when the start winning designation command cannot be received, a blue circle is displayed on the total pending storage display unit 18c.

  As shown in FIG. 68C, at the time of power failure recovery, the production control microcomputer 100 displays a display corresponding to the original first reserved memory (first start winning memory) (in this example, a red circle is displayed). ) And the display corresponding to the second reserved memory (second start-up winning memory) (in this example, the display of the green circle) is a display of the number specified by the total reserved memory number designation command (this In the example, an asterisk) is displayed on the summed hold storage display unit 18c. Therefore, it becomes possible to easily grasp that the gaming state has been restored by using the display of the total suspension storage display unit 18c. In addition, if the display mode of the summed hold storage display unit 18c at the time of power failure recovery is different from the display mode corresponding to the original first hold memory and the display mode corresponding to the second hold memory, this embodiment. It is not restricted to changing the shape of the displayed image. For example, the color may be changed without changing the shape, or the size may be changed.

  As shown in FIG. 68D, when the start winning designation command cannot be received, the effect control microcomputer 100 displays the display corresponding to the original first reserved memory (in this example, a red circle). Image corresponding to the increased reserved memory in a mode different from the display corresponding to the second reserved memory (in this example, the green circle is displayed), and in a different manner (in this example, the blue circle is displayed). Is displayed. Therefore, it is possible to easily grasp that an abnormality has occurred with respect to transmission / reception of the effect control command (in this example, the start winning designation command). The production control microcomputer 100 does not display the display corresponding to the first reserved memory and the display corresponding to the second reserved memory in a different manner. You may make it display with the mode (for example, the display mode of a red circle when there is more 1st memory), when a game state is a probability change state or a time-short state. In addition, the display may be performed in a reserved storage mode (a green circle display mode corresponding to the second reserved storage) in which the number of reserved memories is likely to increase. Further, if the display mode of the combined hold storage display unit 18c at the time of power failure recovery is different from the display mode corresponding to the original first hold memory and the display mode corresponding to the second hold memory, this embodiment It is not restricted to changing the color of the image displayed like this. For example, the shape may be changed without changing the color, or the size may be changed.

  69 to 71 are flowcharts showing the hold storage display control process in the effect control main process. In the hold memory display control process, the effect control CPU 101 stores the data in the sum hold memory number storage area in which the second byte data (EXT data) of the sum hold memory number designation command is stored in the sum hold memory number counter. It is confirmed whether it is larger than the value (step S901). If the data in the total pending storage number storage area is not greater than the value of the total pending storage number counter, the process proceeds to step S941.

  The fact that the data in the total pending storage count storage area is larger than the value of the total pending storage count counter means that a new total pending storage count designation command has been received. When the power is turned on, the value of the total pending storage number counter is 0 by the initialization process in step S701.

  When the data in the total reserved memory number storage area is larger than the value of the total reserved memory number counter, whether or not the production control CPU 101 has a power failure recovery flag indicating that a power failure recovery designation command has been received is set. Confirmation is made (step S902). If the power failure recovery flag is set, the power failure recovery flag is reset (step S903), and the number of stars corresponding to the data (value) in the total pending storage number storage area is displayed in the total pending storage display unit 18c. It is displayed (step S904). That is, the number of star images stored in the total pending storage number storage area is displayed (see FIG. 38C).

  In addition, the production control CPU 101 sets the data in the total reserved memory number storage area in the unknown start winning memory number counter (step S905). The unknown start winning memory number counter is a counter formed in the RAM 113, and is a counter for counting the number of reserved memories that are unknown whether the reserved memory corresponding to the first starting prize or the reserved memory corresponding to the second starting prize. It is. Hereinafter, the reserved memory in which the reserved memory corresponding to the first start prize or the reserved memory corresponding to the second start prize is unknown is referred to as unknown reserved memory.

  Further, in the total pending storage table, the number of data corresponding to the data (value) in the total pending storage number storage area is changed to data indicating “unknown” (step S906). The total hold storage table is a table formed in the RAM 113, and whether each hold storage is a hold storage according to the first start winning, a hold storage according to the second start winning, or is unknown. This is a table in which data indicating is set.

  Then, the data in the total pending storage number storage area is set in the total pending storage number counter (step S907).

  When the power failure recovery flag is not set, the effect control CPU 101 checks whether or not the first start winning flag indicating that the first start winning designation command has been received is set (step S909). If the first start winning flag is set, the first starting winning flag is reset (step S910), the number of circles displayed in the total pending storage display unit 18c is increased by 1, and the increased circle is displayed in red. Control is performed (step S911). Further, the value of the first start winning counter is incremented by 1 (step S912), and the data corresponding to the data (value) in the total reserved storage number storage area is set to data indicating “first” in the total pending storage table (step S912). S913). For example, if the data in the total pending storage number storage area is “5”, the fifth data in the total pending storage table is set to data indicating “first”. That is, the data corresponding to the increased reserved storage is set to data indicating “first”.

  Then, it is confirmed whether or not the value of the first start winning counter has reached the upper limit “4” (step S914). If it is not “4”, the process proceeds to step S907. If it is “4”, it is checked whether or not the value of the unknown start winning counter is 0 (step S915). If the value of the unknown start winning counter is 0, the process proceeds to step S907. If the value of the unknown start winning counter is not 0 at this stage, it means that the number of unknown reserved memories indicated by the value of the unknown start winning counter is actually a reserved memory based on the second start winning prize. Because the upper limit number of the first reserved memory number is 4 and the value of the first start winning counter is 4, other reserved memories (the number of reserved memories exceeding 4) are the first start winning prizes. This is because it is not based on the reserved memory. That is, the other reserved memory is a reserved memory based on the second start winning prize.

  Therefore, when the value of the unknown start winning counter is not 0, the effect control CPU 101 changes the star displayed on the total pending storage display unit 18c to a green circle corresponding to the second start winning. (Step S916). Further, the data indicating “unknown” in the total pending storage table is changed to data indicating “second” (step S917). Further, the value of the unknown start winning counter is set to 0 (step S918), and the value of the second starting winning counter is updated (step S919). In step S919, the value of the unknown start winning counter before being set to 0 is added to the value of the second starting winning counter. Then, control goes to a step S907.

  By performing such control, an abnormality occurs in the transmission / reception of the production control command, an unknown hold memory is generated, and when the display corresponding to the unknown hold memory is displayed on the total hold memory display unit 18c, the display is normal. Display can be restored.

  If the first start winning flag is not set, it is confirmed whether the second starting winning flag is set (step S921). If the second start winning flag is not set, the process proceeds to step S931. If the second start winning flag is set, the second starting winning flag is reset (step S922), the number of circles displayed in the total pending storage display unit 18c is increased by 1, and the increased circle is displayed. Control is performed to display green (step S923). Further, the value of the second start winning counter is incremented by 1 (step S924), and the data corresponding to the data (value) in the total reserved storage number storage area is set to data indicating “second” in the total pending storage table (step S924). S925).

  Then, it is confirmed whether or not the value of the second start winning counter has reached the upper limit “4” (step S926). If it is not “4”, the process proceeds to step S935. If it is “4”, it is confirmed whether or not the value of the unknown start winning counter is 0 (step S927). When the value of the unknown start winning counter is 0, the process proceeds to step S935. When the value of the unknown start winning counter is not 0, the effect control CPU 101 changes the star displayed on the summation pending storage display unit 18c to a red circle corresponding to the first start winning (step). S928). Further, the data indicating “unknown” in the total pending storage table is changed to data indicating “first” (step S929). Further, the value of the unknown start winning counter is set to 0 (step S930), and the value of the first starting winning counter is updated (step S934). In step S934, the value of the unknown start winning counter before being set to 0 is added to the value of the first starting winning counter. Then, control goes to a step S935.

  In step S935, the data in the total pending storage number storage area is set in the total pending storage number counter.

  In step S931, control is performed so that the number of displays in the total pending storage display unit 18c is increased by 1, and the increased display is displayed in blue. Further, the value of the unknown start winning counter is incremented by 1 (step S932), and the data corresponding to the data (value) in the total reserved storage number storage area is set to data indicating “unknown” in the total pending storage table (step S933). . Then, control goes to a step S935.

  In step S941, the effect control CPU 101 confirms whether or not the total pending storage number subtraction designation command reception flag is set. If the total pending storage number subtraction designation command reception flag is set, the total pending storage number subtraction designation command reception flag is reset (step S942), and the circle displayed most recently in the total pending storage display portion 18c is displayed. Alternatively, the star mark is erased, and each circle mark or star mark is controlled to be shifted and displayed on the erased circle mark or star mark side (step S943). Then, it is checked whether or not the oldest data in the summation pending storage table is data indicating “first” (step S944). If the data indicates “first”, the value of the first start winning counter is set to − 1 (step S945). Further, in order to erase the oldest data in the total pending storage table, the data in the total pending storage table is shifted (step S951). Also, the value of the total pending storage number counter is decremented by -1 (step S952), and the value of the total pending storage number counter is set in the total pending storage number storage area (step S953).

  If the oldest data in the summation pending storage table is not data indicating “first”, it is confirmed whether or not it is data indicating “second” (step S946). If the data indicates “second”, the value of the second start winning counter is decremented by 1 (step S947). Then, control goes to a step S951. If the oldest data in the total pending storage table is not data indicating “second”, the value of the unknown start winning counter is decremented by 1 (step S948). Then, control goes to a step S951.

  By the control as described above, the red circle is incremented by 1 when the first start winning designation command and the total pending storage designation command are received in the total pending storage display unit 18c, and the second start winning designation command and the total are displayed. Control is executed to increase the green circle by 1 when a pending storage number designation command is received. Further, when the total pending storage number designation command is received but neither the first start prize designation command nor the second start prize designation command is received, control for increasing the blue circle by one is realized. When the total pending storage number subtraction designation command is received, the circle or star displayed in the total pending storage display unit 18c is decremented by one.

  72 to 74 are explanatory diagrams illustrating examples of data set in the summation pending storage table and display examples of the summation pending storage display unit 18c.

  FIG. 72A shows an example when the process of step S913 is executed. That is, an example is shown in the case where the reserved memory based on the first start winning memory is increased. FIG. 72B shows an example when the process of step S933 is executed. That is, an example is shown in which it is unclear whether the first start winning memory or the second starting winning memory is based, but the reserved memory increases. FIG. 72C shows an example of the case where the processes of steps S913 and S916 are executed. That is, an example is shown in which the hold memory based on the first start winning memory is increased and the value of the first start winning counter is “4”.

  FIG. 73D shows an example when the process of step S951 is executed. That is, an example in which the data in the total pending storage table is shifted to delete the oldest data in the total pending storage table based on the reception of the total pending storage number subtraction designation command. FIG. 73E shows an example of the case where the processes of steps S904 and S906 are executed. That is, based on the receipt of the total pending storage number designation command together with the power failure recovery designation command, a number of stars corresponding to the data (value) in the total pending storage number storage area is displayed on the total pending storage display unit 18c, An example in which the number of pieces of data corresponding to the data (value) in the total reserved storage number storage area is set as data indicating “unknown” in the total pending storage table.

  FIG. 73 (F) shows an example of the case where the combined pending storage number designation command is received after receiving the combined pending storage count designation command together with the power failure recovery designation command. In the example shown in FIG. 73 (F), after the total pending storage number designation command is received together with the power failure recovery designation command, the total pending storage number designation command is received together with the second start prize designation command, and the processes of steps S923 and S925 are performed. It is an example when it is executed.

  When the total pending storage number designation command is received together with the power failure recovery designation command, the data as shown on the left side of FIG. 73 (F) is set in the total pending storage table, and the total pending storage display unit 18c displays the data shown in FIG. The display shown on the left side of 73 (F) is made. Thereafter, when the total pending storage number designation command is received together with the second start winning designation command, the regular second startup is performed in the total pending storage display portion 18c. Display about winning (display of NO5) is made.

  FIG. 74 (G) shows an example of the case where the combined pending storage number designation command is received after receiving the combined pending storage count designation command together with the power failure recovery designation command. In the example shown in FIG. 74 (G), after receiving the combined pending storage number designation command together with the power failure recovery designation command, the combined pending storage number designation command is received together with the first start winning designation command, and the processes of steps S911 and S913 are performed. It is an example when it is executed.

  When the total pending storage number designation command is received together with the power failure recovery designation command, the data as shown on the left side of FIG. 74 (G) is set in the total pending storage table, and the total pending storage display unit 18c displays the data shown in FIG. 74 (G) is displayed on the left side, but when the total pending storage number designation command is received together with the first start winning designation command, the regular first startup is performed in the total pending storage display portion 18c. Display about winning (display of NO5) is made.

  FIG. 74 (H) received the total pending storage number designation command together with the second start prize designation command in the state shown on the left side of FIG. 74 (H) (the same as the state shown on the right side of FIG. 74 (G)). An example of the case is shown. In that case, as shown on the right side of FIG. 74 (H), a display about the regular second start winning (NO6 display) is made.

  As described above, after the total pending storage number designation command is transmitted together with the power failure recovery designation command, display capable of specifying the first pending memory number and the second pending memory number can be normally performed.

  In addition, when an unknown start winning occurs, only the portion corresponding to the unknown reserved memory is displayed in blue indicating that it is unknown in the total reserved memory display unit 18c (see FIG. 68D). ), When an unknown start winning is generated, all the displays in the summation pending storage display unit 18c may be displayed in blue indicating that they are unknown.

Embodiment 2. FIG.
The VDP 109 may perform an image enlargement process when performing a display effect such as a change in decorative design. FIG. 75 is an explanatory diagram for explaining an image enlargement process. The display signal control unit 87 in the VDP 109 creates an image signal based on the image data developed in the frame memory 84A and outputs the image signal to the image display device 9. The rendering control register 101 uses the rendering control CPU 101. When the enlargement ratio is set in the enlargement ratio setting register (see FIG. 36) at 95, the number of pixels is increased by performing pixel interpolation processing, and an image signal based on the image data of each pixel is output to the image display device 9. .

  For example, when the number of pixels of the screen of the image display device 9 is 1024 (horizontal) × 768 (vertical) (XVGA), the number of pixels of one screen is 640 (horizontal) × 480 (vertical) (VGA) in the frame memory 84A. ) Is stored, the screen is enlarged 1.6 times vertically and horizontally. That is, the number of pixels in the horizontal direction is increased 1.6 times by interpolation processing, and the number of pixels in the vertical direction is increased 1.6 times by interpolation processing. Further, when the frame memory 84A stores image data in which the number of pixels of one screen is 800 (horizontal) × 600 (vertical) (SVGA), processing for enlarging the screen by 1.28 times in the vertical and horizontal directions is performed. That is, the number of pixels in the horizontal direction is increased by 1.28 times by interpolation processing, and the number of pixels in the vertical direction is increased by 1.28 times by interpolation processing.

  As an example, the number of pixels converted into one screen of a still image (sprite image) stored in the CGROM 83 is 800 (horizontal) × 600 (vertical). Further, the number of pixels converted into one screen of the movie image is 640 (horizontal) × 480 (vertical). The CPU 101 for effect control enlarges 1.6 times vertically and horizontally in the enlargement ratio setting register (see FIG. 36) when the image display device 9 performs display based on the image data of the still image developed in the frame memory 84A. Set the rate. Further, at the time when the display based on the movie image developed in the frame memory 84A is performed, an enlargement ratio of 1.28 times in length and width is set in the enlargement ratio setting register (see FIG. 36).

  For example, a movie image is used as an image to be displayed on the image display device 9 when a decorative design change accompanied by a super reach effect is performed. A still image is used as an image to be displayed. In this case, the effect control CPU 101 sets an enlargement ratio of 1.6 times or 1.28 times in the enlargement ratio setting register when starting the change of the decorative design.

  In this embodiment, the number of pixels corresponding to 640 (horizontal) × 480 (vertical) is set for a movie image having a relatively large amount of data (an image in an effect accompanied by a super reach effect). The image data of the image in the effect accompanying the effect may be image data having a larger number of pixels (in this example, the number of pixels is 800 (horizontal) × 600 (vertical)). In that case, when the reliability that is a big hit is higher, the effect by the high-resolution image is executed, and the effect is increased.

  FIG. 76 is a flowchart showing a decorative symbol variation start process (step S802) according to the second embodiment. In the decorative symbol variation start process, the effect control CPU 101 selects a process table (first process table) corresponding to the variation pattern (step S842A), and the variation pattern uses a moving image (movie image). It is confirmed whether or not the fluctuation pattern is accompanied by (step S842E). If the variation pattern is accompanied by a super reach effect, an enlargement factor of 1.28 times in length and width is set in the enlargement factor setting register (step S842F). If the variation pattern is not accompanied by a super reach effect, an enlargement factor of 1.68 times in length and breadth is set in the enlargement factor setting register (step S842G). The other processes are the same as those shown in FIG.

  FIG. 77 is a flowchart showing a decorative symbol variation process (step S803) according to the modification of the second embodiment. In the modified example, the decorative symbol variation start process shown in FIG. 46 is not executed, but the decorative symbol variation start process shown in FIG. 46 is executed as in the case of the first embodiment.

  Then, as shown in FIG. 77, when the effect control CPU 101 confirms that the reach timing has arrived in the decorative symbol variation processing (step S867), the variation pattern uses a moving image (movie image). It is confirmed whether or not the fluctuation pattern is accompanied by (step S868). If the variation pattern is accompanied by a super reach effect, an enlargement factor of 1.28 times in length and width is set in the enlargement factor setting register (step S869). If the variation pattern is not accompanied by a super reach effect, an enlargement factor of 1.28 times in length and width is set in the enlargement factor setting register (step S870). Other processes are the same as those shown in FIG.

  Note that the arrival of reach timing means the time when reach is reached. In the example shown in FIG. 10, it is when 5 seconds have elapsed since the start of the fluctuation. The effect control CPU 101 determines whether or not the reach timing has arrived, for example, based on the value of the variation time timer. Further, in this embodiment, since the process data switching in the process table during the decorative pattern change is executed by the V blank interrupt process, the process data switching when the reach timing comes in the V blank interrupt process. When the time comes, it may be determined that the reach timing has arrived.

  FIG. 78 is a flowchart showing the effect symbol variation stop process (step S803) in the second embodiment. In the second embodiment, the CPU 101 for effect control initializes the enlargement ratio setting register (for example, sets the enlargement ratio 1.0) when the confirmation command reception flag is set. Execute (Step S873A). Other processes are the same as those shown in FIG.

  As described above, the display signal control unit 87 in the VDP 109 creates an image signal based on the image data developed in the frame memory 84A and outputs the image signal to the image display device 9. When an enlargement factor other than 1.0 is set in the register, pixel interpolation is performed to increase the number of pixels, and an image signal based on the image data of each pixel is output to the image display device 9. Therefore, an enlarged image is displayed on the image display device 9 in accordance with the setting of the enlargement ratio setting register.

  In this embodiment, when the number of pixels of the image display device 9 is the same as that in the first embodiment, the image data of the still image and movie image stored in the CGROM 83 is used as the image data of the first embodiment. It is sufficient that image data having a smaller number of pixels than that in the case is stored in the CGROM 83. Therefore, the capacity of the CGROM 83 can be reduced when displaying images with the same number of pixels.

  In this embodiment, the VDP 109 performs the process of enlarging the image. However, the process of reducing the image can also be performed. Further, the display signal control unit 87 in the VDP 109 may execute an enlargement process on a component image displayed on a part of the screen of the image display device 9.

Embodiment 3 FIG.
In the first embodiment, the effect control CPU 101 uses the frame memory 84A from the VRAM 84 or the CGROM 83 when the image data of the component image required for the display effect does not exist in the frame memory 84A in the V blank interruption process. However, the effect control CPU 101 checks whether or not the image data of the component image required for the display effect exists in the frame memory 84A and confirms that it does not exist. If confirmed, a command to transfer the image data of the component image may be output to the VDP 109.

  FIG. 79 is an explanatory diagram showing an example of a component image necessary for each variation pattern. Note that data indicating a component image necessary for each variation pattern is stored in the ROM 112 as a table.

  FIG. 80 is an explanatory diagram showing a configuration example of a component image data transfer area data table in this embodiment. As shown in FIG. 80, the storage address (start address) and data size (data length) of the image data of each component image in the CGROM 83 are set in the component image data transfer area data table.

  FIG. 81 is a flowchart showing command analysis processing (step S707). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control CPU 101 confirms the contents of the command stored in the command reception buffer.

  In the command analysis process, the effect control CPU 101 first checks whether or not a reception command is stored in the command reception buffer (step S611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the effect control CPU 101 reads the reception command from the command reception buffer (step S612). When read, the value of the read pointer is incremented by +2 (step S613). The reason for +2 is that two bytes (one command) are read out.

  If the received effect control command is a variation pattern command (step S614), the effect control CPU 101 stores the variation pattern command in a variation pattern command storage area formed in the RAM (step S615). Then, a variation pattern command reception flag is set (step S616).

  Further, it is confirmed whether or not image data of a component image necessary for performing a display effect according to the variation pattern is stored in the VRAM 84 (step S617). When the CPU 101 for effect control outputs a command for transferring the image data of the component image to the VRAM 84 to the VDP 109, the RAM 113 or the like stores data that can identify the component image. Therefore, the CPU 101 for effect control can check whether the image data of the necessary component image is stored in the VRAM 84 based on the data stored in the RAM 113 or the like. The production control CPU 101 outputs a command for transferring the image data of the main component image to the VRAM 84 in the second data transfer process (step S702), but the component image can also be specified at that time. Data is stored in the RAM 113 or the like.

  When it is determined in step S617 that there is a part image for which no image data is stored in the VRAM 84, the effect control CPU 101 determines the head address of the part image data transfer area data table corresponding to the part image as follows: For example, it is set in the internal register (step S618), and the start address of the transfer destination area in the buffer area 84b2 of the VRAM 84 is set in the VRAM start address register (see FIG. 36) in the drawing control register 95 (step S619). Is set to 0 (step S620. Then, the component image data transfer control process is executed (step S621).

  If the received effect control command is not a variation pattern command, the effect control CPU 101 sets a flag corresponding to the received effect control command (step S621). Then, control goes to a step S611.

  FIG. 82 is a flowchart showing the component image data transfer control process. In the component image data transfer control process, the effect control CPU 101 reads data at the address indicated by the address pointer in the component image data transfer area data table (data storage start address (transfer source start address) in the CGROM 83) (step S631). Since the head address of the component image data transfer area data table in the ROM 112 is not 0000, when reading data from the component image data transfer area data table, the value of the address pointer is set to the head address of the part image data transfer area data table. Is added as an offset value. The effect control CPU 101 sets the data read from the component image data transfer area data table in the CGROM head address register (see FIG. 36) (step S632). Then, the value of the address pointer is incremented by 1 (step S633).

  Next, the data (data length) of the address pointed to by the address pointer in the component image data transfer area data table is read (step S634), and the read data is set in the VRAM transfer data size register (see FIG. 36) (step S635). ). Then, the corresponding bit of the VRAM fixed area transfer execution instruction register is set (step S636).

  As described above, the instruction for transferring the image data of the component image stored in the CGROM 83 to the VRAM 84 is given to the VDP 109 from the effect control CPU 101 to the VDP 109. When a command for transferring image data to the VRAM 84 is given from the effect control CPU 101, the VDP 109 executes data transfer from the CGROM 83 to the VRAM 84 (see FIG. 62).

  In the first embodiment, the CPU 101 for effect control outputs a command for transferring the image data of the main component image to the VRAM 84 in the second data transfer process (step S702), and the VDP 109 responds to the command. The image data of main component images is transferred from the CGROM 83 to the VRAM 84 so that display effects using these component images can be executed. Then, if there is a part image that is not stored in the VRAM 84 among the part images used for the display effect, the effect control CPU 101 instructs the VDP 109 to transfer the image data of the component image from the CGROM 83 to the VRAM 84 as appropriate. (See FIG. 59 and FIG. 63).

  In the third embodiment, as in the case of the first embodiment, the effect control CPU 101 transfers image data of main component images to the VRAM 84 in the second data transfer process (step S702). The command is output to the VDP 109, and the VDP 109 transfers the image data of the main component images from the CGROM 83 to the VRAM 84 in accordance with the command so that a display effect using these component images can be executed. Then, if there is a part image that is not stored in the VRAM 84 among the part images used for the display effect, the CPU 101 for effect control gives a command to the VDP 109 to transfer the image data of the part image from the CGROM 83 to the VRAM 84. (See FIG. 81).

  For example, among the image data of the component images used for display effects, frequently used component images (for example, decorative symbols) are transferred from the CGROM 83 to the VRAM 84 in advance, and then there are insufficient component image image data in the VRAM 84. In each case, the image data of the component image is transferred from the CGROM 83 to the VRAM 84 so that a display effect using the component image can be executed.

  However, if the capacity of the VRAM 84 is sufficient, in order to immediately execute all types of display effects, all the display data of the component images used in any display effect can be transferred to the VRAM 84 in advance. it can. In that case, for example, in the sprite / video data transfer process (step S704) shown in FIG. 39, control is performed to transfer all of the display data of the component image used in any display effect to the VRAM 84.

  In the above embodiment, a gaming machine including two special symbol displays 8a and 8b is taken as an example. However, the image display device 9 includes a special symbol display (variable display unit). The present invention can also be applied to a gaming machine configured to variably display decorative symbols in synchronization with the variable display of special symbols on the symbol display.

  In the above-described embodiment, the game control microcomputer 560 directly transmits a command to the effect control microcomputer 100. However, the game control microcomputer 560 transmits another command (for example, FIG. 3). The sound output board 70 and the lamp driver board 35 shown in FIG. 5 or the sound / lamp board having the function of the circuit mounted on the sound output board 70 and the function of the circuit mounted on the lamp driver board 35). A control command may be transmitted and transmitted to the effect control microcomputer 100 on the effect control board 80 via another board. In that case, the command may simply pass through another board, or the sound output board 70, the lamp driver board 35, and the sound / lamp board are equipped with control means such as a microcomputer, and the control means receives the command. In response to this, control related to sound control and lamp control is executed, and the received command is changed as it is or, for example, to a simplified command to control the effect display device 9. You may make it transmit to. Even in that case, the effect control microcomputer 100 performs the display control in accordance with the effect control command directly received from the game control microcomputer 560 in the above-described embodiment. Display control can be performed in accordance with commands received from the board 35 or the sound / lamp board.

  The present invention is preferably applied to a gaming machine including an image display device and capable of displaying still images and moving images for production on the image display device.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 8a 1st special symbol display 8b 2nd special symbol display 9 Image display device 13 1st start winning opening 14 2nd starting winning opening 18c Total pending storage display part 31 Game control board (main board)
56 CPU
83 CGROM
84 VRAM
84A Frame memory 85 Frame buffer 87 Display signal control unit 89 Moving image decompression unit 91 Drawing control unit 94 Data transfer circuit 95 Drawing control register 560 Game control microcomputer 80 Production control board 100 Production control microcomputer 101 Production control CPU
109 Drawing processor (VDP)

Claims (1)

After the game ball has won the first start area, the first identification information based on the first identification information that can identify each is based on the fact that the first start condition that enables the start of the variable display based on the winning is established. A first variation display means for starting a variation display of 1 and deriving and displaying a display result; and a second start condition that allows a variation display based on the winning to be started after a game ball has won the second start area And second variation display means for deriving and displaying a display result based on the second identification information that can identify each of the first variation display means and the first variation display means or A gaming machine that controls a specific gaming state advantageous to the player when a predetermined specific display result is derived and displayed on the second variation display means,
Game control means for controlling the progress display of the game, and for controlling the change display in the first change display means and the second change display means,
Production control means for controlling the production parts provided in the gaming machine,
The effect part includes an effect display device that performs change display of the identification information for effect corresponding to the first change display or the second change display,
The game control means includes
The first variation by the first variation display means when the first start condition is satisfied on condition that neither the first variation display nor the second variation display is executed. First variation display start means for starting display;
When the second start condition is satisfied on the condition that neither the first fluctuation display nor the second fluctuation display is executed, the second fluctuation display by the second fluctuation display means is performed. Second variation display start means for starting display;
A first variation pattern for selecting a variation pattern including a variation display time from the start of variation display of the first variation display to the end of variation display in the first variation display means in which the first start condition is satisfied. For selecting a variation pattern including a variation display time from a variation display start time to a variation display end time of the second variation display in the second variation display means in which the second start condition is satisfied and the selection process. The second variation pattern selection process is executed by the same processing routine, and the variation display of the variation display in the variation display means in which the variation display start condition is satisfied among the first variation display means and the second variation display means. A variation pattern selecting means for selecting a variation pattern including time from a plurality of variation patterns;
Based on the variation pattern selected by the variation pattern selection means, first data indicating a variation display time of variation display executed in the first variation display means when the first start condition is satisfied; Fluctuation display time storage means for storing, in the same storage area, second data indicating the fluctuation display time of the fluctuation display executed in the second fluctuation display means when the second start condition is satisfied;
A change display means specifying command capable of specifying which of the first change display means and the second change display means to start change display when starting the change display; and the change pattern selection means. A variation start time command transmission means for transmitting a variation pattern command capable of specifying the selected variation pattern;
When the power supply is restored when the power supply is restored when the power supply to the gaming machine is stopped and the power supply is restored, the effect control means displays the fluctuation display of the effect identification information. It is executed in a mode different from the mode before stopping.

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