JP2015136522A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of preventing a case where a game is not pertinently executed due to irregular in a distribution device.SOLUTION: A game machine comprises: adding means for adding a predetermined value to a value stored in the storage region, as an adding target, corresponding to a start region through which a game media has passed when a game media passes through a first start region or second start region; irregular determination means for determining irregularity based on that the adding result by the adding means meets a predetermined requirement; storage means which may store information created upon a control regarding to a game is created even if supplementation of electric power to the game machine is terminated and comprises at least a storage region; predetermined process executing means capable of executing a predetermined process; and initialization means initializing the memory content in the storage means when a predetermined phenomenon occurs during execution of a predetermined process.

Description

  In the present invention, a predetermined game can be played using a game medium, a game area into which the game medium can enter is provided, and each can be identified based on the fact that the game medium has passed through the starting area. The present invention relates to a gaming machine such as a pachinko gaming machine that variably displays a plurality of types of identification information.

  As a gaming machine, a game ball, which is a game medium, is launched into a game area by a launching device, and when a game ball wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Further, a variable display unit capable of variably displaying the identification information (also referred to as “fluctuation”) is provided, and a predetermined game value is obtained when the display result of the variable display of the identification information in the variable display unit becomes a specific display result. Are configured to give the player.

  The game value is the right that the state of the variable winning ball apparatus provided in the gaming area of the gaming machine becomes advantageous for a player who is easy to win, and the right for becoming advantageous for a player. In other words, or a condition for winning a prize ball is easily established.

  In a pachinko machine, a specific display mode determined in advance is derived and displayed as a display result of variable display of a special symbol (identification information) that is started in the variable display unit based on the winning of a game ball at the start winning opening. If this happens, a “big hit” will occur. Note that the derivation display is to stop and display a symbol (excluding stop before so-called re-variation). When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. And the number of times the special winning opening is opened is fixed to a predetermined number (for example, 15 rounds). An opening time (for example, 29 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Hereinafter, the opening period of each special winning opening may be referred to as a round.

  Some of these gaming machines are configured such that a distribution device for distributing game media (game balls) is provided in the game area. For example, in Patent Document 1, a distribution device (distribution unit) is provided in the game area, and a rotating body provided in the distribution device rotates by the weight of the game medium flowing into the distribution device. It is described that the game media flowing into the distribution device are alternately distributed to the first area and the second area.

JP 2010-104564 A (paragraphs 0044-0056, FIG. 38)

  However, in the gaming machine described in Patent Document 1, if any abnormality occurs with respect to the sorting device, it is not possible to normally distribute the game media (game balls), and the game may not be performed normally. There is.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a gaming machine that can prevent a game from being unable to be normally performed due to an abnormality of a sorting device.

(Means 1) The gaming machine according to the present invention is capable of performing a predetermined game using a game medium (for example, a game ball), and is provided with a game area (for example, a game area 7) into which the game medium can enter. And a plurality of types of identification information (for example, each of which can be identified based on the fact that the game medium has passed through the starting area (for example, the first starting winning port 13, the second starting winning port 14, and the third starting winning port 17)). For example, a gaming machine that performs variable display of a first special symbol, a second special symbol, and a production symbol, and the first starting region (for example, the first starting winning award 13) and the second starting region (for example, the starting region) , A second start winning opening 14) is provided, a distribution device (for example, a distribution device 200) for distributing game media is provided in the game area, and the distribution device has the game media that has entered the game area in question Inlet that can flow into the sorting device (for example, , Inflow port 201), a plurality of passages through which the game medium flowing in from the inflow port can pass (for example, the left side passage 203 and the right side passage 204), and the game medium flowing in from the inflow port Distribution means (e.g., a distribution member 202) that distributes to the first passage (e.g., the left-side passage 203) of the plurality of passages based on the flow of the game medium from the inflow port. ) In the first state (for example, the state in which the sorting member 202 is tilted to the right side as shown in FIGS. 2A and 2D) and the second passage (for example, the right passage 204). Switching to a second state in which the medium is easily distributed (for example, as shown in FIGS. 2B and 2C, the state in which the sorting member 202 is tilted to the left) is performed in a predetermined order (for example, as illustrated in FIG. 2). Alternate) The first start area is provided in such a manner that game media distributed to the first passage can easily pass through (for example, as shown in FIGS. 2 and 3, the first start winning port 13 is provided below the left outlet 205. The second start area is provided in such a manner that the game media distributed to the second passage can easily pass through (for example, as shown in FIGS. 2 and 3, the second start winning opening 14 is provided on the right side). A storage area corresponding to the start area through which the game medium has passed based on the fact that the game medium has passed through the first start area or the second start area (for example, first start port monitoring) Addition means for adding a predetermined value to the value stored in the storage area with the addition buffer as the addition start buffer and the second start port monitoring buffer, for example, the game control microcomputer 560 executes step S254. Part) and the addition result by the adding means satisfy a predetermined condition (for example, the addition result is equal to or greater than the determination value (5), or the difference between the addition buffer value and the clear buffer value is equal to or greater than the predetermined value). Abnormality determination means (for example, the part in which the game control microcomputer 560 executes step S259) that determines abnormality based on the above, and the game control microcomputer that controls the progress of the game (for example, the game control microcomputer 560) ) And a first event (for example, system reset) is generated based on occurrence of a predetermined event (for example, input of IAT signal from IAT circuit 506a, input of timeout signal from watchdog timer (WDT) 506b) Or a second reset (for example, user reset) that can be set. And a first setting means (for example, a part for executing steps S1001 and S1011 according to the set value of bit 7 of the reset setting (KRES) shown in FIG. 14 of the program management area in the game control microcomputer 560). While the security check is performed after the occurrence of the reset, the security check is not performed after the occurrence of the second reset (for example, the game control microcomputer 560 performs the process after step S1004 as shown in FIG. 48A). In step S1006, the security check is executed, and as shown in FIG. 48B, the security check is not executed after step S1014). The gaming control microcomputer has stopped supplying power to the gaming machine. Is also used when performing game-related controls. Storage means (for example, RAM 55 (backup RAM)) including at least a storage area (for example, an addition buffer or a clear buffer) and predetermined processing (for example, loop processing in the main processing, A predetermined event occurred during execution of a predetermined process executing means (for example, a portion executing steps S16 to S19 and S20 to S34 in the game control microcomputer 560) capable of executing a timer interrupt process) Initializing means for initializing the storage contents of the storage means (for example, in the game control microcomputer 560, during the execution of steps S16 to S19, S20 to S34, the IAT signal from the IAT circuit 506a and the watchdog timer (WDT ) When the time-out signal from 506b is input, 52 and FIG. 53 without executing the power-off process, and a part that executes steps S10 to S13 when the main process is started after resetting).
With such a configuration, it is possible to perform abnormality determination of the sorting device, so that it is possible to prevent the game from being performed normally due to the abnormality of the sorting device.

(Means 2) The gaming machine according to the present invention is capable of performing a predetermined game using a game medium (for example, a game ball), and has a game area (for example, a game area 7) into which the game medium can enter. And a plurality of types of identification information (for example, each of which can be identified based on the fact that the game medium has passed through the starting area (for example, the first starting winning port 13, the second starting winning port 14, and the third starting winning port 17)). For example, a gaming machine that performs variable display of a first special symbol, a second special symbol, and a production symbol, and the first starting region (for example, the first starting winning award 13) and the second starting region (for example, the starting region) , A second start winning opening 14) is provided, a distribution device (for example, a distribution device 200) for distributing game media is provided in the game area, and the distribution device has the game media that has entered the game area in question Inlet that can flow into the sorting device (for example, , Inflow port 201), a plurality of passages through which the game medium flowing in from the inflow port can pass (for example, the left side passage 203 and the right side passage 204), and the game medium flowing in from the inflow port Distribution means (e.g., a distribution member 202) that distributes to the first passage (e.g., the left-side passage 203) of the plurality of passages based on the flow of the game medium from the inflow port. ) In the first state (for example, the state in which the sorting member 202 is tilted to the right side as shown in FIGS. 2A and 2D) and the second passage (for example, the right passage 204). Switching to a second state in which the medium is easily distributed (for example, as shown in FIGS. 2B and 2C, the state in which the sorting member 202 is tilted to the left) is performed in a predetermined order (for example, as illustrated in FIG. 2). Alternate) The first start area is provided in such a manner that game media distributed to the first passage can easily pass through (for example, as shown in FIGS. 2 and 3, the first start winning port 13 is provided below the left outlet 205. The second start area is provided in such a manner that the game media distributed to the second passage can easily pass through (for example, as shown in FIGS. 2 and 3, the second start winning opening 14 is provided on the right side). A storage area corresponding to the start area through which the game medium has passed based on the fact that the game medium has passed through the first start area or the second start area (for example, first start port monitoring) Subtracting means (for example, the game control microcomputer 560 executes step S254b) by subtracting a predetermined value from the value stored in the storage area for the subtraction target and the second start port monitoring buffer). The subtraction result by the subtracting means satisfies a predetermined condition (for example, the subtraction result is 0, or the difference between the value of the subtraction buffer and the value of the initial value setting buffer is equal to or greater than the predetermined value). An abnormality determination means (for example, a part where the game control microcomputer 560 executes step S259b) for determining an abnormality based on the above, and a game control microcomputer (for example, a game control microcomputer 560) for controlling the progress of the game And a first reset (for example, system reset) is generated based on occurrence of a predetermined event (for example, input of an IAT signal from the IAT circuit 506a, input of a time-out signal from the watchdog timer (WDT) 506b). Or a reset that can be set to generate a second reset (for example, a user reset) And a first reset unit (for example, a part that executes steps S1001 and S1011 in accordance with the set value of bit 7 of the reset setting (KRES) shown in FIG. 14 of the program management area in the game control microcomputer 560). After the occurrence of the second reset, the security check is executed, but the security check is not executed after the occurrence of the second reset (for example, the game control microcomputer 560 does not execute the step S1004 as shown in FIG. 48A). In step S1006, the security check is executed, and as shown in FIG. 48B, the security check is not executed after step S1014). Even if the power supply to the gaming machine is stopped, the gaming control microcomputer stops. Occurs when performing game-related controls Storage means (for example, RAM 55 (backup RAM)) including at least a storage area (for example, a subtraction buffer or an initial value setting buffer) and a predetermined process (for example, a loop in the main process). Processing, timer interrupt processing) (for example, a part for executing steps S16 to S19 and S20 to S34 in the game control microcomputer 560) and a predetermined event during execution of the predetermined processing. Initialization means for initializing the stored contents of the storage means when it occurs (for example, in the game control microcomputer 560, during the execution of steps S16 to S19, S20 to S34, the IAT signal from the IAT circuit 506a and the watchdog timer (WDT) When a time-out signal is input from 506b 52 and FIG. 53, without executing the power-off process shown in FIG. 52 and FIG. 53, a part that executes steps S <b> 10 to S <b> 13 when the main process is started after resetting.
With such a configuration, it is possible to perform abnormality determination of the sorting device, so that it is possible to prevent the game from being performed normally due to the abnormality of the sorting device.

(Means 3) In the means 1 or 2, the high-frequency state control means (for example, the game control microcomputer 560) controls the start area to the high-frequency state (for example, the high base state) that allows the game medium to easily pass through the start area. And the abnormality determining means does not determine that there is an abnormality when the high frequency state is controlled (for example, the game control microcomputer 560 executes steps S257 and S258). (Part)).
According to such a configuration, it is possible to prevent wasteful use of unnecessary abnormality determination.

(Means 4) In any one of the means 1 to 3, a predetermined variable display means is provided for performing variable display of identification information based on the start condition being satisfied after the game medium has passed through the start area. When a specific display result (for example, jackpot symbol) is derived and displayed, the gaming machine controls to a specific gaming state (for example, jackpot gaming state) that is advantageous to the player, and the game medium has passed through the starting area. Hold storage means (for example, a first hold storage buffer and a second hold storage buffer) for storing up to a predetermined number (for example, an upper limit of 4) as hold storage when the start condition is not satisfied, and hold stored in the hold storage means Whether or not the display result of variable display of identification information based on storage is a specific display result, rather than deriving and displaying the display result of variable display of identification information based on the reserved storage Specific determination means (for example, the portion where the game control microcomputer 560 executes S2061A and S2061B) and the display result of the variable display that is the determination target of the specific determination means based on the determination of the specific determination means A specific effect executing means capable of executing a specific effect for notifying that a specific display result will be obtained (for example, the part where the effect control microcomputer 100 executes S631, S801, and S802) and the game medium pass through the start area. High-frequency state control means (for example, the part in which the game control microcomputer 560 executes step S166 to control to the high-base state) that controls the high-frequency state easily, and the specific effect execution means is in the high-frequency state. When it is not controlled, the first specific effect can be executed over a predetermined number of variable displays. The second specific effect can be executed over a variable number of variable displays less than a predetermined number of times (for example, the part in which the effect control microcomputer 100 executes S631; see FIG. 72). May be.
According to such a structure, the specific effect according to the gaming state can be executed.

It is the front view which looked at the pachinko game machine from the front. It is explanatory drawing for demonstrating a distribution apparatus. It is explanatory drawing for demonstrating the form in which a game ball wins a 2nd start winning opening when the variable winning ball apparatus is controlled by the open state. It is a block diagram which shows the circuit structural example of a game control board (main board). It is a block diagram showing an example of circuit configuration of an effect control board, a lamp driver board and an audio output board. It is a block diagram which shows the structural example of the microcomputer for game control. It is a figure which shows an example of the address map in the microcomputer for game control. It is a figure which illustrates the main part of a program management area. It is a figure which illustrates the principal part of a built-in register. It is a figure which illustrates the principal part of a built-in register. It is a figure which illustrates the principal part of a built-in register. It is a figure which illustrates the correspondence of the setting data and operation | movement in a header (KHDR). It is a figure which shows an example of the setting content in a program code end address (KPCE), a program code start address 2 (KPCS2), and a program code end address 2 (KPCE2). It is a figure which shows an example of the setting content in reset setting (KRES). It is a figure which shows an example of the setting content in 16 bit random number initial setting 1 (KRL1). It is a figure which shows an example of the setting content in 16 bit random number initial setting 2 (KRL2). It is a figure which shows an example of the setting content in 16 bit random number initial setting 3 (KRL3). It is a figure which shows an example of the setting content in 8-bit random number initial setting 1 (KRS1). It is a figure which shows an example of the setting content in 8-bit random number initial setting 2 (KRS2). It is a figure which shows an example of the setting content in security time setting (KSES). It is a figure which shows an example of the setting content in random number clock monitoring setting (KRCS). It is a figure which shows the structural example etc. of an internal information register. It is a block diagram which shows the example of 1 structure of an 8-bit random number circuit. It is a block diagram which shows one structural example of a 16-bit random number circuit. It is explanatory drawing which shows an example of a structure example and setting content of RL0 hard latch selection register 0 (RL0LS0). It is explanatory drawing which shows an example of a structure example and setting content of RL0 hard latch selection register 1 (RL0LS1). It is explanatory drawing which shows an example of a structure of a RLn hard latch selection register (RLnLS), and an example of a setting content. It is explanatory drawing which shows an example of a structure example and setting content of RS hard latch selection register 0 (RSLS0). It is explanatory drawing which shows an example of a structure example and setting content of RS hard latch selection register 1 (RSLS1). It is explanatory drawing which shows an example of a structure of RL interruption control register 0 (RLIC0), and an example of the setting content. It is explanatory drawing which shows an example of a structure example and setting content of RL interrupt control register 1 (RLIC1). It is explanatory drawing which shows an example of a structure of a RS interruption control register (RSIC), and an example of setting content. It is explanatory drawing which shows an example of a structure of a RLn maximum value setting register (RLnMX), and an example of the setting content. It is explanatory drawing which shows an example of a structure example of RSn maximum value setting register (RSnMX), and a setting content. It is explanatory drawing which shows an example of a structure example and setting content of a random number sequence change register (RDSC). It is explanatory drawing which shows an example of a structure example and setting content of a random number soft latch register (RDSL). It is explanatory drawing which shows an example of a structure of a random number soft latch flag register (RDSF), and an example of the setting content. It is explanatory drawing which shows an example of a structure of a RLn soft latch random number value register (RLnSV), and an example of setting content. It is explanatory drawing which shows an example of a structure example of RSn soft latch random number value register (RSnSV), and a setting content. It is explanatory drawing which shows an example of a structure of RL hard latch flag register 0 (RLHF0), and an example of the setting content. It is explanatory drawing which shows an example of a structure example and setting content of RL hard latch flag register 1 (RLHF1). It is explanatory drawing which shows an example of a structure example and setting content of RS hard latch flag register (RSHF). It is explanatory drawing which shows an example of a structure of a RL0 hard latch random number value register m (RL0mHV), and an example of setting content. It is explanatory drawing which shows an example of a structure example of RL1 hard latch random number value register m (RL1mHV), and a setting content. It is explanatory drawing which shows an example of a structure of a RL2 hard latch random number value register m (RL2mHV), and an example of setting content. It is explanatory drawing which shows an example of a structure of a RL3 hard latch random number value register m (RL3mHV), and an example of the setting content. It is explanatory drawing which shows an example of a structure example of RSn hard latch random number value register (RSnHV), and a setting content. It is explanatory drawing for demonstrating the difference in the reset operation by the setting content by reset setting (KRES). It is explanatory drawing which shows the example of how to read the data stored in the internal RAM area. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows a 4 ms timer interruption process. It is a flowchart which shows an example of a power-off process. It is a flowchart which shows an example of a power-off process. It is explanatory drawing which shows each random number. It is explanatory drawing which shows a big hit determination table, a small hit determination table, and a big hit type determination table. It is a flowchart which shows an example of the program of a special symbol process process. It is a flowchart which shows an example of the program of a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is explanatory drawing which shows the structural example of a pending | holding storage buffer. It is a flowchart which shows a special symbol stop process. It is a flowchart which shows a big hit end process. It is a flowchart which shows a normal symbol process process. It is a flowchart which shows a prize order abnormality notification process. It is a flowchart which shows the presentation control main process which CPU for presentation control performs. It is explanatory drawing which shows the structural example of a command reception buffer. It is a flowchart which shows command analysis processing. It is a flowchart which shows production control process processing. It is a flowchart which shows the modification of a winning order abnormality alert | report process. It is a flowchart which shows the modification of the main process which CPU in the main board performs. It is a flowchart which shows the modification of a start port switch passage process. It is a flowchart which shows the modification of command analysis processing. It is explanatory drawing which shows the production | presentation aspect of prefetching production.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, the overall configuration of a pachinko gaming machine 1 that is an example of a gaming machine will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as seen from the front.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) that can be opened and closed with respect to the outer frame, a mechanism plate (not shown) to which mechanism parts and the like are attached, and various parts (games to be described later) attached to them. A structure including the board 6).

  On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, there are provided a surplus ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3, and a hitting operation handle (operation knob) 5 for firing the hitting ball. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. In addition, a game area 7 is formed on the front surface of the game board 6 in which a game ball that has been struck can flow down.

  The member that forms the extra ball tray (lower tray) 4 is configured in a stick shape (bar shape), for example, at a predetermined position on the front side of the upper surface of the lower tray main body (for example, the central portion of the lower tray). Is attached to the stick controller 122 that can be tilted in a plurality of directions (front and rear, left and right). It should be noted that the stick controller 122 has a predetermined operation, for example, by performing a push-pull operation with a predetermined operation finger (for example, an index finger) while the player holds the operation rod of the stick controller 122 with an operation hand (for example, the left hand). A trigger button 121 (see FIG. 5) capable of performing an instruction operation is provided, and a trigger sensor 125 (see FIG. 5) for detecting a predetermined instruction operation by a push-pull operation or the like on the trigger button 121 is provided inside the operation rod of the stick controller 122. 5) is built-in. Further, a tilt direction sensor unit 123 (see FIG. 5) for detecting a tilting operation with respect to the operating rod is provided in the lower pan body inside the stick controller 122 and the like. Further, the stick controller 122 incorporates a vibrator motor 126 (see FIG. 5) for causing the stick controller 122 to vibrate.

  The member that forms the hitting ball supply tray (upper plate) 3 is subjected to a predetermined instruction operation, for example, by a player pressing a predetermined position on the upper surface of the upper plate body (for example, above the stick controller 122). A possible push button 120 is provided. The push button 120 only needs to be configured to be able to detect a predetermined instruction operation such as a pressing operation from a player mechanically, electrically, or electromagnetically. A push sensor 124 (see FIG. 5) that detects the player's operation action performed on the push button 120 may be provided inside the main body of the upper plate at the position where the push button 120 is installed. In the configuration example shown in FIG. 1, the mounting positions of the push button 120 and the stick controller 122 are in a vertical positional relationship in the central portion of the upper plate and the lower plate. On the other hand, it is good also considering the attachment position of the push button 120 and the stick controller 122 as the position approached to either right or left in the upper plate and the lower plate, maintaining the vertical relationship. Alternatively, the mounting position of the push button 120 and the stick controller 122 is not in the vertical relationship, but may be in the horizontal relationship, for example.

  An effect display device 9 composed of a liquid crystal display device (LCD) is provided near the center of the game area 7. The display screen of the effect display device 9 includes an effect symbol display area for performing variable display of the effect symbol in synchronization with the variable display of the first special symbol or the second special symbol. Therefore, the effect display device 9 corresponds to a variable display device that performs variable display of effect symbols. The effect symbol display area includes a symbol display area for variably displaying, for example, three decorative (effect) effect symbols of “left”, “middle”, and “right”. The symbol display area includes “left”, “middle”, and “right” symbol display areas, but the position of the symbol display area does not have to be fixed on the display screen of the effect display device 9. Three areas of the display area may be separated. The effect display device 9 is controlled by an effect control microcomputer mounted on the effect control board. When the first special symbol display 8a is executing variable display of the first special symbol, the effect control microcomputer causes the effect display device 9 to execute the effect display along with the variable display, and the second special symbol display 8a executes the second special display. When the variable display of the second special symbol is executed on the symbol display 8b, the effect display is executed by the effect display device 9 along with the variable display, so that the progress of the game can be easily grasped. .

  Further, in the effect display device 9, symbols other than the symbol that will be the final stop symbol (for example, the middle symbol of the left and right middle symbols) have continued for a predetermined time, and the jackpot symbol (for example, the left middle right symbol is aligned with the same symbol) Stops, swings, scales, or deforms in a state that matches the symbol combination), or multiple symbols fluctuate synchronously in the same symbol, or the position of the display symbol is switched Thus, an effect performed in a state where the possibility of occurrence of a big hit (hereinafter, these states are referred to as reach states) before the final result is displayed is referred to as reach effect. Further, the reach state and its state are referred to as a reach mode. Furthermore, variable display including reach production is called reach variable display. And when the display result of the symbol variably displayed on the effect display device 9 is not a big hit symbol, it becomes “out” and the variation display state ends. A player plays a game while enjoying how to generate a big hit.

  In the upper right part of the display screen of the effect display device 9, there are provided fourth symbol display areas 9c and 9d for displaying a fourth symbol after the effect symbol, a special symbol described later, and a normal symbol. In this embodiment, a fourth symbol display area 9c for the first special symbol in which the variation display of the fourth symbol for the first special symbol is performed in synchronization with the variation display of the first special symbol described later, There is provided a fourth symbol display area 9d for the second special symbol in which the variation display of the fourth symbol for the second special symbol is performed in synchronization with the variation display of the special symbol.

  In this embodiment, the variation display of the effect symbol is executed in synchronization with the variation display of the special symbol (however, to be precise, the variation display of the effect symbol is varied on the effect control microcomputer 100 side). This is done by measuring the variation time recognized based on the pattern command.) When performing an effect using the effect display device 9, for example, the effect content including the change display of the effect symbol disappears from the screen for a moment. There are diversifying effects such as effects being performed and effects such that the movable object shields all or part of the screen. For this reason, even if the display screen on the effect display device 9 is viewed, it may be difficult to recognize whether or not the current variation display is in progress. Therefore, in this embodiment, whether or not the state of the present variation is being displayed by confirming the state of the fourth symbol by further displaying the variation of the fourth symbol on a part of the display screen of the effect display device 9. It is possible to reliably recognize whether or not. Note that the 4th symbol is always variably displayed with a constant operation, and is not disappeared from the screen or shielded by a shielding object, so that it can always be visually recognized.

  The 4th symbol for the first special symbol and the 4th symbol for the 2nd special symbol may be collectively referred to as the 4th symbol, and the 4th symbol display area 9c for the 1st special symbol and the 2nd special symbol The 4th symbol display area 9d for symbols may be collectively referred to as a 4th symbol display area.

  The variation (variable display) of the fourth symbol is realized by continuing the state where the fourth symbol display areas 9c and 9d are repeatedly turned on and off at a predetermined time interval in a predetermined display color (for example, blue). . The variable display of the first special symbol on the first special symbol display unit 8a is synchronized with the variable display of the fourth symbol for the first special symbol in the fourth symbol display area 9c for the first special symbol. The variable display of the second special symbol on the second special symbol display 8b is synchronized with the variable display of the fourth symbol for the second special symbol in the fourth symbol display area 9d for the second special symbol. Synchronous means that the variable display start time and end time are the same, and the variable display period is the same.

  When the big hit symbol is stopped and displayed on the first special symbol display 8a, the display color reminiscent of the big hit in the fourth symbol display area 9c for the first special symbol (a display color different from the loss. Sometimes it is displayed in blue, but it is displayed in red when it is a big hit, and when the big hit symbol is stopped on the second special symbol display 8b, the fourth symbol display area for the second special symbol is displayed. A display color reminiscent of a big hit at 9d (a display color different from an outlier. For example, it is displayed in blue when out of place, but red in a big hit.

  In this embodiment, the case where the 4th symbol display area is provided on a part of the display screen of the effect display device 9 is shown, but a light emitter such as a lamp or LED is used separately from the effect display device 9. Thus, the fourth symbol display area may be realized. In this case, for example, the variation (variable display) of the fourth symbol may be realized by continuing the state in which the two LEDs are alternately lit, and any of the two LEDs is stopped. Whether or not the jackpot symbol is stopped and displayed may be indicated depending on whether or not it is displayed.

  On the right side of the effect display device 9, a first special symbol display (first variable display unit) 8a for variably displaying the first special symbol as identification information is provided. In this embodiment, the first special symbol display 8a is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. In other words, the first special symbol display 8a is configured to variably display numbers (or symbols) from 0 to 9. Further, on the right side of the effect display device 9 (next to the right of the first special symbol display 8a), a second special symbol display (second variable display unit) 8b for variably displaying the second special symbol as identification information. Is also provided. The second special symbol display 8b is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. That is, the second special symbol display 8b is configured to variably display numbers (or symbols) from 0 to 9.

  The small display is formed in a square shape, for example. In this embodiment, the type of the first special symbol and the type of the second special symbol are the same (for example, both 0 to 9), but the types may be different. Further, the first special symbol display 8a and the second special symbol display 8b may be configured to variably display numbers (or two-digit symbols) of, for example, 00 to 99, for example.

  Hereinafter, the first special symbol and the second special symbol may be collectively referred to as a special symbol, and the first special symbol indicator 8a and the second special symbol indicator 8b are collectively referred to as a special symbol indicator (variable display unit). There are things to do.

  Although this embodiment shows a case where two special symbol indicators 8a and 8b are provided, the gaming machine may be provided with only one special symbol indicator.

  The variable display of the first special symbol is after the first start condition, which is the variable display execution condition, is satisfied (in this embodiment, the technical ball passes through the first start winning opening 13 (including winning)). The variable display start condition (for example, when the first reserved memory number is not 0, the variable display of the first special symbol and the second special symbol is not executed, and the big hit game is executed) The display result (stop symbol) is derived and displayed when the variable display time (fluctuation time) elapses. In addition, the variable display of the second special symbol satisfies the second start condition, which is the variable display execution condition (in this embodiment, the game ball has passed through the second start winning opening 14 (including winning)). After that, the variable display start condition (for example, when the second reserved memory number is not 0, the variable display of the first special symbol and the second special symbol is not executed, and the big hit game is When the variable display time (fluctuation time) elapses, the display result (stop symbol) is derived and displayed. Note that the passing of a game ball means that the game ball has passed through a predetermined area such as a prize opening or a gate, and that includes a game ball entering (winning) a prize opening. It is. Deriving and displaying the display result is to finally stop and display a symbol (an example of identification information).

  Below the effect display device 9, there is provided a distribution device 200 for distributing the inflowing game balls. Further, below the effect display device 9, a first start winning opening 13 and a second starting winning opening 14 are provided so as to be arranged side by side. The game ball won in the first start winning opening 13 is guided to the back of the game board 6 and detected by the first start opening switch 13a. Also, the game ball that has won the second start winning opening (second start opening) 14 is guided to the back of the game board 6 and detected by the second start opening switch 14a.

  The second start winning opening 14 is provided with a variable winning ball apparatus 15 that can be changed between an open state and a closed release state. The variable winning ball device 15 is opened by a solenoid 16. When the variable winning ball device 15 is in the open state, it becomes easier for the game ball to start and win the second starting winning port 14, which is advantageous to the player. In this embodiment, even when the variable winning ball device 15 is in the closed and released state, the second start winning port 14 is won via the sorting device 200 which is difficult to win compared to the open state. Although the case where it is configured so as to be possible is shown, it may be configured so that the start winning prize can be made at the second start winning opening 14 only when the variable winning ball apparatus 15 is in the open state.

  In this embodiment, as described later, when the gaming state is a probable change state (in this embodiment, it is controlled to a high probability state and also to a short time state (high base state)). The frequency at which the variable winning ball device 15 is opened is increased, and it becomes easier to start a winning at the second starting winning port 14. Therefore, in this embodiment, when the gaming state is controlled to be in a probable state, the player performs a launching operation so as to launch a game ball aiming at the right side of the gaming area 7 (so-called right-handed). Is more advantageous. When the gaming state is controlled to the probability changing state, for example, it is desirable to display on the effect display device 9 such as “Aim right”!

  Hereinafter, the first start winning opening 13 and the second start winning opening 14 may be collectively referred to as a start winning opening or a starting opening.

  In this embodiment, as shown in FIG. 1, the variable winning ball apparatus 15 that opens and closes only the second start winning opening 14 is provided. Any of the start winning ports 14 may be provided with a variable winning ball device that performs an opening / closing operation.

  In addition, even if the gaming state is a probability change state or a short time state (high base state), if the gaming machine has a specification that consistently aims at the left side of the gaming area 7 and launches a game ball, The variable winning ball device 15 may be provided only at the first start winning opening 13.

  Above the second special symbol display 8b, there is a second special symbol hold memory display 18b comprising four displays for displaying the number of effective winning balls that have entered the second start winning opening 14, that is, the second reserved memory number. Is provided. The second special symbol storage memory display 18b increases the number of indicators to be lit by 1 every time there is an effective start winning. Then, each time the variable display on the second special symbol display 8b is started, the number of indicators to be turned on is reduced by one.

  Further, above the second special symbol hold memory display 18b, the number of effective winning balls that have entered the first start winning opening 13, that is, the first hold memory number (the hold memory is also referred to as start memory or start prize memory). ) Is displayed, a first special symbol reservation storage display 18a is provided. The first special symbol storage memory indicator 18a increases the number of indicators to be lit by 1 each time there is an effective start winning. Then, each time the variable display on the first special symbol display 8a is started, the number of indicators to be turned on is reduced by one.

  In addition, at the lower part of the display screen of the effect display device 9, there is provided a total pending storage display unit 18c for displaying the total number (total number of pending pending storage) that is the sum of the first reserved memory count and the second reserved memory count. ing. As described above, in this embodiment, the total pending storage display unit 18c that displays the total number is provided, so that it is easy to grasp the total number of execution conditions that have not met the variable display start condition. can do. In this embodiment, in the total hold storage display unit 18c, the first hold storage and the second hold storage are displayed side by side in the order of winning in the first start winning opening 13 and the second starting winning opening 14, It is displayed in a manner capable of recognizing whether it is the first reserved memory or the second reserved memory (for example, the first reserved memory is displayed in red and the second reserved memory is displayed in blue). In addition, it replaces with the total pending | holding memory | storage display part 18c, and it may comprise so that the 1st pending | holding memory display part which displays the 1st pending | holding memory number and the 2nd pending memory display part which displays the 2nd pending memory number Good.

  The effect display device 9 is for decoration (for effects) during the variable display time of the first special symbol by the first special symbol display 8a and during the variable display time of the second special symbol by the second special symbol display 8b. A variable display of the effect symbol as the symbol is performed. The variable display of the first special symbol on the first special symbol display 8a and the variable display of the effect symbol on the effect display device 9 are synchronized. Further, the variable display of the second special symbol on the second special symbol display 8b and the variable display of the effect symbol on the effect display device 9 are synchronized. Further, when the jackpot symbol is stopped and displayed on the first special symbol display 8a and when the jackpot symbol is stopped and displayed on the second special symbol display 8b, the effect display device 9 reminds the jackpot The combination of is stopped and displayed.

  As shown in FIG. 1, a special variable winning ball apparatus 20 that forms a large winning opening is provided below the first starting winning opening 13 and the second starting winning opening 14. The special variable winning ball apparatus 20 includes an opening / closing plate, and when the specific display result (big hit symbol) is derived and displayed on the first special symbol display 8a, and the specific display result (big hit symbol) on the second special symbol display 8b. When the open / close plate is controlled to be open by the solenoid 21 in the specific game state (big hit game state) that occurs when the symbol is derived and displayed, the big winning opening serving as the winning area is opened. The game ball that has won the big winning opening is detected by the count switch 23.

  On the left side of the effect display device 9, a normal symbol display 10 for variably displaying normal symbols is provided. In this embodiment, the normal symbol display 10 is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. That is, the normal symbol display 10 is configured to variably display numbers (or symbols) from 0 to 9. Moreover, the small display is formed in, for example, a square shape. Note that the normal symbol display 10 may be configured to variably display a number (or a two-digit symbol) of, for example, 00 to 99. In addition, the normal symbol display 10 is not limited to a 7-segment LED or the like, for example, a display capable of lighting a predetermined symbol display (for example, a decoration lamp capable of alternately lighting and displaying “O” and “X”). It may be comprised.

  When the game ball passes through the gates 32 provided on the left and right sides of the game area 7 and is detected by the gate switch 32a, the variable display of the normal symbol display 10 is started. When the stop symbol on the normal symbol display 10 is a predetermined symbol (a winning symbol, for example, a symbol “7”), the variable winning ball apparatus 15 is opened for a predetermined number of times. That is, the state of the variable winning ball device 15 is a state that is advantageous from a disadvantageous state for the player when the normal symbol is a stop symbol (a state in which the game ball is likely to win the second start winning port 14). To change. In the vicinity of the normal symbol display 10, a normal symbol holding storage display 41 having a display unit with four LEDs for displaying the number of winning balls that have passed through the gate 32 is provided. Each time there is a game ball passing through the gate 32, that is, every time a game ball is detected by the gate switch 32a, the normal symbol storage memory display 41 increases the number of LEDs to be turned on by one. Each time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one. In addition, a probability variation state in which the probability of being determined to be a big hit compared to the normal state is high (a state in which the probability of being determined to be a big hit as a result of fluctuation display of special symbols is increased compared to the normal state). Then, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. In this embodiment, when controlled to the probable variation state, it is also controlled to a short time state (game state in which the special symbol variable display time is shortened) in which the symbol variation time is shortened.

  At the lower part of the game board 6, there is an out port 26 into which a hit ball (out ball) that has not won a prize is taken. In addition, four speakers 27 that utter sound effects and sounds as predetermined sound outputs are provided on the upper left and right and lower left and right outside the game area 7. On the outer periphery of the game area 7, a frame LED 28 provided on the front frame is provided.

  In the gaming machine, a ball striking device (not shown) that drives a driving motor in response to a player operating the batting operation handle 5 and uses the rotational force of the driving motor to launch a gaming ball to the gaming area 7. ) Is provided. A game ball launched from the ball striking device enters the game area 7 through a ball striking rail (not shown) formed in a circular shape so as to surround the game area 7, and then descends the game area 7. When the game ball enters the first start winning opening 13 and is detected by the first start opening switch 13a, if the variable display of the first special symbol can be started (for example, the variable display of the special symbol ends, 1), the variable display (variation) of the first special symbol is started on the first special symbol display 8a, and the variable display of the effect symbol is started on the effect display device 9. That is, the variable display of the first special symbol and the effect symbol corresponds to winning in the first start winning opening 13. If the variable display of the first special symbol cannot be started, the first reserved memory number is increased by 1 on the condition that the first reserved memory number has not reached the upper limit value.

  When the game ball enters the second start winning opening 14 and is detected by the second start opening switch 14a, if the variable display of the second special symbol can be started (for example, the special symbol variable display ends, 2), the second special symbol display 8b starts variable display (variation) of the second special symbol, and the effect display device 9 starts variable display of the effect symbol. That is, the variable display of the second special symbol and the effect symbol corresponds to winning in the second start winning opening 14. If the variable display of the second special symbol cannot be started, the second reserved memory number is increased by 1 on condition that the second reserved memory number has not reached the upper limit value.

  In this embodiment, when a big hit (15R probability change big hit, 7R probability change big hit, sudden probability change big hit) is made, the game state is shifted to a high probability state (probability change state), and the game ball is easy to start. Transition to the high base state, which is a gaming state controlled so that the variable display execution conditions in the special symbol indicators 8a and 8b and the effect display device 9 are easily established (in this embodiment, the time-short state ). In the case of the high base state, for example, the frequency at which the variable winning ball device 15 is in the open state is increased or the time in which the variable winning ball device 15 is in the open state is extended compared to the case in which the high base state is not. It becomes easier to win a start.

  Instead of extending the time for the variable winning ball apparatus 15 to be in the open state (also referred to as the open extended state), the normal symbol display unit 10 shifts to a normal symbol probability changing state in which the probability that the stop symbol in the normal symbol display unit 10 becomes a winning symbol is increased. Depending on the situation, the high base state may be entered. When the stop symbol on the normal symbol display 10 becomes a predetermined symbol (winning symbol), the variable winning ball apparatus 15 is opened for a predetermined number of times. In this case, by performing the transition control to the normal symbol probability changing state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the frequency at which the variable winning ball apparatus 15 is opened is increased. Therefore, if the normal symbol probability changing state is entered, the opening time and the number of opening times of the variable winning ball device 15 are increased, and a state where it is easy to start a winning (high base state) is achieved. That is, the opening time and the number of times of opening of the variable winning ball device 15 can be increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probabilistic symbol. It changes to an advantageous state (a state where it is easy to win a start). It should be noted that increasing the number of times of opening is a concept including changing from a closed release state to an open state.

  Moreover, you may transfer to a high base state by shifting to the normal symbol time short state where the fluctuation time (variable display period) of the normal symbol in the normal symbol display 10 is shortened. In the normal symbol short-time state, the variation time of the normal symbol is shortened, so that the frequency of starting the variation of the normal symbol increases, and as a result, the frequency of hitting the normal symbol increases. Therefore, when the frequency that the normal symbol is won increases, the frequency that the variable winning ball apparatus 15 is in the open state is increased, and the start winning state is easily set (high base state).

  In addition, the change time of special symbols and production symbols will be shortened by shifting to the short time state when the variation time (variable display period) of special symbols and production symbols is shortened. The frequency of being played (in other words, the digestion of the reserved memory becomes faster), and the situation where an invalid start prize is generated can be reduced. Therefore, an effective start winning is likely to occur, and as a result, the possibility of a big hit game being increased.

  Furthermore, by making transitions to all the states shown above (open extended state, normal symbol probability change state, normal symbol short time state, and special symbol short time state), it will be easier to win a start (shift to a high base state). May be. In addition, it is easier to win a start (high base) by shifting to any one of the above states (open extended state, normal symbol probability changing state, normal symbol short time state, and special symbol short time state). Transition to a state). In addition, it is easier to win a start by shifting to any one of the above states (open extended state, normal symbol probability changing state, normal symbol short time state, and special symbol short time state). You may make it move to a base state.

  Next, the distribution device 200 will be described. FIG. 2 is an explanatory diagram for explaining the sorting apparatus 200. As shown in FIG. 2, an inflow port 201 into which a game ball can flow is provided at the top of the sorting apparatus 200. In addition, a sorting member 202 is provided inside the sorting device 200 for sorting the game balls that have flowed into the sorting device 200 from the inlet 201 into either the left passage 203 or the right passage 204. Further, at the lower part of the sorting device 200, a left outlet 205 from which the game ball that has passed through the left passage 203 can flow out of the sorting device 200, and a game ball that has passed through the right passage 204 can flow out of the sorting device 200. And a right outlet 206 is provided.

  In the example shown in FIG. 2A, a state in which the right passage 204 in the sorting apparatus 200 is shielded by the sorting member 202 and a game ball can pass through the left passage 203 is shown. When the game ball flows into the sorting device 200 from the inlet 201 in the state shown in FIG. 2A, the gaming ball that flows in from the inlet 201 is left by the sorting member 200 as shown in FIG. It is distributed to the passage 203, passes through the left passage 203, and flows out from the left outlet 205. Since the first start winning opening 13 is positioned below the left outlet 205, the game ball that has flowed out of the left outlet 205 wins the first start winning opening 13.

  Further, when the game ball passes through the left passage 203, the game ball hits the blade portion 202a provided in the rotation shaft portion of the sorting member 202, and the blade portion 202a is pushed by the weight of the game ball, As shown in FIGS. 2 (a) and 2 (b), the sorting member 202 changes from a state of being tilted to the right side to a state of being tilted to the left side. With such a change, as shown in FIG. 2B, the left passage 203 in the sorting apparatus 200 is shielded by the sorting member 202, and the game ball can pass through the right passage 204.

  Next, in such a state, as shown in FIG. 2 (c), when the game ball flows into the sorting device 200 from the inflow port 201, it flows in from the inflow port 201 as shown in FIG. 2 (d). The game balls are distributed to the right passage 204 by the distribution member 200, pass through the right passage 204, and flow out from the right outlet 206. Since the second start winning opening 14 is located below the right outlet 206, the game ball that has flowed out of the right outlet 206 wins the second start winning opening 14.

  Further, when the game ball passes the right passage 204, the game ball hits the blade portion 202a provided in the rotation shaft portion of the sorting member 204, and the blade portion 202a is pushed by the weight of the game ball, As shown in FIGS. 2 (c) and 2 (d), the sorting member 202 changes from a state of falling to the left side to a state of falling to the right side. With such a change, as shown in FIG. 2D, the right passage 204 in the sorting apparatus 200 is shielded by the sorting member 202, and the game ball can pass through the left passage 203.

  By performing the operation shown in FIG. 2, in this embodiment, the game balls that have flowed into the sorting device 200 by the sorting member 202 are alternately distributed to the left passage 203 and the right passage 204, and the first start It is possible to win alternately at the winning opening 13 and the second start winning opening 14.

  On the other hand, in this embodiment, regardless of the state of the sorting member 202 of the sorting apparatus 200, the game ball wins the second start winning opening 14 even when the variable winning ball apparatus 15 is controlled to the open state. Is possible. FIG. 3 is an explanatory diagram for explaining a mode in which a game ball wins the second start winning opening 14 when the variable winning ball apparatus 15 is controlled to be in the open state. As shown in FIG. 3, the right passage 204 in the sorting apparatus 200 is shielded by the sorting member 202, and the game ball can pass through the left passage 203 (the right passage 204 cannot pass or is difficult to pass). Even if it is, if the variable winning ball device 15 is controlled to be in the open state, the game ball can enter from the right side of the sorting device 200 and win the second start winning port 14.

  In this embodiment, as shown in FIG. 3, the case where the blade components of the variable winning ball device 15 are provided on both the left and right sides of the second start winning port 14 is shown. When the player enters the second start winning opening 14 without going through the sorting device 200 when the player is in the open state, the game ball enters from the right side of the sorting device 200 and wins as shown in FIG. In most cases, the left wing component of the variable winning ball apparatus 15 may be omitted. However, if this is done, there may be a case where a game ball that has entered from the right side of the sorting apparatus 200 cannot pass through the second start winning opening 14, and therefore, from the right side of the sorting apparatus 200. The variable winning ball device 15 is open by providing a shielding portion (for example, a synthetic resin protrusion or nail) on the left side of the opening of the second start winning opening for stopping the momentum of the game ball that has entered. The second starting winning opening 14 may be configured such that a game ball wins a prize.

  Further, in this embodiment, as shown in FIGS. 2 and 3, the first passage winning opening 13 and the second starting winning opening 14 are provided below the distribution device 200, whereby the left passage The game balls distributed to 203 win the first start winning opening 13 at about 100%, and the game balls distributed to the right passage 204 win about the second start winning opening 14 at about 100%. The game balls distributed to the left passage 203 and the right passage 204 may be spilled out of the sorting device 200. Even if the game balls are distributed to the left passage 203 and the right passage 204, the first start winning opening 13 is not necessarily provided. Alternatively, the second start winning opening 14 may not be won. For example, in FIG. 2 and FIG. 3, the game ball is configured to fall directly below the left outlet 205 and the right outlet 206, but a bottom member is provided at the left outlet 205 and the right outlet 206 to provide a player. The game ball is configured to flow to the first start winning opening 13 and the second starting winning opening 14 after being guided to the far side as viewed from the side, and an opening is provided on the outer side surface of the left passage 203 and the right passage 204. Thus, a part of the game balls distributed to the left passage 203 and the right passage 204 may spill out of the sorting device 200 from the opening and do not win the first start winning opening 13 or the second starting winning opening 14. You may comprise.

  In this embodiment, the first start winning port 13 and the second start winning port 14 are provided outside the sorting apparatus 200 (specifically, as shown in FIGS. 2 and 3) Although the case where it is provided below the distribution device 200 is shown, the first start winning port 13 and the second start winning port 14 may be included in the distribution device 200.

  Moreover, in this embodiment, although the case where the two passages 203 and 204 were provided in the distribution apparatus 200 was shown, not only when it is two, but three or more passages may be provided. . In this case, for example, a configuration may be adopted in which a plurality of paths that can be awarded exist in either one or both of the first start winning opening 13 and the second starting winning opening 14.

  Moreover, in this embodiment, although the distribution member 202 of the distribution apparatus 200 showed the case where it switches to right and left physically with the dead weight of a game ball, for example, the solenoid and motor for driving the distribution member 202 are used. The distribution member 202 may be alternately switched by control from the game control microcomputer 560.

  On the contrary, in this embodiment, the variable winning ball device 15 provided in the second start winning port 14 is shown to open and close by driving and controlling the solenoid 16, but the variable winning ball is shown. A mechanism similar to the distribution member 202 is applied to the device 15 so as to perform an opening / closing operation by the weight of the game ball. For example, the variable winning ball device 15 is physically controlled without being controlled by the game control microcomputer 560. It may be configured to open and close. In this case, for example, a sensor (for example, an optical sensor) for detecting the open state of the variable winning ball device 15 is provided, and whether or not the variable winning ball device 15 is in an open state based on an input from the sensor. It may be determined.

  FIG. 4 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. FIG. 4 also shows a payout control board 37, an effect control board 80, and the like. On the main board 31, a game control microcomputer (corresponding to a game control means) 560 for controlling the pachinko gaming machine 1 according to a program, a control clock generation circuit 111, and a random number clock generation circuit 112 are mounted. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as a storage means used as a work memory, and a CPU 56 for performing a control operation in accordance with the program. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the CPU 56 and the RAM 55, and the ROM 54 may be external or built-in. The game control microcomputer 560 further includes random number circuits 508a and 508b that generate hardware random numbers (random numbers generated by the hardware circuit).

  Here, the control clock generation circuit 111 generates a control clock CCLK that becomes an oscillation signal of a predetermined frequency outside the game control microcomputer 560. The control clock CCLK generated by the control clock generation circuit 111 is supplied to the clock circuit 502 via, for example, a control external clock terminal of a game control microcomputer 560 as shown in FIG. The random number clock generation circuit 112 generates a random number clock RCLK that is an oscillation signal having a predetermined frequency different from the oscillation frequency of the control clock CCLK, outside the game control microcomputer 560. The random number clock RCLK generated by the random number clock generation circuit 112 is, for example, random number circuits 508a and 508b via a random number external clock terminal (RCK terminal) of a game control microcomputer 560 as shown in FIG. To be supplied. As an example, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 112 may be equal to or lower than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111. Alternatively, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 112 may be higher than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111.

  In this embodiment, the case where the dedicated random number clock RCLK is input from the random number clock generation circuit 112 to the random number circuits 508a and 508b is shown, but the present invention is not limited to such a mode. For example, instead of using a dedicated clock, the control clock CCLK from the control clock generation circuit 111 may be input to the random number circuits 508a and 508b inside the game control microcomputer 560. In this case, for example, a random number counter (random number generation circuits 525a and 525b described later) may be updated using a signal obtained by dividing the control clock CCLK. In this case, the random number clock generation circuit 112 may not be provided on the main board 31.

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power source created on the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data (a special symbol process flag or the like) corresponding to the game state, that is, the control state of the game control means, and data indicating the number of unpaid winning balls are stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like occurs. Further, data corresponding to the control state and data indicating the number of unpaid winning balls are defined as data indicating the progress state of the game. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31. However, as will be described later, when the gaming machine is powered on or a system reset occurs, the gaming control microcomputer 560 sets the internal reset operation and the random number circuits 508a and 508b according to the setting contents of the program management area. The register is set, and the setting operation is performed by the game control microcomputer 560 by hardware without using a program.

  Further, an input driver circuit 58 for supplying detection signals from the gate switch 32a, the first start port switch 13a, the second start port switch 14a and the count switch 23 to the game control microcomputer 560 is also mounted on the main board 31. The main board also includes an output circuit 59 for driving the solenoid 16 for opening and closing the variable winning ball device 15 and the solenoid 21 for opening and closing the special variable winning ball device 20 that forms a big winning opening in accordance with a command from the game control microcomputer 560. 31.

  In addition, the game control microcomputer 560 includes a first special symbol display 8a, a second special symbol display 8b that variably displays special symbols, a normal symbol display 10 that variably displays normal symbols, and a first special symbol hold memory. Display control of the display 18a, the second special symbol storage memory display 18b, and the normal symbol storage memory display 41 is performed.

  An information output circuit 64 that outputs information output signals such as jackpot information indicating the occurrence of a jackpot gaming state to an external device such as a hall computer via the terminal board 160 is also mounted on the main board 31.

  Between the main board 31 and the effect control board 80, for example, by performing serial communication only in a single direction from the main board 31 to the effect control board 80 via the relay board 77, various effect control commands are sent. Is transmitted. In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 instructs the effect contents from the game control microcomputer 560 via the relay board 77. An effect control command is received, and display control of the effect display device 9 for variably displaying effect symbols is performed.

  In addition, the effect control means mounted on the effect control board 80 controls the display of the decoration LED 25 provided on the game board and the frame LED 28 provided on the frame side via the lamp driver board 35. The sound output from the speaker 27 is controlled via the sound output board 70.

  FIG. 5 is a block diagram illustrating a circuit configuration example of the relay board 77, the effect control board 80, the lamp driver board 35, and the audio output board 70. In the example shown in FIG. 5, the lamp driver board 35 and the audio output board 70 are not equipped with a microcomputer, but may be equipped with a microcomputer. Further, without providing the lamp driver board 35 and the audio output board 70, only the effect control board 80 may be provided for effect control.

  The effect control board 80 includes an effect control CPU 101 and an effect control microcomputer 100 including a RAM for storing information related to effects such as effect symbol process flags. The RAM may be externally attached. In this embodiment, the RAM in the production control microcomputer 100 is not backed up. In the effect control board 80, the effect control CPU 101 operates in accordance with a program stored in a built-in or external ROM (not shown), and receives an effect control command via the relay board 77. Further, the effect control CPU 101 causes the VDP (video display processor) 109 to perform display control of the effect display device 9 based on the effect control command.

  In this embodiment, a VDP 109 that performs display control of the effect display device 9 in cooperation with the effect control microcomputer 100 is mounted on the effect control board 80. The VDP 109 has an address space independent of the production control microcomputer 100, and maps a VRAM therein. VRAM is a buffer memory for developing image data. Then, the VDP 109 outputs the image data in the VRAM to the effect display device 9 via the frame memory.

  The effect control CPU 101 outputs to the VDP 109 a command for reading out necessary data from a CGROM (not shown) in accordance with the received effect control command. The CGROM stores character image data and moving image data displayed on the effect display device 9, specifically, a person, characters, figures, symbols (including effect symbols), and background image data in advance. ROM. The VDP 109 reads image data from the CGROM in response to the instruction from the effect control CPU 101. The VDP 109 executes display control based on the read image data.

  In addition, the effect control CPU 101 inputs an operation detection signal as an information signal indicating that the player's operation action on the trigger button 121 of the stick controller 122 has been detected from the trigger sensor 125 via the input port 106. Further, the effect control CPU 101 inputs an operation detection signal as an information signal indicating that a player's operation action on the push button 120 has been detected from the push sensor 124 via the input port 106. In addition, the production control CPU 101 inputs an operation detection signal as an information signal indicating that the player's operation action with respect to the operation rod of the stick controller 122 has been detected from the tilt direction sensor unit 123 via the input port 106. . Further, the effect control CPU 101 outputs a drive signal to the vibrator motor 126 via the output port 105 to cause the stick controller 122 to vibrate.

  Further, the effect control CPU 101 outputs a signal for driving the LED to the lamp driver board 35 via the output port 105. Further, the production control CPU 101 outputs sound number data to the audio output board 70 via the output port 104.

  In the lamp driver board 35, a signal for driving the LED is input to the LED driver 352 via the input driver 351. The LED driver 352 supplies a current to a light emitter provided on the frame side such as the frame LED 28 based on a signal for driving the LED. Further, an electric current is supplied to the decoration LED 25 provided on the game board side.

  In the voice output board 70, the sound number data is input to the voice synthesis IC 703 via the input driver 702. The voice synthesizing IC 703 generates voice or sound effect according to the sound number data, and outputs it to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. The voice data ROM 704 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data showing the output form of the sound effect or sound in a time series in a predetermined period (for example, the changing period of the effect design).

FIG. 6 shows a configuration example of the game control microcomputer 560 mounted on the main board 31. The game control microcomputer 560 shown in FIG. 6 is, for example, a one-chip microcomputer, and includes an external bus interface 501, a clock circuit 502, a verification block 503, a specific information storage circuit 504, an arithmetic circuit 505, and a reset. / Interrupt controller 506, CPU (Central Processing Unit) 56, ROM (Read Only)
Memory) 54, RAM (Random Access Memory) 55, and free-run counter circuit 5
07, random number circuits 508a and 508b, a timer circuit 509, an interrupt controller 510, a parallel input port 511, a serial communication circuit 512, a parallel output port 513, and an address decoding circuit 514.

  The random number circuits installed in the game control microcomputer 560 include an 8-bit random number circuit 508a that generates an 8-bit random number and a 16-bit random number circuit 508b that generates a 16-bit random number. In the example shown in FIG. 6, an 8-bit random number circuit 508a and a 16-bit random number circuit 508b for generating a 16-bit random number are illustrated one by one. However, the game control microcomputer 560 includes an 8-bit random number circuit. 508a and 16-bit random number circuit 508b for generating 16-bit random numbers are mounted on each of four circuits (four channels). In this embodiment, the four channels of the 8-bit random number circuit 508a may be expressed as RS0 to RS3, respectively, and the four channels of the 16-bit random number circuit 508b may be expressed as RL0 to RL3, respectively.

  The reset / interrupt controller 506 also includes an out-of-designated area prohibition (IAT) circuit 506a and a watchdog timer (WDT) 506b. The IAT circuit 506a is a circuit that monitors whether the user program is correctly executed in the designated area, and has a function of outputting an IAT generation signal when it is detected that the user program is executed outside the designated area. The watchdog timer 506b has a function of generating a time-out signal for each set period.

  FIG. 7 shows an example of an address map in the game control microcomputer 560. As shown in FIG. 7, the area from address 0000H to address 2FFFH is allocated to the ROM 54 of the game control microcomputer 560 and includes a program code / data area (an area for storing user programs and data) and a program management area. It is out. FIG. 8 shows an example of the usage and contents of the main part of the program management area in the ROM 54. The area from address F000H to address F3FFH is allocated to the RAM 55 of the game control microcomputer 560. The area from address FE00H to address FEBFH is a built-in register area allocated to the built-in registers of the game control microcomputer 560. 9 to 11 show examples of uses and contents of main parts of the built-in register area. The area from the address FED0H to the address FEFDH is an XCS / XCSE decode area allocated to the address decode circuit 514.

  The program management area is a storage area for storing information necessary for the game control microcomputer 560 to perform various settings such as internal reset operation settings and random number circuits 508a and 508b when the system is reset. As shown in FIG. 8, the program management area includes a header (KHDR), a program code end address (KPCE), a program code start address 2 (KPCS2), a program code end address 2 (KPCE2), a reset setting (KRES), 16-bit random number initial setting 1 (KRL1), 16-bit random number initial setting 2 (KRL2), 16-bit random number initial setting 3 (KRL3), 8-bit random number initial setting 1 (KRS1), 8-bit random number initial setting 2 (KRS2), Security time setting (KSES), random number clock monitoring setting (KRCS), and the like are included. 9 to 11, the built-in register area includes an internal information register (CIF), various registers used in the random number circuits 508a and 508b, and the like.

  The header (KHDR) stored in the program management area indicates the setting of an 8-byte code string indicating the start of the program management area and the reading setting of internal data in the game control microcomputer 560. FIG. 12 illustrates the correspondence between the setting data and the operation in the header (KHDR). Here, in the game control microcomputer 560, a ROM read prevention function and a bus output mask function can be set. The ROM read prevention function is a function for permitting or prohibiting the read operation for the data stored in the ROM 54 included in the game control microcomputer 560. When the read prohibition is set, the data stored in the ROM 54 cannot be read. The bus output mask function is an address bus output, data bus output and control signal in the external bus interface 501 when an external device connected to the external bus interface 501 makes a read request for the internal data of the game control microcomputer 560. This function makes it impossible to read internal data from an external device by masking the output. As shown in FIG. 12, in accordance with the setting data set as an 8-byte code string indicating the start of the program management area, the operation combinations of the ROM read prevention function and the bus output mask function are set to be different. Of the setting data shown in FIG. 12, the setting data for which ROM reading is permitted and the bus output mask is valid is also referred to as bus output mask valid data. Further, the setting data (all “00H”) in which ROM reading is prohibited and the bus output mask is valid is also referred to as ROM reading prohibiting data. The setting data for which ROM reading is permitted and the bus output mask becomes invalid is also referred to as bus output mask invalid data.

  The program code end address (KPCE) stored in the program management area indicates the setting of the final address of the program code area that continues from 0000H of the user program. FIG. 13A shows an example of setting contents in the program code end address (KPCE).

  In this embodiment, two program code areas can be set in the program code / data area from address 0000H to address 2FBFH. Specifically, the first program code area can be set as an area from address 0000H to the address set by the program code end address (KPCE), and the second program code area is the program code start It can be set as an area from the address set by address 2 (KPCS2) to the address set by program code end address 2 (KPCE2). Hereinafter, the program code stored in the first program code area is also referred to as program code 1, and the program code stored in the second program code area is also referred to as program code 2.

  As shown in FIG. 13A, the lower address of the final address of the program code 1 is set in the address 2FD3H of the program code end address (KPCE). In addition, the upper address of the final address of the program code 1 is set in the address 2FD4H.

  Program code start address 2 (KPCS2) stored in the program management area indicates the setting of the start address of the second program code area when the user program is divided into two blocks. FIG. 13B shows an example of setting contents in the program code start address 2 (KPCS2).

  As shown in FIG. 13B, the lower address of the head address of the program code 2 is set in the address 2FD5H of the program code start address 2 (KPCS2). In addition, the upper address of the head address of the program code 2 is set in the address 2FD6H. If the program code area is not divided into two, 0000H may be set to address 2FD5H and address 2FD6H of program code start address 2 (KPCS2).

  The program code end address 2 (KPCE2) stored in the program management area indicates the setting of the final address of the second program code area when the user program is divided into two blocks. FIG. 13C shows an example of setting contents in the program code end address 2 (KPCE2).

  As shown in FIG. 13C, the lower address of the final address of the program code 2 is set in the address 2FD7H of the program code end address 2 (KPCE2). In addition, the upper address of the final address of the program code 2 is set in the address 2FD8H. If the program code area is not divided into two, 0000H may be set to address 2FD7H and address 2FD8H of program code end address 2 (KPCE2).

  The setting contents of the program code end address (KPCE), the program code start address 2 (KPCS2), and the program code end address 2 (KPCE2) shown in FIG. 13 are executed correctly in the designated area by the IAT circuit 506a. Referenced when monitoring whether or not. That is, the IAT circuit 506a designates from 0000H to the address indicated by the program code end address (KPCE) or from the address indicated by the program code start address 2 (KPCS2) to the address indicated by the program code end address 2 (KPCE2). It is determined whether or not the user program is being executed within the range, and an IAT signal is output based on the detection that the user program is being executed outside the specified range.

  The reset setting (KRES) stored in the program management area indicates an internal reset operation or operation permission / prohibition setting of the watchdog timer (WDT) 506b. FIG. 14 shows an example of setting contents in the reset setting (KRES).

  Bit [7] of reset setting (KRES) is reset internally when a time-out signal is input from watchdog timer (WDT) 506b or when an IAT occurs (when an IAT signal is input from IAT circuit 506a) It shows the setting of the operation when this occurs. In the example shown in FIG. 14, if the bit value in the reset setting (KRES) bit [7] is “0”, a user reset occurs when a timeout signal or an IAT signal is input. On the other hand, if the bit value in the reset setting (KRES) bit [7] is “1”, a system reset occurs when a time-out signal or an IAT signal is input.

  Bit [6] of the reset setting (KRES) indicates the setting of the activation method of the watchdog timer (WDT) 506b. In the example shown in FIG. 14, if the bit value in the reset setting (KRES) bit [6] is “0”, the watch automatically switches to the user mode when a reset occurs regardless of the user program. The dog timer (WDT) 506b is activated and time measurement is started. On the other hand, if the bit value in bit [6] of the reset setting (KRES) is “1”, the watchdog timer (WDT) 506b is activated by the software (user program) after the transition to the user mode. Measurement starts.

  Bit [5-4] of the reset setting (KRES) indicates the setting of the reference clock signal of the watchdog timer (WDT) 506b. In the example shown in FIG. 14, when “00” is set in the reset setting (KRES) bits [5-4], 215 × TSCLK is selected as the reference clock signal. Further, when “01” is set in the reset setting (KRES) bit [5-4], 219 × TSCLK is selected as the reference clock signal. When “10” is set in the reset setting (KRES) bit [5-4], 222 × TSCLK is selected as the reference clock signal. When “11” is set in the reset setting (KRES) bit [5-4], 225 × TSCLK is selected as the reference clock signal. SCLK represents the internal system clock of the game control microcomputer 560, and TSCLK represents 1 / SCLK.

  Bits [3-0] of the reset setting (KRES) indicate the setting of the timeout time of the watchdog timer (WDT) 506b. Specifically, the time-out period of the watchdog timer (WDT) 506b is set to the reference clock selected by the bit [5-4] of the reset setting (KRES) using the bits [3-0] of the reset setting (KRES). It is a value obtained by multiplying the set value. For example, when “1000” is set to the bit [3-0] of the reset setting (KRES) (that is, the value “8” is set), “00” is set to the bit [5-4] of the reset setting (KRES). When set, the timeout time is 215 × TSCLK × 8. When the reset setting (KRES) bit [5-4] is set to “01”, the timeout time is 219 × TSCLK × 8 and reset. If bit [5-4] of setting (KRES) is set to “10”, the timeout time is 222 × TSCLK × 8, and bit [5-4] of reset setting (KRES) is set to “11”. In this case, the timeout time is 225 × TSCLK × 8. In addition, when “1111” is set to the bit [3-0] of the reset setting (KRES) (that is, the value “15” is set), “00” is set to the bit [5-4] of the reset setting (KRES). When set, the timeout time is 215 × TSCLK × 15. When the reset setting (KRES) bit [5-4] is set to “01”, the timeout time is 219 × TSCLK × 15, which is reset. When bit [5-4] of setting (KRES) is set to “10”, the timeout time is 222 × TSCLK × 15, and bit [5-4] of reset setting (KRES) is set to “11”. In this case, the timeout time is 225 × TSCLK × 15. FIG. 14 also shows specific examples of timeout values when the internal system clock is 10.0 MHz and 12.0 MHz.

  When setting not to use the watchdog timer (WDT) 506b, as shown in FIG. 14, it is only necessary to set “0000” in bits [3-0] of the reset setting (KRES). However, even if the reset setting (KRES) bit [3-0] is set to “0000” and the watchdog timer (WDT) 506b is disabled, the reset setting (KRES) bit By setting the value of [7], it is possible to set whether to perform system reset or user reset.

  16-bit random number initial setting 1 (KRL1), 16-bit random number initial setting 2 (KRL2), and 16-bit random number initial setting 3 (KRL3) stored in the program management area indicate settings of the 16-bit random number circuit 508b. FIG. 15 shows an example of setting contents in 16-bit random number initial setting 1 (KRL1). FIG. 16 shows an example of setting contents in 16-bit random number initial setting 2 (KRL2). Further, FIG. 17 shows an example of setting contents in 16-bit random number initial setting 3 (KRL3).

  First, the setting contents in 16-bit random number initial setting 1 (KRL1) will be described with reference to FIG. Bit “7” of 16-bit random number initial setting 1 (KRL1) indicates the setting of the activation method of the 16-bit random number circuit 508b of channel 1 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 15, if the bit value in the bit “7” of the 16-bit random number initial setting 1 (KRL1) is “0”, the maximum random number is set by software (user program) after shifting to the user mode. As a result, the 16-bit random number circuit 508b of channel 1 is activated. On the other hand, if the bit value in the bit “7” of the 16-bit random number initial setting 1 (KRL1) is “1”, regardless of the user program, it is automatically based on the transition to the user mode when a reset occurs. Then, the 16-bit random number circuit 508b of channel 1 is activated.

  Bit “6” of 16-bit random number initial setting 1 (KRL1) indicates the setting of the update clock of the 16-bit random number circuit 508b of channel 1. In the example shown in FIG. 15, if the bit value of the bit “6” of the 16-bit random number initial setting 1 (KRL1) is “0”, the internal system clock of the game control microcomputer 560 is used as the update clock. On the other hand, if the bit value in the bit “6” of the 16-bit random number initial setting 1 (KRL1) is “1”, the external clock signal input from the outside of the game control microcomputer 560 is divided by two. The signal is used as an update clock.

  In this embodiment, the random number clock RCLK generated by the random number clock generation circuit 112 described above is input via the random number external clock terminal (RCK terminal), and the random number clock RCLK is divided by two. This signal is used as an update clock. The same applies to the 16-bit random number circuit 508b and the 8-bit random number circuit 508a of other channels.

  Bit “5-4” of 16-bit random number initial setting 1 (KRL1) indicates whether to change the random number sequence updated by the 16-bit random number circuit 508b of channel 1. In the example shown in FIG. 15, if the bit value in the bit “5-4” of the 16-bit random number initial setting 1 (KRL1) is “00”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 1 is not changed. . Further, if the bit value in the bit “5-4” of the 16-bit random number initial setting 1 (KRL1) is “01”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 1 is changed by software (user program). it can. If the bit value in the bit “5-4” of the 16-bit random number initial setting 1 (KRL1) is “10”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 1 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “5-4” of the 16-bit random number initial setting 1 (KRL1) is “11”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 1 is automatically set from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Bit “3” of 16-bit random number initial setting 1 (KRL1) indicates the setting of the activation method of the 16-bit random number circuit 508b of channel 0 among the 16-bit random number circuit 508b of 4 channels. In the example shown in FIG. 15, if the bit value in the bit “3” of the 16-bit random number initial setting 1 (KRL1) is “0”, the maximum random number is set by software (user program) after shifting to the user mode. Is activated, the channel 0 16-bit random number circuit 508b is activated. On the other hand, if the bit value in the bit “3” of the 16-bit random number initial setting 1 (KRL1) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 16-bit random number circuit 508b of channel 0 is activated.

  Bit “2” of 16-bit random number initial setting 1 (KRL1) indicates the setting of the update clock of the 16-bit random number circuit 508b of channel 0. In the example shown in FIG. 15, if the bit value in the bit “2” of the 16-bit random number initial setting 1 (KRL1) is “0”, the internal system clock of the game control microcomputer 560 is used as the update clock. On the other hand, if the bit value in the bit “2” of the 16-bit random number initial setting 1 (KRL1) is “1”, the external clock signal input from the outside of the game control microcomputer 560 is divided by two. The signal is used as an update clock.

  Bits “1-0” of 16-bit random number initial setting 1 (KRL1) indicate whether to change the random number sequence updated by the 16-bit random number circuit 508b of channel 0. In the example shown in FIG. 15, if the bit value of bit “1-0” of 16-bit random number initialization 1 (KRL1) is “00”, the random number sequence updated by the 16-bit random number circuit 508b of channel 0 is not changed. . Further, if the bit value in the bit “1-0” of the 16-bit random number initial setting 1 (KRL1) is “01”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 0 is changed by software (user program). it can. If the bit value in the bit “1-0” of the 16-bit random number initial setting 1 (KRL1) is “10”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 0 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “1-0” of the 16-bit random number initial setting 1 (KRL1) is “11”, the random number sequence updated by the channel 0 16-bit random number circuit 508b is automatically generated from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Next, setting contents in 16-bit random number initial setting 2 (KRL2) will be described with reference to FIG. Bit “7” of 16-bit random number initial setting 2 (KRL2) indicates the setting of the activation method of the 16-bit random number circuit 508b of channel 3 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 16, if the bit value of bit “7” of 16-bit random number initial setting 2 (KRL2) is “0”, the maximum random number value is set by software (user program) after shifting to the user mode. Is activated, the 16-bit random number circuit 508b of channel 3 is activated. On the other hand, if the bit value in bit “7” of 16-bit random number initial setting 2 (KRL2) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 16-bit random number circuit 508b of channel 3 is activated.

  Bit “6” of 16-bit random number initial setting 2 (KRL2) indicates the setting of the update clock of the 16-bit random number circuit 508b of channel 3. In the example shown in FIG. 16, if the bit value of bit “6” of 16-bit random number initialization 2 (KRL2) is “0”, the internal system clock of the game control microcomputer 560 is used as the update clock. On the other hand, if the bit value in the bit “6” of the 16-bit random number initial setting 2 (KRL2) is “1”, the external clock signal input from the outside of the game control microcomputer 560 is divided by two. The signal is used as an update clock.

  Bit “5-4” of 16-bit random number initial setting 2 (KRL2) indicates whether or not the random number sequence updated by the 16-bit random number circuit 508b of channel 3 is changed. In the example shown in FIG. 16, if the bit value in the bit “5-4” of the 16-bit random number initialization 2 (KRL2) is “00”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 3 is not changed. . If the bit value in the bit “5-4” of the 16-bit random number initial setting 2 (KRL2) is “01”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 3 is changed by software (user program). it can. If the bit value in the bit “5-4” of the 16-bit random number initialization 2 (KRL2) is “10”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 3 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “5-4” of the 16-bit random number initialization 2 (KRL2) is “11”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 3 is automatically set from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Bit “3” of 16-bit random number initial setting 2 (KRL2) indicates the setting of the activation method of the 16-bit random number circuit 508b of channel 2 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 16, if the bit value in the bit “3” of the 16-bit random number initial setting 2 (KRL2) is “0”, the maximum random number value is set by software (user program) after shifting to the user mode. Is activated, the 16-bit random number circuit 508b of channel 2 is activated. On the other hand, if the bit value in the bit “3” of the 16-bit random number initial setting 2 (KRL2) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 16-bit random number circuit 508b of channel 2 is activated.

  Bit “2” of 16-bit random number initial setting 2 (KRL2) indicates the setting of the update clock of the 16-bit random number circuit 508b of channel 2. In the example shown in FIG. 16, if the bit value in bit “2” of 16-bit random number initialization 2 (KRL2) is “0”, the internal system clock of the game control microcomputer 560 is used as the update clock. On the other hand, if the bit value in the bit “2” of the 16-bit random number initial setting 2 (KRL2) is “1”, the external clock signal input from the outside of the game control microcomputer 560 is divided by two. The signal is used as an update clock.

  Bits “1-0” of 16-bit random number initial setting 2 (KRL2) indicate whether to change the random number sequence updated by the 16-bit random number circuit 508b of channel 2. In the example shown in FIG. 16, if the bit value in bit “1-0” of 16-bit random number initialization 2 (KRL2) is “00”, the random number sequence updated by the 16-bit random number circuit 508b of channel 2 is not changed. . Also, if the bit value in bit “1-0” of 16-bit random number initialization 2 (KRL2) is “01”, the random number sequence updated by the 16-bit random number circuit 508b of channel 2 is changed by software (user program). it can. If the bit value in the bit “1-0” of the 16-bit random number initial setting 2 (KRL2) is “10”, the random number sequence updated by the 16-bit random number circuit 508b of the channel 2 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in bit “1-0” of 16-bit random number initialization 2 (KRL2) is “11”, the random number sequence updated by the 16-bit random number circuit 508b of channel 2 is automatically updated from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Next, setting contents in 16-bit random number initial setting 3 (KRL3) will be described with reference to FIG. Bit “7” of 16-bit random number initial setting 3 (KRL3) indicates the setting of the start value from the first round of the 16-bit random number circuit 508b of channel 3 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 17, if the bit value at bit “7” of 16-bit random number initial setting 3 (KRL3) is “0”, 0001H is used as the start value for the first round of random number update. On the other hand, if the bit value in the bit “7” of the 16-bit random number initial setting 3 (KRL3) is “1”, the ID number of the game control microcomputer 560 is used as the start value of the first round of random number update. The original value is used. Since the ID number of the game control microcomputer 560 is different for each chip, it is possible to make it difficult to predict the update timing of the random number by using a value based on the ID number as the start value. It is possible to prevent an act of illegally generating a big hit aiming at. Note that the ID number itself may be used as a value based on the ID number, or a predetermined calculation (for example, a value obtained by adding or subtracting a predetermined value) may be used for the ID number.

  Bit “6” of 16-bit random number initial setting 3 (KRL3) indicates whether or not the start value of the 16-bit random number circuit 508b of channel 3 is changed at every system reset. In the example shown in FIG. 17, if the bit value in bit “6” of 16-bit random number initial setting 3 (KRL3) is “0”, the start value is not changed at the time of system reset. On the other hand, if the bit value in bit “6” of 16-bit random number initial setting 3 (KRL3) is “1”, the start value is changed at every system reset.

  Bit “5” of 16-bit random number initial setting 3 (KRL3) indicates the setting of the start value from the first round of the 16-bit random number circuit 508b of channel 2 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 17, if the bit value at bit “5” of 16-bit random number initial setting 3 (KRL3) is “0”, 0001H is used as the start value for the first round of random number update. On the other hand, if the bit value in bit “5” of 16-bit random number initial setting 3 (KRL3) is “1”, the ID number of the game control microcomputer 560 is used as the start value of the first round of random number update. The original value is used.

  Bit “4” of 16-bit random number initial setting 3 (KRL3) indicates whether or not the start value of the 16-bit random number circuit 508b of channel 2 is changed at every system reset. In the example shown in FIG. 17, if the bit value in bit “4” of 16-bit random number initial setting 3 (KRL3) is “0”, the start value is not changed at the time of system reset. On the other hand, if the bit value in bit “6” of 16-bit random number initial setting 3 (KRL3) is “1”, the start value is changed at every system reset.

  Bit “3” of 16-bit random number initial setting 3 (KRL3) indicates the setting of the start value from the first round of the 16-bit random number circuit 508b of channel 1 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 17, if the bit value in the bit “3” of the 16-bit random number initial setting 3 (KRL3) is “0”, 0001H is used as the start value for the first round of random number update. On the other hand, if the bit value in the bit “3” of the 16-bit random number initial setting 3 (KRL3) is “1”, the ID number of the game control microcomputer 560 is used as the start value of the first round of random number update. The original value is used.

  Bit “2” of 16-bit random number initial setting 3 (KRL3) indicates whether or not the start value of the 16-bit random number circuit 508b of channel 1 is changed at every system reset. In the example shown in FIG. 17, if the bit value in bit “2” of 16-bit random number initial setting 3 (KRL3) is “0”, the start value is not changed when the system is reset. On the other hand, if the bit value in the bit “2” of the 16-bit random number initial setting 3 (KRL3) is “1”, the start value is changed at every system reset.

  Bit “1” of 16-bit random number initial setting 3 (KRL3) indicates the setting of the start value from the first round of the 16-bit random number circuit 508b of channel 0 out of the 4-bit 16-bit random number circuit 508b. In the example shown in FIG. 17, if the bit value at bit “1” of 16-bit random number initial setting 3 (KRL3) is “0”, 0001H is used as the start value for the first round of random number update. On the other hand, if the bit value in the bit “1” of the 16-bit random number initial setting 3 (KRL3) is “1”, the ID number of the game control microcomputer 560 is used as the start value of the first round of random number update. The original value is used.

  Bit “0” of 16-bit random number initial setting 3 (KRL3) indicates whether or not the start value of the 16-bit random number circuit 508b of channel 0 is changed at every system reset. In the example shown in FIG. 17, if the bit value at bit “0” of 16-bit random number initial setting 3 (KRL3) is “0”, the start value is not changed at the time of system reset. On the other hand, if the bit value at bit “0” of 16-bit random number initial setting 3 (KRL3) is “1”, the start value is changed at every system reset.

  The 8-bit random number initial setting 1 (KRS1) and the 8-bit random number initial setting 2 (KRS2) stored in the program management area indicate settings of the 8-bit random number circuit 508a. FIG. 18 shows an example of setting contents in the 8-bit random number initial setting 1 (KRS1). FIG. 19 shows an example of setting contents in the 8-bit random number initial setting 2 (KRS2).

  First, the setting contents in 8-bit random number initial setting 1 (KRS1) will be described with reference to FIG. Bit “7” of 8-bit random number initial setting 1 (KRS1) indicates the setting of the activation method of the 8-bit random number circuit 508a of channel 1 out of the 4-bit 8-bit random number circuit 508a. In the example shown in FIG. 18, if the bit value in the bit “7” of the 8-bit random number initial setting 1 (KRS1) is “0”, the maximum value of the random number is set by software (user program) after shifting to the user mode. As a result, the 8-bit random number circuit 508a of channel 1 is activated. On the other hand, if the bit value in the bit “7” of the 8-bit random number initial setting 1 (KRS1) is “1”, regardless of the user program, it is automatically based on the transition to the user mode when a reset occurs. Then, the 8-bit random number circuit 508a of channel 1 is activated.

  Bit “6” of 8-bit random number initial setting 1 (KRS1) indicates the setting of the update clock of the 8-bit random number circuit 508a of channel 1. In the example shown in FIG. 18, if the bit value of the bit “6” of the 8-bit random number initial setting 1 (KRS1) is “0”, the internal system clock of the game control microcomputer 560 is used as the update clock. On the other hand, if the bit value in the bit “6” of the 8-bit random number initial setting 1 (KRS1) is “1”, the external clock signal input from the outside of the game control microcomputer 560 is divided by two. The signal is used as an update clock.

  Bit “5-4” of 8-bit random number initial setting 1 (KRS1) indicates whether to change the random number sequence updated by the 8-bit random number circuit 508a of channel 1. In the example shown in FIG. 18, if the bit value in the bit “5-4” of the 8-bit random number initial setting 1 (KRS1) is “00”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 1 is not changed. . If the bit value in the bit “5-4” of the 8-bit random number initial setting 1 (KRS1) is “01”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 1 is changed by software (user program). it can. If the bit value in the bit “5-4” of the 8-bit random number initial setting 1 (KRS1) is “10”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 1 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “5-4” of the 8-bit random number initial setting 1 (KRS1) is “11”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 1 is automatically started from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Bit “3” of 8-bit random number initial setting 1 (KRS1) indicates the setting of the activation method of the 8-bit random number circuit 508a of channel 0 out of the 4-channel 8-bit random number circuit 508a. In the example shown in FIG. 18, if the bit value in the bit “3” of the 8-bit random number initial setting 1 (KRS1) is “0”, the maximum value of the random number is set by software (user program) after shifting to the user mode. As a result, the 8-bit random number circuit 508a of channel 0 is activated. On the other hand, if the bit value in the bit “3” of the 8-bit random number initial setting 1 (KRS1) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 8-bit random number circuit 508a of channel 0 is activated.

  Bit “2” of 8-bit random number initial setting 1 (KRS1) indicates the setting of the update clock of the 8-bit random number circuit 508a of channel 0. In the example shown in FIG. 18, if the bit value in the bit “2” of the 8-bit random number initial setting 1 (KRS1) is “0”, the internal system clock of the game control microcomputer 560 is used as the update clock. On the other hand, if the bit value in the bit “2” of the 8-bit random number initial setting 1 (KRS1) is “1”, the external clock signal input from the outside of the game control microcomputer 560 is divided by two. The signal is used as an update clock.

  Bits “1-0” of 8-bit random number initial setting 1 (KRS1) indicate whether to change the random number sequence updated by the 8-bit random number circuit 508a of channel 0. In the example shown in FIG. 18, if the bit value in the bit “1-0” of the 8-bit random number initial setting 1 (KRS1) is “00”, the random number sequence updated by the 8-bit random number circuit 508a of channel 0 is not changed. . If the bit value in bits “1-0” of the 8-bit random number initial setting 1 (KRS1) is “01”, the random number sequence updated by the 8-bit random number circuit 508a of channel 0 is changed by software (user program). it can. If the bit value in the bit “1-0” of the 8-bit random number initial setting 1 (KRS1) is “10”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 0 is automatically started from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “1-0” of the 8-bit random number initial setting 1 (KRS1) is “11”, the random number sequence updated by the 8-bit random number circuit 508a of channel 0 is automatically started from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Next, setting contents in the 8-bit random number initial setting 2 (KRS2) will be described with reference to FIG. Bit “7” of the 8-bit random number initial setting 2 (KRS2) indicates the setting of the activation method of the 8-bit random number circuit 508a of channel 3 out of the 4-bit 8-bit random number circuit 508a. In the example shown in FIG. 19, if the bit value in the bit “7” of the 8-bit random number initial setting 2 (KRS2) is “0”, the maximum value of the random number is set by software (user program) after shifting to the user mode. Is activated, the 8-bit random number circuit 508a of channel 3 is activated. On the other hand, if the bit value in bit “7” of the 8-bit random number initial setting 2 (KRS2) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 8-bit random number circuit 508a of channel 3 is activated.

  Bit “6” of the 8-bit random number initial setting 2 (KRS2) indicates the setting of the update clock of the 8-bit random number circuit 508a of the channel 3. In the example shown in FIG. 19, if the bit value of the bit “6” of the 8-bit random number initial setting 2 (KRS2) is “0”, the internal system clock of the game control microcomputer 560 is used as the update clock. On the other hand, if the bit value in the bit “6” of the 8-bit random number initial setting 2 (KRS2) is “1”, the external clock signal input from the outside of the game control microcomputer 560 is divided by two. The signal is used as an update clock.

  Bit “5-4” of 8-bit random number initial setting 2 (KRS2) indicates whether to change the random number sequence updated by 8-bit random number circuit 508a of channel 3. In the example shown in FIG. 19, if the bit value in the bit “5-4” of the 8-bit random number initial setting 2 (KRS2) is “00”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 3 is not changed. . If the bit value in the bit “5-4” of the 8-bit random number initial setting 2 (KRS2) is “01”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 3 is changed by software (user program). it can. If the bit value in the bit “5-4” of the 8-bit random number initial setting 2 (KRS2) is “10”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 3 is automatically updated from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “5-4” of the 8-bit random number initial setting 2 (KRS2) is “11”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 3 is automatically updated from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Bit “3” of the 8-bit random number initial setting 2 (KRS2) indicates the setting of the activation method of the 8-bit random number circuit 508a of channel 2 out of the 4-bit 8-bit random number circuit 508a. In the example shown in FIG. 19, if the bit value in the bit “3” of the 8-bit random number initial setting 2 (KRS2) is “0”, the maximum value of the random number is set by software (user program) after shifting to the user mode. Is activated, the channel 2 8-bit random number circuit 508a is activated. On the other hand, if the bit value in bit “3” of 8-bit random number initial setting 2 (KRS2) is “1”, it is automatically based on the transition to the user mode when a reset occurs regardless of the user program. Then, the 8-bit random number circuit 508a of channel 2 is activated.

  Bit “2” of 8-bit random number initial setting 2 (KRS2) indicates the setting of the update clock of the 8-bit random number circuit 508a of channel 2. In the example shown in FIG. 19, if the bit value in the bit “2” of the 8-bit random number initial setting 2 (KRS2) is “0”, the internal system clock of the game control microcomputer 560 is used as the update clock. On the other hand, if the bit value in the bit “2” of the 8-bit random number initial setting 2 (KRS2) is “1”, the external clock signal input from the outside of the game control microcomputer 560 is divided by two. The signal is used as an update clock.

  Bits “1-0” of 8-bit random number initial setting 2 (KRS2) indicate whether to change the random number sequence updated by the 8-bit random number circuit 508a of channel 2. In the example shown in FIG. 19, if the bit value in the bit “1-0” of the 8-bit random number initial setting 2 (KRS2) is “00”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 2 is not changed. . If the bit value in the bit “1-0” of the 8-bit random number initial setting 2 (KRS2) is “01”, the random number sequence updated by the 8-bit random number circuit 508a of the channel 2 is changed by software (user program). it can. If the bit value in the bit “1-0” of the 8-bit random number initial setting 2 (KRS2) is “10”, the random number sequence updated by the 8-bit random number circuit 508a of channel 2 is automatically updated from the second round. After that, the random number sequence is automatically changed every time the random number sequence is completed. If the bit value in the bit “1-0” of the 8-bit random number initial setting 2 (KRS2) is “11”, the random number sequence updated by the 8-bit random number circuit 508a of channel 2 is automatically updated from the first round. After that, the random number sequence is automatically changed every time the random number sequence is completed.

  Note that the 8-bit random number circuit 508a is different from the 16-bit random number circuit 508b in that it does not have a function for setting a start value as shown in FIG.

  The security time setting (KSES) stored in the program management area indicates a time setting for extending the security mode. FIG. 20 shows an example of setting contents in the security time setting (KSES).

  Bit [7-6] of the security time setting (KSES) indicates the setting of the time for extending the security mode time at random. In the example shown in FIG. 20, when “01” is set in the bit [7-6] of the security time setting (KSES), the short mode is set as a mode for extending the security mode time at random. Specifically, when the internal system clock is 10.0 MHz, the time in the range of 0 to 0.816 ms is randomly extended, and when the internal system clock is 12.0 MHz, the range of 0 to 0.51 ms. The time is extended randomly. In addition, when “10” is set in the bit [7-6] of the security time setting (KSES), the middle mode is set as a mode for randomly extending the security mode time. When the system clock is 10.0 MHz, the time in the range of 0 to 26.112 ms is randomly extended, and when the internal system clock is 12.0 MHz, the time in the range of 0 to 16.32 ms is randomly selected. Extended. Further, when “11” is set in the bit [7-6] of the security time setting (KSES), the long mode is set as a mode for randomly extending the security mode time. When the system clock is 10.0 MHz, the time in the range of 0 to 855.584 ms is randomly extended, and when the internal system clock is 12.0 MHz, the time in the range of 0 to 522.24 ms is randomly selected. Extended.

  When setting so as not to perform random extension of the security mode time, as shown in FIG. 20, it is sufficient to set “00” in bits [7-6] of the security time setting (KSES).

  Bit [5] of the security time setting (KSES) indicates the setting of the reference clock signal for the time for fixing and extending the security mode time. In the example shown in FIG. 20, when “0” is set in the bit [5] of the security time setting (KSES), 222 × TSCLK is selected as the reference clock signal. When “1” is set in bit [5] of the security time setting (KSES), 224 × TSCLK is selected as the reference clock signal.

  Bits [4-0] of the security time setting (KSES) indicate a time setting for extending the security mode time in a fixed manner. Specifically, the fixed extension time of the security mode time is the set value set by the bit [4-0] of the security time setting (KSES) to the reference clock selected by the bit [5] of the security time setting (KSES). Is the value multiplied by. For example, when “00001” is set to the bit [4-0] of the security time setting (KSES) (that is, the value “1” is set), “0” is set to the bit [5] of the security time setting (KSES). When set, the fixed extension time is 222 × TSCLK × 1, and when “1” is set to bit [5] of the security time setting (KSES), the fixed extension time is 224 × TSCLK × 1. . Also, when “01000” is set in the bit [4-0] of the security time setting (KSES) (that is, the value “8” is set), “0” is set in the bit [5] of the security time setting (KSES). When set, the fixed extension time is 222 × TSCLK × 8, and when “1” is set to bit [5] of the security time setting (KSES), the fixed extension time is 224 × TSCLK × 8. . Also, when “10000” is set to the bit [4-0] of the security time setting (KSES) (that is, the value “16” is set), “0” is set to the bit [5] of the security time setting (KSES). When set, the fixed extension time is 222 × TSCLK × 16, and when “1” is set to bit [5] of the security time setting (KSES), the fixed extension time is 224 × TSCLK × 16. . Further, when “11111” is set to the bit [4-0] of the security time setting (KSES) (that is, the value “31” is set), “0” is set to the bit [5] of the security time setting (KSES). When set, the fixed extension time is 222 × TSCLK × 31, and when “1” is set to bit [5] of the security time setting (KSES), the fixed extension time is 224 × TSCLK × 31. . FIG. 20 also shows specific examples of fixed extension time values when the internal system clock is 10.0 MHz and 12.0 MHz.

  When setting so that the security mode time is not fixedly extended, “00000” may be set in bits [4-0] of the security time setting (KSES) as shown in FIG.

  As shown in FIG. 20, the security mode time is randomly extended by setting bit [7-6] of security time setting (KSES) and fixed extension by setting of bit [5-0] of security time setting (KSES). The extension can be set in two ways. And the addition time of the time set by these two types of methods becomes the extension time of the final security mode time.

  The random number clock monitoring setting (KRCS) stored in the program management area indicates the setting of the monitoring frequency of the external clock signal input from the random number external clock terminal (RCK terminal). FIG. 21 shows an example of setting contents in the random number clock monitoring setting (KRCS).

  Bit [7-2] of the random number clock monitoring setting (KRCS) is a fixed bit (that is, a bit that is not particularly used for setting), and all bits are always set to “0”.

  Bits [1-0] of the random number clock monitoring setting (KRCS) are input clocks when an external clock signal input from the random number external clock terminal (RCK terminal) is selected as a clock for updating the random number. The setting of the frequency used as the detection target of frequency anomalies is shown. In the example shown in FIG. 21, when “00” is set in bits [1-0] of the random number clock monitoring setting (KRCS), the monitoring frequency is set to less than the frequency of SCLK (internal system clock). When “01” is set in bits [1-0] of the random number clock monitoring setting (KRCS), the monitoring frequency is set to less than the frequency of SCLK (internal system clock) / 2. When “10” is set in bits [1-0] of the random number clock monitoring setting (KRCS), the monitoring frequency is set to less than the frequency of SCLK (internal system clock) / 22. When “11” is set in bits [1-0] of the random number clock monitoring setting (KRCS), the monitoring frequency is set to a frequency less than the frequency of SCLK (internal system clock) / 23.

  When an abnormality in the monitoring frequency of the external clock signal input from the random number external clock terminal (RCK terminal) is detected, “1” is set in bit 3 of the internal information register (CIF) described later.

  In this embodiment, the game control microcomputer 560 detects an abnormal operation (external clock frequency abnormality and update abnormality) of the 16-bit random number circuit 508b out of the 8-bit random number circuit 508a and the 16-bit random number circuit 508b. It has a function to do. Specifically, the game control microcomputer 560 sets the random number clock monitoring setting (KRCS) when the external clock signal input from the random number external clock terminal (RCK terminal) is selected as the random number update clock. Based on the set monitoring frequency, it is detected whether or not the frequency of the external clock signal has decreased, and when a decrease in the frequency of the external clock signal (external clock frequency error) is detected, an internal information register described later Set "1" to bit 3 of (CIF).

  In addition, the game control microcomputer 560 has a function of monitoring the update state of the random number of the 16-bit random number circuit 508b, and when an abnormality is detected in the update state (for example, the random number value is not updated with the same value, If the random number is counted up one by one and the random number is suddenly detected to have increased by 2 or more), the correspondence among bits 7 to 4 of the internal information register (CIF) Set the bit to be “1”.

  In this embodiment, a setting is made using the random number clock monitoring setting (KRCS) to set the monitoring frequency of the external clock signal to be monitored with respect to the detection of the abnormal operation of the 16-bit random number circuit 508b. Although illustrated, it may be configured to be able to set whether or not to detect external clock frequency abnormality itself, or to be able to set whether or not to detect update abnormality itself. In this case, it may be configured such that the setting of whether or not the external clock frequency abnormality detection itself is performed and the setting of whether or not the update abnormality detection itself is performed can be performed independently. May be configured to enable or disable all of them at once.

  In order to be able to set whether or not to detect external clock frequency abnormality itself or whether or not to detect update abnormality itself, for example, whether to start the random number circuit itself is set. If the random number circuit is set not to start, the external clock frequency abnormality detection and update abnormality detection cannot be performed effectively, so the external clock frequency abnormality detection and update abnormality detection are not performed. It can be said that. As described above, setting whether or not to detect the external clock frequency abnormality itself or whether or not to detect the update abnormality itself includes realizing whether or not to start the random number circuit itself. It is a concept.

  In this embodiment, a case where the dedicated random number clock RCLK is externally input to the random number circuits 508 a and 508 b from the random number clock generation circuit 112 is shown. For example, for control from the control clock generation circuit 111 Even when a clock other than the dedicated random number clock RCLK is externally input, such as when the clock CCLK is externally input, it is possible to detect an external clock frequency abnormality or update abnormality. Regarding detection of update abnormality of the random number circuit, other clocks such as a random number update using the dedicated random number clock RCLK from the random number clock generation circuit 112 and a control clock CCLK from the control clock generation circuit 111 are used. It may be configured so that it can be set only in either of the cases of random number updating by using.

  In this embodiment, the abnormality of the external clock frequency is detected, and the abnormality of the frequency of the internal system clock SCLK of the game control microcomputer 560 is not particularly detected. This is because of the following reason. . That is, when the internal system clock SCLK is used for updating the random number, the operation of the CPU 56 itself should have stopped in a situation where an abnormality has occurred in the internal system clock SCLK. However, there is no case where only the update of the random number is stopped, and there is no possibility that some problem will occur. On the other hand, when an external clock signal is used for the random number update, there is a possibility that only the update of the random number is stopped even though the CPU 56 is operating, which may cause an adverse effect. It is.

  The external bus interface 501 provided in the game control microcomputer 560 shown in FIG. 6 includes an interface function between the external bus and the internal bus of the chip constituting the game control microcomputer 560, an address bus, a data bus, and each control signal. A bus interface having a direction control function and the like. For example, the external bus interface 501 is connected to an external memory or an external input / output device externally attached to the game control microcomputer 560, and an address signal, a data signal, various control signals, etc. are connected to these external devices. As long as it transmits and receives.

  The clock circuit 502 included in the game control microcomputer 560 is a circuit that generates the internal system clock SCLK by, for example, dividing the oscillation signal input to the control external clock terminal EX by two. The generated internal system clock is output from the external output terminal (CLKO terminal) to the outside.

  The verification block 503 provided in the game control microcomputer 560 is connected to an external verification machine and has a function of performing chip verification.

  The unique information storage circuit 504 included in the game control microcomputer 560 is a circuit that stores a plurality of types of unique information that is internal information of the game control microcomputer 560, for example. As an example, the unique information storage circuit 504 stores three kinds of unique information such as a ROM code, a chip individual number, and an ID number. The ROM 54 code is a 4-byte numerical value generated from stored data in a predetermined area of the ROM 54, and four numerical values with different generation methods may be prepared. The chip individual number is a 4-byte number assigned when the game control microcomputer 560 is manufactured, and indicates a different value for each chip constituting the game control microcomputer 560. The ID number is an 8-byte number assigned when the game control microcomputer 560 is manufactured, and shows a different numerical value for each chip constituting the game control microcomputer 560. Here, the chip individual number may be read from the user program, while the ID number may be set so as not to be read from the user program. The unique information storage circuit 504 may be included in the ROM 54 by using a predetermined area of the ROM 54, for example. Alternatively, the unique information storage circuit 504 may be included in the CPU 56 by using, for example, a built-in register of the CPU 56.

  An arithmetic circuit 505 provided in the game control microcomputer 560 is a circuit that performs multiplication and division.

  The reset / interrupt controller 506 provided in the game control microcomputer 560 is for controlling various reset and interrupt requests generated inside or outside the game control microcomputer 560. The reset controlled by the reset / interrupt controller 506 includes a system reset and a user reset. The system reset is a reset that occurs when a low level signal is input to the external system reset terminal XSRST for a certain period. In this embodiment, the system reset is also performed when the watchdog timer (WDT) time-out signal is generated or when the travel outside the designated area is prohibited (IAT) due to the reset setting (KRES). May occur. The user reset is a reset that occurs due to a predetermined factor, such as a watchdog timer (WDT) time-out signal or a non-designated area travel prohibition (IAT).

  Interrupts controlled by the reset / interrupt controller 506 include a non-maskable interrupt NMI and a maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that is unconditionally accepted even when the CPU 56 is in an interrupt disabled state, and is an interrupt that is generated when a low level signal is input to the external non-maskable interrupt terminal XNMI (also used as the input port PI6) for a certain period. is there. The maskable interrupt INT is an interrupt that can permit / prohibit acceptance of an interrupt request by a setting instruction of the CPU 56, and multiple interrupts can be executed by setting priority. The cause of the maskable interrupt INT is that a low level signal is input to the external maskable interrupt terminal XINT (also used as the input port PI5) for a certain period, a time-out occurs in the timer circuit 509, the serial communication circuit 512 Multiple types of interrupt factors may be determined in advance, such as the occurrence of an interrupt factor due to data reception or data transmission, or the occurrence of an interrupt factor due to the acquisition of numeric data that is a random value in the random number circuits 508a and 508b. That's fine.

  The reset / interrupt controller 506 uses the internal information register CIF (address FE25H) among the built-in registers of the game control microcomputer 560 as shown in FIGS. 9 to 11 to control interrupts and manage resets. Do. The internal information register CIF is a register for managing a reset factor generated immediately before, reading a random number update state, and a state of an input frequency when the random number update clock is an external clock.

  FIG. 22A shows a configuration example of the internal information register CIF. FIG. 22B shows an example of setting contents in each bit of the internal information data stored in the internal information register CIF. The internal information data RL3ER stored in the bit number [7] of the internal information register CIF indicates an abnormality in the update state of the 16-bit random number RL3 updated by the 16-bit random number circuit 508b of the channel 3. In the example shown in FIG. 22B, when the update abnormality of the 16-bit random number RL3 is not detected, the bit value of the internal information data RL3ER becomes “0”, whereas when the update abnormality of the 16-bit random number RL3 is detected. The bit value is “1”. The internal information data RL2ER stored in the bit number [6] of the internal information register CIF indicates an abnormality in the update state of the 16-bit random number RL2 updated by the 16-bit random number circuit 508b of the channel 2. In the example shown in FIG. 22B, when the update abnormality of the 16-bit random number RL2 is not detected, the bit value of the internal information data RL2ER becomes “0”, whereas when the update abnormality of the 16-bit random number RL2 is detected. The bit value is “1”. The internal information data RL1ER stored in the bit number [5] of the internal information register CIF indicates an abnormality in the update state of the 16-bit random number RL1 updated by the 16-bit random number circuit 508b of the channel 1. In the example shown in FIG. 22B, when the update abnormality of the 16-bit random number RL1 is not detected, the bit value of the internal information data RL1ER becomes “0”, while when the update abnormality of the 16-bit random number RL1 is detected. The bit value is “1”. The internal information data RL0ER stored in the bit number [4] of the internal information register CIF indicates an abnormality in the update state of the 16-bit random number RL0 updated by the 16-bit random number circuit 508b of the channel 0. In the example shown in FIG. 22B, when the update abnormality of the 16-bit random number RL0 is not detected, the bit value of the internal information data RL0ER becomes “0”, while when the update abnormality of the 16-bit random number RL0 is detected. The bit value is “1”. The bit number [7-4] of the internal information register CIF is set to “0” as an initial value.

  The internal information data RCER stored in the bit number [3] of the internal information register CIF is obtained when the external clock signal input from the random number external clock terminal (RCK terminal) is selected as the random number update clock. Indicates a frequency error in the external clock signal. In the example shown in FIG. 22B, when the frequency abnormality of the external clock signal is not detected, the bit value of the internal information data RCER is “0”, while when the frequency abnormality of the external clock signal is detected, The bit value is “1”. The bit number [3] of the internal information register CIF is set to “0” as an initial value.

  The internal information data SRSF stored in the bit number [2] of the internal information register CIF indicates that the reset factor generated immediately before is a system reset. In the example shown in FIG. 22B, when the immediately preceding reset cause is not a system reset (system reset has not occurred), the bit value of the internal information data SRSF is “0”, whereas when the system reset is a system reset (system reset) When the reset occurs), the bit value becomes “1”. The bit number [2] of the internal information register CIF is set to “1” as an initial value.

  The internal information data WDTF stored in the bit number [1] of the internal information register CIF indicates that the reset factor generated immediately before is a user reset due to the input of a time-out signal from the watchdog timer (WDT) 506b. In the example shown in FIG. 22B, when the reset factor immediately before is not a user reset by the timeout signal (user reset by the timeout signal has not occurred), the bit value of the internal information data WDTF becomes “0” while the timeout occurs. When it is a user reset by a signal (a user reset is generated by a time-out signal), the bit value becomes “1”. The bit number [1] of the internal information register CIF is set to “0” as an initial value.

  Internal information data IATF stored in bit number [0] of internal information register CIF indicates that the reset factor generated immediately before is a user reset due to the input of an IAT generation signal from IAT circuit 506a. In the example shown in FIG. 22B, when the immediately preceding reset factor is not a user reset by the IAT generation signal (user reset has not occurred by the IAT generation signal), the bit value of the internal information data IATF becomes “0”. When the user reset is performed by the IAT generation signal (user reset is generated by the IAT generation signal), the bit value is “1”. The bit number [0] of the internal information register CIF is set to “0” as an initial value.

  The CPU 56 included in the game control microcomputer 560 executes a user program (game control processing program for game control) based on the control code read from the ROM 54, thereby executing a game control in the pachinko gaming machine 1. CPU. When such game control is executed, the CPU 56 reads the fixed data from the ROM 54, the variable data writing operation in which the CPU 56 writes various data to the RAM 55 and temporarily stores the data, and the CPU 56 is temporarily stored in the RAM 55. A variable data read operation for reading various variable data being received, and a reception operation in which the CPU 56 receives input of various signals from outside the game control microcomputer 560 via the external bus interface 501, the parallel input port 511, the serial communication circuit 512, and the like. The CPU 56 also performs a transmission operation for outputting various signals to the outside of the game control microcomputer 560 via the external bus interface 501, the serial communication circuit 512, the parallel output port 513, and the like.

  The ROM 54 provided in the game control microcomputer 560 stores a control code indicating a user program (game control processing program for game control), fixed data, and the like.

  The RAM 55 provided in the game control microcomputer 560 provides a work area for game control. Here, at least a part of the RAM 55 may be a backup RAM that is backed up by a backup power source created in the power supply board 910. That is, even if the power supply to the pachinko gaming machine 1 is stopped, at least a part of the contents of the RAM 55 is stored for a predetermined period.

  The game control microcomputer 560 is equipped with four channels of 8-bit free-run counters as the free-run counter circuit 507.

  The random number circuits 508a and 508b included in the game control microcomputer 560 are circuits that generate numerical data that is a random value having a predetermined update range, such as an 8-bit random number or a 16-bit random number. In this embodiment, the hardware random number generated by the 16-bit random number circuit 508b among the random number circuits 508a and 508b is used as a big hit determination random number (random R) for determining whether or not to make a big hit. The CPU 56 is used for games by processing or updating various numerical data by software using a random counter different from the random number circuits 508a and 508b based on the numerical data extracted from the random number circuits 508a and 508b. Numerical data indicating all or part of the random number value may be counted. Alternatively, the CPU 56 may count (update) a part of numerical data indicating a random value such as a big hit determination random number by software without using the random number circuits 508a and 508b. As an example, the numerical data extracted by the CPU 56 from the random number circuits 508a and 508b serving as hardware is processed by software to update the numerical data indicating the big hit determination random number (random R), and other random values The numerical data indicating the jackpot type determination random number, the variation pattern type determination random number, or the variation pattern determination random number may be updated by software by the CPU 56 using a random counter or the like.

  FIG. 23 is a block diagram illustrating a configuration example of the 8-bit random number circuit 508a. FIG. 24 is a block diagram illustrating a configuration example of the 16-bit random number circuit 508b. As shown in FIGS. 23 and 24, the 8-bit random number circuit 508a and the 16-bit random number circuit 508b are random number sequence change selection circuits 523a and 523b, random number generation circuits 525a and 525b, random number sequence change circuits 526a and 526b, and a maximum value. Comparing circuits 527a and 527b are provided. In addition to the components included in the 8-bit random number circuit 508a, the 16-bit random number circuit 508b includes a random number start value selection circuit 535, as shown in FIG. Further, as shown in FIG. 24, the 16-bit random number circuit 508b includes an update monitoring circuit 537 in addition to the components included in the 8-bit random number circuit 508a.

  In the example shown in FIG. 24, only the configuration of the circuit portion of the 16-bit random number circuit 508b is shown, and description of each register used by the 16-bit random number circuit 508b other than the random number sequence change register 522 and the maximum value setting register 524b is omitted. doing. Specifically, the 16-bit random number circuit 508b replaces the RS hard latch selection registers 528a and 528b shown in FIG. 23 with the RL0 hard latch selection register 0 (RL0LS0) to the RL3 hard latch selection register (RL3LS) shown in FIG. ), Instead of the RS0 hard latch random value register 529a to RS3 hard latch random value register 529d shown in FIG. 23, the RL0 hard latch random value register 0 (RL0HV0) to RL3 hard latch random value register shown in FIGS. 1 (RL3HV1) is used, and instead of the RS hard latch flag register 530 shown in FIG. 23, RL hard latch flag register 0 (RLHF0) to RL hard latch flag register 1 (RLHF1) shown in FIG. RS interrupt control register RL interrupt control register 0 (RLIC0) to RL interrupt control register 1 (RLIC1) shown in FIG. The RL0 soft latch random value register (RL0SV) to RL3 soft latch random value register (RL3SV) shown in FIG. 10 are used. The 16-bit random number circuit 508b uses the same register as the 8-bit random number circuit 508a for the random value soft latch register 532 and the random number soft latch flag register 534.

  The 8-bit random number circuit 508a is an 8-bit random number initial setting 521a (8-bit random number initial setting 1 (KRS1) and 8-bit random number initial setting 2 (KRS2) shown in FIG. 8) provided in the program management area described above. Operates according to the set contents.

  The 16-bit random number circuit 508b is a 16-bit random number initial setting 521b (16-bit random number initial setting 1 (KRL1) to 16-bit random number initial setting 2 (KRL2) shown in FIG. 8) provided in the program management area already described. Operates according to the set contents. In addition to the function of the 8-bit random number circuit 508a, the 16-bit random number circuit 508b sets the 16-bit random number initial setting 536 (16-bit random number initial setting 3 (KRL3) shown in FIG. 8). By operating according to the contents, it has a function of changing the start value of the random number value in the first round (see FIG. 17).

  In the 16-bit random number circuit 508b, the random number generation circuit 525b includes an update monitoring circuit 537. In addition to the function of the 8-bit random number circuit 508a, the update monitoring circuit 537 operates to cause an external clock frequency abnormality and an update abnormality. (See FIG. 21). In this embodiment, the case where both the external clock frequency abnormality and the update abnormality are detected by one update monitoring circuit 537 is shown. However, the monitoring circuit for detecting the external clock frequency abnormality and the monitoring for detecting the update abnormality are shown. A circuit may be provided separately.

  Note that the 8-bit random number circuit 508a may also be configured to include an update monitoring circuit so that an external clock frequency abnormality and an update abnormality of the 8-bit random number circuit 508a can be detected.

  The random number sequence change register 522 corresponds to the random number sequence change register RDSC included in the built-in register of the game control microcomputer 560 as shown in FIG. As the random number sequence change register RDSC, a common register is used in each channel of the 8-bit random number circuit 508a and the 16-bit random number circuit 508b.

  The maximum value setting registers 524a and 524b correspond to the RS0 maximum value setting register (RS0MX) to the RS3 maximum value setting register (RS3MX) included in the built-in registers of the game control microcomputer 560 as shown in FIG. (In the case of the 16-bit random number circuit 508b, it corresponds to the RL0 maximum value setting register (RL0MX) to the RL3 maximum value setting register (RL3MX)).

  The hard latch selection register 528a corresponds to the RS hard latch selection register 0 (RSLS0) included in the built-in register of the game control microcomputer 560 as shown in FIG. The hard latch selection register 528b corresponds to the RS hard latch selection register 1 (RSLS1) included in the built-in register of the game control microcomputer 560 as shown in FIG. Note that the 16-bit random number circuit 508b corresponds to the RL0 hard latch selection register 0 (RL0LS0) to RL3 hard latch selection register 3 (RL3LS) shown in FIG.

  The RS0 hard latch random value registers 529a to RS3 hard latch random value registers 529d are RS0 hard latch random value registers (RS0HV) to RS3 hard latches included in the built-in registers of the game control microcomputer 560 as shown in FIG. It corresponds to the random value register (RS3HV). In the case of the 16-bit random number circuit 508b, the RL0 hard latch random value register 0 (RL0HV0) to RL1 hard latch random value register 1 (RL1HV1) shown in FIG. 10 and the RL2 hard latch random value register 0 (RL2HV0) shown in FIG. ) To RL3 hard latch random number value register 1 (RL3HV1).

  The RS hard latch flag register 530 corresponds to the RS hard latch flag register (RSHF) shown in FIG. Note that the 16-bit random number circuit 508b corresponds to the RL hard latch flag register 0 (RLHF0) to the RL hard latch flag register 1 (RLHF1) shown in FIG.

  The RS interrupt control register 531 corresponds to the RS interrupt control register (RSIC) shown in FIG. Note that the 16-bit random number circuit 508b corresponds to the RL interrupt control register 0 (RLIC0) to the RL interrupt control register 1 (RLIC1) shown in FIG.

  The random number soft latch register 532 corresponds to the random number soft latch register (RDSL) shown in FIG. As the soft latch register RDSL, a common register is used in each channel of the 8-bit random number circuit 508a and the 16-bit random number circuit 508b.

  The RS0 soft latch random value registers 533a to RS3 soft latch random value registers 533d correspond to the RS0 soft latch random value registers (RS0SV) to RS3 soft latch random value registers (RS3SV) shown in FIG. Note that the 16-bit random number circuit 508b corresponds to the RL0 soft latch random value (RL0SV) to the RL3 soft latch random value (RL3SV) shown in FIG.

  The random number soft latch flag register 534 corresponds to the random number soft latch flag register (RDSF) shown in FIG. As the random number soft latch flag register RDSF, a common register is used in each channel of the 8-bit random number circuit 508a and the 16-bit random number circuit 508b.

  The random number sequence change selection circuits 523a and 523b follow the setting contents of the 8-bit random number initial setting 1 (KRS1) and the 8-bit random number initial setting 2 (KRS2) shown in FIGS. 18 and 19 (in the case of the 16-bit random number circuit 508b). According to the setting contents of 16-bit random number initial setting 1 (KRL1) and 16-bit random number initial setting 2 (KRL2) shown in FIG. 15 and FIG. 16, the change method of the random number sequence is “do not change”, “change by software” , “Automatically change from the second lap” or “Automatically change from the first lap” is selected. Then, when any one of “change by software”, “automatic change from the second round” or “automatic change from the first round” is selected, the random number sequence changing circuits 526a and 526b receive random numbers according to the selection method. Change the column. Further, when “Do not change” is selected, control for changing the random number sequence is not performed.

  The random number sequence changing circuits 526a and 526b are circuits that can change the permutation of the numerical data generated by the random number generating circuits 525a and 525b in accordance with instructions from the random number sequence change selecting circuits 523a and 523b. For example, when “change by software” is instructed, the random number sequence change circuits 526a and 526b change the random number sequence updated by the random number generation circuits 525a and 525b by software (user program). In addition, for example, when “automatic change from the second round” is instructed, the random number sequence change circuits 526a and 526b automatically change the random number sequence updated by the random number generation circuits 525a and 525b from the second round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed. In addition, for example, when “automatic change from the first round” is instructed, the random number sequence change circuits 526a and 526b automatically change the random number sequence updated by the random number generation circuits 525a and 525b from the first round. Thereafter, the random number sequence is automatically changed every time the random number sequence is completed.

  The random number generation circuits 525a and 525b are constituted by, for example, an 8-bit counter (in the case of the 16-bit random number circuit 508b, a 16-bit counter), and the like, and predetermined numerical data can be updated based on an input of a random number update clock signal or the like. In the range, the circuit cyclically updates from a predetermined initial value to a predetermined final value. For example, the random number generation circuits 525a and 525b add one by one from the initial value set in the range from “0” to “255” in response to the falling edge in the random number update clock signal. The numerical data is counted up (in the case of the 16-bit random number circuit 508b, the numerical data is incremented by 1 from the initial value set within the range of “0” to “65535” to “65535”. Count up) Then, after counting up to “255”, the numerical data is updated cyclically by counting up from “0” to a numerical value that becomes a final value that is 1 smaller than the initial value.

  The maximum value comparison circuits 527a and 527b follow the setting contents of the 8-bit random number initial setting 1 (KRS1) and the 8-bit random number initial setting 2 (KRS2) shown in FIG. 18 and FIG. According to the setting contents of 16-bit random number initial setting 1 (KRL1) and 16-bit random number initial setting 2 (KRL2) shown in FIG. 15 and FIG.

  FIG. 25A shows a configuration example of the RL0 hard latch selection register 0 (RL0LS0). FIG. 25B shows an example of setting contents in each bit of data stored in the RL0 hard latch selection register 0 (RL0LS0). The data RL01RF stored in the bit number [7] of the RL0 hard latch selection register 0 (RL0LS0) is obtained when the value of the 16-bit random number RL0 is input to the RL0 hard latch random value register 1 (RL0HV1) by an external terminal input. The setting of conditions is shown. In the example shown in FIG. 25B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RL01RF becomes “0”. When the value is set to be latched, the bit value is “1”. The data RL01RF is set to “0” as an initial value.

  In this embodiment, regarding the register of the program management area and the built-in register, specifically, by setting the corresponding bit in the program management area or the like to a value of “0” or “1”, The corresponding bit value is read, and the read “0” or “1” value is written in the control register of the game control microcomputer 560 by hardware, so that various settings are made. For example, for bit 7 of RL0 hard latch select register 0 (RL0LS0), if the value read from bit 7 is “0”, the control register of game control microcomputer 560 is “0” in hardware. Is set so that the next value is not latched unless a value is read from the RL0 hard latch random number value register 1 (RL0HV1). If the value read from bit 7 is “1”, game control is performed. By writing “1” to the control register of the microcomputer 560 for hardware, the next value is latched without reading the value from the RL0 hard latch random value register 1 (RL0HV1). The same applies to each setting item in other program management areas and each bit of each register of the built-in register.

  The data RL01LS0 to RL01LS2 stored in the bit number [6-4] of the RL0 hard latch selection register 0 (RL0LS0) is input to the RL0 hard latch random number value register 1 (RL0HV1) according to which external terminal is input. It shows the setting of whether to import a value. In the example shown in FIG. 25B, when “000” is set in the bit number [6-4] of the RL0 hard latch select register 0 (RL0LS0), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. If “110” or “111” is set in the bit number [6-4] of the RL0 hard latch selection register 0 (RL0LS0), the setting is invalid. The data RL01LS0 to RL01LS2 is set to “000” as an initial value.

  The data RL00RF stored in the bit number [3] of the RL0 hard latch select register 0 (RL0LS0) is obtained when the value of the 16-bit random number RL0 is input to the RL0 hard latch random value register 0 (RL0HV0) by an external terminal input. The setting of conditions is shown. In the example shown in FIG. 25B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RL00RF becomes “0”, while the next value is not read. When the value is set to be latched, the bit value is “1”. The data RL00RF is set to “0” as an initial value.

  The data RL00LS0 to RL00LS2 stored in the bit number [2-0] of the RL0 hard latch selection register 0 (RL0LS0) is input to the RL0 hard latch random number value register 0 (RL0HV0) according to which external terminal is input to the 16-bit random number RL0. It shows the setting of whether to import a value. In the example shown in FIG. 25B, when “000” is set in the bit number [2-0] of the RL0 hard latch selection register 0 (RL0LS0), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [2-0] of the RL0 hard latch select register 0 (RL0LS0), the setting is invalid. The data RL00LS0 to RL00LS2 is set to “000” as an initial value.

  FIG. 26A shows a configuration example of the RL0 hard latch selection register 1 (RL0LS1). FIG. 26B shows an example of setting contents in each bit of data stored in the RL0 hard latch selection register 1 (RL0LS1). The data RL03RF stored in the bit number [7] of the RL0 hard latch selection register 1 (RL0LS1) is obtained when the value of the 16-bit random number RL0 is input to the RL0 hard latch random value register 3 (RL0HV3) by an external terminal input. The setting of conditions is shown. In the example shown in FIG. 26B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RL03RF becomes “0”. When the value is set to be latched, the bit value is “1”. The data RL03RF is set to “0” as an initial value.

  The data RL03LS0 to RL03LS2 stored in the bit number [6-4] of the RL0 hard latch selection register 1 (RL0LS1) is input to the RL0 hard latch random value register 3 (RL0HV3) according to which external terminal is input to the 16-bit random number RL0. It shows the setting of whether to import a value. In the example shown in FIG. 26B, when “000” is set in the bit number [6-4] of the RL0 hard latch selection register 1 (RL0LS1), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. When “110” or “111” is set in the bit number [6-4] of the RL0 hard latch selection register 1 (RL0LS1), the setting is invalid. The data RL03LS0 to RL03LS2 is set to “000” as an initial value.

  The data RL02RF stored in the bit number [3] of the RL0 hard latch selection register 1 (RL0LS1) is obtained when the value of the 16-bit random number RL0 is input to the RL0 hard latch random value register 2 (RL0HV2) by external terminal input. The setting of conditions is shown. In the example shown in FIG. 26B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RL02RF becomes “0”, while the next value is not read. When the value is set to be latched, the bit value is “1”. The data RL02RF is set to “0” as an initial value.

  The data RL02LS0 to RL02LS2 stored in the bit number [2-0] of the RL0 hard latch selection register 1 (RL0LS1) is input to the RL0 hard latch random number value register 2 (RL0HV2) according to which external terminal is input to the 16-bit random number RL0. It shows the setting of whether to import a value. In the example shown in FIG. 26B, when the bit number [2-0] of the RL0 hard latch selection register 1 (RL0LS1) is set to “000”, the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. If “110” or “111” is set in the bit number [2-0] of the RL0 hard latch selection register 1 (RL0LS1), the setting is invalid. The data RL02LS0 to RL02LS2 is set to “000” as an initial value.

  FIG. 27A shows a configuration example of the RLn hard latch selection register (RLnLS). FIG. 27B shows an example of setting contents in each bit of data stored in the RLn hard latch selection register (RLnLS). In FIG. 27, n takes a value from 0 to 3. Data RLn1RF stored in the bit number [7] of the RLn hard latch selection register (RLnLS) is a condition when the value of the 16-bit random number RLn is input to the RLn hard latch random value register 1 (RLnHV1) by an external terminal input. Shows the settings. In the example shown in FIG. 27B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RLn1RF becomes “0”, while the next value is not read. When the value is set to be latched, the bit value is “1”. The data RLn1RF is set to “0” as an initial value.

  The data RLn1LS0 to RLn1LS2 stored in the bit number [6-4] of the RLn hard latch selection register (RLnLS) is the value of the 16-bit random number RLn depending on which external terminal is input to the RLn hard latch random value register 1 (RLnHV1). Indicates whether to capture. In the example shown in FIG. 27B, when “000” is set in the bit number [6-4] of the RLn hard latch selection register (RLnLS), the PI0 terminal is selected and “001” is set. In this case, the PI1 terminal is selected. When “010” is set, the PI2 terminal is selected. When “011” is set, the PI3 terminal is selected. When “100” is set. When the PI4 terminal is selected and “101” is set, the PI5 / XINT terminal is selected. If “110” or “111” is set in the bit number [6-4] of the RLn hard latch selection register (RLnLS), the setting is invalid. The data RLn1LS0 to RLn1LS2 is set to “000” as an initial value.

  Data RLn0RF stored in the bit number [3] of the RLn hard latch selection register (RLnLS) is a condition when the value of the 16-bit random number RLn is input to the RLn hard latch random value register 0 (RLnHV0) by an external terminal input. Shows the settings. In the example shown in FIG. 27B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RLn0RF becomes “0”, while the next value is not read. When the value is set to be latched, the bit value is “1”. The data RLn0RF is set to “0” as an initial value.

  The data RLn0LS0 to RLn0LS2 stored in the bit number [2-0] of the RLn hard latch selection register (RLnLS) is the value of the 16-bit random number RLn depending on which external terminal is input to the RLn hard latch random value register 0 (RLnHV0). Indicates whether to capture. In the example shown in FIG. 27B, when “000” is set in the bit number [2-0] of the RLn hard latch selection register (RLnLS), the PI0 terminal is selected and “001” is set. In this case, the PI1 terminal is selected. When “010” is set, the PI2 terminal is selected. When “011” is set, the PI3 terminal is selected. When “100” is set. When the PI4 terminal is selected and “101” is set, the PI5 / XINT terminal is selected. If “110” or “111” is set in the bit number [2-0] of the RLn hard latch selection register (RLnLS), the setting is invalid. In addition, the data RLn0LS0 to RLn0LS2 is set to “000” as an initial value.

  FIG. 28A shows a configuration example of the RS hard latch selection register 0 (RSLS0). FIG. 28B shows an example of setting contents in each bit of data stored in the RS hard latch selection register 0 (RSLS0). Data RS1RF stored in the bit number [7] of the RS hard latch selection register 0 (RSLS0) is a condition for capturing the value of the 8-bit random number RS1 into the RS1 hard latch random value register (RS1HV) by external terminal input. Shows the settings. In the example shown in FIG. 28B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RS1RF becomes “0”. When the value is set to be latched, the bit value is “1”. The data RS1RF is set to “0” as an initial value.

  The data RS1LS0 to RS1LS2 stored in the bit number [6-4] of the RS hard latch selection register 0 (RSLS0) is an 8-bit random number RS1 value depending on which external terminal is input to the RS1 hard latch random value register (RS1HV). Indicates whether to capture. In the example shown in FIG. 28B, when “000” is set in the bit number [6-4] of the RS hard latch selection register 0 (RSLS0), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. If “110” or “111” is set in the bit number [6-4] of the RS hard latch selection register 0 (RSLS0), the setting is invalid. In addition, the data RS1LS0 to RS1LS2 is set to “000” as an initial value.

  Data RS0RF stored in the bit number [3] of the RS hard latch selection register 0 (RSLS0) is a condition for taking the value of the 8-bit random number RS0 into the RS0 hard latch random value register (RS0HV) by inputting an external terminal Shows the settings. In the example shown in FIG. 28B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RS0RF becomes “0”. When the value is set to be latched, the bit value is “1”. The data RS0RF is set to “0” as an initial value.

  The data RS0LS0 to RS0LS2 stored in the bit number [2-0] of the RS hard latch selection register 0 (RSLS0) is the value of the 8-bit random number RS0 depending on which external terminal input to the RS0 hard latch random value register (RS0HV). Indicates whether to capture. In the example shown in FIG. 28B, when the bit number [2-0] of the RS hard latch selection register 0 (RSLS0) is set to “000”, the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. If “110” or “111” is set in the bit number [2-0] of the RS hard latch selection register 0 (RSLS0), the setting is invalid. Further, the data RS0LS0 to RS0LS2 is set to “000” as an initial value.

  FIG. 29A shows a configuration example of the RS hard latch selection register 1 (RSLS1). FIG. 29B shows an example of setting contents in each bit of data stored in the RS hard latch selection register 1 (RSLS1). Data RS3RF stored in the bit number [7] of the RS hard latch selection register 1 (RSLS1) is a condition for taking the value of the 8-bit random number RS3 into the RS3 hard latch random number value register (RS3HV) by external terminal input Shows the settings. In the example shown in FIG. 29B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RS3RF becomes “0”. When the value is set to be latched, the bit value is “1”. The data RS3RF is set to “0” as an initial value.

  The data RS3LS0 to RS3LS2 stored in the bit number [6-4] of the RS hard latch selection register 1 (RSLS1) is an 8-bit random number RS3 value depending on which external terminal is input to the RS3 hard latch random number value register (RS3HV). Indicates whether to capture. In the example shown in FIG. 29B, when “000” is set in the bit number [6-4] of the RS hard latch selection register 1 (RSLS1), the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. If “110” or “111” is set in the bit number [6-4] of the RS hard latch selection register 0 (RSLS1), the setting is invalid. In addition, the data RS3LS0 to RS3LS2 is set to “000” as an initial value.

  Data RS2RF stored in the bit number [3] of the RS hard latch selection register 1 (RSLS1) is a condition for taking the value of the 8-bit random number RS2 into the RS2 hard latch random value register (RS2HV) by inputting an external terminal Shows the settings. In the example shown in FIG. 29B, when setting is made so that the next value is not latched unless a value is read, the bit value of the data RS2RF becomes “0”. When the value is set to be latched, the bit value is “1”. The data RS2RF is set to “0” as an initial value.

  The data RS2LS0 to RS2LS2 stored in the bit number [2-0] of the RS hard latch selection register 1 (RSLS1) is an 8-bit random number RS2 value depending on which external terminal is input to the RS2 hard latch random value register (RS2HV). Indicates whether to capture. In the example shown in FIG. 29B, when the bit number [2-0] of the RS hard latch selection register 1 (RSLS1) is set to “000”, the PI0 terminal is selected and “001” is set. When the PI1 terminal is selected, the PI2 terminal is selected when “010” is set, the PI3 terminal is selected when “011” is set, and “100” is set. In this case, the PI4 terminal is selected, and when “101” is set, the PI5 / XINT terminal is selected. If “110” or “111” is set in the bit number [2-0] of the RS hard latch selection register 1 (RSLS1), the setting is invalid. In addition, the data RS2LS0 to RS2LS2 is set to “000” as an initial value.

  FIG. 30A shows a configuration example of the RL interrupt control register 0 (RLIC0). FIG. 30B shows an example of setting contents in each bit of data stored in the RL interrupt control register 0 (RLIC0). Note that the bit value of the bit [7-6] of the RL interrupt control register 0 (RLIC0) is always “0”.

  The data RL11IE stored in the bit number [5] of the RL interrupt control register 0 (RLIC0) is forbidden / permitted for an interrupt caused by the random number value taken into the RL1 hard latch random number value register 1 (RL1HV1). Shows the settings. In the example shown in FIG. 30B, when the interrupt is disabled, the bit value of the data RL11IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL11IE is set to “0” as an initial value.

  The data RL10IE stored in the bit number [4] of the RL interrupt control register 0 (RLIC0) is forbidden / permitted for interrupts caused by the random number value taken into the RL1 hard latch random number value register 0 (RL1HV0). Shows the settings. In the example shown in FIG. 30B, when the interrupt is disabled, the bit value of the data RL10IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL10IE is set to “0” as an initial value.

  The data RL03IE stored in the bit number [3] of the RL interrupt control register 0 (RLIC0) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL0 hard latch random number value register 3 (RL0HV3). Shows the settings. In the example shown in FIG. 30B, when the interrupt is disabled, the bit value of the data RL03IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL03IE is set to “0” as an initial value.

  The data RL02IE stored in the bit number [2] of the RL interrupt control register 0 (RLIC0) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL0 hard latch random number value register 2 (RL0HV2). Shows the settings. In the example shown in FIG. 30B, when the interrupt is disabled, the bit value of the data RL02IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL02IE is set to “0” as an initial value.

  The data RL01IE stored in the bit number [1] of the RL interrupt control register 0 (RLIC0) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL0 hard latch random value register 1 (RL0HV1). Shows the settings. In the example shown in FIG. 30B, when the interrupt is disabled, the bit value of the data RL01IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL01IE is set to “0” as an initial value.

  The data RL00IE stored in the bit number [1] of the RL interrupt control register 0 (RLIC0) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL0 hard latch random value register 0 (RL0HV0). Shows the settings. In the example shown in FIG. 30B, when the interrupt is disabled, the bit value of the data RL00IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL00IE is set to “0” as an initial value.

  FIG. 31A shows a configuration example of the RL interrupt control register 1 (RLIC1). FIG. 31B shows an example of setting contents in each bit of data stored in the RL interrupt control register 1 (RLIC1). Note that the bit values of the bits [7-6] and [3-2] of the RL interrupt control register 1 (RLIC1) are always “0”.

  The data RL31IE stored in the bit number [5] of the RL interrupt control register 1 (RLIC1) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL3 hard latch random number value register 1 (RL3HV1). Shows the settings. In the example shown in FIG. 31B, when the interrupt is disabled, the bit value of the data RL31IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL31IE is set to “0” as an initial value.

  The data RL30IE stored in the bit number [4] of the RL interrupt control register 1 (RLIC1) prohibits / permits an interrupt due to the fact that a random value is taken into the RL3 hard latch random value register 0 (RL3HV0). Shows the settings. In the example shown in FIG. 31B, when the interrupt is disabled, the bit value of the data RL30IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL30IE is set to “0” as an initial value.

  The data RL21IE stored in the bit number [1] of the RL interrupt control register 1 (RLIC1) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL2 hard latch random number value register 1 (RL2HV1). Shows the settings. In the example shown in FIG. 31B, when the interrupt is disabled, the bit value of the data RL21IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL21IE is set to “0” as an initial value.

  The data RL20IE stored in the bit number [0] of the RL interrupt control register 1 (RLIC1) prohibits / permits an interrupt due to the fact that the random number value is taken into the RL2 hard latch random number value register 0 (RL2HV0). Shows the settings. In the example shown in FIG. 31B, when the interrupt is disabled, the bit value of the data RL20IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RL20IE is set to “0” as an initial value.

  FIG. 32A shows a configuration example of the RS interrupt control register (RSIC). FIG. 32B shows an example of setting contents in each bit of data stored in the RS interrupt control register (RSIC). The RS interrupt control register (RSIC) is a register that is shared by the 8-bit random number circuit 508a and the free-run counter circuit 507, and bits [7-4] of the RS interrupt control register (RSIC) are free-run. The settings related to the hard latch registers (FRC0 hard latch register (FR0HV) to FRC3 hard latch register (FR3HV)) used by the counter 507 are shown.

  The data RS3IE stored in the bit number [3] of the RS interrupt control register (RSIC) is set to disable / enable interrupts due to the fact that the RS3 hard latch random value register (RS3HV) has received a random value. Is shown. In the example shown in FIG. 32B, when the interrupt is disabled, the bit value of the data RS3IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RS3IE is set to “0” as an initial value.

  The data RS2IE stored in the bit number [2] of the RS interrupt control register (RSIC) is set to disable / enable interrupts due to the fact that the random value is taken into the RS2 hard latch random number value register (RS2HV). Is shown. In the example shown in FIG. 32B, the bit value of the data RS2IE becomes “0” when the interrupt is disabled, whereas the bit value becomes “1” when the interrupt is enabled. . The data RS2IE is set to “0” as an initial value.

  The data RS1IE stored in the bit number [1] of the RS interrupt control register (RSIC) is set to disable / permit interrupts due to the fact that the random value is taken into the RS1 hard latch random number value register (RS1HV). Is shown. In the example shown in FIG. 32B, when the interrupt is disabled, the bit value of the data RS1IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RS1IE is set to “0” as an initial value.

  The data RS0IE stored in the bit number [0] of the RS interrupt control register (RSIC) is set to disable / permit interrupts due to the fact that the random value is taken into the RS0 hard latch random number value register (RS0HV). Is shown. In the example shown in FIG. 32B, when the interrupt is disabled, the bit value of the data RS0IE is “0”, whereas when the interrupt is enabled, the bit value is “1”. . The data RS0IE is set to “0” as an initial value.

  FIG. 33A shows a configuration example of the RLn maximum value setting register (RLnMX). FIG. 33B shows an example of setting contents in each bit of data stored in the RLn maximum value setting register (RLnMX). In FIG. 33, n takes a value from 0 to 3. As shown in FIG. 33B, the maximum value of the 16-bit random number RLn is set in the data RLnMX15 to RLnMX0 stored in the bit number [15-0] of the RLn maximum value setting register (RLnMX).

  FIG. 34A shows a configuration example of the RSn maximum value setting register (RSnMX). FIG. 34B shows an example of setting contents in each bit of data stored in the RSn maximum value setting register (RSnMX). In FIG. 34, n takes a value from 0 to 3. As shown in FIG. 34B, the maximum value of the 8-bit random number RSn is set in the data RSnMX7 to RSnMX0 stored in the bit number [7-0] of the RSn maximum value setting register (RSnMX).

  FIG. 35A shows a configuration example of a random number sequence change register (RDSC). FIG. 35B shows an example of setting contents in each bit of data stored in the random number sequence change register (RDSC). Data RS3SC stored in the bit number [7] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of the 8-bit random number RS3. In the example shown in FIG. 35B, when the random number sequence is set not to be changed, the bit value of the data RS3SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS3SC is set to “0” as an initial value.

  Data RS2SC stored in the bit number [6] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of the 8-bit random number RS2. In the example shown in FIG. 35B, when the random number sequence is set not to be changed, the bit value of the data RS2SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS2SC is set to “0” as an initial value.

  The data RS1SC stored in the bit number [5] of the random number sequence change register (RDSC) indicates the random number sequence change request bit of the 8-bit random number RS1. In the example shown in FIG. 35B, when the random number sequence is set not to be changed, the bit value of the data RS1SC becomes “0”, whereas when the random number sequence is set to be changed, the bit value Becomes “1”. The data RS1SC is set to “0” as an initial value.

  Data RS0SC stored in bit number [4] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of 8-bit random number RS0. In the example shown in FIG. 35B, when the random number sequence is set not to be changed, the bit value of the data RS0SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS0SC is set to “0” as an initial value.

  Data RL3SC stored in bit number [3] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of 16-bit random number RL3. In the example shown in FIG. 35B, when the random number sequence is set not to be changed, the bit value of the data RL3SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL3SC is set to “0” as an initial value.

  The data RL2SC stored in the bit number [2] of the random number sequence change register (RDSC) indicates the random number sequence change request bit of the 16-bit random number RL2. In the example shown in FIG. 35B, when the random number sequence is set not to be changed, the bit value of the data RL2SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL2SC is set to “0” as an initial value.

  The data RL1SC stored in the bit number [1] of the random number sequence change register (RDSC) indicates the random number sequence change request bit of the 16-bit random number RL1. In the example shown in FIG. 35B, when the random number sequence is set not to be changed, the bit value of the data RL1SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL1SC is set to “0” as an initial value.

  Data RL0SC stored in bit number [0] of the random number sequence change register (RDSC) indicates a random number sequence change request bit of 16-bit random number RL0. In the example shown in FIG. 35B, when the random number sequence is set not to be changed, the bit value of the data RL0SC is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL0SC is set to “0” as an initial value.

  FIG. 36A shows a configuration example of a random number soft latch register (RDSL). FIG. 36B illustrates an example of setting contents in each bit of data stored in the random number soft latch register (RDSL). Data RS3SL stored in bit number [7] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 8-bit random number RS3 into the RS3 soft latch random number value register (RS3SV). In the example shown in FIG. 36 (B), when the random number value is set not to be taken in, the bit value of the data RS3SL becomes “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS3SL is set to “0” as an initial value.

  Data RS2SL stored in the bit number [6] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 8-bit random number RS2 into the RS2 soft latch random number value register (RS2SV). In the example shown in FIG. 36B, when the random value is set not to be taken in, the bit value of the data RS2SL becomes “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS2SL is set to “0” as an initial value.

  The data RS1SL stored in the bit number [5] of the random number soft latch register (RDSL) indicates a bit for taking the random value of the 8-bit random number RS1 into the RS1 soft latch random value register (RS1SV). In the example shown in FIG. 36B, when the random value is set not to be taken in, the bit value of the data RS1SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS1SL is set to “0” as an initial value.

  Data RS0SL stored in bit number [4] of the random number soft latch register (RDSL) indicates a bit for taking the random value of the 8-bit random number RS0 into the RS0 soft latch random value register (RS0SV). In the example shown in FIG. 36B, when the random value is set not to be taken in, the bit value of the data RS0SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RS0SL is set to “0” as an initial value.

  Data RL3SL stored in the bit number [3] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 16-bit random number RL3 into the RL3 soft latch random value register (RL3SV). In the example shown in FIG. 36 (B), when the random value is set not to be taken in, the bit value of the data RL3SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL3SL is set to “0” as an initial value.

  Data RL2SL stored in the bit number [2] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 16-bit random number RL2 into the RL2 soft latch random number value register (RL2SV). In the example shown in FIG. 36B, when the random value is set not to be fetched, the bit value of the data RL2SL becomes “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL2SL is set to “0” as an initial value.

  Data RL1SL stored in the bit number [1] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 16-bit random number RL1 into the RL1 soft latch random number value register (RL1SV). In the example shown in FIG. 36B, when the random value is set not to be taken in, the bit value of the data RL1SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL1SL is set to “0” as an initial value.

  Data RL0SL stored in the bit number [0] of the random number soft latch register (RDSL) indicates a bit for taking the random number value of the 16-bit random number RL0 into the RL0 soft latch random value register (RL0SV). In the example shown in FIG. 36B, when the random value is set not to be taken in, the bit value of the data RL0SL is “0”, whereas when the random number sequence is set to be changed, the bit value is set. Becomes “1”. The data RL0SL is set to “0” as an initial value.

  FIG. 37A shows a configuration example of a random number soft latch flag register (RDSF). FIG. 37B shows an example of setting contents in each bit of data stored in the random number soft latch flag register (RDSF). The data RS3SF stored in the bit number [7] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RS3 soft latch random value register (RS3SV). In the example shown in FIG. 37B, when the random value has not been captured, the bit value of the data RS3SF is “0”, whereas when the random value has been captured, the bit value is “ 1 ". The data RS3SF is set to “0” as an initial value.

  The data RS2SF stored in the bit number [6] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RS2 soft latch random value register (RS2SV). In the example shown in FIG. 37B, when the random value is not captured, the bit value of the data RS2SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS2SF is set to “0” as an initial value.

  The data RS1SF stored in the bit number [5] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RS1 soft latch random number value register (RS1SV). In the example shown in FIG. 37B, when the random value is not captured, the bit value of the data RS1SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS1SF is set to “0” as an initial value.

  The data RS0SF stored in the bit number [4] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RS0 soft latch random value register (RS0SV). In the example shown in FIG. 37B, when the random value is not captured, the bit value of the data RS0SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS0SF is set to “0” as an initial value.

  The data RL3SF stored in the bit number [3] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RL3 soft latch random value register (RL3SV). In the example shown in FIG. 37B, when the random value is not captured, the bit value of the data RL3SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL3SF is set to “0” as an initial value.

  The data RL2SF stored in the bit number [2] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RL2 soft latch random number value register (RL2SV). In the example shown in FIG. 37B, when the random value is not captured, the bit value of the data RL2SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL2SF is set to “0” as an initial value.

  The data RL1SF stored in the bit number [1] of the random number soft latch flag register (RDSF) indicates that the random number value is taken into the RL1 soft latch random number value register (RL1SV). In the example shown in FIG. 37B, when the random value is not captured, the bit value of the data RL1SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL1SF is set to “0” as an initial value.

  Data RL0SF stored in the bit number [0] of the random number soft latch flag register (RDSF) indicates that the random number value has been taken into the RL0 soft latch random number value register (RL0SV). In the example shown in FIG. 37B, when the random value is not captured, the bit value of the data RL0SF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL0SF is set to “0” as an initial value.

  FIG. 38A shows a configuration example of the RLn soft latch random value register (RLnSV). FIG. 38B shows an example of the contents stored in each bit of the data stored in the RLn soft latch random value register (RLnSV). In FIG. 38, n takes a value from 0 to 3. As shown in FIG. 38B, the data RLnSV15 to RLnSV0 stored in the bit number [15-0] of the RLn soft latch random value register (RLnSV) are 16 bits taken by the random number soft latch register (RDSL). The value of the random number RLn is stored. When a random number value is fetched, “1” is set in the corresponding bit of the random number soft latch flag register (RDSF).

  FIG. 39A shows a configuration example of the RSn soft latch random number value register (RSnSV). FIG. 39B shows an example of the contents stored in each bit of data stored in the RSn soft latch random number register (RSnSV). In FIG. 39, n takes a value from 0 to 3. As shown in FIG. 39B, the data RSnSV7 to RSnSV0 stored in the bit number [7-0] of the RSn soft latch random value register (RSnSV) are 8 bits taken by the random number soft latch register (RDSL). The value of the random number RSn is stored. When a random number value is fetched, “1” is set in the corresponding bit of the random number soft latch flag register (RDSF).

  FIG. 40A shows a configuration example of the RL hard latch flag register 0 (RLHF0). FIG. 40B shows an example of setting contents in each bit of data stored in the RL hard latch flag register 0 (RLHF0). The bit value of bit [7-6] of the RL hard latch flag register 0 (RLHF0) is always “0”.

  The data RL11HF stored in the bit number [5] of the RL hard latch flag register 0 (RLHF0) indicates that the random number value is taken into the RL1 hard latch random value register 1. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL11HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL11HF is set to “0” as an initial value.

  The data RL10HF stored in the bit number [4] of the RL hard latch flag register 0 (RLHF0) indicates that a random value has been taken into the RL1 hard latch random value register 0. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL10HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL10HF is set to “0” as an initial value.

  The data RL03HF stored in the bit number [3] of the RL hard latch flag register 0 (RLHF0) indicates that the random value is taken into the RL0 hard latch random value register 3. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL03HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL03HF is set to “0” as an initial value.

  The data RL02HF stored in the bit number [2] of the RL hard latch flag register 0 (RLHF0) indicates that the random value is taken into the RL0 hard latch random value register 2. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL02HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL02HF is set to “0” as an initial value.

  The data RL01HF stored in the bit number [1] of the RL hard latch flag register 0 (RLHF0) indicates that the random value is taken into the RL0 hard latch random value register 1. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL01HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL01HF is set to “0” as an initial value.

  The data RL00HF stored in the bit number [0] of the RL hard latch flag register 0 (RLHF0) indicates that a random value has been taken into the RL0 hard latch random value register 0. In the example shown in FIG. 40B, when the random value is not captured, the bit value of the data RL00HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL00HF is set to “0” as an initial value.

  FIG. 41A shows a configuration example of the RL hard latch flag register 1 (RLHF1). FIG. 41B shows an example of setting contents in each bit of data stored in the RL hard latch flag register 1 (RLHF1). The bit values of the bits [7-6] and [3-2] of the RL hard latch flag register 1 (RLHF1) are always “0”.

  Data RL31HF stored in the bit number [5] of the RL hard latch flag register 1 (RLHF1) indicates that a random number value has been taken into the RL3 hard latch random value register 1. In the example shown in FIG. 41B, when the random value is not captured, the bit value of the data RL31HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL31HF is set to “0” as an initial value.

  The data RL30HF stored in the bit number [4] of the RL hard latch flag register 1 (RLHF1) indicates that a random value has been taken into the RL3 hard latch random value register 0. In the example shown in FIG. 41B, when the random value is not captured, the bit value of the data RL30HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL30HF is set to “0” as an initial value.

  The data RL21HF stored in the bit number [1] of the RL hard latch flag register 1 (RLHF1) indicates that a random value has been taken into the RL2 hard latch random value register 1. In the example shown in FIG. 41B, when the random value is not captured, the bit value of the data RL21HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL21HF is set to “0” as an initial value.

  The data RL20HF stored in the bit number [1] of the RL hard latch flag register 1 (RLHF1) indicates that the random number value is taken into the RL2 hard latch random value register 0. In the example shown in FIG. 41B, when the random value is not captured, the bit value of the data RL20HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RL20HF is set to “0” as an initial value.

  FIG. 42A shows a configuration example of the RS hard latch flag register (RSHF). FIG. 42B shows an example of setting contents in each bit of data stored in the RS hard latch flag register (RSHF). The RS hard latch flag register (RSHF) is a register that is used in common by the 8-bit random number circuit 508a and the free-run counter circuit 507, and bits [7-4] of the RS hard latch flag register (RSHF) are: The settings related to the hard latch registers (FRC0 hard latch register (FR0HV) to FRC3 hard latch register (FR3HV)) used by the free-run counter 507 are shown.

  The data RS3HF stored in the bit number [3] of the RS hard latch flag register (RSHF) indicates that the random number value is taken into the RS3 hard latch random value register (RS3HV). In the example shown in FIG. 42B, when the random value is not captured, the bit value of the data RS3HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS3HF is set to “0” as an initial value.

  The data RS2HF stored in the bit number [2] of the RS hard latch flag register (RSHF) indicates that the random value is taken into the RS2 hard latch random value register (RS2HV). In the example shown in FIG. 42B, when the random value is not captured, the bit value of the data RS2HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS2HF is set to “0” as an initial value.

  The data RS1HF stored in the bit number [1] of the RS hard latch flag register (RSHF) indicates that the random value has been taken into the RS1 hard latch random value register (RS1HV). In the example shown in FIG. 42B, when the random value is not captured, the bit value of the data RS1HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS1HF is set to “0” as an initial value.

  The data RS0HF stored in the bit number [0] of the RS hard latch flag register (RSHF) indicates that the random value is taken into the RS0 hard latch random value register (RS0HV). In the example shown in FIG. 42B, when the random value is not captured, the bit value of the data RS0HF is “0”, whereas when the random value has been captured, the bit value is “0”. 1 ". The data RS0HF is set to “0” as an initial value.

  FIG. 43A shows a configuration example of the RL0 hard latch random number value register m (RL0mHV). FIG. 43B shows an example of the contents stored in each bit of data stored in the RL0 hard latch random number value register m (RL0mHV). In FIG. 43, m takes a value from 0 to 3. As shown in FIG. 43B, the data RL0mHV15 to RL0mHV0 stored in the bit number [15-0] of the RL0 hard latch random number value register m (RL0mHV) are the 16-bit random number RL0 captured by the external terminal input. Stores the value. When a random value is taken in, “1” is set in the corresponding bit of the RL hard latch flag register 0 (RLHF0).

  FIG. 44A shows a configuration example of the RL1 hard latch random number value register m (RL1mHV). FIG. 44B shows an example of the contents stored in each bit of the data stored in the RL1 hard latch random value register m (RL1mHV). In FIG. 44, m takes a value from 0 to 3. As shown in FIG. 44B, the data RL1mHV15 to RL1mHV0 stored in the bit number [15-0] of the RL1 hard latch random number value register m (RL1mHV) are the 16-bit random number RL1 fetched by the external terminal input. Stores the value. When a random value is taken in, “1” is set in the corresponding bit of the RL hard latch flag register 0 (RLHF0).

  FIG. 45A shows a configuration example of the RL2 hard latch random number value register m (RL2mHV). FIG. 45B shows an example of the contents stored in each bit of data stored in the RL2 hard latch random number value register m (RL2mHV). In FIG. 45, m takes a value from 0 to 3. As shown in FIG. 45B, the data RL2mHV15 to RL2mHV0 stored in the bit number [15-0] of the RL2 hard latch random number value register m (RL2mHV) are the 16-bit random number RL2 fetched by the external terminal input. Stores the value. When a random value is taken in, “1” is set in the corresponding bit of the RL hard latch flag register 1 (RLHF1).

  FIG. 46A shows a configuration example of the RL3 hard latch random number value register m (RL3mHV). FIG. 46B shows an example of the contents stored in each bit of data stored in the RL3 hard latch random number value register m (RL3mHV). In FIG. 46, m takes a value from 0 to 3. As shown in FIG. 46B, the data RL3mHV15 to RL3mHV0 stored in the bit number [15-0] of the RL3 hard latch random value register m (RL3mHV) are the 16-bit random number RL3 fetched by the external terminal input. Stores the value. When a random value is taken in, “1” is set in the corresponding bit of the RL hard latch flag register 1 (RLHF1).

  FIG. 47A shows a configuration example of the RSn hard latch random number value register (RSnHV). FIG. 47B shows an example of the contents stored in each bit of data stored in the RSn hard latch random number value register (RSnHV). In FIG. 47, n takes a value from 0 to 3. As shown in FIG. 47 (B), the data RSnHV7 to RSnHV0 stored in the bit number [70] of the RSn hard latch random number register (RLnHV) stores the value of the 8-bit random number RSn fetched by the external terminal input. Is done. When a random value is taken in, “1” is set in the corresponding bit of the RS hard latch flag register (RSHF).

  The timer circuit 509 provided in the game control microcomputer 560 shown in FIG. 6 is an 8-bit programmable timer, and the game control microcomputer 560 includes three channels of 8-bit counters as the timer circuit 509. In this embodiment, it is possible to perform a real-time interrupt request and time measurement by setting by a user program using the timer circuit 509.

  The interrupt controller 510 provided in the game control microcomputer 560 shown in FIG. 6 includes an external interrupt request from the PI5 / XINT terminal and built-in peripheral circuits (for example, serial communication circuit 512, random number circuits 508a and 508b, timer circuit 509). This is a circuit for controlling an interrupt request from.

  A parallel input port 511 provided in the game control microcomputer 560 shown in FIG. 6 incorporates an input-only port (PIP) having an 8-bit width. Further, the parallel output port 513 provided in the game control microcomputer 560 shown in FIG. 6 incorporates an 11-bit wide output dedicated port (POP).

  The serial communication circuit 512 provided in the game control microcomputer 560 shown in FIG. 6 is a circuit that performs asynchronous serial communication in the input / output with respect to the outside. The game control microcomputer 560 includes, as the serial communication circuit 512, a 1-channel circuit for both transmission and reception and a 3-channel circuit for transmission only. For example, the circuit for both transmission and reception is used for communication between the game control microcomputer 560 that requires two-way communication and the payout control microcomputer mounted on the payout control board 37, for example. For example, the circuit for transmission only is used for communication from the game control microcomputer 560, which may be one-way communication, to the effect control microcomputer 100.

  An address decode circuit 514 provided in the game control microcomputer 560 shown in FIG. 6 decodes each functional block in the game control microcomputer 560 and a chip select signal which is a decode signal for an external device. Circuit. By the chip select signal, an internal circuit of the game control microcomputer 560 or an external device as a peripheral device is selectively operated effectively, and can be accessed from the CPU 56.

  Next, the operation of the gaming machine will be described. First, in this embodiment, as described above, when a time-out signal from the watchdog timer (WDT) 506b or an IAT signal from the IAT circuit 506a is generated, a user reset or a system reset is generated. Is possible (see FIG. 14). FIG. 48 is an explanatory diagram for explaining the difference in reset operation depending on the setting content in the reset setting (KRES).

  First, a case where a system reset is set to occur when a time-out signal from the watchdog timer (WDT) 506b or an IAT signal from the IAT circuit 506a is generated will be described with reference to FIG. In this case, as shown in FIG. 48A, when the gaming machine is turned on and the power supply is started, the gaming control microcomputer 56 initializes all internal circuits including the CPU core. At the same time, according to the setting contents of the program management area, various settings of the game control microcomputer 560 such as setting of the internal reset operation and setting of the random number circuits 508a and 508b are performed by hardware (step S1001). Specifically, the internal reset operation is set according to the setting contents of the reset setting (KRES) shown in FIG. 14 of the program management area, or the 16-bit random number initial setting 1 (FIG. 15 to FIG. 19) shown in FIG. The random number circuits 508a and 508b are set according to the setting contents of KRL1) to 8-bit random number initial setting 2 (KRS2). In the example shown in FIG. 48A, the game control microcomputer 56 sets the system reset as the internal reset operation setting according to the setting contents of the program management area. In addition, the setting contents of the program management area are set in advance by a gaming machine manufacturer (user) at the time of manufacturing the gaming machine.

  When various settings of the game control microcomputer 560 are completed, the game control microcomputer 56 shifts to a security mode and executes a security check (step S1002). In the security check executed in step S1002, the user program is authenticated. Specifically, it is recalculated whether the authentication code calculated based on the user program is correct. If the authentication code is correct, the process proceeds to step S1003. If the authentication code is not correct, the CPU 56 is stopped. The security mode time for shifting to the security mode is variable according to the setting contents of the security time setting (KSES) shown in FIG. 20 of the program management area as already described. Specifically, the security mode time is set by setting in step S1001 according to the setting contents of the security time setting (KSES) shown in FIG. 20 of the program management area. It is assumed that the authentication code is written in advance together with the user program by the gaming machine manufacturer (user) when writing into the built-in ROM 54 when the gaming machine is manufactured.

  When the security check is completed, the game control microcomputer 560 shifts to the user mode and starts executing the user program. Specifically, execution of the main process of FIG. 50 described later is started.

  Next, when the user program is being executed (specifically, during the execution of the loop process in the main process of FIG. 50 described later and the timer interrupt process of FIG. 51), the watchdog timer (WDT) 506b And the IAT signal from the IAT circuit 506a are generated. In the example shown in FIG. 48A, since the system reset is set as the setting of the internal reset operation in step S1001, the system reset is generated based on the generation of the timeout signal or the IAT signal.

  Similar to step S1001, the game control microcomputer 56 initializes all internal circuits including the CPU core, and sets the internal reset operation and random number circuits 508a and 508b according to the setting contents of the program management area. Various settings of the game control microcomputer 560 such as settings are performed by hardware (step S1005). When various settings of the game control microcomputer 560 are completed, the game control microcomputer 56 shifts to the security mode and executes a security check (step S1006), as in step S1002.

  When the security check is completed, the game control microcomputer 560 shifts to the user mode and starts executing the user program, as in step S1003. Specifically, execution of the main process of FIG. 50 described later is started again.

  Thereafter, each time a time-out signal from the watchdog timer (WDT) 506b or an IAT signal from the IAT circuit 506a is generated, the operations in steps S1004 to S1007 are executed. In FIG. 48A, the specific processing contents of steps S1001 and S1002 and the specific processing contents of steps S1005 and S1006 are the same.

  Next, a case where a user reset is set to occur when a time-out signal from the watchdog timer (WDT) 506b or an IAT signal from the IAT circuit 506a is generated will be described with reference to FIG. In this case, as shown in FIG. 48 (B), when the gaming machine is turned on and the power supply is started, the gaming control microcomputer 56 initializes all internal circuits including the CPU core. At the same time, according to the setting contents of the program management area, various settings of the game control microcomputer 560 such as setting of the internal reset operation and setting of the random number circuits 508a and 508b are performed by hardware (step S1011). Specifically, the internal reset operation is set according to the setting contents of the reset setting (KRES) shown in FIG. 14 of the program management area, or the 16-bit random number initial setting 1 (FIG. 15 to FIG. 19) shown in FIG. The random number circuits 508a and 508b are set according to the setting contents of KRL1) to 8-bit random number initial setting 2 (KRS2). In the example shown in FIG. 48B, the game control microcomputer 56 sets the user reset as the internal reset operation setting according to the setting contents of the program management area. In addition, the setting contents of the program management area are set in advance by a gaming machine manufacturer (user) at the time of manufacturing the gaming machine.

  When the various settings of the game control microcomputer 560 are completed, the game control microcomputer 56 shifts to the security mode and executes a security check (step S1012). In the security check executed in step S1012, the user program is authenticated. Specifically, it is recalculated whether the authentication code calculated based on the user program is correct. If the authentication code is correct, the process proceeds to step S1013. If the authentication code is not correct, the CPU 56 is stopped. The security mode time for shifting to the security mode is variable according to the setting contents of the security time setting (KSES) shown in FIG. 20 of the program management area as already described. Specifically, the security mode time is set by performing the setting in step S1011 according to the setting contents of the security time setting (KSES) shown in FIG. 20 of the program management area. It is assumed that the authentication code is written in advance together with the user program by the gaming machine manufacturer (user) when writing into the built-in ROM 54 when the gaming machine is manufactured.

  When the security check is completed, the game control microcomputer 560 shifts to the user mode and starts executing the user program. Specifically, execution of the main process of FIG. 50 described later is started.

  Next, when the user program is being executed (specifically, during the execution of the loop process in the main process of FIG. 50 described later and the timer interrupt process of FIG. 51), the watchdog timer (WDT) 506b And the IAT signal from the IAT circuit 506a are generated. In the example shown in FIG. 48B, the user reset is generated based on the generation of the time-out signal or the IAT signal because the user reset is set as the setting of the internal reset operation in step S1011.

  When a user reset occurs, the various settings of the game control microcomputer 560 in step S1011 and the security check in step S1012 are not executed. Of the internal circuits of the game control microcomputer 560, the CPU core and timer circuit 509 The free-run counter circuit 507, the arithmetic circuit 505, the parallel input port 511, the parallel output port 513, the serial communication circuit 512, the interrupt controller 510, and the like are initialized. Then, it returns to the top address of the user program as it is, and the execution of the user program is started again from the top address (step S1015). Specifically, execution of the main process of FIG. 50 described later is started again.

  Thereafter, each time the time-out signal from the watchdog timer (WDT) 506b or the IAT signal from the IAT circuit 506a is generated, the operations in steps S1014 to S1015 are executed.

  In this embodiment, when the game control microcomputer 560 reads data stored in the internal RAM area during execution of the user program, all of the upper and lower levels of the internal RAM area in which the data is stored are read. It is possible to read out data by designating only the lower order of the address instead of designating the address of the address. FIG. 49 is an explanatory diagram showing an example of how to read data stored in the internal RAM area. In this embodiment, it is assumed that data referred to by the user program is stored in the F000H to F0FFH areas in the built-in RAM area, and the upper address of the data storage area is always F0H. Further, the game control microcomputer 560 includes a dedicated register (Q register) for storing the upper address of the data storage area as a fixed value, and a fixed value F0H is set in the Q register. .

  In the example shown in FIG. 49, the case where the data stored in the address F020H of the internal RAM area is read is shown. In this case, using the command LDQ for reading data using the Q register, only the lower address 20H is designated and the data read operation is performed (specifically, LDQ A, (20H) is executed). . Then, the CPU 56 specifies the upper address of the data storage area as F0H from the fixed value set in the Q register, specifies the lower address 20H specified by the LDQ instruction, and combines the upper and lower data storage areas. Is specified as F020H. Then, the CPU 56 reads out the data a stored in the data storage area corresponding to the specified F020H and stores it in the register A.

  Note that the value of the Q register is initialized by hardware at the time of system reset and automatically set to the initial value F0H. For example, when power is supplied to the gaming machine and the power supply is started, the lower 4 bits of the Q register are initialized to 0, and the upper 4 bits are inverted by an inverting circuit so that all values become 1. As a result, F0H is automatically set as the initial value of the Q register. As will be described later, in this embodiment, even when the execution of the user program is started, a process for setting the initial value F0H in the Q register is executed by the user program (see step S5A described later).

  The initial value of the Q register may be set only by hardware automatic setting when power is supplied to the gaming machine and power supply is started, or by the user program executed when the user program is started. Only setting is acceptable.

  Next, a process that is executed according to the user program after the system check is executed and the mode is changed to the user mode will be described. When shifting to the user mode, the game control microcomputer 560 starts execution of the main process.

  FIG. 50 is a flowchart showing main processing executed by the game control microcomputer 560 on the main board 31. In the main process, the CPU 56 first performs necessary initial settings. In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, an interrupt mode is set (step S2), and a stack pointer designation address is set in the stack pointer (step S3). Then, after initialization of the built-in device (such as initialization of the timer circuit 509, the parallel input port 511, and the parallel output port 513, which are built-in devices (built-in peripheral circuits)), the RAM is made accessible. Set (step S5).

  Next, the CPU 56 sets an initial value F0H in the Q register (step S5A). That is, the initial value F0H is set in the Q register at the timing when step S5 is executed and the RAM 55 is set in an accessible state.

  Next, the CPU 56 checks the state of the output signal (clear signal) of a clear switch (for example, mounted on the power supply board) input via the input port (step S6). When the ON is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S10 to S15).

  If the clear switch is not in the on state, the data protection processing of the backup RAM area (for example, power supply stop processing (power-off processing) such as addition of parity data) is performed when power supply to the gaming machine is stopped. It is confirmed whether or not it has been received (step S7). When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing. Whether or not there is backup data in the backup RAM area is determined by, for example, whether the backup monitoring timer value set in the backup RAM area in the power-off process is the same value as the determination value (for example, 2). It can be confirmed that the processing result of the stop processing is saved. Instead of the backup monitoring timer, for example, a backup flag may be set in the power-off process, and in step S7, it may be confirmed whether or not the backup flag is set.

  When it is confirmed that the power supply stop process has been performed, the CPU 56 performs data check of the backup RAM area (step S8). In this embodiment, a parity check is performed as a data check. Therefore, in step S8, the calculated checksum is compared with the checksum calculated and stored by the same process in the power supply stop process. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, an initialization process that is executed when the power is turned on is not performed when the power supply is stopped.

  If the check result is normal, the CPU 56 recovers the game state restoration process (steps S41 to S43) for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Process). Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S41), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S42). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S41 and S42, the saved contents of the work area that should not be initialized remain as they are. The part that should not be initialized is, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, probability variation flag, time reduction flag, etc.), and the area where the output state of the output port is saved (output port buffer) ), A portion in which data indicating the number of unpaid prize balls is set.

  Further, the CPU 56 transmits a power failure recovery designation command as an initialization command at the time of power supply recovery (step S43). Further, the CPU 56 transmits a display result designation command designating a display result (probability big hit, normal big hit, sudden probability big hit, small hit, or off) stored in the backup RAM to the effect control board 80 (step). S44). Then, the process proceeds to step S15.

  In this embodiment, the value of a variable time timer (to be described later) is also stored in the backup RAM area. Therefore, when the power failure is restored, after the display result designation command is transmitted in step S44, measurement of the saved variation time timer value is resumed, and the variation display of the special symbol is resumed and saved. When the value of the changed time timer has timed out, a symbol determination designation command to be described later is further transmitted. In this embodiment, a special symbol process flag value, which will be described later, is also stored in the backup RAM area. Therefore, when the power failure is recovered, the special symbol process is resumed from the process corresponding to the value of the stored special symbol process flag.

  Note that the display result designation command is not necessarily transmitted when the power failure is restored, but the CPU 56 may first confirm whether or not the value of the variable time timer stored in the backup RAM area is zero. . If the value of the variation time timer is not 0, it is determined that a power failure occurs during the variation, and a display result designation command is transmitted. It may be determined that the state has not been reached, and the display result designation command may not be transmitted.

  Further, the CPU 56 may first check whether or not the value of the special symbol process flag stored in the backup RAM area is 3. If the value of the special symbol process flag is 3, it is determined that the power failure occurs during the fluctuation, and a display result designation command is transmitted. If the special symbol process flag is not 3, the fluctuation occurs at the time of the power failure. The display result designation command may not be transmitted because it is determined that it is not in the middle.

  In this embodiment, whether or not the data in the backup RAM area is stored is confirmed using both the backup monitoring timer (or backup flag) and the check data, but only one of them is used. May be. In other words, either the backup monitoring timer (or backup flag) or the check data may be used as an opportunity for executing the gaming state recovery process.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10), and clears the addition buffer and the clear buffer (step S10a). The addition buffer and the clear buffer are formed in the RAM 55 (that is, an area in the RAM), and are used to detect that a winning order abnormality at the starting port has occurred in a winning order abnormality notification process described later. The RAM clear process initializes predetermined data (for example, count value data of a counter for generating a random number for normal symbol determination) to 0, but an arbitrary value or a predetermined value It may be initialized to. In addition, the entire area of the RAM 55 may not be initialized, and predetermined data (for example, count value data of a counter for generating a random number for normal symbol determination) may be left as it is. In this embodiment, when the game state restoration process (steps S41 to S43) is executed, the normal initialization process (steps S10 to S13) is not executed, but the game state restoration process (step S41). Even when the processing of S41 to S43 is executed, the addition buffer and clear buffer may be cleared (step S10a). In this way, it is possible to perform the winning order abnormality notifying process in a new state, instead of performing the winning order abnormality notifying process by restoring the state before the power supply is stopped.

  Next, the CPU 56 sets the start address of the initialization setting table stored in the ROM 54 as a pointer (step S11), and sequentially sets the contents of the initialization setting table in the work area (step S12).

  By the processing in steps S11 and S12, for example, a normal symbol per-determining random number counter, a special symbol buffer, a total prize ball number storage buffer, a special symbol process flag, and other flags for selectively performing processing according to the control state Value is set.

  Further, the CPU 56 initializes a sub board (a board on which a microcomputer other than the main board 31 is mounted) (a command indicating that the game control microcomputer 560 has executed an initialization process). Is also transmitted to the sub-board (step S13). For example, when the effect control microcomputer 100 receives the initialization designation command, the effect display device 9 performs screen display for notifying that the control of the gaming machine has been performed, that is, initialization notification.

  In step S15, the CPU 56 sets a register of the timer circuit 509 built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 4 ms). That is, a value corresponding to, for example, 4 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the execution of the initialization process (steps S10 to S15) is completed, the CPU 56 repeatedly executes the display random number update process (step S17) and the initial value random number update process (step S18) in the main process. When executing the display random number update process and the initial value random number update process, the interrupt disabled state is set (step S16). When the display random number update process and the initial value random number update process are finished, the interrupt enabled state is set. Set (step S19). In this embodiment, the display random number is a random number for determining the stop symbol of the special symbol when it is not a big hit, or a random number for determining whether to reach when it is not a big hit, The random number update process is a process for updating the count value of the counter for generating the display random number. The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. In this embodiment, the initial value random number is the initial value of the count value of the counter for generating a random number for determining whether or not to win for a normal symbol (normal random number generation counter for normal symbol determination). It is a random number to determine. A game control process for controlling the progress of the game, which will be described later (the game control microcomputer 560 controls game devices such as an effect display device, a variable winning ball device, a ball payout device, etc. provided in the game machine itself. In the process of transmitting a command signal to be controlled by another microcomputer, or a game machine control process), the count value of the random number for determination per normal symbol is one round (the random number for determination per normal symbol is taken). When the value is incremented by the number of values between the minimum value and the maximum value of the possible values), an initial value is set in the counter.

  In this embodiment, the reach effect is executed using effect symbols that are variably displayed on the effect display device 9. Further, when the display result of the special symbol is a jackpot symbol, the reach effect is always executed. When the display result of the special symbol is not a jackpot symbol, the game control microcomputer 560 determines whether or not to execute the reach effect by lottery using a random number. However, it is the production control microcomputer 100 that actually executes the reach production control.

  When the timer interrupt occurs, the CPU 56 executes the timer interrupt process in steps S20 to S34 shown in FIG. In the timer interrupt process, first, a power-off detection process for detecting whether or not a power-off signal is output (whether or not an on-state is turned on) is executed (step S20). The power-off signal is output, for example, when a power supply monitoring circuit mounted on the power supply board detects a decrease in the voltage of the power supplied to the gaming machine. In the power-off detection process, when detecting that the power-off signal has been output, the CPU 56 executes a power supply stop process for saving necessary data in the backup RAM area. Next, detection signals from the gate switch 32a, the first start port switch 13a, the second start port switch 14a, and the count switch 23 are input via the input driver circuit 58, and their state is determined (switch processing: step S21). ).

  Next, the CPU 56 executes a winning order abnormality notification process for detecting a winning order abnormality in the first starting winning opening 13 and the second starting winning opening 14 and notifying the winning order abnormality (step S21a).

  It should be noted that “abnormal winning order” means the order in which game balls have won the first start winning opening 13 and the second starting winning opening 14 (specifically, the first start opening switch 13a and the second start opening switch 14a). The order in which game balls are detected is different from the predetermined order. In this embodiment, as already described, the game balls that have flowed into the distribution device 200 are configured to alternately win the first start winning opening 13 and the second start winning opening 14 by the distribution member 202. (However, in the probability variation state (high base state), there may be cases where the second start winning opening 14 can be won regardless of the state of the distribution device 200), so the first start winning opening 13 or the second start A game ball does not continuously win the winning opening 14 (however, in the probability variation state (high base state), there may be a continuous winning in the second start winning opening 14). For this reason, in this embodiment, a winning order abnormality is detected when a predetermined number or more (four or more in this example) are continuously won in either the first start winning opening 13 or the second starting winning opening 14. Control for notifying such a winning order abnormality is performed.

  Next, the CPU 56 has a first special symbol display 8a, a second special symbol display 8b, a normal symbol display 10, a first special symbol hold storage display 18a, a second special symbol hold storage display 18b, a normal symbol. A display control process for controlling the display of the on-hold storage display 41 is executed (step S22). About the 1st special symbol display 8a, the 2nd special symbol display 8b, and the normal symbol display 10, a drive signal is output with respect to each display according to the content of the output buffer set by step S32, S33. Execute control.

  Also, a process of updating the count value of each counter for generating each random number for determination such as a random number for determination per ordinary symbol used for game control is performed (determination random number update process: step S23). The CPU 56 further performs a process of updating the count value of the counter for generating the initial value random number and the display random number (initial value random number update process, display random number update process: steps S24 and S25).

  Further, the CPU 56 performs special symbol process processing (step S26). In the special symbol process, corresponding processing is executed according to a special symbol process flag for controlling the first special symbol indicator 8a, the second special symbol indicator 8b, and the special winning award in a predetermined order. The CPU 56 updates the value of the special symbol process flag according to the gaming state.

  Next, normal symbol process processing is performed (step S27). In the normal symbol process, the CPU 56 executes the corresponding process according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The CPU 56 updates the value of the normal symbol process flag according to the gaming state.

  Further, the CPU 56 performs a process of sending an effect control command to the effect control microcomputer 100 (effect control command control process: step S28).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S29).

  Further, the CPU 56 executes a prize ball process for setting the number of prize balls based on detection signals from the first start port switch 13a, the second start port switch 14a and the count switch 23 (step S30). Specifically, the payout control micro mounted on the payout control board 37 in response to the winning detection based on any one of the first start port switch 13a, the second start port switch 14a and the count switch 23 being turned on. A payout control command (prize ball number signal) indicating the number of prize balls is output to the computer. The payout control microcomputer drives the ball payout device 97 in accordance with a payout control command indicating the number of winning balls.

  In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 relates to on / off of the solenoid in the RAM area corresponding to the output state of the output port. The contents are output to the output port (step S31: output process).

  Further, the CPU 56 performs special symbol display control processing for setting special symbol display control data for effect display of the special symbol in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S32).

  Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in the output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S33). For example, when the start flag related to the variation of the normal symbol is set, the CPU 56 switches the display state (“◯” and “×”) for the variation rate of the normal symbol every 0.2 seconds until the end flag is set. With such a speed, the value of the display control data set in the output buffer (for example, 1 indicating “◯” and 0 indicating “x”) is switched every 0.2 seconds. Further, the CPU 56 outputs a normal signal on the normal symbol display 10 by outputting a drive signal in step S22 according to the display control data set in the output buffer.

  Thereafter, the interrupt permission state is set (step S34), and the process is terminated.

  With the above control, in this embodiment, the game control process is started every 4 ms. The game control process corresponds to the processes in steps S21 to S33 (excluding step S29) in the timer interrupt process. In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed.

  When the shifted symbol is stopped and displayed on the first special symbol display 8a or the second special symbol display 8b and the effect display device 9, the variable display state of the effect symbol is started after the variable display of the effect symbol is started. There may be a case where a predetermined combination of effects that does not reach reach is stopped and displayed without reaching the reach state. Such a variable display mode of the effect symbol is referred to as a variable display mode of “non-reach” (also referred to as “normally shift”) in a case where the variable display result is a loss symbol.

  When the shifted symbol is stopped and displayed on the first special symbol display 8a or the second special symbol display 8b and the effect display device 9, the variable display state of the effect symbol is started after the variable display of the effect symbol is started. After reaching the reach state, a reach effect is executed, and a combination of predetermined effect symbols that do not eventually become a jackpot symbol may be stopped and displayed. Such a variable display result of the effect design is referred to as a variable display mode of “reach” (also referred to as “reach out”) when the variable display result is “out of”.

  In this embodiment, when the big win symbol is stopped and displayed on the first special symbol display 8a or the second special symbol display 8b, the reach effect is executed after the variable display state of the effect symbol becomes the reach state. Eventually, the effect symbols are all stopped and displayed in the “left”, “middle”, and “right” symbol display areas 9L, 9C, and 9R on the effect display device 9.

  When “5”, which is a small hit, is stopped and displayed on the first special symbol display 8a or the second special symbol display 8b, the effect display variable display mode is “suddenly probable big hit” on the effect display device 9. In the same manner as in the case where the effect symbol is variably displayed, a predetermined small hit symbol (the same symbol as the sudden probability variation big hit symbol, for example, "135") may be stopped and displayed. The display effect in the effect display device 9 corresponding to the fact that “5”, which is the small hit symbol, is stopped and displayed on the first special symbol display 8a or the second special symbol indicator 8b is referred to as a “small hit” variable display mode. .

  Here, the small win is a hit that is allowed up to a small number of times that the big winning opening is opened compared to the big win (in this embodiment, the opening for 0.1 second is twice). When the small hit game ends, the game state does not change. That is, there is no transition from the probability variation state to the normal state or from the normal state to the certain variation state. In addition, the sudden probability change big hit is allowed up to a small number of times of opening of the big prize opening in the big hit gaming state (in this embodiment, the opening for 0.1 second is twice), but the opening time of the big prize opening is extremely large. It is a big jackpot that is a short jackpot and the game state after the big jackpot game is shifted to a probabilistic state (that is, by doing so, it appears to the player as if it suddenly became a probable state) Is). In other words, in this embodiment, the sudden winning odds and the small wins have the same opening pattern of the big prize opening. By controlling in such a way, if the winning opening is opened twice for 0.1 seconds, it is impossible to recognize whether it is suddenly a big hit or a small hit, so a high probability state for the player (Probable change state) can be expected, and the interest of the game can be improved.

  52 and 53 are flowcharts showing an example of the power-off process in step S20. In the power-off process, the game control microcomputer 560 first checks whether or not a power-off signal is output (whether or not it is turned on) (step S450). If not on, the value of the backup monitoring timer formed in the RAM 55 is cleared to 0 (step S451). If it is on, the value of the backup monitoring timer is incremented by 1 (step S452). If the value of the backup monitoring timer matches the determination value (for example, 2) (step S453), the power supply stop processing after step S454, that is, the preparation processing for power supply stop is executed. That is, the state shifts from the state in which the progress of the game is controlled to the state in which the power supply stop process (the power-off control process) for saving the game state is executed. Note that “formed in the RAM” means an area in the RAM.

  By using the backup monitoring timer and the determination value, if the power-off signal is kept on for a time corresponding to the determination value, the power supply stop process is started. That is, even when the power-off signal is turned on for a moment due to noise or the like, the power supply stop process is not erroneously started. Note that the value of the backup monitoring timer is stored by the backup power source for a predetermined period even when power supply to the gaming machine is stopped. Therefore, in step S8 in the main process, it is possible to confirm that the processing result of the power supply stop process is stored because the value of the backup monitoring timer is the same value as the determination value.

  In the power supply stop process, the game control microcomputer 560 creates parity data (steps S454 to S463). That is, first, clear data (00) is set in the checksum data area (step S454), and the checksum calculation start address corresponding to the start address of the RAM area in which the contents are to be stored even when power supply is stopped is set in the pointer. (Step S455). Further, the number of checksum calculations corresponding to the final address of the RAM area where the contents are to be stored even when the power supply is stopped is set (step S456).

  Next, an exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S457). The calculation result is stored in the checksum data area (step S458), the pointer value is incremented by 1 (step S459), and the value of the checksum calculation count is decremented by 1 (step S460). Then, the processes in steps S457 to S460 are repeated until the value of the checksum calculation count becomes 0 (step S461).

  When the value of the checksum calculation count becomes 0, the game control microcomputer 560 inverts the value of each bit of the contents of the checksum data area (step S462). Then, the inverted data is stored in the checksum data area (step S463). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S471). Thereafter, the built-in RAM 55 cannot be accessed.

  Further, the game control microcomputer 560 sets the head address of the port clear setting table stored in the ROM 54 as a pointer (step S472). In the port clear setting table, the number of processes (the number of output ports to be cleared) is set to the head address, and then the output port address and output value data (clear data: the value of the off state of each bit of the output port) However, the output ports for the number of processes are sequentially set.

  The game control microcomputer 560 loads data at the address pointed to by the pointer (that is, the number of processes) (step S473). Further, the value of the pointer is incremented by 1 (step S474), and the data of the address pointed to by the pointer (that is, the address of the output port) is loaded (step S475). Further, the value of the pointer is incremented by 1 (step S476), and the data of the address pointed to by the pointer (that is, output value data) is loaded (step S477). Then, the output value data is output to the output port (step S478). Thereafter, the number of processes is reduced by 1 (step S479), and if the number of processes is not 0, the process returns to step S474. If the number of processes is 0, that is, if all the output ports to be cleared are cleared, the timer interrupt is stopped (step S481) and the loop process is started. Note that the process of clearing the output port may be executed before the process of creating checksum data. For example, the CPU 56 may execute the output port clear processing in steps S472 to S480 immediately after determining Y in step S453.

  In the loop processing, it is monitored whether or not the power-off signal is turned off (step S482). Then, while the power-off signal is in the ON state (Y in step S482), the process in step S482 is repeatedly executed to stand by.

  On the other hand, when the power-off signal is turned off in step S482 (N in step S482), after setting for a predetermined power-off recovery (step S487), the main process shown in FIG. Return to the beginning. As an example, in the process of step S487, the storage address of the power-off recovery vector table is stored in the stack pointer built in the CPU 56, and the game control timer interrupt process is returned (returned). Here, the power-off recovery vector table may be any table that specifies the head address of the control code (game control program) stored in the ROM 54. When returning from an interrupt process such as the timer interrupt process shown in FIG. 51, the stored data at the address specified by the stack pointer is read as the return address. Thus, after executing the processing of step S487, the CPU 56 can start (restart) the execution of the game control from the head of the control code stored in the ROM 54.

  When the power supply is stopped by the above processing, the power supply stop processing in steps S454 to S481 is executed, and data indicating that the power supply stop processing has been executed (backup monitoring having a determination value). Timer and checksum) are stored in the backup RAM, RAM access is disabled, the output port is cleared, and timer interrupt for executing the game control process is set to disabled.

  In this embodiment, after the processing such as generation of check data and output port clear is completed in the power-off processing, the process proceeds to a power-off waiting loop that repeatedly confirms the input of the power-off signal in step S482. Such a configuration for confirming the input of the power-off signal may not be used. In this case, for example, the watchdog timer (WTD) 506b is set to be activated by the user program, and then the watchdog timer (WTD) 506b is activated when entering the power-off waiting loop. When the power supply is not cut off and the voltage value of the power supply does not drop completely, a reset by a time-out signal from the watchdog timer (WTD) 506b may be generated.

  Also, for example, confirm whether or not a power-off signal is input when turning on the power to the gaming machine, and if it is input, transition to an infinite loop or confirm the input of the power-off signal in the infinite loop, When it is configured to continue the infinite loop until there is no more input, the watchdog timer (WTD) 506b is activated when entering the infinite loop in the same manner as described above, and the same processing is performed. It may be configured.

  If the watchdog timer (WTD) 506b is set to be activated (except for the watchdog timer (WTD) 506b that is activated only in the power-off waiting loop as described above), it is normal. The CPU 56 is programmed to output a signal for clearing the watchdog timer (WTD) 506b so as not to time out when the CPU 56 is operating. Specifically, it is programmed to write a value for clearing in a WDT clear register (not shown) provided in the built-in register area.

  In this embodiment, the RAM 55 is backed up by a backup power source (the contents of the RAM 55 are preserved for a predetermined period even when the power supply to the gaming machine is stopped). In this example, the checksum based on the content of the RAM 55 when the power-off signal is output is stored in the backup area of the RAM 55 together with the value of the backup monitoring timer by the processing of steps S452 to S479. After the power supply to the gaming machine is stopped, when the power supply is restored within a predetermined period, the game control means performs the data stored in the RAM 55 (immediately before the power supply is stopped) by the processing of steps S41 to S44 described above. In accordance with the data indicating the game state that is the control state by the game control means (for example, including the process flag state, the big hit flag state, the probability change flag state, the output port output state, etc.) It is possible to return to the state immediately before the supply is stopped. If the power supply stop period exceeds the predetermined period, the value of the backup monitoring timer and the checksum should be different from the regular values. In this case, the initialization process of steps S10 to S13 is executed. The

  As described above, the power supply stop process (preparation process for stopping the power supply) ensures that the data for returning the gaming state to the state immediately before the power supply stopped is the fluctuation data storage means (in this example) Stored in a part of the RAM 55). Therefore, even if the power is cut off due to a power failure or the like, if the power is restored within a predetermined period, the gaming state can be returned to the state immediately before the power supply is stopped.

  If the power-off signal is turned off, the process returns to step S1. In this case, since data indicating that the power supply stop process has been executed is set, the recovery process of steps S41 to S44 is executed. Therefore, when the power-off signal from the payout control board 37 is turned off after executing the power supply stop process, the process returns to the state of controlling the progress of the game. Therefore, even if a power interruption or the like occurs, the game control process does not stop, and the game control process is automatically continued.

  48 and 50 to 53, the gaming machine operates in this embodiment, so that in this embodiment, a predetermined process (in this example, steps S16 to S19 of the main process shown in FIG. 50). When a predetermined event occurs during execution of the loop processing and the timer interrupt processing of FIG. 51 (input of IAT signal from IAT circuit 506a, input of timeout signal from watchdog timer (WDT) 506b), RAM 55 (backup RAM) ) To initialize the stored contents. Specifically, during the execution of the loop process of steps S16 to S19 of the main process shown in FIG. 50 and the timer interrupt process of FIG. 51, an IAT signal from the IAT circuit 506a or a timeout from the watchdog timer (WDT) 506b When a signal is input, a system reset or a user reset (see steps S1004 and S1014 in FIG. 48) occurs without executing the power-off process shown in FIGS. Then, after a system reset occurs, a security check is executed, and then in step S1007, the mode is shifted to the user mode and the main process shown in FIG. 50 is started again. After a user reset occurs, the user program is updated in step S1015. Returning to the top, the execution of the main process shown in FIG. 50 is started again. However, since neither the backup monitoring timer (or the backup flag) nor the check data is set, the main process shown in FIG. The process proceeds to S10 and the initialization process is executed.

  The “predetermined process” is a process that is executed in a state where the game is possible after the initialization process and the recovery process at the time of power-on to the gaming machine are executed, as described above. Specifically, the loop process of steps S16 to S19 of the main process shown in FIG. 50 and the timer interrupt process of FIG. However, when the power-off process is executed due to the power supply voltage drop, it is excluded from the predetermined process.

  It should be noted that, by operating the gaming machine in the manner shown in FIGS. 48 and 50 to 53, predetermined processing is performed after the power supply stop process (in this example, the power-off process shown in FIGS. 52 and 53) is executed. When an event occurs (IAT signal is input from IAT circuit 506a and timeout signal is input from watchdog timer (WDT) 506b), the control status is processed when power supply is stopped based on the stored contents of RAM 55 (backup RAM). Execute recovery processing to restore to the state when started. Specifically, when the power-off process shown in FIGS. 52 and 53 is executed based on the input of the power-off signal and the loop process of FIG. 53 is executed, the IAT signal 506a is output from the IAT circuit 506a. When a time-out signal is input from the watchdog timer (WDT) 506b (however, when an IAT signal is input from the IAT circuit 506a, a program outside the designated area is being executed for some reason. Therefore, more precisely, this corresponds to the case where the IAT circuit 506a makes an IAT signal after shifting to the power-off process loop process once), and the system reset or user reset (based on the input of the IAT signal or timeout signal) 48 (see steps S1004 and S1014 in FIG. 48). Then, after a system reset occurs, a security check is executed, and then in step S1007, the mode is shifted to the user mode and the main process shown in FIG. 50 is started again. After a user reset occurs, the user program is updated in step S1015. Returning to the top, the execution of the main process shown in FIG. 50 is started again. However, since both the backup monitoring timer (or backup flag) and the check data are set, the main process shown in FIG. In both S7 and S8, it is determined as Y, and the recovery process of steps S41 to S44 is executed.

FIG. 54 is an explanatory diagram showing each software random number used in this embodiment. Each software random number is used as follows. As described above, in this embodiment, a hardware random number output from the 16-bit random number circuit 508b is used for the big hit determination random number (random R) for determining whether or not to win.
(1) Random 1 (MR1): Determines the type of jackpot (normal jackpot, probability variation jackpot, sudden probability variation jackpot described later) (for jackpot type determination)
(2) Random 2 (MR2): The type (type) of the variation pattern is determined (for variation pattern type determination)
(3) Random 3 (MR3): A variation pattern (variation time) is determined (for variation pattern determination)
(4) Random 4 (MR4): Determines whether or not to generate a hit based on a normal symbol (for normal symbol hit determination)
(5) Random 5 (MR5): Determine the initial value of random 4 (for determining the initial value of random 4)

  In this embodiment, the hardware random number extracted from the random number circuit is used only for the jackpot determination random number (random R), and the software random number is used for the other random numbers. It is not limited to what is shown in. For example, in addition to the big hit determination random number (random R), hardware random numbers extracted from the random number circuit may be used for all of random numbers 1 to 5 shown in FIG. Also, hardware random numbers extracted from the random number circuit may be used only for some of the random numbers 1 to 5 shown in FIG. 54, and software random numbers may be used for the rest.

  In this embodiment, the variation pattern is first determined using the variation pattern type determination random number (random 2), and then the variation pattern determined using the variation pattern determination random number (random 3). One of the variation patterns included in the pattern type is determined. Thus, in this embodiment, the variation pattern is determined by a two-stage lottery process.

  The variation pattern type is a group of a plurality of variation patterns according to the characteristics of the variation mode. For example, a plurality of variation patterns are grouped by reach type, and include a variation pattern type including a variation pattern with normal reach, a variation pattern type including a variation pattern with super reach A, and a variation pattern with super reach B. It may be divided into variable pattern types. Further, for example, a plurality of variation patterns are grouped by the number of re-variations of pseudo-continuations, a variation pattern type including a variation pattern without pseudo-ream, a variation pattern type including a variation pattern of one re-variation, It may be divided into a variation pattern type including a variation pattern of two variations and a variation pattern type including a variation pattern of three variations. Further, for example, a plurality of variation patterns may be grouped according to the presence / absence of a specific effect such as a pseudo ream or a slip effect.

  In step S23 in the game control process shown in FIG. 51, the game control microcomputer 560 uses a counter for generating the jackpot type determination random number (1) and the determination random number per normal symbol (4). Count up (add 1). That is, they are determination random numbers, and other random numbers are display random numbers (random 2, random 3) or initial value random numbers (random 5). In addition, in order to improve a game effect, you may use random numbers other than said random number. For example, an initial value determining random number for determining the initial value of the jackpot type determining random number (random 1) may be provided. In this embodiment, a random number generated by hardware incorporated in the game control microcomputer 560 (or hardware external to the game control microcomputer 560) is used as the jackpot determination random number.

  FIG. 55A is an explanatory diagram showing a big hit determination table. The jackpot determination table is a collection of data stored in the ROM 54 and is a table in which a jackpot determination value to be compared with the random R is set. The jackpot determination table includes a normal-time jackpot determination table used in a normal state (a gaming state that is not a probability change state) and a probability change jackpot determination table used in a probability change state. Each numerical value described in the left column of FIG. 55 (A) is set in the normal jackpot determination table, and each numerical value described in the right column of FIG. 55 (A) is set in the probability variation big hit determination table. Is set. The numerical value described in FIG. 55 (A) is the jackpot determination value.

  55B and 55C are explanatory diagrams showing a small hit determination table. The small hit determination table is a collection of data stored in the ROM 54 and is a table in which a small hit determination value to be compared with the random R is set. The small hit determination table includes a small hit determination table (for the first special symbol) used when the variable display of the first special symbol is performed, and a small hit determination table used when the variable display of the second special symbol is performed. (For the second special symbol). Each value described in FIG. 55B is set in the small hit determination table (for the first special symbol), and in the small hit determination table (for the second special symbol), the values shown in FIG. Each numerical value listed is set. Also, the numerical values described in FIGS. 55B and 55C are the small hit determination values.

  Note that it may be determined that a small hit is made only when the variable display of the first special symbol is performed, and the small hit may not be provided when the variable display of the second special symbol is performed. In this case, the small hit determination table for the second special symbol shown in FIG. In this embodiment, when the gaming state is shifted to the probability changing state, the variation display of the second special symbol is mainly executed. Even if the game state is shifted to the probability change state, a small hit will be generated, and if it is configured to produce an effect asking whether or not the probability change will occur, even though the current game state is the probability change state On the contrary, it makes the player feel annoying. Therefore, if it is configured so that the small hit does not occur during the variation display of the second special symbol, if the gaming state is the probability variation state, it is difficult for the small hit to occur and the excessive effect is not given to the probability variation. This can prevent the player from feeling annoyed.

  The CPU 56 extracts the count value of the 16-bit random number circuit 508b at a predetermined time and sets the extracted value as the value of the jackpot determination random number (random R). If it matches any of the jackpot determination values shown in (1), it is determined that the special symbol will be jackpot (15R probability variation jackpot, 7R probability variation jackpot, sudden probability variation jackpot described later). Further, when the big hit determination random number value matches one of the small hit determination values shown in FIGS. 55B and 55C, it is decided to make a small hit for the special symbol. Note that the “probability” shown in FIG. 55A indicates the probability (ratio) of a big hit. In addition, “probabilities” shown in FIGS. 55B and 55C indicate the probability (ratio) of small hits. Further, deciding whether or not to win a jackpot means deciding whether or not to shift to the jackpot gaming state, but the stop symbol in the first special symbol display 8a or the second special symbol display 8b is determined. It also means deciding whether or not to make a jackpot symbol. Further, determining whether or not to make a small hit means determining whether or not to shift to the small hit gaming state, but stopping in the first special symbol display 8a or the second special symbol display 8b. It also means determining whether or not the symbol is to be a small hit symbol.

  In this embodiment, as shown in FIGS. 55B and 55C, when the small hit determination table (for the first special symbol) is used, the small hit is determined at a ratio of 1/300. On the other hand, a case where a small hit is determined at a ratio of 1/3000 when the small hit determination table (second special symbol) is used will be described. Therefore, in this embodiment, when the start winning prize is given to the first start winning opening 13 and the first special symbol variation display is executed, the start winning prize is given to the second starting winning prize slot 14 and the second special symbol is displayed. The ratio determined as “small hit” is higher than when the variable display is executed.

  55D and 55E are explanatory diagrams showing the jackpot type determination tables 131a and 131b stored in the ROM 54. FIG. Among these, FIG. 55 (D) determines the jackpot type using the holding memory based on the game ball having won the first start winning opening 13 (that is, when the first special symbol is displayed in a variable manner). This is a jackpot type determination table (for the first special symbol) 131a. FIG. 55 (E) shows a case where the jackpot type is determined by using the holding memory based on the fact that the game ball has won the second start winning opening 14 (that is, when the variation display of the second special symbol is performed). Is a jackpot type determination table (for the second special symbol) 131b.

  The jackpot type determination tables 131a and 131b, when it is determined that the variable display result is a jackpot symbol, based on the random number (random 1) for determining the jackpot type, This table is referred to in order to determine either “7R probability variation big hit” or “sudden probability variation big hit”. In this embodiment, as shown in FIGS. 55D and 55E, in the big hit type determination table 131a, five determination values are assigned to “suddenly probable big hit” (40 minutes). Is determined to be a sudden probability change big hit at a rate of 5), whereas in the big hit type determination table 131b, one determination value is assigned to "sudden probability change big hit" (a ratio of 1/40) Will suddenly be determined to be a promising big hit). Therefore, in this embodiment, when the start winning prize is given to the first start winning opening 13 and the first special symbol variation display is executed, the start winning prize is given to the second starting winning prize slot 14 and the second special symbol is displayed. Compared with the case where the variable display is executed, the ratio determined as “suddenly probable big hit” is high. Note that “sudden probability variation big hit” is assigned only to the first special symbol jackpot type determination table 131a, and “sudden probability variation big hit” is not assigned to the second special symbol big hit type determination table 131b (ie. It may be determined that “suddenly probable big hit” may be determined only when the variable display of the first special symbol is performed.

  Further, as shown in FIGS. 55D and 55E, in this embodiment, the big hit type determination table 131b is larger than the big hit type determination table 131a with respect to “15R probability variation big hit”. Judgment value of is assigned. Therefore, in this embodiment, when a start winning prize is given to the second starting prize opening 14 or the third starting prize opening 17 and the variation display of the second special symbol is executed, the start winning prize is given to the first start prize opening 13. As compared with the case where the variation display of the first special symbol is executed, the ratio of advantageous “15R probability variation big hit” is high.

  In this embodiment, the case where the variation display of the second special symbol is executed is more advantageous than the case where the variation display of the first special symbol is executed. The allocation of the type determination table 131a and the jackpot type determination table 131b is the same, and the advantage is the same between the case of performing the variable display of the first special symbol and the case of performing the variable display of the second special symbol. May be.

  In this embodiment, as shown in FIGS. 55 (D) and 55 (E), there are “15R probability variation big hit”, “7R probability variation big hit” and “sudden probability variation big hit” as the big hit types. In this embodiment, the case where the number of rounds executed in the jackpot game is three types of 15 rounds, 7 rounds, and 2 rounds, but the number of rounds executed in the jackpot game is the number of rounds executed in this implementation. It is not limited to those shown in the form. For example, a 10R probability variable jackpot that is controlled for a 10-round jackpot game and a 5R probability variable jackpot that is controlled for a 5-round jackpot game may be provided. In this embodiment, there are three types of jackpot types: “15R probability variation big hit”, “7R probability variation big hit”, and “sudden probability variation big hit”. The above jackpot type may be provided. Conversely, the jackpot type may be less than three types, for example, only two types may be provided as the jackpot type. In this embodiment, only the probability variation big hit that is shifted to the probability change state after the big hit game is provided as the big hit type. You may make it provide.

  The “15R probability variable big hit” is a big hit that is controlled to the 15-round big hit gaming state, and is shifted to the probability changed state after the big hit gaming state is finished (in this embodiment, the state is shifted to the probability changed state and the time reduction state is entered. (See step S166 described later). Then, after shifting to the probability changing state, when the variable display is finished a predetermined number of times (70 times in this embodiment), the probability changing state (and the time shortening state) is finished (see steps S167 and S141 to S144). Even before the variable display is finished a predetermined number of times, even if the next big hit occurs, the probability variation state (and the time reduction state) is terminated (see step S132).

  The “7R probable big hit” is a big hit that is controlled to a seven-round big hit gaming state and shifts to the probable change state after the big hit gaming state is finished (in this embodiment, the time is changed to the probable change state and the time is shortened). The state is also shifted to (see step S166 described later). Then, after shifting to the probability changing state, when the variable display is finished a predetermined number of times (70 times in this embodiment), the probability changing state (and the time shortening state) is finished (see steps S167 and S141 to S144). Even before the variable display is finished a predetermined number of times, even if the next big hit occurs, the probability variation state (and the time reduction state) is terminated (see step S132).

  The “sudden probability change big hit” is the number of times that the special winning opening is less than the “15R probability change big hit” or “7R probability change big hit” (in this embodiment, the opening for 0.1 seconds is twice). The jackpot allowed up to. In other words, when “suddenly promising big hit”, the game is controlled to a two round big hit gaming state. Also, in the case of “15R probability variation big hit” and “7R probability variation big hit”, the opening time of the big winning opening per round is as long as 29 seconds, whereas in “sudden probability changing big hit”, the big winning opening is released per round The time is as short as 0.1 seconds, and it is almost impossible to expect a game ball to win a big prize during the big hit game. In this embodiment, after the sudden probability change big hit gaming state is finished, the state is changed to the probability change state (in this embodiment, the state is changed to the probability change state and also to the short time state. See step S166 described later. ). Then, after shifting to the probability changing state, when the variable display is finished a predetermined number of times (70 times in this embodiment), the probability changing state (and the time shortening state) is finished (see steps S167 and S141 to S144). Even before the variable display is finished a predetermined number of times, even if the next big hit occurs, the probability variation state (and the time reduction state) is terminated (see step S132).

  As described above, in this embodiment, even in the case of “small hit”, the big winning opening is opened twice for 0.1 seconds, and the big hit gaming state by “suddenly probable big hit” Similar control is performed. In the case of “small hit”, the game state does not change after the opening of the big winning opening twice, and the game state before “small hit” is maintained. By doing so, it is made impossible to recognize whether it is “suddenly promising big hit” or “small hit”, and the interest of the game is improved. In addition, when it is configured such that the big hit types are all probable big hits as in this embodiment, the small hits need not be provided. In addition, when the big hit types are all probabilistic big hits as in this embodiment, a short hit state (high base state) can be obtained simply by shifting to a probable state (high probability state). It is preferable to provide a sudden probability variation big hit without the parenthesis (the opening pattern of the big prize opening is also the same in the case of sudden probability variation big hit and small hit).

  The jackpot type determination tables 131a and 131b are numerical values to be compared with a random value of 1, which corresponds to each of “15R probability variation big hit”, “7R probability variation big hit”, and “sudden probability variation big hit” (big hit type Judgment value) is set. When the value of random 1 matches any of the jackpot type determination values, the CPU 56 determines the jackpot type as a type corresponding to the matched jackpot type determination value.

  56 and 57 are flowcharts showing an example of a special symbol process (step S26) program executed by the game control microcomputer 560 (specifically, the CPU 56) mounted on the main board 31. As described above, in the special symbol process, a process for controlling the first special symbol display 8a or the second special symbol display 8b and the special winning opening is executed. In the special symbol process, the CPU 56 turns on the first start winning opening 13 when the first start opening switch 13a for detecting that the game ball has won the first start winning opening 13 is turned on. If a winning has occurred, a first start port switch passage process is executed (steps S311 and S312). If the second start port switch 14a for detecting that the game ball has won the second start winning port 14 is turned on, that is, the start winning to the second start winning port 14 has occurred. Then, the second start port switch passage process is executed (steps S313, S314). Then, any one of steps S300 to S310 is performed. If the first start winning port switch 13a or the second start port switch 14a is not turned on, any one of steps S300 to S310 is performed according to the internal state.

  The processes in steps S300 to S310 are as follows.

  Special symbol normal processing (step S300): Executed when the value of the special symbol process flag is zero. When the game control microcomputer 560 is in a state where variable display of the special symbol can be started, the game control microcomputer 560 checks the number of numerical data stored in the reserved storage number buffer (total number of reserved storage). The stored number of numerical data stored in the pending storage number buffer can be confirmed by the count value of the total pending storage number counter. In addition, if the count value of the total pending storage number counter is not 0, a lottery process using a big hit determination random number (random R) is executed to display a variable display result of the first special symbol or the second special symbol. Whether or not to be a big hit (or small hit). In case of big hit, set big hit flag. In the case of a small hit, a small hit flag is set. Then, the internal state (special symbol process flag) is updated to a value (1 in this example) according to step S301. The jackpot flag is reset when the jackpot game ends. The small hit flag is reset when the small hit game ends.

  Fluctuation pattern setting process (step S301): This process is executed when the value of the special symbol process flag is 1. Also, the variation pattern is determined, and the variation time in the variation pattern (variable display time: the time from the start of variable display until the display result is derived and displayed (stop display)) is defined as the variation display variation time of the special symbol. Decide to do. Also, a variable time timer for measuring the special symbol variable time is started. Then, the internal state (special symbol process flag) is updated to a value (2 in this example) corresponding to step S302.

  Display result designation command transmission process (step S302): This process is executed when the value of the special symbol process flag is 2. Control for transmitting a display result designation command to the production control microcomputer 100 is performed. Then, the internal state (special symbol process flag) is updated to a value (3 in this example) corresponding to step S303.

  Special symbol changing process (step S303): This process is executed when the value of the special symbol process flag is 3. When the variation time of the variation pattern selected in the variation pattern setting process elapses (the variation time timer set in step S301 times out, that is, the variation time timer value becomes 0), the design control microcomputer 100 determines the symbol. Control to transmit the specified command is performed, and the internal state (special symbol process flag) is updated to a value (4 in this example) corresponding to step S304. The effect control microcomputer 100 controls the effect display device 9 to stop the fourth symbol when receiving the symbol confirmation designation command transmitted by the game control microcomputer 560.

  Special symbol stop process (step S304): executed when the value of the special symbol process flag is 4. When the big hit flag is set, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. If the small hit flag is set, the internal state (special symbol process flag) is updated to a value (8 in this example) corresponding to step S308. If neither the big hit flag nor the small hit flag is set, the internal state (special symbol process flag) is updated to a value corresponding to step S300 (in this example, 0). In this embodiment, as will be described later, a special symbol display control for stopping and displaying a special symbol stop symbol in the special symbol display control process based on the fact that the value of the special symbol process flag is 4. The data is set in the output buffer for setting the special symbol display control data, and the special symbol stop symbol is actually stopped and displayed according to the setting contents of the output buffer in the display control processing in step S22.

  Preliminary winning opening opening process (step S305): This is executed when the value of the special symbol process flag is 5. In the pre-opening process for the big prize opening, control for opening the big prize opening is performed. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized and the solenoid 21 is driven to open the big prize opening. Also, the execution time of the special prize opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value corresponding to step S306 (6 in this example). The pre-opening process for the big winning opening is executed for each round, but when the first round is started, the pre-opening process for the big winning opening is also a process for starting the big hit game.

  Large winning opening opening process (step S306): This process is executed when the value of the special symbol process flag is 6. A control for transmitting a presentation control command for round display during the big hit gaming state to the microcomputer 100 for the presentation control, a process for confirming that the closing condition for the big prize opening is satisfied, and the like are performed. If the closing condition for the special prize opening is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. When all the rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S307 (7 in this example).

  Big hit end process (step S307): executed when the value of the special symbol process flag is 7. Control is performed to cause the microcomputer 100 for effect control to perform display control for notifying the player that the big hit gaming state has ended. In addition, a process for setting a flag indicating a gaming state (for example, a probability change flag or a time reduction flag) is performed. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  Small hit release pre-processing (step S308): This process is executed when the value of the special symbol process flag is 8. In the pre-opening process for small hits, control is performed to open the big prize opening. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized and the solenoid 21 is driven to open the big prize opening. Also, the execution time of the special prize opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value (9 in this example) corresponding to step S309. It should be noted that although the pre-opening process for small hits is executed for each round, the pre-opening process for small hits is also a process for starting a small hit game when starting the first round.

  Small hit release processing (step S309): executed when the value of the special symbol process flag is 9. Processing to confirm the establishment of the closing condition of the big prize opening is performed. If the closing condition for the big prize opening is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to a value corresponding to step S308 (8 in this example). When all rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S310 (in this example, 10 (decimal number)).

  Small hit end process (step S310): executed when the value of the special symbol process flag is 10. Control is performed to cause the microcomputer 100 for effect control to perform display control for notifying the player that the small hit gaming state has ended. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  FIG. 58 is a flowchart showing the start-port switch passing process in steps S312 and S314. Among these, FIG. 58 (A) is a flowchart showing the first start port switch passing process of step S312. FIG. 58B is a flowchart showing the second start port switch passing process in step S314.

  First, the first start port switch passing process will be described with reference to FIG. In the first start port switch passing process executed when the first start port switch 13a is in the ON state, the CPU 56 determines whether or not the first reserved memory number has reached the upper limit value (specifically, the first hold port number). Whether or not the value of the first reserved memory number counter for counting the memory number is 4 is confirmed (step S201A).

  If the first reserved memory number has not reached the upper limit value, the CPU 56 increases the value of the first reserved memory number counter by 1 (step S202A), and the value of the total reserved memory number counter for counting the total reserved memory number Is increased by 1 (step S203A).

  Next, the CPU 56 extracts a value from each counter for generating a software random number (a jackpot type determination random number (random 1), a variation pattern type determination random number (random 2), and a variation pattern determination random number (random 3)). (Step S204A). Further, the CPU 56 extracts numerical data as a big hit determination random number (random R) from the RL0 hard latch random value register 0 (RL0HV0) used by the 16-bit random number circuit 508b of the channel 0 (step S205A).

  As already described with reference to FIG. 25, the RL0 hard latch random value register based on the signal (latch signal) from any terminal depending on the setting contents of bits 2-0 of the RL0 hard latch select register 0 (RL0LS0). Whether to latch the random value to 0 (RL0HV0) is set. Further, in this embodiment, it is assumed that the detection signal from the first start port switch 13a is inputted as a latch signal to the set terminal, and the start winning to the first start winning port 13 has occurred. The random number value can be latched in the RL0 hard latch random value register 0 (RL0HV0) at the timing.

  Then, the CPU 56 executes processing for storing the extracted software random numbers and jackpot determination random number (random R) in the storage area in the first reserved storage buffer (see FIG. 59) (step S206A). In addition, the random number for random pattern determination (random 3) is not extracted in the first start port switch passing process (at the time of start winning) and stored in the storage area in advance, but is extracted at the start of the variation of the first special symbol. You may do it. For example, the game control microcomputer 560 may directly extract a value from a variation pattern determination random number counter for generating a variation pattern determination random number (random 3) in a variation pattern setting process described later.

  FIG. 59 is an explanatory diagram showing a configuration example of an area (holding storage buffer) for storing random numbers and the like corresponding to holding storage. As shown in FIG. 59, a storage area corresponding to the upper limit value (4 in this example) of the first reserved storage number is secured in the first reserved storage buffer. In addition, a storage area corresponding to the upper limit value of the second reserved storage number (4 in this example) is secured in the second reserved storage buffer. In this embodiment, the first reserved storage buffer and the second reserved storage buffer include a random R (big hit determination random number) that is a hardware random number, a big hit type determination random number (random 1) that is a software random number, a variation A random number for pattern type determination (random 2) and a random number for variation pattern determination (random 3) are stored. The first reserved storage buffer and the second reserved storage buffer are formed in the RAM 55.

  Then, the CPU 56 performs control to transmit a first reserved memory number addition designation command designating that the first reserved memory number has increased by 1 to the effect control microcomputer 100 (step S207A).

  If the first reserved storage number has reached the upper limit (Y in step S201A), the CPU 56 extracts numerical data from the RL0 hard latch random value register 0 (RL0HV0) (step S208A), and the extracted numerical data (random number) ) Is not stored, and the first start port switch passing process is terminated. That is, in this embodiment, bit 3 of RL0 hard latch select register 0 (RL0LS0) in the program management area shown in FIG. 25 is set to “0”, and a value is read from RL0 hard latch random number register 0 (RL0HV0). Otherwise, it is assumed that the next value cannot be latched. Therefore, even when the first reserved storage number reaches the upper limit value, the CPU 56 performs only the process of extracting numerical data from the RL0 hard latch random number value register 0 (RL0HV0) (until the value is stored). RL0 hard latch random value register 0 (RL0HV0) can latch the next value.

  Note that bit 3 of RL0 hard latch select register 0 (RL0LS0) is set to “1” and the next value can be latched without reading the value from RL0 hard latch random value register 0 (RL0HV0). Also good. In such a case, the process of step S208A becomes unnecessary.

  Next, the second start port switch passing process will be described with reference to FIG. In the second start port switch passing process executed when the second start port switch 14a is in the ON state, the CPU 56 determines whether or not the second reserved memory number has reached the upper limit value (specifically, the second hold port number). It is confirmed whether or not the value of the second reserved storage number counter for counting the stored number is 4) (step S201B).

  If the second reserved memory number has not reached the upper limit value, the CPU 56 increases the value of the second reserved memory number counter by 1 (step S202B), and the value of the aggregate reserved memory number counter for counting the total reserved memory number Is increased by 1 (step S203B).

  Next, the CPU 56 extracts a value from each counter for generating a software random number (a jackpot type determination random number (random 1), a variation pattern type determination random number (random 2), and a variation pattern determination random number (random 3)). (Step S204B). Further, the CPU 56 extracts numerical data as a jackpot determination random number (random R) from the RL1 hard latch random value register 0 (RL1HV0) used by the 16-bit random number circuit 508b of the channel 1 (step S205B).

  As already described in FIG. 27, the RL1 hard latch random value register 0 based on the signal (latch signal) from either terminal according to the setting contents of bits 2-0 of the RL1 hard latch selection register (RL1LS). Whether or not to latch a random value in (RL1HV0) is set. Further, in this embodiment, it is assumed that the detection signal from the second start port switch 14a is input as a latch signal to the set terminal, and the start winning to the second start winning port 14 occurs. The random number value can be latched in the RL1 hard latch random number value register 0 (RL1HV0) at the timing.

  Then, the CPU 56 executes processing for storing the extracted software random numbers and jackpot determination random number (random R) in the storage area in the second reserved storage buffer (see FIG. 59) (step S206B). Note that the random number for random pattern determination (random 3) is not extracted in the second start port switch passing process (at the time of start winning) and stored in the storage area in advance, but is extracted at the start of the variation of the second special symbol. You may do it. For example, the game control microcomputer 560 may directly extract a value from a variation pattern determination random number counter for generating a variation pattern determination random number (random 3) in a variation pattern setting process described later.

  Then, the CPU 56 performs control to transmit a second reserved memory number addition designation command designating that the second reserved memory number has increased by 1 to the effect control microcomputer 100 (step S207B).

  If the second reserved storage number has reached the upper limit (Y in step S201B), the CPU 56 extracts numerical data from the RL1 hard latch random value register 0 (RL1HV0) (step S208B), and the extracted numerical data (random number) ) Is not stored, and the second start port switch passing process is terminated. That is, in this embodiment, bit 3 of the RL1 hard latch selection register (RL1LS) in the program management area is set to “0” (corresponding to the case where n = 1 in FIG. 27), and the RL1 hard latch random value It is assumed that the next value cannot be latched unless a value is read from register 0 (RL1HV0). Therefore, even when the second reserved storage number reaches the upper limit value, the CPU 56 performs only the process of extracting numerical data from the RL1 hard latch random number value register 0 (RL1HV0) (until the value is stored). RL1 hard latch random value register 0 (RL1HV0) can latch the next value.

  Note that bit 3 of RL1 hard latch select register 0 (RL1LS) is set to “1” and the next value can be latched without reading the value from RL1 hard latch random value register 0 (RL1HV0). Also good. By doing so, the process of step S208B is not necessary.

  Further, in this embodiment, by executing the processing of steps S205A and S205B, the random value register that is different between the case of executing the variable display of the first special symbol and the case of executing the variable display of the second special symbol. A random number value is extracted from and stored. By doing so, for example, the change display of the first special symbol is executed by changing the start value of random number update, changing the setting of changing the random number sequence, or changing the setting of the random number maximum value. The random number value can be made difficult to synchronize between the case where it is performed and the case where the variation display of the second special symbol is executed, and it is difficult to perform an act such as illegally generating a big hit aiming at a predetermined random number update timing. .

  In this embodiment, the random number value is extracted from the different channels (channel 0 and channel 1 in this example) of the 16-bit random number circuit 508b, and the first special symbol variation display is executed. Although the case where the random number value register for extracting the random number is different from the case where the special symbol variation display is executed is shown, it is not limited to the mode shown in this embodiment. For example, even in the same channel of the 16-bit random number circuit 508b, from different hard latch random number value registers used in the same channel (for example, RL0 hard latch random number value register 0 (RL0HV0) and RL0 hard latch random number value of the same channel 0) By extracting the random number value (from the register 1 (RL0HV1)), the random number value register for extracting the random number is different between the case where the variation display of the first special symbol is executed and the case where the variation display of the second special symbol is executed. It may be allowed.

  In this embodiment, the case where the random number value is extracted from the hard latch random value register has been described. However, for example, the random value may be extracted from the soft latch random value register. Even in this case, the first special symbol can be obtained by extracting random values from different channels of the 16-bit random number circuit 508b or by extracting random values from different soft latch random number registers even in the same channel. The random number value register for extracting random numbers may be made different between the case where the variable display is executed and the case where the variable display of the second special symbol is executed.

  In this embodiment, the case where the random value is extracted from the 16-bit random number circuit 508b has been described. However, for example, the random value may be extracted from the 8-bit random number circuit 508a. Even in this case, a random value is extracted from a different channel of the 8-bit random number circuit 508a, or a random value is extracted from a different hard latch random value register or soft latch random value register even in the same channel. Thus, the random number value register for extracting random numbers may be different between the case where the variable display of the first special symbol is executed and the case where the variable display of the second special symbol is executed.

  In this embodiment, as already described, the game control microcomputer 560 executes steps S1001 and S1011 when the power to the gaming machine is turned on, and performs settings related to the random number circuits 508a and 508b in hardware. Then, during the execution of the user program, the random number extraction process of steps S205A and S205B is executed in the first start port switch passage process (see step S312) and the second start port switch passage process (see step S314). Therefore, in this embodiment, the setting relating to the monitoring of the random number circuit is performed before the timing of extracting the numerical data (random number value) from the random number circuit.

  Next, the special symbol stop process in the special symbol process will be described. FIG. 60 is a flowchart showing the special symbol stop process (step S304) in the special symbol process. In the special symbol stop process, the CPU 56 checks whether or not the big hit flag is set (step S131). The jackpot flag is set when it is determined that the jackpot is in the special symbol normal process. If the big hit flag is set, the CPU 56 resets the probability variation flag indicating the probability variation state and the probability variation counter indicating the number of times the special symbol can be varied in the probability variation state if the flag is set (step). S132). Further, the CPU 56 performs control to transmit a big hit start designation command to the effect control microcomputer 100 (step S134). Specifically, when the type of jackpot is “15R probability variation jackpot” or “7R probability variation jackpot”, a jackpot start designation command is transmitted. When the big hit type is sudden probability change big hit, a small hit / sudden probability change big hit start designation command is transmitted. Whether the type of jackpot is “15R probability variation big hit”, “7R probability variation big hit” or “sudden probability variation big hit” is data indicating the big hit type stored in the RAM 55 (stored in the big hit type buffer). Data).

  In addition, a value corresponding to the jackpot display time (a time for which the effect display device 9 notifies that the jackpot has occurred, for example) is set in the jackpot display time timer (step S135). Also, the number of times of opening the winning prize opening counter (for example, “15R probability variation big hit” is 15 times, “7R probability variation big hit” is 7 times, and “sudden probability variation big hit” is 2 times. ) Is set (step S136). The round time per round in the big hit game is also set. Specifically, 0.1 seconds is set as the round time in the case of sudden probability variation big hit, and 29 seconds is set as the round time in the case of 15R probability variation big hit or 7R probability variation big hit. Then, the value of the special symbol process flag is updated to a value corresponding to the pre-winner opening pre-processing (step S305) (step S137).

  On the other hand, if the big hit flag is not set in step S131, the CPU 56 checks whether or not the value of the probability variation counter indicating the number of possible variations of the special symbol in the probability variation state is 0 (step S141). If the value of the probability variation counter is not 0, the CPU 56 decrements the value of the probability variation counter by −1 (step S142). When the value of the probability variation counter after subtraction becomes 0 (step S143), the CPU 56 resets the probability variation flag (step S144).

  Next, the CPU 56 checks whether or not the small hit flag is set (step S145). The small hit flag is set when it is determined that a small hit is made in the special symbol normal process. If the small hit flag is set, the CPU 56 transmits a small hit / suddenly probable big hit start designation command to the effect control microcomputer 100 (step S146). Further, a value corresponding to the small hit display time (for example, a time when the effect display device 9 notifies that the small hit has occurred) is set in the small hit display time timer (step S147). Further, the number of times of opening (for example, 2 times) is set in the special winning opening opening number counter (step S148). In addition, the opening time per time of the big winning opening in the small hit game is set. Specifically, 0.1 seconds which is the same as the round time for the sudden probability change big hit is set as the opening time for one big winning opening in the small hit game. Then, the value of the special symbol process flag is updated to a value corresponding to the small hit start pre-processing (step S308) (step S149).

  If the small hit flag is not set (N in step S145), the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol normal process (step S300) (step S150).

  Next, the jackpot end process in the special symbol process will be described. FIG. 61 is a flowchart showing the jackpot end process (step S307) in the special symbol process. In the jackpot end process, the CPU 56 checks whether or not the jackpot end display timer is set (step S160). If the jackpot end display timer is set, the process proceeds to step S164. If the jackpot end display timer is not set, the jackpot flag is reset (step S161), and control for transmitting a jackpot end designation command is performed (step S162). Here, if it is “15R probability variation big hit” or “7R probability variation big hit”, a big hit end designation command is transmitted, and if it is “sudden probability variation big hit”, a small hit / sudden probability sudden variation big hit end designation command is transmitted. To do. Then, a value corresponding to the display time corresponding to the time during which the big hit end display is performed in the effect display device 9 (big hit end display time) is set in the big hit end display timer (step S163), and the processing is ended.

  In step S164, 1 is subtracted from the value of the big hit end display timer (step S164). Then, the CPU 56 checks whether or not the value of the jackpot end display timer is 0, that is, whether or not the jackpot end display time has elapsed (step S165). If not, the process ends.

  If the big hit end display time has elapsed (Y in step S165), the CPU 56 sets the probability variation flag and shifts to the probability variation state (step S166). In this embodiment, when the probability variation flag is set, the probability variation state is controlled and the time-short state (high base state) is also controlled. Further, the CPU 56 sets a predetermined number of times (in this example, 70 times) in the probability variation counter (step S167).

  It is also possible to set a time reduction flag indicating that the time reduction state is set so that the probability variation state management and the time reduction state management are performed separately. Further, in this embodiment, after the big hit game is finished and the state is shifted to the probability variation state and the time reduction state, when the variation display of the same number of times (70 times in this example) is terminated, both the probability variation state and the time reduction state are terminated. Although the case has been shown, the number of end times in the probability variation state may be different from the number of end times in the time reduction state.

  Then, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol normal process (step S300) (step S170).

  Next, the normal symbol process (step S28) executed by the game control microcomputer 560 (specifically, the CPU 56) will be described. FIG. 62 is a flowchart showing an example of the normal symbol process. In the normal symbol process, when detecting that the game ball has passed through the gate 32 and the gate switch 32a is turned on (step S511), the CPU 56 executes a gate switch passage process (step S512). Then, the CPU 56 executes any one of the processes shown in steps S500 to S503 according to the value of the normal symbol process flag.

  Gate switch passage processing (step S512): The CPU 56 checks whether or not the count value (gate passage storage number) of the gate passage storage counter has reached the maximum value ("4" in this example). If the maximum value has not been reached, the count value of the gate passage storage counter is incremented by one. Note that the LED of the normal symbol storage memory display 41 is turned on according to the value of the gate passage storage counter. Then, the CPU 56 performs processing for extracting the value of the random number for normal symbol determination (random 4) and storing it in the storage area (normal symbol determination buffer) corresponding to the value of the number of passages through the gate.

  Normal symbol normal processing (step S500): The CPU 56 can start the variation of the normal symbol (for example, when the value of the normal symbol process flag is a value indicating step S500, specifically, the normal symbol When the display 10 does not display the change of the normal symbol and when the variable winning ball apparatus 15 is not in the open / close operation based on the normal symbol display 10 having been derived and displayed) Check the memory count value. Specifically, the count value of the gate passing memory number counter is confirmed. If the gate passing memory number is not 0, it is determined whether or not to win (whether or not to stop the normal symbol as a winning symbol). Then, the normal symbol variation time is set in the normal symbol process timer, and the timer is started. Then, the value of the normal symbol process flag is updated to a value (specifically “1”) indicating the normal symbol variation process (step S501).

  Normal symbol variation processing (step S501): The CPU 56 checks whether or not the normal symbol process timer has timed out, and if it has timed out, stops the variation of the normal symbol on the normal symbol display 10 and sets the normal symbol process timer to normal. Set the symbol stop symbol display time and start the timer. Then, the value of the normal symbol process flag is updated to a value (specifically “2”) indicating the normal symbol stop process (step S502).

  Normal symbol stop process (step S502): The CPU 56 checks whether or not the normal symbol process timer has timed out, and if it has timed out, checks whether the stop symbol of the normal symbol is a winning symbol. If it is not a winning symbol (if it is a missing symbol), the value of the normal symbol process flag is updated to a value (specifically “0”) indicating the normal symbol normal process (step S500). On the other hand, if the stop symbol of the normal symbol is a winning symbol, the normal electric accessory operating time is set in the normal symbol process timer, and the timer is started. In addition, it is confirmed whether or not the current gaming state is a probability variation state. 15) Select the opening pattern, and if it is not the probability variation state (that is, if it is in the low base state), select the opening pattern of the ordinary electric accessory (variable winning ball apparatus 15) in the low base state and select it. Set the open pattern. Then, the value of the normal symbol process flag is updated to a value (specifically “3”) indicating the normal electric accessory operation processing (step S503).

  Normal electric accessory operation processing (step S503): The CPU 56 opens the normal electric accessory with the set release pattern on the condition that the normal symbol process timer has not timed out (opening / closing of the variable winning ball apparatus 15). Execute the normal electric accessory release pattern process. In this embodiment, it is assumed that the variable payball apparatus 15 has a longer open period in the probability variation state (ie, the high base state) than in the low base state. When the normal symbol process timer times out, the value of the normal symbol process flag is updated to a value (specifically, “0”) indicating the normal symbol normal process (step S500).

  Next, a special symbol display control process (step S33) executed by the game control microcomputer 560 (specifically, the CPU 56) mounted on the main board 31 will be described (a flowchart or the like is not shown). In the special symbol display control process, the CPU 56 checks whether or not the value of the special symbol process flag is 3 (step S3201). If the value of the special symbol process flag is 3 (that is, if the special symbol variation processing is being executed), the CPU 56 sets the special symbol display control data for special symbol variation display for setting the special symbol display control data. Processing for setting or updating the output buffer is performed (step S3202). In this case, the CPU 56 sets or updates special symbol display control data for performing variable display of the special symbol (the first special symbol or the second special symbol) indicated by the special symbol pointer. For example, if the fluctuation speed is 1 frame / 0.2 seconds, the value of the special symbol display control data set in the output buffer is incremented by 1 every time 0.2 seconds elapse. After that, display control processing (see step S23) is executed, and a drive signal is output to the special symbol displays 8a and 8b according to the contents of the output buffer for setting the special symbol display control data. The special symbol display on the special symbol indicators 8a and 8b is executed.

  If the value of the special symbol process flag is not 3, the CPU 56 checks whether or not the value of the special symbol process flag is 4 (step S3203). If the value of the special symbol process flag is 4 (that is, when the special symbol process is shifted to the special symbol stop process), the CPU 56 stops the special symbol stop symbol set in the special symbol normal process. Processing for setting the display control data in the output buffer for setting the special symbol display control data is performed (step S3204). In this case, the CPU 56 sets special symbol display control data for stopping and displaying the stop symbol of the special symbol (the first special symbol or the second special symbol) indicated by the special symbol pointer. After that, display control processing (see step S23) is executed, and a drive signal is output to the special symbol displays 8a and 8b according to the contents of the output buffer for setting the special symbol display control data. The special symbol stop symbols are stopped and displayed on the special symbol indicators 8a and 8b. In addition, since the setting data is not changed after the processing of step S3204 is executed and the special symbol display control data for stopping symbol display is set, the latest special symbol display control data is displayed in the display control processing of step S23. Based on this, the latest stop symbol is stopped and displayed until the next variable display is started. If the value of the special symbol process flag is 2 or 3 in step S3201 (that is, if either the display result designation command transmission process or the special symbol variation process), the special symbol variation display is performed. The special symbol display control data may be updated. In this case, the display result designation command transmission process also varies in order to prevent a deviation between the variation time recognized on the game control microcomputer 560 side and the variation time recognized on the effect control microcomputer 100 side. What is necessary is just to comprise so that 1 may subtract a time timer.

  In this embodiment, the special symbol display control data is set in the output buffer according to the value of the special symbol process flag. However, in the special symbol process, the start flag is set at the start of the variation of the special symbol. In addition, an end flag may be set at the end of the variation of the special symbol. In the special symbol display control process (step S33), the CPU 56 starts updating the value of the special symbol display control data based on the start flag being set, and based on the end flag being set. Thus, special symbol display control data for stopping and displaying the stop symbol may be set.

  Next, the winning order abnormality notification process (step S21a) executed by the game control microcomputer 560 (specifically, the CPU 56) will be described. FIG. 63 is a flowchart showing the winning order abnormality notifying process in step S21a. In the winning order abnormality notification process, the game control microcomputer 560 (specifically, the CPU 56) sets the second start port monitoring buffer corresponding to the second start winning port 14 in the addition buffer (step S250). The first start port monitoring buffer corresponding to the first start winning port 13 is set in the clear buffer (step S251).

  The first start port monitoring buffer and the second start port monitoring buffer are formed in the RAM 55 in the same manner as the addition buffer and the clear buffer. ) A predetermined value (1 in this example) is added to the stored value. The addition buffer is used to set the set start port monitoring buffer as an addition target of a predetermined value (1 in this example). The clear buffer is used to clear the set start port monitoring buffer (in this example, the stored value is set to 0). In this embodiment, the expression that the start port monitoring buffer is set in the addition buffer or the clear buffer is used. For example, the first start port monitoring buffer or the second start port monitoring is used in the addition buffer or the clear buffer. This is realized by setting a pointer for specifying the buffer for use.

  Next, the CPU 56 checks whether or not the first start port switch is in an on state (step S252). If the first start port switch is in an on state, the set contents of the addition buffer and the clear buffer are switched. (Step S253). That is, in step S253, the CPU 56 sets the first start port monitoring buffer in the addition buffer, and sets the second start port monitoring buffer in the clear buffer. In step S253, for example, replacement can be performed by executing one instruction (for example, EX instruction) for exchanging values.

  In this embodiment, the CPU 56 sets the second start port monitoring buffer in the addition buffer and the first start port monitoring buffer in the clear buffer in steps S250 and S251 (hereinafter, also referred to as a temporary set). If the start port switch is on (that is, if the start port monitoring buffer corresponding to the start port where the game ball has won is not set in the addition buffer (Y in step S252)), the addition buffer is cleared in step S253. The set contents of the buffer are switched (if the start port monitoring buffer corresponding to the start port where the game ball has won is set in the addition buffer, the set content is not replaced). As described above, the first start port monitoring buffer and the second start port monitoring buffer are temporarily set in the addition buffer and the clear buffer, and the start port monitoring buffer corresponding to the start port where the game ball has won is added to the addition buffer. If it is not set, the start port monitoring buffer corresponding to the start port (for example, the first start winning port 13) where the game ball has won is added, by exchanging the set contents of the addition buffer and the clear buffer. The start port monitoring buffer corresponding to the start port (for example, the second start winning port 14) can be set as a clear target. Therefore, for example, when a winning is continuously generated at the same start port, the corresponding start port monitoring buffer is continuously set as an addition target, and the start port monitoring buffer corresponding to the other start port is continuously set. And set as a clearing target. In addition, when a winning opening different from the previous winning opening is won, the starting opening monitoring buffer set as the addition target last time is set as the clearing object, and the starting opening monitoring buffer set as the previous clearing object is set. Is set as the addition target. Note that replacing the set contents of the addition buffer and the clear buffer only requires that the set contents (for example, a pointer) are finally switched (before executing step S254), and data indicating a pointer once during the processing. May be stored in other areas. In other words, it is not limited to directly replacing the set contents of the addition buffer and the set contents of the clear buffer, but after temporarily storing the set contents of the addition buffer and the set contents of the clear buffer (or only one of them) in another area, It may be replaced.

  In this embodiment, the second start port monitoring buffer is provisionally set in the addition buffer and the first start port monitoring buffer is temporarily set in the clear buffer in steps S250 and S251. You may make it set temporarily. In this case, in step S252, it is confirmed whether or not the second start port switch is in the on state. If it is in the on state, the process may proceed to step S253.

  When the set contents of the addition buffer and the clear buffer are exchanged in step S253, the CPU 56 adds 1 to the addition buffer and loads the addition buffer (step S254). Further, the CPU 56 sets clear data (0 in this example) and stores it in the clear buffer (step S255). That is, in step S254, a predetermined value (1 in this example) is added to the value stored in the start port monitoring buffer set in the addition buffer, and in step S255, the start port monitoring buffer set in the clear buffer. The value stored in is cleared (to 0 in this example). In this way, when a winning continuously occurs at the same starting port, the value stored in the corresponding starting port monitoring buffer is continuously incremented by 1, and the starting corresponding to the other starting port is performed. The value stored in the mouth monitoring buffer is cleared. In addition, when the winning opening is different from the starting opening that was won last time, the value stored in the starting opening monitoring buffer to which a predetermined value (1 in this example) is added as the previous addition target is cleared (this example) Is set to 0), and a predetermined value (1 in this example) is added to the value stored in the start port monitoring buffer that was cleared as the previous clearing target. Hereinafter, the expression “value of the addition buffer” may be used. Specifically, it indicates a value stored in the start port monitoring buffer set in the addition buffer. In addition, the expression “add 1 to the addition buffer” may be used. Specifically, a predetermined value (1 in this example) is added to the value stored in the start port monitoring buffer set in the addition buffer. It is to be. In addition, the expression “clear the addition buffer” may be used. Specifically, the value stored in the start port monitoring buffer set in the addition buffer is cleared (in this example, 0). It is.

  Next, the CPU 56 determines whether or not the value of the addition buffer is 5 or more (step S259). If the value of the addition buffer is 5 or more, the CPU 56 clears the addition buffer (step S260), and proceeds to step S261. If the value of the addition buffer is not 5 or more, the processing is terminated as it is.

  In step S261, the CPU 56 performs control to transmit a winning order abnormality notification designation command to the effect control microcomputer 100 (step S261). Further, the CPU 56 sets a predetermined time (in this example, 30 seconds) in the security signal information timer (step S262). In this embodiment, based on the fact that the predetermined time is set in the security signal information timer in step S262, the information output process (see S30) is executed, so that the security signal is output for a predetermined time (in this example, 30). Seconds) external output. That is, when the value of the addition buffer is 5 or more (Y in step S259), the winning order is abnormal because 5 or more winnings are continuously generated in the first starting winning port 13 or the second starting winning port 14. Control for transmitting a winning order abnormality notification designation command to notify the winning order abnormality notification, and processing for externally outputting the security signal for a predetermined period (30 seconds in this example). Do.

  If the first start port switch is not in the on state in step S252, the CPU 56 checks whether or not the second start port switch is in the on state (step S256). If the second start port switch is not in the on state (that is, if no winning port has been won), the process is terminated.

  On the other hand, if the second start port switch 14a is in the ON state, the CPU 56 checks whether or not the probability variation flag is set (step S257). If the probability variation flag is set (that is, if the probability variation state and the short time state (high base state)), the process proceeds to step S255. If the probability variation flag is not set, the CPU 56 checks whether or not the value of the normal symbol process flag is 3 (step S258). In this embodiment, if the value of the normal symbol process flag is 3 (that is, if the normal electric accessory operation process of the normal symbol process process is being executed), the process proceeds to step S255.

  If the probability variation flag is set in step S257, or if the value of the normal symbol process flag is 3 in step S258, the CPU 56 sets clear data (0 in this example) and clears it in step S255. The buffer is set (step S255). That is, the fact that the probability variation flag is set is controlled to the short-time state (high base state) and the frequency of the variable winning ball device 15 being in the open state is increased, so the state of the distribution device 200 Regardless of this, it is easy to win continuously at the second start winning opening 14. Therefore, in this case, control is performed so as not to determine that the winning order is abnormal by executing only step S255 without executing step S254 and adding 1 to the addition buffer and clearing the clear buffer. In addition, the value of the normal symbol process flag is 3, and the normal electric accessory actuating process of the normal symbol process is being executed. This is because the variable winning ball apparatus 15 is controlled to the open state. It is easy to win continuously at the start winning opening 14. Therefore, also in this case, the control is performed so as not to determine that the winning order is abnormal by clearing the clear buffer by executing only step S255 without executing step S254 and adding 1 to the addition buffer. Then, control goes to a step S259.

  63, for example, the processing corresponding to steps S257 and S258 is executed at the start of winning order abnormality notification processing, and the probability variation flag is set or the value of the normal symbol process flag is 3. In such a case, the processing may be terminated as it is, and the subsequent processing may not be executed. Further, for example, when the probability variation flag is set or the value of the normal symbol process flag is 3 (that is, when Y in step S257 or Y in step S258), step S255 (clears the clear buffer) (Processing) may not be executed. In other words, when the probability variation flag is set or when the value of the normal symbol process flag is 3, neither the process of adding 1 to the addition buffer nor the process of clearing the clear buffer may be executed. .

  Further, in this embodiment, there is shown a case where both the determination as to whether or not the probability variation state (that is, the high base state) is performed and the determination as to whether or not the variable winning ball device 15 is open are executed. However, only one of them may be executed. Specifically, only one of the determination process in step S257 and the determination process in step S258 may be executed.

  Further, based on the fact that the second start port switch 14a is in the ON state, the processing immediately after step S257 is executed, and a predetermined value (1 in this example) is added to the value stored in the second start port monitoring buffer. In addition, a predetermined value (1 in this example) is added to the value stored in the second start port monitoring buffer on condition that the second reserved memory number does not reach the upper limit (4 in this example). You may make it add (that is, you may make it count only an effective start prize). Conversely, a predetermined value (1 in this example) is added to the value stored in the second start port monitoring buffer only when the second reserved storage number reaches the upper limit (4 in this example). (In other words, only invalid start winnings may be counted).

  Further, in this embodiment, the winning at the first start winning opening 13 is counted regardless of whether it is in a certain change state (that is, a high base state) or whether the variable winning ball apparatus 15 is open. (I.e., adding 1 to the addition buffer), the game balls continue to the first start winning opening 13 during the probability changing state (that is, the high base state) and during the period when the variable winning ball apparatus 15 is opened. Although the case where it is determined that the winning order is abnormal based on the detection of the winning is shown, the counting may be interrupted during the probability changing state (that is, the high base state) or during the period when the variable winning ball device 15 is opened. Good. Then, it is determined that the winning order is abnormal when a consecutive winning of the game balls to the first start winning opening 13 is detected during the probability changing state (that is, the high base state) or during the opening of the variable winning ball apparatus 15. You may do it. Specifically, for example, the count is temporarily interrupted when the probability variation state (that is, the high base state) or the variable winning ball device 15 is in the open state after winning two balls continuously at the first start winning opening 13. When the probability variation state (that is, the high base state) and the open state of the variable winning ball apparatus 15 are finished, when two consecutive winnings are made in the first start winning opening 13 (the probability variation state (that is, the high base state) State) or during the opening of the variable winning ball apparatus 15, there is no winning at the second starting winning hole 14), and it is determined that a total of five consecutive balls have been won at the first starting winning hole 13. You may make it determine.

  In this embodiment, the case where it is determined that the winning order is abnormal for both the case where the first start winning opening 13 is continuously won and the case where the second start winning opening 14 is continuously won is shown. The winning order may be determined to be abnormal only in one of the cases where the first start winning opening 13 is continuously won and the second start winning opening 14 is continuously won. .

  Further, in this embodiment, when the first start winning opening 13 is continuously won and the winning order is abnormal, and when the second starting winning opening 14 is continuously won and the winning order is abnormal, In the above, the case where a common command is transmitted as the winning order abnormality notification designation command is shown. However, when the winning order is abnormal after consecutively winning the first starting winning opening 13 and the second starting winning opening 14 is continuous. Then, a winning order abnormality notification designating command may be transmitted so as to be distinguishable from the case where the winning order is abnormal. Specifically, when a winning is made consecutively at the first start winning opening 13 and the winning order is abnormal, a first winning order abnormality notification designating command is transmitted, and the second starting winning opening 14 is continuously received. If the winning order becomes abnormal after winning a prize, a second winning order abnormality notification designation command may be transmitted.

  Further, in this embodiment, the case where the determination value to be compared with the value of the addition buffer is 5 is shown. However, the value is not limited to the value shown in this embodiment. Other values may be used as the determination value, such as determining whether it is above. Further, for example, if it is determined in step S259 whether or not the value of the addition buffer is 2 or more, and even if one ball is continuously received in the first start winning opening 13 or the second starting winning opening 14, the winning is immediately performed. It may be determined that the order is abnormal. However, in this embodiment, the determination criterion is given a margin by determining that the winning order is abnormal on the condition that four balls have been consecutively won at the first start winning opening 13 or the second starting winning opening 14. This prevents erroneous determination.

  In this embodiment, the value of the addition buffer is compared with the determination value (5 in this example) to determine whether or not the winning order abnormality has occurred. The buffer value and the clear buffer value may be compared, and if the difference is a predetermined value (for example, 5) or more, it may be determined that the winning order is abnormal.

  Further, in this embodiment, the case where the determination of abnormality in winning order is executed on the game control microcomputer 560 side, but it may be executed on the effect control microcomputer 100 side. In this case, for example, the game control microcomputer 560 has a command indicating that there is a new start prize in the first start prize opening 13 or a command indicating that there is a new start prize in the second start prize slot 14. Based on the reception of these commands, the production control microcomputer 100 performs a process similar to the winning order abnormality notification process shown in FIG. 63 to determine the winning order abnormality. That's fine.

  The winning order abnormality notifying process is executed in the process at the time of winning the start opening (specifically, the first start opening switch passing process and the second starting opening switch passing process of the special symbol process) (specifically, The processing corresponding to the winning order abnormality notification processing of FIG. 63 may be executed).

  Next, the operation of the effect control means will be described. FIG. 64 is a flowchart showing a main process executed by the effect control microcomputer 100 (specifically, the effect control CPU 101) as effect control means mounted on the effect control board 80. The effect control CPU 101 starts executing the main process when the power is turned on. In the main processing, first, initialization processing for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval (for example, 4 ms) is performed (step S701). . Thereafter, the effect control CPU 101 proceeds to a loop process for monitoring a timer interrupt flag (step S702). When a timer interrupt occurs, the effect control CPU 101 sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the effect control CPU 101 clears the flag (step S703) and executes the following effect control process.

  In the effect control process, the effect control CPU 101 first analyzes the received effect control command and performs a process of setting a flag according to the received effect control command (command analysis process: step S704).

  Next, the effect control CPU 101 performs effect control process processing (step S705). In the effect control process, the process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the effect display device 9 is executed.

  Next, the production control CPU 101 performs the fourth symbol process (step S706). In the 4th symbol process, the process corresponding to the current control state (4th symbol process flag) is selected from the processes corresponding to the control state, and the 4th symbol display areas 9c and 9d of the effect display device 9 are selected. The display control of the 4th symbol is executed.

  Next, a random number update process for updating a count value of a counter for generating a random number such as a jackpot symbol determining random number is executed (step S707). Thereafter, the process proceeds to step S702.

  FIG. 65 is an explanatory diagram showing a configuration example of a command reception buffer for storing an effect control command received from the game control microcomputer 560 of the main board 31. In this example, a command reception buffer of a ring buffer type capable of storing six 2-byte configuration effect control commands is used. Therefore, the command reception buffer is configured by a 12-byte area of reception command buffers 1 to 12. A command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11. The ring buffer format is not necessarily required.

  The effect control command transmitted from the game control microcomputer 560 is received by an interrupt process based on the effect control INT signal, and is stored in a buffer area formed in the RAM. In the command analysis process, which command is the effect control command stored in the buffer area is analyzed. Note that the interrupt process based on the effect control INT signal is executed in preference to the timer interrupt process executed every 4 ms.

  FIG. 66 is a flowchart illustrating a specific example of command analysis processing (step S704). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control CPU 101 confirms the contents of the command stored in the command reception buffer.

  In the command analysis process, the effect control CPU 101 first checks whether or not a reception command is stored in the command reception buffer (step S611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the effect control CPU 101 reads the reception command from the command reception buffer (step S612). When read, the value of the read pointer is incremented by +2 (step S613). The reason for +2 is that two bytes (one command) are read out.

  If the received effect control command is a variation pattern command (step S614), the effect control CPU 101 stores the received variation pattern command in a variation pattern command storage area formed in the RAM (step S615). Then, a variation pattern command reception flag is set (step S616).

  If the received effect control command is a display result designation command (step S617), the effect control CPU 101 forms the received display result designation command (display result 1 designation command to display result 5 designation command) in the RAM. Is stored in the display result designation command storage area (step S618).

  If the received effect control command is a symbol confirmation designation command (step S619), the effect control CPU 101 sets a confirmed command reception flag (step S620).

  If the received effect control command is a jackpot start designation command (step S621), the effect control CPU 101 sets a jackpot start designation command reception flag (step S622).

  If the received effect control command is a small hit / sudden probability sudden change big hit start designation command (step S623), the effect control CPU 101 sets a small hit / sudden probability sudden change big hit start designation command reception flag (step S624).

  If the received effect control command is a winning order abnormality notification designation command (step S625), the effect control CPU 101 outputs a control signal (lamp control execution data) to the lamp driver board 35, thereby causing a predetermined abnormality. Lighting control of the frame LED 28 is performed with the notification pattern (step S626). Further, the production control CPU 101 outputs a predetermined abnormality notification sound from the speaker 27 by outputting a control signal (sound number data) to the sound output board 70 (step S627).

  In this embodiment, the case where the winning order abnormality notification is performed by turning on the frame LED 28 with a predetermined abnormality notification pattern and outputting a predetermined abnormality notification sound from the speaker 27 is shown. This aspect is not limited to that shown in this embodiment. For example, the winning order abnormality notification may be performed by performing only one of lighting of the frame LED 28 with a predetermined abnormality notification pattern and output of a predetermined abnormality notification sound from the speaker 27. Also, for example, the winning order abnormality notification may be performed by displaying a winning order abnormality notification screen including a character string such as “abnormal winning order” on the effect display device 9.

  If the received effect control command is another command, effect control CPU 101 sets a flag corresponding to the received effect control command (step S628). Then, control goes to a step S611.

  FIG. 67 is a flowchart showing the effect control process (step S705) in the main process shown in FIG. In the effect control process, the effect control CPU 101 performs one of steps S800 to S807 according to the value of the effect control process flag. In each process, the following process is executed. In the effect control process, the display state of the effect display device 9 is controlled and variable display of the effect symbol is realized. However, control related to variable display of the effect symbol synchronized with the change of the first special symbol is also the second. Control related to the variable display of the effect symbol synchronized with the change of the special symbol is also executed in one effect control process. It should be noted that the variable display of the effect symbol synchronized with the variation of the first special symbol and the variable display of the effect symbol synchronized with the variation of the second special symbol may be executed by separate effect control process processing. Good. Further, in this case, it may be determined which special symbol variation display is being executed depending on which representation control process processing is performing the variation display of the representation symbol.

  Fluctuation pattern command reception waiting process (step S800): It is confirmed whether or not a variation pattern command has been received from the game control microcomputer 560. Specifically, it is confirmed whether or not the variation pattern command reception flag set in the command analysis process is set. If the change pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the effect symbol change start process (step S801).

  Production symbol variation start processing (step S801): Control is performed so that the variation of the production symbol is started. Then, the value of the effect control process flag is updated to a value corresponding to the effect symbol changing process (step S802).

  Production symbol variation processing (step S802): Controls the switching timing of each variation state (variation speed) constituting the variation pattern and monitors the end of the variation time. When the variation time ends, the value of the effect control process flag is updated to a value corresponding to the effect symbol variation stop process (step S803).

  Effect symbol variation stop processing (step S803): Control is performed to stop the variation of the effect symbol and derive and display the display result (stop symbol). Then, the value of the effect control process flag is updated to a value corresponding to the jackpot display process (step S804) or the variation pattern command reception waiting process (step S800).

  Big hit display process (step S804): After the end of the variation time, control is performed to display a screen for notifying the effect display device 9 of the occurrence of the big hit. Then, the value of the effect control process flag is updated to a value corresponding to the in-round processing (step S805).

  In-round processing (step S805): Display control during round is performed. If the round end condition is satisfied, if the final round has not ended, the value of the effect control process flag is updated to a value corresponding to the post-round processing (step S806). If the final round has ended, the value of the effect control process flag is updated to a value corresponding to the jackpot end process (step S807).

  Post-round processing (step S806): Display control between rounds is performed. When the round start condition is satisfied, the value of the effect control process flag is updated to a value corresponding to the in-round process (step S805).

  Big hit end effect processing (step S807): In the effect display device 9, display control is performed to notify the player that the big hit game state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800).

  In this embodiment, when a winning at the starting winning port occurs, a predetermined value is added to the value stored in the corresponding starting port monitoring buffer, and it is detected that a winning order abnormality has occurred based on the addition result. However, the present invention is not limited to this. For example, when a winning at a starting winning opening occurs, a predetermined value is subtracted from the value stored in the corresponding starting opening monitoring buffer, and the winning is determined based on the subtraction result. You may comprise so that it may detect that the order abnormality generate | occur | produced.

  FIG. 68 is a flowchart showing a modification of the winning order abnormality notification process. In the modified example of the winning order abnormality notification process shown in FIG. 68, in place of steps S250 and 251, the second start port monitoring buffer is set in the subtraction buffer (step S250b), and the first start port monitoring buffer is set to the initial value setting buffer. (Step S251b) is executed. The subtraction buffer is used to set the set start port monitoring buffer as a subtraction target of a predetermined value (1 in this example). The initial value setting buffer is used to set the start port monitoring buffer as a target for initial value setting (in this example, the initial value (5) is set).

  In the modified example of the winning order abnormality notification process shown in FIG. 68, instead of steps S254 and S255, 1 is subtracted from the subtraction buffer, the subtraction buffer is loaded (step S254b), and initial value data (5 in this example). Is stored and stored in the initial value setting buffer (step S255b). That is, in step S254b, a predetermined value (1 in this example) is subtracted from the value stored in the start port monitoring buffer set in the subtraction buffer, and in step S255b, the start port monitoring set in the initial value setting buffer. The value stored in the buffer is set to the initial value (5 in this example). In this way, when a winning continuously occurs at the same starting port, the value stored in the corresponding starting port monitoring buffer is continuously subtracted by 1, and the starting corresponding to the other starting port is performed. The value stored in the mouth monitoring buffer is set to the initial value (5 in this example). In addition, when a winning opening different from the previously winning starting opening is won, the value stored in the starting opening monitoring buffer from which a predetermined value (1 in this example) has been subtracted as the previous subtraction target is the initial value (this In the example, it is set to 5), and a predetermined value (1 in this example) is subtracted from the value stored in the start port monitoring buffer in which the initial value (5 in this example) is set as the previous initial value setting target. Hereinafter, the expression “value of the subtraction buffer” may be used. Specifically, it indicates a value stored in the start port monitoring buffer set in the subtraction buffer. In addition, the expression “subtract 1 from the subtraction buffer” may be used. Specifically, a predetermined value (1 in this example) is obtained from the value stored in the start port monitoring buffer set in the subtraction buffer. Is to subtract. In addition, the expression “set an initial value in the subtraction buffer” may be used. Specifically, the value stored in the start port monitoring buffer set in the subtraction buffer is set to the initial value (5 in this example). ).

  In the modified example of the winning order abnormality notification process shown in FIG. 68, it is determined whether or not the value of the subtraction buffer is 0 instead of steps S259 and S260 (step S259b), and the value of the subtraction buffer is 0. If so, a process of setting an initial value in the subtraction buffer (step S260b) is executed. The value of the subtraction buffer is compared with the determination value (0 in this example) to determine whether or not a winning order abnormality has occurred. However, the present invention is not limited to this. For example, the value of the subtraction buffer and the initial value are determined. The value in the setting buffer is compared, and if the difference is a predetermined value (for example, 5) or more, it may be determined that the winning order is abnormal.

  By performing the processing as described above, when a winning at the starting winning opening occurs, a predetermined value is subtracted from the value stored in the corresponding starting opening monitoring buffer, and a winning order abnormality occurs based on the subtraction result. Can be configured to detect this. In the case of the configuration as shown in FIG. 68, a process of setting an initial value in the subtraction buffer (step S10b) is executed instead of S10a as in the modification of the main process shown in FIG. In this way, the value of the subtraction buffer is initialized after the power is turned on, so that it is possible to prevent erroneous detection of the winning order.

  Further, in this embodiment, a pre-reading notice effect that is executed before the start of the variable display that is the target of the notice effect may be executed. When configured to execute the pre-reading notice effect, for example, as shown in FIG. 70, the game control microcomputer 560 has a timing at which the start winning to the first start winning opening 13 or the second starting winning opening 14 occurs. In the first start port switch passing process (refer to step S312) and the second start port switch passing process (refer to step S314), a determination is made at the time of starting winning, and a control for transmitting a winning determination result command indicating the determination result is transmitted. (Steps S2061A and S2061B in FIG. 70). In this case, for example, as a determination result designation command at the time of winning a prize, a symbol designation command indicating whether or not a big hit, a small hit or not, a decision result of the type of jackpot, and a random number value for determining a variation pattern type A variation category command indicating a determination result (determination result of variation pattern type) of which determination value range is transmitted. Therefore, in this case, the symbol designation command, the variable category command, and the reserved memory number addition designation command (first reserved memory number addition designation command, first command) 2 pending storage number addition designation command) is transmitted.

  As shown in FIG. 71, in the command analysis process, when a winning determination result designation command is received (step S629), the effect control microcomputer 100 displays a winning determination result according to the winning determination result designation command. The winning determination result storage buffer is stored (step S630), and pre-reading effect determination processing is performed based on the winning determination result stored in the winning determination result storage buffer (step S631). Thereafter, the effect control microcomputer 100 executes the prefetch effect according to the determination result of the prefetch effect determination process (for example, executed in the effect symbol changing process (step S802)). The pre-reading effect is, for example, a display of changing the background display of the effect display device 9 to a special background during the variable display started before the variable display to be notified, the countdown display, the variable display This is realized by changing the display mode of the hold display corresponding to. In step S631, for example, as shown in FIG. 72, the production control microcomputer 100 determines the production mode of the prefetching production according to whether or not the high base state is set and the total number of pending storages. Specifically, as shown in FIG. 72, in the high base state, the pre-reading effect is executed from the first to the maximum four times of the variable display that is started before the variable display, and is not in the high base state. In some cases, pre-reading effects are performed from once to a maximum of eight variable displays that are started before the variable display. By doing in this way, when it is not in the high base state (that is, in the normal state), the first start winning opening 13 and the second starting winning opening 14 are alternately won by the distribution device, so that the maximum It is possible to execute a continuous effect (for example, switching to a special background) that is completed eight times (the upper limit obtained by adding the first reserved memory number and the second reserved memory number). Since it is easy to win only the second start winning opening 14 by the variable winning ball apparatus 15 without making it possible, it is possible to execute a continuous effect (for example, countdown display) that is completed in a maximum of four times (upper limit of the second reserved memory number). Can do. Therefore, a pre-reading effect according to the gaming state can be executed.

  In addition, the effect mode of the prefetch effect may be determined according to whether or not the display result of the variable display is a big hit. For example, when the hold display corresponding to the change display is the eighth hold display (that is, when the change display executed first is 8 times), whether or not the display result of the change display is a big hit Accordingly, the pre-reading effect is started immediately after the start winning (that is, it is executed over eight variation displays), or the pre-reading effect is started after several variable displays are performed after the starting winning (for example, It is also possible to determine whether it is executed over four fluctuation displays). In this way, depending on whether or not the display result of the variable display is a big hit, by determining the presentation mode of the pre-reading effect (how many variable displays are executed), for example, many As the pre-reading effect is performed over the variable display, the expectation degree of the big hit can be made higher, and the game entertainment can be enhanced.

  As described above, according to this embodiment, the distribution device 200 for distributing game balls is provided in the game area 7. The sorting device 200 includes an inflow port 201 through which game balls that have entered the game area 7 can flow into the sorting device 200, and a plurality of passages through which game balls that have flowed in from the inflow port can pass (in this example, the left-side passage). 203, a right passage 204), and a distribution means (in this example, a distribution member 202) that distributes the game balls flowing in from the inflow port to any one of the plurality of passages. Further, the distribution means is based on the fact that the game ball has flowed in from the inflow port 201, and in the first state (this book) that easily distributes the game ball to the first passage (the left passage 203 in this example) among the plurality of passages. In the example, as shown in FIGS. 2 (a) and 2 (d), the distribution member 202 is tilted to the right) and the second state in which game balls are easily distributed to the second passage (in this example, the right passage 204) ( In this example, as shown in FIGS. 2B and 2C, the distribution member 202 is switched to the left side) according to a predetermined order (in this example, the distribution member 202 is alternately switched according to the weight of the game ball). In addition, the first start area (in this example, the first start winning opening 13) is provided in such a manner that the game balls distributed in the first passage easily pass through (in this example, as shown in FIG. 2). The first start winning opening 13 is provided below the left outlet 205), and the second starting area (in this example, the second starting winning opening 14) has game balls distributed to the second passage. (In this example, as shown in FIG. 2, the second start winning opening 14 is provided below the right outlet 206). Further, the game control microcomputer 560 has a storage area (in this example, a first start port) corresponding to the start area through which the game medium has passed based on the fact that the game medium has passed through the first start area or the second start area. A predetermined value (1 in this example) is added to the value stored in the storage area with the monitoring buffer or the second start port monitoring buffer as an addition target, and the addition result is set to a predetermined condition (for example, the addition target) The value stored in the storage area is 5 or more, or the difference between the value stored in the first start port monitoring buffer and the value stored in the second start port monitoring buffer (the value of the addition buffer and the clear buffer) It is determined that there is an abnormality based on the fact that the difference between the first value and the second value satisfies a predetermined value (for example, 5 or more). Therefore, since the abnormality determination of the sorting apparatus 200 can be performed, it is possible to prevent the game from being performed normally due to the abnormality of the sorting apparatus 200.

  Further, according to this embodiment, the first reset (based on the input of the IAT signal from the IAT 506a and the input of the time-out signal from the watchdog timer (WDT) 506b) in this example (the first reset) In this example, it is possible to set whether to generate a system reset or a second reset (in this example, a user reset) (see bit 7 of the reset setting (KRES) shown in FIG. 16). The security check is executed after the first reset occurs, while the security check is not executed after the second reset occurs. Therefore, the type of reset to be performed when a predetermined event occurs according to the situation of the gaming machine or game store can be set to an optimum one, so that the security related to the game control microcomputer 560 can be improved.

  In this embodiment, as the occurrence of the predetermined event, the case where the IAT signal from the IAT 506a is input and the case where the time-out signal is input from the watchdog timer (WDT) 506b are shown. The game control microcomputer 560 is not limited to that shown in the embodiment, and may be reset based on the occurrence of a certain event such as an error that should be reset.

  Further, according to this embodiment, the occurrence of the predetermined event includes a timeout of the watchdog timer (WDT) 506b, and it is possible to set whether or not to activate the watchdog timer (WDT) 506b (this book) In the example, "0000" is set in bits 3-0 of the reset setting (KRES) shown in FIG. Even when it is set not to activate the watchdog timer (WDT) 506b, it is possible to set whether to generate the first reset or the second reset based on the occurrence of the predetermined event. Specifically, in the reset setting (KRES) shown in FIG. 14, even if “0000” is set in bits 3-0, the type of reset can be set by setting bit 7. Therefore, regardless of the setting of the watchdog timer (WDT) 506b, the setting of the type of reset that is generated based on the occurrence of the predetermined event can be made common.

  Further, according to this embodiment, the occurrence of the predetermined event includes an out-of-designated area execution (in this example, out-of-designated area prohibition (IAT)) that executes a program stored in an area other than the designated area. Then, the game control microcomputer 560 performs a timer interrupt process (timer interrupt shown in FIG. 51) executed in response to a timer interrupt that occurs every predetermined time (4 ms in this example) as a predetermined process. When execution outside the specified area occurs during execution of processing (in this example, an IAT signal is input from the IAT circuit 506a), the storage contents of the RAM 55 (backup RAM) are initialized (in this example, after reset) Step S10 shown in Fig. 50 is executed.) Therefore, it is possible to improve security when an unintended program is executed.

  Further, according to the modification of this embodiment, the game control microcomputer 560 corresponds to the start area through which the game medium has passed based on the fact that the game medium has passed through the first start area or the second start area. A predetermined value (1 in this example) is subtracted from the value stored in the storage area with the storage area (in this example, the first start port monitoring buffer or the second start port monitoring buffer) as a subtraction target, and the subtraction result Is a predetermined condition (for example, the value stored in the storage area to be subtracted is 0, or the value stored in the first start port monitoring buffer and the value stored in the second start port monitoring buffer) Is determined to be abnormal based on the fact that the difference (the difference between the value of the subtraction buffer and the value of the initial value setting buffer) is a predetermined value (for example, 5) or more. Therefore, since the abnormality determination of the sorting apparatus 200 can be performed, it is possible to prevent the game from being performed normally due to the abnormality of the sorting apparatus 200.

  Further, according to this embodiment, the storage contents of the RAM 55 (backup RAM) are initialized (in this example, step S10 shown in FIG. 50 is executed after resetting), and in step S10a, the addition buffer and The clear buffer is cleared (or an initial value (5 in this example) is set in the subtraction buffer in step S10b). Therefore, since the abnormality determination of the sorting apparatus 200 can be performed correctly even when the power failure is restored, it is possible to prevent the game from being performed normally due to the abnormality of the sorting apparatus 200.

  Further, according to this embodiment, the game control microcomputer 560 adds a storage area corresponding to the first start area (in this example, the first start opening monitoring buffer or the second start opening monitoring buffer). Target and clear the storage area corresponding to the second start area (in this example, the first start port monitoring buffer or the second start port monitoring buffer (different from the storage area corresponding to the first start area)) Is temporarily set, and based on the fact that the game medium has passed through the second start area, the provisional addition target and the clear target are exchanged, and a predetermined value (this In the example, 1) is added, and the value stored in the storage area to be cleared is cleared. Then, based on the value stored in the storage area (for example, when the value stored in the storage area to be added is 5 or more, or the value stored in the first start port monitoring buffer and the second It is determined that the difference from the value stored in the start port monitoring buffer (the difference between the value of the addition buffer and the value of the clear buffer) is a predetermined value (for example, 5) or more is abnormal. Therefore, since the abnormality determination of the sorting apparatus 200 can be performed, it is possible to prevent the game from being performed normally due to the abnormality of the sorting apparatus 200.

  In addition, according to the modification of this embodiment, the game control microcomputer 560 also includes a storage area corresponding to the first start area (in this example, the first start opening monitoring buffer or the second start opening monitoring). The storage area corresponding to the second start area (in this example, the first start opening monitoring buffer or the second start opening monitoring buffer (the storage area corresponding to the first start area) is different. )) Is temporarily set as the initial value setting target, and based on the fact that the game medium has passed the second start area, the temporarily set subtraction target and the initial value setting target are switched, and the subtraction target is stored in the storage area. A predetermined value (1 in this example) is subtracted from the stored value, and the value stored in the storage area targeted for initial value setting is set to the initial value (5 in this example). Then, based on the value stored in the storage area (for example, when the value stored in the storage area to be subtracted is 0, or the value stored in the first start port monitoring buffer and the second start It is determined that the difference from the value stored in the mouth monitoring buffer (the difference between the value in the subtraction buffer and the value in the initial value setting buffer) is a predetermined value (for example, 5) or more is abnormal. Therefore, since the abnormality determination of the sorting apparatus 200 can be performed, it is possible to prevent the game from being performed normally due to the abnormality of the sorting apparatus 200.

  In the above-described embodiment, in order to notify the effect control microcomputer 100 of the change pattern indicating the change mode such as the change time, the type of reach effect, the presence / absence of the pseudo-ream, etc., 1 is used when the change is started. Although an example in which one variation pattern command is transmitted has been shown, the variation pattern may be notified to the effect control microcomputer 100 by two or more commands. Specifically, in the case of notifying by two commands, the game control microcomputer 560 uses the first command to indicate whether there is a pseudo-ream, a slip effect, etc. before reaching (so-called if not reach). A command indicating the variation time and variation mode before the second stop) is transmitted, and the second command has reached the reach such as the type of reach and presence / absence of re-lottery effect (if the reach is not reach, so-called first) You may make it transmit the command which shows the fluctuation | variation time and fluctuation | variation aspect (after 2 stop). In this case, the effect control microcomputer 100 may perform effect control in variable display based on the variable time derived from the combination of two commands. The game control microcomputer 560 notifies the change time by each of the two commands, and the effect control microcomputer 100 selects the specific change mode executed at each timing. It may be. When sending two commands, two commands may be sent within the same timer interrupt. After sending the first command, a certain period of time has passed (for example, the next timer interrupt). The second command may be transmitted. Note that the variation mode indicated by each command is not limited to this example, and the order of transmission can be appropriately changed. In this way, by notifying the variation pattern by two or more commands, the amount of data that must be stored as the variation pattern command can be reduced.

  In the above-described embodiment, the production control board 80, the audio output board 70, and the lamp driver board 35 are provided as the boards on which the circuit for controlling the production apparatus is mounted. You may mount on one board | substrate. Further, a first effect control board (display control board) on which a circuit for controlling the effect display device 9 and the like is mounted and a circuit for controlling other effect devices (lamps, LEDs, speakers 27, etc.) are mounted. You may make it provide two board | substrates with two production | presentation control boards.

  In the above-described embodiment, the game control microcomputer 560 directly transmits a command to the effect control microcomputer 100. However, the game control microcomputer 560 transmits another command (for example, FIG. 5). The sound output board 70 and the lamp driver board 35 shown in FIG. 5 or the sound / lamp board having the function of the circuit mounted on the sound output board 70 and the function of the circuit mounted on the lamp driver board 35). A control command may be transmitted and transmitted to the effect control microcomputer 100 on the effect control board 80 via another board. In that case, the command may simply pass through another board, or the sound output board 70, the lamp driver board 35, and the sound / lamp board are equipped with control means such as a microcomputer, and the control means receives the command. In response to this, control related to sound control and lamp control is executed, and the received command is changed as it is or, for example, to a simplified command to control the effect display device 9. You may make it transmit to. Even in that case, the effect control microcomputer 100 performs the display control in accordance with the effect control command directly received from the game control microcomputer 560 in the above-described embodiment. Display control can be performed in accordance with commands received from the board 35 or the sound / lamp board.

  In the above embodiment, a pachinko machine is taken as an example of the gaming machine. However, according to the present invention, a predetermined number of bets are set by inserting medals, and a plurality of types are set according to the operation of the operation lever by the player. When the symbol is rotated and the symbol is stopped according to the stop button operation by the player, if the combination of the stop symbol becomes a specific symbol combination, it applies to a slot machine in which a predetermined number of medals are paid out to the player It is also possible.

  In the above embodiment, the game machine uses a game medium as an example. However, the game machine according to the present invention is not limited to a game machine that pays out a predetermined number of game media, and a game ball The present invention can also be applied to an enclosed game machine that encloses game media such as the above and gives a score when a prize granting condition is satisfied.

  In the above-described embodiment, “the ratios are different” is not limited to those having different ratios such as A: B = 70%: 30% or A: B = 40%: 60%, This is a concept including a ratio that is different in a relationship of A: B = 100%: 0% (that is, one with 100% allocation and the other with 0% allocation).

  The present invention is preferably applied to a gaming machine such as a pachinko gaming machine capable of performing a predetermined game.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 8a 1st special symbol display device 8b 2nd special symbol display device 9 Production display device 13 1st starting winning port 14 2nd starting winning port 20 Special variable winning ball device 31 Game control board (main board)
56 CPU
502 clock circuit 506 reset / interrupt controller 506a IAT circuit 506b watchdog timer (WDT)
507 Free-run counter circuit 508a 8-bit random number circuit 508b 16-bit random number circuit 525a, 525b Random number generation circuit 537 Update monitoring circuit 560 Game control microcomputer 80 Production control board 100 Production control microcomputer 101 Production control CPU
109 VDP

Claims (2)

It is possible to perform a predetermined game using a game medium, a game area into which the game medium can enter is provided, and a plurality of types of identification that can identify each based on the game medium passing through the start area A gaming machine that performs variable display of information,
A first start area and a second start area are provided as start areas,
A distribution device for distributing game media is provided in the game area,
The sorting device is
An inflow port through which game media entering the game area can flow into the distribution device;
A plurality of passages through which game media flowing in from the inflow port can pass;
Distribution means for distributing game media flowing in from the inflow port to any of the plurality of passages,
The allocating means is configured to easily distribute game media to the first state and the second passage in which the game media are easily distributed to the first passage of the plurality of passages based on the flow of game media from the inflow port. Switch to 2 states according to a predetermined order,
The first start area is provided in such a manner that the game media distributed in the first passage easily pass through,
The second start area is provided in such a manner that game media distributed in the second passage easily pass through,
Based on the fact that the game medium has passed through the first start area or the second start area, the storage area corresponding to the start area through which the game medium has passed is added, and a predetermined value is added to the value stored in the storage area. Adding means for
An abnormality determining means for determining an abnormality based on the addition result by the adding means satisfying a predetermined condition;
A game control microcomputer for controlling the progress of the game;
Reset setting means capable of setting whether to generate a first reset or a second reset based on the occurrence of a predetermined event;
Security check is performed after the occurrence of the first reset, while security check is not performed after the occurrence of the second reset,
The game control microcomputer is:
Storage means including at least the storage area capable of holding information generated when performing control related to a game for a predetermined period even when power supply to the gaming machine is stopped;
Predetermined processing execution means capable of executing predetermined processing;
And an initialization unit that initializes the storage contents of the storage unit when the predetermined event occurs during the execution of the predetermined process. It is possible to perform a predetermined game using a game medium, a game area into which the game medium can enter is provided, and a plurality of types of identification that can identify each based on the game medium passing through the start area A gaming machine that performs variable display of information,
A first start area and a second start area are provided as start areas,
A distribution device for distributing game media is provided in the game area,
The sorting device is
An inflow port through which game media entering the game area can flow into the distribution device;
A plurality of passages through which game media flowing in from the inflow port can pass;
Distribution means for distributing game media flowing in from the inflow port to any of the plurality of passages,
The allocating means is configured to easily distribute game media to the first state and the second passage in which the game media are easily distributed to the first passage of the plurality of passages based on the flow of game media from the inflow port. Switch to 2 states according to a predetermined order,
The first start area is provided in such a manner that the game media distributed in the first passage easily pass through,
The second start area is provided in such a manner that game media distributed in the second passage easily pass through,
A predetermined value is subtracted from the value stored in the storage area with the storage area corresponding to the start area through which the game medium has passed as a result of the game medium passing through the first start area or the second start area being subtracted. Subtracting means to
An abnormality determining means for determining an abnormality based on a result of the subtraction by the subtracting means satisfying a predetermined condition;
A game control microcomputer for controlling the progress of the game;
Reset setting means capable of setting whether to generate a first reset or a second reset based on the occurrence of a predetermined event;
Security check is performed after the occurrence of the first reset, while security check is not performed after the occurrence of the second reset,
The game control microcomputer is:
Storage means including at least the storage area capable of holding information generated when performing control related to a game for a predetermined period even when power supply to the gaming machine is stopped;
Predetermined processing execution means capable of executing predetermined processing;
And an initialization unit that initializes the storage contents of the storage unit when the predetermined event occurs during the execution of the predetermined process.