JP2015125347A - Thin-film transistor, thin-film transistor manufacturing method, and display device using thin-film transistor - Google Patents
Thin-film transistor, thin-film transistor manufacturing method, and display device using thin-film transistor Download PDFInfo
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本発明は、コモン電極とピクセル電極との間の層間絶縁膜材料を工夫することで、工程の簡略化、コストの削減、および生産性向上を実現する薄膜トランジスタ、薄膜トランジスタの製造方法、および薄膜トランジスタを用いた表示装置に関する。 The present invention uses a thin film transistor, a method for manufacturing a thin film transistor, and a thin film transistor that achieves simplification of processes, reduction of cost, and improvement of productivity by devising an interlayer insulating film material between a common electrode and a pixel electrode. Related to the display device.
図３は、従来の薄膜トランジスタの積層構造を示す断面図である。図３に示すように、従来の薄膜トランジスタは、ガラス基板１０１の上に、ゲート電極１０２、ゲート絶縁膜１０３、アモルファスシリコン（ａ−Ｓｉ）１０４、ソース／ドレイン電極１０５、バッファ層１０６、第１の層間絶縁膜１０７ａ、コモン電極１０８、第２の層間絶縁膜１０７ｂ、およびピクセル電極１０９が順次積層されて構成されている。 FIG. 3 is a cross-sectional view showing a conventional laminated structure of thin film transistors. As shown in FIG. 3, the conventional thin film transistor includes a gate electrode 102, a gate insulating film 103, amorphous silicon (a-Si) 104, a source / drain electrode 105, a buffer layer 106, a first electrode on a glass substrate 101. The interlayer insulating film 107a, the common electrode 108, the second interlayer insulating film 107b, and the pixel electrode 109 are sequentially stacked.
図４は、従来の薄膜トランジスタにおいて、第１の層間絶縁膜１０７ａの上に、コモン電極１０８、第２の層間絶縁膜１０７ｂ、およびピクセル電極１０９を形成する工程を示した説明図である。従来の薄膜トランジスタでは、コモン電極１０８とピクセル電極１０９の間の第２の層間絶縁膜１０７ｂとして、ＳｉＮｘ（窒化シリコン）が用いられている。 FIG. 4 is an explanatory diagram showing a process of forming the common electrode 108, the second interlayer insulating film 107b, and the pixel electrode 109 on the first interlayer insulating film 107a in the conventional thin film transistor. In the conventional thin film transistor, SiNx (silicon nitride) is used as the second interlayer insulating film 107 b between the common electrode 108 and the pixel electrode 109.
図４に示す工程の詳細を説明する。まず始めに、ステップＢ１（コモン電極の形成工程）において、第１の層間絶縁膜１０７ａの上にコモン電極１０８を成膜する。その上にフォトレジストを塗布し、フォトマスクを介して露光を行い、現像液の中に浸し、フォトレジストの現像を行う。その後、コモン電極をエッチング工程でパターニングした後、剥離工程でフォトレジストを剥離する。 Details of the process shown in FIG. 4 will be described. First, in step B1 (common electrode formation step), the common electrode 108 is formed on the first interlayer insulating film 107a. A photoresist is applied thereon, exposed through a photomask, dipped in a developer, and the photoresist is developed. Then, after patterning the common electrode in the etching process, the photoresist is stripped in the stripping process.
次に、第２の層間絶縁膜１０７ｂとしてＳｉＮｘ（窒化シリコン）を成膜し、その上にフォトレジストを塗布した後、フォトマスクを介して露光し、現像液の中に浸して、フォトレジストを現像する。現像後、ポストベークを行い、フォトレジストを硬化させた後、エッチング工程でＳｉＮｘをパターニングし、その後、フォトレジストを剥離する。 Next, a SiNx (silicon nitride) film is formed as the second interlayer insulating film 107b, and a photoresist is applied thereon, then exposed through a photomask, immersed in a developer, and the photoresist is applied. develop. After the development, post baking is performed to cure the photoresist, and then the SiNx is patterned in an etching process, and then the photoresist is peeled off.
さらに、ピクセル電極１０９としてＩＴＯを成膜し、成膜後、ＩＴＯ上にフォトレジストを塗布し、フォトマスクを介して露光した後、現像液に浸し、フォトレジストを現像する。現像後、ポストベーク工程でフォトレジストを硬化させた後、エッチング工程でＩＴＯをパターニングする。最後に、剥離工程でフォトレジストを剥離し、ＴＦＴが完成する。 Further, an ITO film is formed as the pixel electrode 109, and after the film formation, a photoresist is applied onto the ITO, exposed through a photomask, and then immersed in a developer to develop the photoresist. After development, the photoresist is cured in a post-bake process, and then ITO is patterned in an etching process. Finally, the photoresist is stripped in a stripping process to complete the TFT.
しかしながら、従来技術には、以下のような課題がある。
第２の層間絶縁膜１０７ｂとして用いられるＳｉＮｘは、真空装置を使用して成膜を行う必要がある。また、従来技術によるＴＦＴ形成工程は、上記の通り工程数が非常に多い。これらの理由により、初期投資やランニングコストが高くなるという問題があった。
However, the prior art has the following problems.
SiNx used as the second interlayer insulating film 107b needs to be formed using a vacuum apparatus. In addition, as described above, the number of steps in the conventional TFT forming process is very large. For these reasons, there has been a problem that initial investment and running cost are increased.
このような課題に対し、工程簡略化およびコスト削減のため 、ＳｉＮｘ成膜の代わりに第２の層間絶縁膜に有機絶縁樹脂を塗布することが提案された（例えば、特許文献１、２参照）。しかしながら、一般的な有機絶縁膜の誘電率は、３〜４程度で、ＳｉＮｘよりも誘電率が低いため、残像が発生してしまう、あるいは駆動電圧が上昇してしまうという問題が発生する。 In order to simplify the process and reduce costs, it has been proposed to apply an organic insulating resin to the second interlayer insulating film instead of the SiNx film formation (for example, see Patent Documents 1 and 2). . However, a general organic insulating film has a dielectric constant of about 3 to 4, which is lower than that of SiNx, and thus causes a problem that an afterimage is generated or a driving voltage is increased.
本発明は、前記のような課題を解決するためになされたものであり、第２の層間絶縁膜として高誘電率の感光性塗布型絶縁膜を用いることによって、工程の簡略化、コストの削減、および生産性向上を実現することのできる薄膜トランジスタ、薄膜トランジスタの製造方法、および薄膜トランジスタを用いた表示装置を得ることを目的とする。 The present invention has been made to solve the above-described problems. By using a photosensitive coating insulating film having a high dielectric constant as the second interlayer insulating film, the process is simplified and the cost is reduced. It is an object of the present invention to obtain a thin film transistor capable of realizing improvement in productivity, a method for manufacturing the thin film transistor, and a display device using the thin film transistor.
本発明に係る薄膜トランジスタは、絶縁層を介してコモン電極とピクセル電極が配置されることを特徴とするフリンジフィールドスイッチング（Ｆｒｉｎｇｅ Ｆｉｅｌｄ Ｓｗｉｔｃｈｉｎｇ：ＦＦＳ）構造を有する薄膜トランジスタにおいて、コモン電極とピクセル電極との間の層間絶縁膜が、誘電率４以上の有機絶縁膜を塗布することで形成されているものである。 A thin film transistor according to the present invention is a thin film transistor having a fringe field switching (FFS) structure in which a common electrode and a pixel electrode are disposed through an insulating layer. The interlayer insulating film is formed by applying an organic insulating film having a dielectric constant of 4 or more.
また、本発明に係る薄膜トランジスタの製造方法は、コモン電極とピクセル電極との間の層間絶縁膜が、誘電率４以上の有機絶縁膜を塗布することで形成されている薄膜トランジスタの製造方法であって、コモン電極の上に、有機絶縁膜を塗布する絶縁膜形成工程と、絶縁膜形成工程により塗布された有機絶縁膜をマスクとして、コモン電極をエッチングするエッチング工程と、有機絶縁膜をリフロー処理することで、エッチング工程でエッチングされたコモン電極の端部を有機絶縁膜で覆うポストベーク工程と、ポストベーク工程の後に、ピクセル電極を成膜形成するピクセル電極形成工程とを有するものである。 The thin film transistor manufacturing method according to the present invention is a thin film transistor manufacturing method in which an interlayer insulating film between a common electrode and a pixel electrode is formed by applying an organic insulating film having a dielectric constant of 4 or more. , An insulating film forming step of applying an organic insulating film on the common electrode, an etching step of etching the common electrode using the organic insulating film applied by the insulating film forming step as a mask, and a reflow treatment of the organic insulating film Thus, the method includes a post-bake step of covering the end portion of the common electrode etched in the etching step with an organic insulating film, and a pixel electrode formation step of forming a pixel electrode after the post-bake step.
本発明によれば、真空装置を使用して形成される第２の層間絶縁膜であるＳｉＮｘの代替として、塗布型の感光性高誘電率縁膜材料を使用することにより、工程の簡略化、コストの削減、および生産性向上を実現することのできる薄膜トランジスタ、薄膜トランジスタの製造方法、および薄膜トランジスタを用いた表示装置を得ることができる。 According to the present invention, as a substitute for SiNx, which is a second interlayer insulating film formed using a vacuum apparatus, a coating type photosensitive high dielectric constant edge film material is used, thereby simplifying the process, A thin film transistor capable of realizing cost reduction and productivity improvement, a method for manufacturing the thin film transistor, and a display device using the thin film transistor can be obtained.
以下、本発明の薄膜トランジスタ、薄膜トランジスタの製造方法、および薄膜トランジスタを用いた表示装置の好適な実施の形態につき図面を用いて説明する。 Hereinafter, preferred embodiments of a thin film transistor, a method of manufacturing a thin film transistor, and a display device using the thin film transistor of the present invention will be described with reference to the drawings.
実施の形態１．
図１は、本発明の実施の形態１における薄膜トランジスタの積層構造を示す断面図である。図１に示すように、本実施の形態１における薄膜トランジスタは、ガラス基板１の上に、ゲート電極２、ゲート絶縁膜３、アモルファスシリコン（ａ−Ｓｉ）４、ソース／ドレイン電極５、バッファ層６、第１の層間絶縁膜７ａ、コモン電極８、第２の層間絶縁膜７ｂ、およびピクセル電極９が順次積層されて構成されている。
Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a laminated structure of a thin film transistor according to Embodiment 1 of the present invention. As shown in FIG. 1, the thin film transistor according to the first embodiment has a gate electrode 2, a gate insulating film 3, amorphous silicon (a-Si) 4, a source / drain electrode 5, and a buffer layer 6 on a glass substrate 1. The first interlayer insulating film 7a, the common electrode 8, the second interlayer insulating film 7b, and the pixel electrode 9 are sequentially stacked.
図２は、本実施の形態１の薄膜トランジスタにおいて、第１の層間絶縁膜７ａの上に、コモン電極８、第２の層間絶縁膜７ｂ、およびピクセル電極９を形成する工程を示した説明図である。本実施の形態１における薄膜トランジスタの各層の積層順序は、従来の薄膜トランジスタと基本的に同じであるが、第２の層間絶縁膜に関して、以下のような違いがある。 FIG. 2 is an explanatory diagram showing a process of forming the common electrode 8, the second interlayer insulating film 7b, and the pixel electrode 9 on the first interlayer insulating film 7a in the thin film transistor of the first embodiment. is there. The stacking order of the layers of the thin film transistor in the first embodiment is basically the same as that of the conventional thin film transistor, but there are the following differences with respect to the second interlayer insulating film.
従来の薄膜トランジスタでは、コモン電極１０８とピクセル電極１０９の間の第２の層間絶縁膜１０７ｂとして、ＳｉＮｘ（窒化シリコン）が用いられていた。これに対して、本実施の形態１の薄膜トランジスタでは、コモン電極８とピクセル電極９の間の第２の層間絶縁膜７ｂとして、感光性高誘電率有機絶縁膜が用いられている。そして、本実施の形態１では、この感光性高誘電率有機絶縁膜を塗布することで第２の層間絶縁膜７ｂを形成することを技術的特徴としており、この結果、真空成膜装置を不要とすることができる。 In the conventional thin film transistor, SiNx (silicon nitride) is used as the second interlayer insulating film 107 b between the common electrode 108 and the pixel electrode 109. In contrast, in the thin film transistor of the first embodiment, a photosensitive high dielectric constant organic insulating film is used as the second interlayer insulating film 7b between the common electrode 8 and the pixel electrode 9. The first embodiment has a technical feature in that the second interlayer insulating film 7b is formed by applying this photosensitive high dielectric constant organic insulating film, and as a result, no vacuum film forming apparatus is required. It can be.
図２に示す工程の詳細を説明する。まず始めに、ステップＡ１（コモン電極／第２の層間絶縁膜の形成工程）において、第１の層間絶縁膜７ａの上にコモン電極８を成膜する。その後、真空成膜装置を用いることなく、第２の層間絶縁膜７ｂである感光性高誘電率有機絶縁膜をコモン電極８の上に塗布する。次に、感光性高誘電率有機絶縁膜７ｂをフォトマスクを介して露光し、現像工程で前記絶縁膜を現像する。その後、第２の層間絶縁膜７ｂをマスクとして、コモン電極８をエッチング工程でパターニングする。 Details of the process shown in FIG. 2 will be described. First, in step A1 (common electrode / second interlayer insulating film forming step), the common electrode 8 is formed on the first interlayer insulating film 7a. Thereafter, a photosensitive high dielectric constant organic insulating film, which is the second interlayer insulating film 7b, is applied on the common electrode 8 without using a vacuum film forming apparatus. Next, the photosensitive high dielectric constant organic insulating film 7b is exposed through a photomask, and the insulating film is developed in a developing process. Thereafter, the common electrode 8 is patterned by an etching process using the second interlayer insulating film 7b as a mask.
次に、ポストベーク工程により、感光性高誘電率有機絶縁膜７ｂをリフロー処理することで、エッチング工程でエッチングされたコモン電極８の端部を、感光性高誘電率有機絶縁膜７ｂで覆うことができる。 Next, the end portion of the common electrode 8 etched in the etching process is covered with the photosensitive high dielectric constant organic insulating film 7b by performing a reflow process on the photosensitive high dielectric constant organic insulating film 7b by a post baking process. Can do.
その後、ステップＡ２（ピクセル電極の形成工程）において、ピクセル電極９を成膜した後、その上にフォトレジストを塗布し、フォトマスクを介して露光を行い、現像液の中に浸し、フォトレジストを現像する。更に、ピクセル電極９をエッチング工程でパターニングした後、剥離工程でフォトレジストを剥離し、ＴＦＴが完成する。なお、ポストベーク工程で、コモン電極８の端部を、感光性高誘電率有機絶縁膜７ｂで適切に覆うことができなかった場合、ピクセル電極９の成膜時にコモン電極８とピクセル電極９がショートする問題が生じる。 Thereafter, in step A2 (pixel electrode forming step), after the pixel electrode 9 is formed, a photoresist is applied thereon, exposed through a photomask, immersed in a developer, and the photoresist is applied. develop. Further, after patterning the pixel electrode 9 in the etching process, the photoresist is stripped in the stripping process, thereby completing the TFT. If the end of the common electrode 8 cannot be properly covered with the photosensitive high dielectric constant organic insulating film 7b in the post-bake process, the common electrode 8 and the pixel electrode 9 are not formed when the pixel electrode 9 is formed. The problem of short-circuiting occurs.
ここで、本発明の技術的特徴である、第２の層間絶縁膜７ｂとして使用する感光性高誘電率有機絶縁膜について、補足説明する。本実施の形態１における感光性高誘電率有機絶縁膜の誘電率εは、ε≧４としている。この理由は、一例として、ε＝３程度の誘電率とした場合には、寄生キャパシタの影響でフリッカが生じたり、分極が起きにくく残像が発生したり、駆動電圧が上昇したりする問題が発生することによる。 Here, the photosensitive high dielectric constant organic insulating film used as the second interlayer insulating film 7b, which is a technical feature of the present invention, will be supplementarily described. The dielectric constant ε of the photosensitive high dielectric constant organic insulating film in the first embodiment is ε ≧ 4. This is because, for example, when the dielectric constant is about ε = 3, there are problems that flickering occurs due to the influence of parasitic capacitors, polarization is difficult to occur, an afterimage is generated, and driving voltage is increased. By doing.
また、従来の薄膜トランジスタにおいて、第２の層間絶縁膜１０７ｂとして採用していたＳｉＮｘの誘電率は、６．７であるが、本実施の形態１の薄膜トランジスタにおいて、第２の層間絶縁膜７ｂとして採用した感光性高誘電率有機絶縁膜の誘電率は、４以上であれば、特性劣化が抑えられることを確認済みである。 In addition, the dielectric constant of SiNx used as the second interlayer insulating film 107b in the conventional thin film transistor is 6.7, but is used as the second interlayer insulating film 7b in the thin film transistor of the first embodiment. It has been confirmed that the deterioration of characteristics can be suppressed when the dielectric constant of the photosensitive high dielectric constant organic insulating film is 4 or more.
第２の層間絶縁膜７ｂとして使用する樹脂に、酸化金属ナノ粒子を分散させることで、感光性高誘電率有機絶縁膜の誘電率を高めることができ、所望の４以上の誘電率を得ることができる。 By dispersing metal oxide nanoparticles in the resin used as the second interlayer insulating film 7b, the dielectric constant of the photosensitive high dielectric constant organic insulating film can be increased, and a desired dielectric constant of 4 or more can be obtained. Can do.
また、感光性高誘電率有機絶縁膜を用いた薄膜トランジスタを適用した液晶表示装置において、従来の透明であったＳｉＮｘを用いた薄膜トランジスタを適用した液晶表示装置と同等の表示性能を確保するためには、感光性高誘電率有機絶縁膜として、透過率が９０％以上の透明樹脂を採用することが適切である。 In addition, in a liquid crystal display device to which a thin film transistor using a photosensitive high dielectric constant organic insulating film is applied, in order to ensure the same display performance as a liquid crystal display device to which a conventional thin film transistor using SiNx is applied. As the photosensitive high dielectric constant organic insulating film, it is appropriate to employ a transparent resin having a transmittance of 90% or more.
また、本実施の形態１における高誘電率有機絶縁膜としては、ネガ型、ポジ型のいずれの感光性樹脂も採用することができる。 In addition, as the high dielectric constant organic insulating film in the first embodiment, any of negative-type and positive-type photosensitive resins can be employed.
また、ステップＡ１で説明したリフロー処理としては、２００℃以上の温度で行うことが適切であることを確認済みである。 In addition, it has been confirmed that the reflow process described in step A1 is appropriate to be performed at a temperature of 200 ° C. or higher.
また、ステップＡ１の現像工程とコモン電極エッチング工程間に、ミドルベーク工程による加熱処理を加えることもできる。このような加熱処理により、その後のコモン電極エッチング工程における高誘電有機絶縁膜７ｂのエッチング液耐性を高めることができる。また、その後のポストベーク工程の熱により高誘電有機絶縁膜７ｂが適切にリフローできるように、このミドルベーク工程の温度は、例えば、１５０℃とし、ポストベーク工程よりも低い温度で行う必要がある。 Further, a heat treatment by a middle baking process can be added between the developing process and the common electrode etching process in step A1. Such heat treatment can increase the resistance of the high dielectric organic insulating film 7b to the etching solution in the subsequent common electrode etching step. In addition, the temperature of the middle baking process is set to 150 ° C., for example, so that the high dielectric organic insulating film 7b can be appropriately reflowed by the heat of the subsequent post baking process.
以上のように、実施の形態１によれば、コモン電極とピクセル電極との間の層間絶縁膜を、誘電率が４以上の感光性高誘電率有機絶縁膜を塗布することで形成している。この結果、真空成膜装置を不要にできるとともに、製造工程が簡素化され、コストの削減、および生産性向上を実現することができる。 As described above, according to the first embodiment, the interlayer insulating film between the common electrode and the pixel electrode is formed by applying a photosensitive high dielectric constant organic insulating film having a dielectric constant of 4 or more. . As a result, a vacuum film forming apparatus can be dispensed with, the manufacturing process is simplified, and cost reduction and productivity improvement can be realized.
また、コモン電極とピクセル電極との間の層間絶縁膜として、無機材料から樹脂材料へ変更した本発明の薄膜トランジスタを採用することで、Ｆｌｅｘｉｂｌｅ Ｄｉｓｐｌａｙに適用することができる。 Further, by adopting the thin film transistor of the present invention in which the inorganic material is changed to the resin material as the interlayer insulating film between the common electrode and the pixel electrode, it can be applied to a flexible display.
また、コモン電極とピクセル電極との間の層間絶縁膜は、ネガ型、ポジ型のいずれの感光性樹脂も採用することができ、設計の自由度を増大することができる。 In addition, as the interlayer insulating film between the common electrode and the pixel electrode, either negative type or positive type photosensitive resin can be adopted, and the degree of freedom in design can be increased.
また、２００℃以上の温度でリフロー処理を行うことで、コモン電極の端部を感光性高誘電率絶縁樹脂で覆うことができ、コモン電極とピクセル電極のショートを防止できる。 Further, by performing the reflow treatment at a temperature of 200 ° C. or higher, the end portion of the common electrode can be covered with a photosensitive high dielectric constant insulating resin, and a short circuit between the common electrode and the pixel electrode can be prevented.
１ ガラス基板、２ ゲート電極、３ ゲート絶縁膜、４ アモルファスシリコン、５ ソース／ドレイン電極、６ バッファ層、７ａ 第１の層間絶縁膜、７ｂ 第２の層間絶縁膜、８ コモン電極、９ ピクセル電極。 1 glass substrate, 2 gate electrode, 3 gate insulating film, 4 amorphous silicon, 5 source / drain electrode, 6 buffer layer, 7a first interlayer insulating film, 7b second interlayer insulating film, 8 common electrode, 9 pixel electrode .
Claims (10)
前記コモン電極と前記ピクセル電極との間の層間絶縁膜が、誘電率４以上の有機絶縁膜を塗布することで形成されている
薄膜トランジスタ。 In a thin film transistor having a fringe field switching (FFS) structure in which a common electrode and a pixel electrode are disposed through an insulating layer,
A thin film transistor in which an interlayer insulating film between the common electrode and the pixel electrode is formed by applying an organic insulating film having a dielectric constant of 4 or more.
前記層間絶縁膜は、ネガ型あるいはポジ型のいずれかの感光性樹脂である
薄膜トランジスタ。 The thin film transistor according to claim 1, wherein
The interlayer insulating film is a negative or positive photosensitive resin.
前記層間絶縁膜は、誘電率を４以上とするために、酸化金属ナノ粒子が分散されている
薄膜トランジスタ。 The thin film transistor according to claim 1 or 2,
The interlayer insulating film is a thin film transistor in which metal oxide nanoparticles are dispersed so as to have a dielectric constant of 4 or more.
前記層間絶縁膜は、透過率が９０％以上の透明樹脂である
薄膜トランジスタ。 The thin film transistor according to any one of claims 1 to 3,
The interlayer insulating film is a transparent resin having a transmittance of 90% or more.
前記コモン電極の上に、前記有機絶縁膜を塗布する絶縁膜形成工程と、
前記絶縁膜形成工程により塗布された前記有機絶縁膜をマスクとして、前記コモン電極をエッチングするエッチング工程と、
前記有機絶縁膜をリフロー処理することで、前記エッチング工程でエッチングされた前記コモン電極の端部を前記有機絶縁膜で覆うポストベーク工程と、
前記ポストベーク工程の後に、ピクセル電極を成膜形成するピクセル電極形成工程と
を有する薄膜トランジスタの製造方法。 A method of manufacturing a thin film transistor, wherein an interlayer insulating film between a common electrode and a pixel electrode is formed by applying an organic insulating film having a dielectric constant of 4 or more,
An insulating film forming step of applying the organic insulating film on the common electrode;
An etching step of etching the common electrode using the organic insulating film applied in the insulating film forming step as a mask;
A post-baking step of covering the end portion of the common electrode etched in the etching step with the organic insulating film by reflowing the organic insulating film;
A pixel electrode forming step of forming a pixel electrode into a film after the post-baking step.
前記ポストベーク工程における前記リフロー処理は、２００℃以上の温度で行われる
薄膜トランジスタの製造方法。 In the manufacturing method of the thin-film transistor of Claim 5,
The said reflow process in the said post-baking process is performed at the temperature of 200 degreeC or more. The manufacturing method of a thin-film transistor.
前記絶縁膜形成工程の後であり、前記エッチング工程の前に、ミドルベーク工程を有する
薄膜トランジスタの製造方法。 In the manufacturing method of the thin-film transistor of Claim 5 or 6,
A method for manufacturing a thin film transistor, comprising a middle baking step after the insulating film forming step and before the etching step.
前記ミドルベーク工程の温度は、前記ポストベーク工程の温度よりも低い
薄膜トランジスタの製造方法。 In the manufacturing method of the thin-film transistor of Claim 7,
The temperature of the middle baking process is lower than the temperature of the post baking process.
前記ポストベーク工程の前に前記エッチング工程を行う
薄膜トランジスタの製造方法。 In the manufacturing method of the thin-film transistor of any one of Claim 5 to 8,
The manufacturing method of the thin-film transistor which performs the said etching process before the said post-baking process.
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