JP2015122574A - Transmission circuit and transmission/reception circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To match latency and synchronization release timing among channels.SOLUTION: A transmission circuit, which has a plurality of channels which can operate with different clocks and transmits transmission data to a reception circuit from each of the channels, includes a synchronization signal generation circuit for generating mutually synchronized, same frequency synchronization signals for each of the channels on the basis of each of clocks for the plurality of channels. Each channel includes a FIFO for outputting a digital signal, synchronized to a first clock defined for each channel, and a synchronization signal with synchronizing to a second clock defined for each channel, a control interface for signal processing and outputting a digital signal outputted by the FIFO according to the second clock, and a transmission part for transmitting a signal outputted by the control interface to the reception circuit. The control interface of each channel starts signal processing for a digital signal according to a synchronization signal outputted by the FIFO.

Description

  The present invention relates to a transmission circuit and a transmission / reception circuit. In particular, the present invention relates to a transmission circuit using a high-speed serializer and a control interface.

In general, an AD converter for use in a radio base station is required to operate with high accuracy and high speed. For this reason, pipeline AD converters are often used as AD converters for wireless base stations. In general, in a radio base station application, an AD converter having a large number of output bits is provided in parallel. Each AD converter is provided with a signal line for outputting a digital signal. Therefore, there are a plurality of signal lines corresponding to the plurality of AD converters. Here, as a technique for reducing the number of signal lines in the AD converter, a high-speed serial interface is used. (For example, refer to Patent Document 1).
[Prior art documents]
[Patent Literature]
[Patent Document 1] US 2004/0103440

  Examples of the standard for the high-speed serial interface include JESD204B by the US standardization organization JEDEC SOLID STATE TECHNOLOGY ASSOCIATION. The JESD 204B is often used as a serial interface for high-speed A / D converters. The maximum signal rate of JESD204B is supported from 312.5 Mbps to 12.5 Gbps per lane. A lane is a unit in which a pair of serializer differential signal output lines is one lane.

  FIG. 1 is a diagram showing a general transmission / reception circuit 300. The transmission / reception circuit 300 includes a transmission circuit 100 and a reception circuit 200. Although FIG. 1 shows an example in which the number of lanes L is 2, L may be an arbitrary natural number. The transmission circuit 100 is generally a circuit having a plurality of AD converters. The receiving circuit 200 is a circuit generally composed of a logic device.

  The transmission circuit 100 receives synchronization confirmation signals SYNC1_N and SYNC2_N from the reception circuit 200. The transmission circuit 100 converts digital signals output from a plurality of AD converters into serial data represented by a pair of differential signals DO1P and DO1N and another pair of differential signals DO2P and DO2N. The transmission circuit 100 outputs the serial data to the reception circuit 200. The pair of differential signals DO1P and DO1N are called lane 0 signals, and the other pair of differential signals DO2P and DO1N are called lane 1 signals. The transmission circuit 100 transmits serial data to the reception circuit 200 via the lane 0 and the lane 1.

  When the synchronization confirmation signals SYNC1_N and SYNC2_N are at the L level, the transmission circuit 100 synchronizes with the pair of differential signals DO1P and DO1N and the pair of differential signals DO2P and DO2N in order to synchronize with the reception circuit 200, respectively. Embed 5 When the synchronization confirmation signals SYNC1_N and SYNC2_N transition from the L level to the H level, it means that the synchronization between the transmission circuit 100 and the reception circuit 200 is completed. Thereafter, the transmission circuit 100 converts digital signals output from the plurality of AD converters into a standard format of a high-speed serial interface, and receives the pair of differential signals DO1P and DO1N and a pair of differential signals DO2P and DO2N as the reception circuit 200. Output to.

  The receiving circuit 200 converts the pair of differential signals DO1P and DO1N, which is serial data, and the pair of differential signals DO2P and DO2N into parallel data, and restores digital signals output from the plurality of AD converters. The reception circuit 200 outputs L level synchronization confirmation signals SYNC1_N and SYNC2_N to the transmission circuit 100 in order to confirm synchronization with the transmission circuit 100. That is, the reception circuit 200 requests the synchronization data K28.5 from the transmission circuit 100. When the reception circuit 200 normally receives the pair of differential signals DO1P and DO1N output from the transmission circuit 100 and the synchronization data K28.5 embedded in the pair of differential signals DO2P and DO2N, the synchronization confirmation signals SYNC1_N and SYNC2_N are received. Is shifted from the L level to the H level and output to the transmission circuit 100. Thereafter, the reception circuit 200 starts receiving digital signals output from the plurality of AD converters in the transmission circuit 100.

  FIG. 2 is a diagram showing a transmission circuit 100 as a first conventional example. The transmission circuit 100 includes a first channel 10, a second channel 20, a clock interface (CLKIF) 30, a PLL (Phase Locked Loop) 34, and a SYNC combine 36. The first channel 10 includes an AD converter 12 as a plurality of AD converters, a control interface 14, and a serializer 16. Similarly, the second channel 20 includes an AD conversion unit 22, a control interface 24, and a serializer 26.

  The AD conversion unit 12 includes M AD converters connected in parallel. M is an arbitrary natural number. An analog input signal AINP is input to each AD converter of the AD converter 12. Each AD converter of the AD converter 12 converts the analog signal AINP into a digital signal ADP. Similarly to the AD conversion unit 12, the AD conversion unit 22 includes M AD converters connected in parallel. An analog input signal AINP is input to the AD conversion unit 22, and the AD conversion unit 22 converts the analog signal AINP into a digital signal ADP.

  The AD conversion unit 12 outputs the digital signal ADP to the control interface 14. Similarly, the AD conversion unit 22 outputs a digital signal ADS to the control interface 24. Each of the plurality of AD converters outputs an N-bit digital signal. Therefore, the digital signals ADP and ADS are each a digital signal in which M pieces of N-bit signals are arranged in parallel. The parallel digital signals are indicated by thick lines in FIG.

  The control interface 14 converts the digital signal ADP into a digital signal IFO1 having a data format conforming to the high-speed serial interface standard. Similarly, the control interface 24 converts the digital signal ADS into a digital signal IFO2. The digital signals IFO1 and IFO2 are T-bit digital signals, respectively. Digital signal IFO1 and digital signal IFO2 are output to serializers 16 and 26, respectively. Since IFO1 and IFO2 are also parallel digital signals, they are indicated by bold lines in FIG.

  The serializer 16 converts the digital signal IFO1 into serial data for one lane. Then, the serializer 16 outputs a pair of differential signals DO1P and DO1N through the lane 0. Similarly, the serializer 2 converts the digital signal IFO2 into serial data, and outputs a pair of differential signals DO2P and DO2N through the lane 1.

  A pair of differential signals DO1P and DO1N output from the serializer 16 are signals conforming to the amplitude, rise time, fall time, and the like defined by the standard JESD 204B or the like. The pair of differential signals has a small amplitude compared to a general CMOS level output signal. Moreover, since it is a differential signal, EMI (Electro-Magnetic Interference) is reduced. Therefore, high speed operation is realized with low power consumption.

  To the SYNC combine 36, synchronization confirmation signals SYNC1_N and SYNC2_N for each lane are input from the receiving circuit 200. The SYNC combine 36 outputs a signal obtained by combining the synchronization signal confirmation signals SYNC1_N and SYNC2_N to the control interfaces 14 and 24 of each lane. Specifically, the SYNC combine 36 outputs a logical product signal of the synchronization signal confirmation signals SYNC1_N and SYNC2_N to the control interfaces 14 and 24. When synchronization between channels is performed, the synchronization of the control interfaces 14 and 24 is released when the synchronization is released in both channels, that is, when the synchronization signals SYNC1_N and SYNC2_N are both at the H level.

  The clock interface 30 generates a clock signal CKP of the AD conversion units 12 and 22 and a clock signal CKP as a reference clock of the PLL 34. The clock signal CKP becomes a reference clock in the transmission circuit 100.

  The PLL 34 applies feedback control based on the clock signal CKP to synchronize the phases of the input signal and the output signal. As a result, the PLL 34 generates a signal obtained by multiplying the clock signal CKP by an arbitrary integer multiple frequency. For example, the PLL 34 generates a clock signal IFCK obtained by multiplying the frequency of CKP by F and a clock signal SCK obtained by multiplying the frequency of CKP by F × (T / 2). The PLL 34 outputs the clock signal IFCK to the control interfaces 14 and 24, and outputs the clock signal SCK to the serializers 16 and 26.

  F is the number of octet data frames used in the control interfaces 14 and 24, as will be described later. T is the number of IFO1 and IFO2 bits output from the serializers 16 and 26 as described above. In the above-mentioned JESD204B standard, T is usually 10. When the frequency of the clock signal SCK input to the serializers 16 and 26 is f_SCK and the frequency of the clock signal IFCK input to the control interfaces 14 and 24 is f_IFCK, the relationship between them is expressed by the following equation (1). The

  Since the clock signals IFCK and SCK are generated by one PLL 34 based on the clock signal CKP of the clock interface 30, the clock signals of the AD converters 12 and 24, the control interfaces 14 and 24, and the serializers 16 and 26 are All are synchronized. Thereby, the timing at which the synchronization between the transmission circuit 100 and the reception circuit 200 is released by the combined synchronization signal output from the SYNC combine 36 is the same timing for each channel. Thus, synchronization between channels is realized.

  FIG. 3 is a diagram showing the control interface 14. The control interface 14 includes a frame-to-octet mapping unit 142, a scrambler 144, a character replacement unit 146, an initial lane alignment unit 145, a controller 140, a selector 147, and a bit conversion unit 148. Each block operates with a clock signal IFCK1 input from the PLL 34 to the control interface 14. As described above, the thick lines in FIG. 3 indicate parallel digital signals. Details of the controller 140 will be described with reference to FIG.

  The controller 140 outputs a state signal described in FIG. The controller 140 also has an octet counter that operates in units of octet frames used for the operation of the frame to octet mapping unit 142 and a multiframe counter that operates in units of multiframes used for the operation of the initial lane alignment unit 145. The multiframe is a group of frame data, and the upper limit value of the multiframe counter is represented by K (a value obtained by dividing the number of frames by the number of multiframes). Such a control method is a method defined in the JESD204B standard.

  The frame to octet mapping unit 142 groups and maps the digital signal ADP output from the AD conversion unit 12 by octet data in units of 8 bits. For example, when the number of output bits of the AD conversion unit 12 is 12 bits (N = 12) and four AD conversion units 12 are provided in parallel (M = 4), the frame to octet mapping unit 142 is , 48 bits (12 bits × 4) are grouped into 6 (48 bits / 8 bits) and mapped. The value 6 is the value of F (F = 6 (octet / frame)).

  The relationship between the frequency f_CKP of the clock signal CKP of the AD converter 12 and the frequency f_IFCK of the clock signal IFCK of the control interface 14 is expressed by the following formula 2 using F.

  Note that although the number of output bits of the AD conversion unit 12 is 12 bits (N = 12), mapping may be performed by regarding the number of output bits as 16 bits. That is, each AD conversion unit 12 may be allocated in units of 16 bits and mapped with F = (16 × 4) bits / 8 bits = 8 (octets / frame). In this case, control bits can be embedded in the free 4 bits (= 16 bits−12 bits).

  The scrambler 144 receives octet data from the frame to octet mapping unit 142. The scrambler 144 agitates the order between the input octet data and prevents the same data pattern from being repeated. This prevents energy peaks from concentrating on a specific frequency. The scrambler 144 outputs the stirred octet data to the character replacement unit 146.

  When the same data continues in the signal output from the scrambler 144, the character replacement unit 146 replaces a part of the continuous data with synchronous data. By performing the replacement, synchronization data is periodically embedded. Since the synchronization data is monitored by the reception circuit 200, synchronization between the transmission circuit 100 and the reception circuit 200 can be confirmed periodically. The output of the character replacement unit 146 is connected to the first input terminal of the selector 147.

  The initial lane alignment unit 145 operates in units of multiframes. For example, in the multi-frame, the octet data frame may be one frame. The initial lane alignment unit 145 embeds synchronization data in the first and last octet data in the multiframe. Based on the synchronization data, in the receiving circuit 200, an initial lane alignment state (Initial Lane Alignment state, hereinafter abbreviated as ILA state), which is a state in which synchronization is released, and a state (DATA_ENC) for outputting data of the AD conversion unit 12 It is possible to recognize the boundary position of the state transition to (state). The output terminal of the initial lane alignment unit 145 is connected to the second input terminal of the selector 147.

  The selector 147 outputs either one of the initial lane alignment unit 145 and the character replacement unit 146 to the bit conversion unit 148 in accordance with the state signal of the controller 140 described in FIG. When the state signal in the SYNC state or DATA_ENC state described in FIG. 4 is input from the controller 140, the selector 147 outputs an input from the first input terminal. On the other hand, the selector 147 outputs the input from the second input terminal when the controller 140 receives the ILA state signal described in FIG.

  An output signal of the selector 147 is input to the bit conversion unit 148. The bit conversion unit 148 may be an 8b10b conversion unit that performs encoding by extending 8-bit (octet) data to 10-bit data. The bit conversion unit 148 can embed a clock in the data by a technique used for serial data transfer, so that the data and the clock can be transferred through the same wiring. The bit conversion unit 148 converts the data so that the period of the 0 state or the 1 state does not continue for 5 bits or more for any data. Therefore, AC (Alternating Current) coupling of the differential signal of the serializer 16 is possible. The output signal IFO1 of the bit conversion unit 148 is output to the serializer 16.

  The control interface 24 has the same configuration as the control interface 14. However, the difference from the control interface 14 is that SYNC2_N is input to the controller 140, ADS is input to the frame-to-octet mapping unit 142, and the output signal IFO2 is output from the bit conversion unit 148 to the serializer 26. is there.

  FIG. 4 is a diagram illustrating a conceptual diagram of the state machine of the controller 140. The synchronization state (SYNC state) means that the transmission circuit 100 transmits K28.5 data to the reception circuit 200 to synchronize the transmission circuit 100 and the reception circuit 200, and the reception circuit 200 transmits the SYNC1_N and SYNC2_N to the transmission circuit 100. Is the state of the controller 140 that is transmitting The initial lane alignment state (ILA state) is a state of the controller 140 indicating an intermediate state from when the synchronization between the transmission circuit 100 and the reception circuit 200 is completed until data output is performed. The data output state (DATA_ENC state) is a state of the controller 140 that outputs ADP or ADS data from the transmission circuit 100 to the reception circuit 200 after the ILA state.

  The controller 140 receives a combined synchronization signal of the synchronization confirmation signals SYNC1_N and SYNC2_N from the SYNC combine 36. When the controller 140 is in the SYNC state or the DATA_ENC state, the controller 140 controls the frame to octet mapping unit 142 to output an input to the first input terminal of the selector 147. In addition, when the controller 140 is in the ILA state, the controller 140 controls the initial lane alignment unit 145 and outputs an input to the second input terminal of the selector 147.

  Here, it is assumed that the controller 140 is in the SYNC state. In this case, when the controller 140 receives an L level synchronization signal (a synchronization signal when SYNC1_N or SYNC2_N is at L level) from the SYNC combine 36, the controller 140 embeds the synchronization data K28.5 in the data and receives the data. The control interface 14 is controlled to output to 200. This corresponds to the sync_request_tx in FIG. Thereby, the SYNC state is maintained. In the SYNC state, synchronization between the transmission circuit 100 and the reception circuit 200 is not completed.

  On the other hand, in the SYNC state, when the controller 140 receives an H level coupling synchronization signal (a coupling synchronization signal when SYNC1_N and SYNC2_N are both H) from the SYNC combine 36, the SYNC state is canceled. The combined synchronization signal being at the H level means that the synchronization between the transmission circuit 100 and the reception circuit 200 has been completed. When synchronization is complete, the controller 140 transitions to the ILA state. The release of the SYNC state corresponds to an inverted signal of sync_request_tx in FIG. In FIG. 4, the exclamation mark means inversion of the signal.

  Until the initial lane alignment is completed, the controller 140 continues the ILA state. At this time, the controller 140 does not transition to a SYNC state or a DATA_ENC state described later. Continuation of the ILA state corresponds to an inverted signal of lane_seq_end in FIG.

  When the control time of the ILA state is completed, the controller 140 transitions to the DATA_ENC state. The transition to the DATA_ENC state corresponds to lane_seq_end in FIG. Until the data output is completed, the DATA_ENC state continues and does not transit to the SYNC state. The continuation of the DATA_ENC state corresponds to an inverted signal of sync_request_tx in FIG. When synchronization is released in the ILA state or DATA_ENC state, the state transits to the SYNC state. This corresponds to the sync_request_tx transitioning from the ILA state and the DATA_ENC state to the SYNC state in FIG. Since the synchronization release timing of each channel is uniquely determined by the combined synchronization signal output from the SYNC combine 36, synchronization between channels is realized.

  FIG. 5 is a timing chart when the synchronization of the transmission circuit 100 is canceled. The arrow direction represents time. The black portions of ADP and ADS indicate the position of specific data. Also, the black portions of IFO1 and IFO2 correspond to the black portions of ADP and ADS, respectively. ILA_COUNT 1 and ILA_COUNT 2 are octet counters that the controller 140 uses for the operation of the frame-to-octet mapping unit 142. The controller 140 counts up to octet counters # 1 to # 4 to form one multiframe. The period of the one multiframe corresponds to a period in which the ILA state is set. K28.5 corresponds to the SYNC state, and DATA corresponds to the DATA_ENC state.

  As shown in the drawing, the timing at which the synchronization confirmation signal SYNC1_N of lane 0 becomes H level is different from the timing at which the synchronization confirmation signal SYNC2_N of lane 1 becomes H level. However, even if the timing at which synchronization confirmation can be taken differs between channels, the synchronization of each channel can be released simultaneously by combining the synchronization confirmation signals SYNC1_N and SYNC2_N with the SYNC combine 36.

  Further, since the clock signal CKP, the clock signal IFCK, and the clock signal SCK are all in a synchronous relationship, all the clock signals between channels are in a synchronous relationship. As a result, the start position and end position of the ILA state and the start position of the DATA_ENC state coincide between the channels. The data output timings of IFO1 and IFO2 also match between channels.

  FIG. 6 is a diagram illustrating a transmission circuit 101 that controls each channel using a plurality of PLL circuits as Conventional Example 2. In FIG. In the case of a simple transmission circuit 100 as in Conventional Example 1, the clock signal can be managed by a single PLL 34. However, as in Conventional Example 2, in order to realize a flexible transmission circuit using a different PLL for each channel, it is necessary to manage each channel with a different clock for each channel.

  The transmission circuit 101 of the conventional example 2 in FIG. 6 is provided with a PLL 38 for the first channel 10 and a PLL 39 for the second channel 20 in order to operate with different clocks for each channel. This is different from the transmission circuit 100 of the conventional example 1 in FIG. Another difference is that a FIFO 13 is provided between the AD converter 12 and the control interface 14, and a FIFO 23 is provided between the AD converter 22 and the control interface 24. However, the configurations of the AD conversion units 12 and 22, the control interfaces 14 and 24, the serializers 16 and 26, and the SYNC combine 36 are the same as those of the conventional example 1 in FIG.

  The transmission circuit 101 includes a first channel 10, a second channel 20, a clock interface (CLKIF) 30, a PLL 34, a SYNC combine 36, a PLL 38 and a PLL 39. The first channel 10 includes an AD converter 12 as a plurality of AD converters, a control interface 14, and a serializer 16. Similarly, the second channel 20 includes an AD conversion unit 22, a control interface 24, and a serializer 26.

  The clock interface 30 generates a reference clock for the PLL 34. The PLL 34 receives the reference clock and generates clock signals CKP and CKS. Since the clock signals CKP and CKS are generated by the same PLL, they are in synchronization with each other. The clock signal CKP is supplied to the AD conversion unit 12, the FIFO 13, and the PLL 38 in the first channel 10. On the other hand, the clock signal CKS is supplied to the AD conversion unit 22, the FIFO 23, and the PLL 39 in the second channel 20.

  The PLL 38 generates a clock signal IFCK1 obtained by multiplying the frequency of the CKP by F, and a clock signal SCK1 obtained by multiplying the frequency of the CKP by F × (T / 2). The PLL 38 outputs the clock signal IFCK1 to the FIFO 13 and the control interface 14. The PLL 38 outputs the clock signal SCK1 to the serializer 16. As described above, F (octet / frame) is a value obtained by dividing the number of output bits of the AD converter 12 by 8 bits. T is the number of bits of IFO1.

  The PLL 39 generates a clock signal IFCK2 obtained by multiplying the frequency of CKS by F and a clock signal SCK2 obtained by multiplying the frequency of CKP by F × (T / 2). The PLL 39 outputs the clock signal IFCK2 to the FIFO 23 and the control interface 24. The PLL 39 outputs the clock signal SCK2 to the serializer 26. F (octet / frame) is a value obtained by dividing the number of output bits of the AD converter 22 by 8 bits. T is the number of bits of IFO2.

  The AD conversion unit 12 outputs the digital signal ADP to the FIFO 13. Similarly, the AD conversion unit 22 outputs the digital signal ADS to the FIFO 23.

  The FIFOs 13 and 23 are circuits that pass data between circuits that operate with asynchronous clocks. For example, the FIFO 13 can pass data from the AD converter 12 to the control interface 14 even if the clock signal CKP of the AD converter 12 and the clock signal IFCK1 of the control interface 14 are asynchronous. Similarly, the FIFO 23 transfers data from the AD conversion unit 22 to the control interface 24. The configuration of the FIFOs 13 and 23 will be described in more detail in FIG.

  The control interfaces 14 and 24 convert the digital signals ADP and ADS into digital signals IFO1 and IFO2 having a data format conforming to the high-speed serial interface standard, respectively. Digital signal IFO1 and digital signal IFO2 are output to serializers 16 and 26, respectively.

  The relationship between the frequency of the clock signal CKP of the AD conversion unit 12 and the frequency of the clock signal CKS of the AD conversion unit 22 is expressed by the following formula 3. f_CKP and f_CKS are the frequencies of the clock signals CKP and CKS, respectively. D is a natural number that is a power of 2.

  Further, the relationship between the frequency of the clock signal CKP of the AD converter 12 and the frequency of the clock signal IFCK1 of the control interface 14 is expressed by the following equation (4). Here, f_IFCK1 is the frequency of the clock signal IFCK1, and F1 (octet / frame) is a value obtained by dividing all bits output from the AD converter 12 by 8 bits.

  Further, the relationship between the frequency of the clock signal CKS of the AD conversion unit 22 and the frequency of the clock signal IFCK2 of the control interface 24 is expressed by the following formula 5. Here, f_IFCK2 is the frequency of the clock signal IFCK2, and F2 (octet / frame) is a value obtained by dividing all the bits output from the AD converter 22 by 8 bits.

  Further, the relationship between the frequency of the clock signal SCK1 of the serializer 16 and the frequency IFCK1 of the clock signal of the control interface 14 is expressed by the following equation (6). The relationship between the frequency of the clock signal SCK2 of the serializer 26 and the frequency IFCK2 of the clock signal of the control interface 24 is expressed by the following Expression 7. Here, f_SCK1 and f_SCK2 are the frequencies of the clock signals SCK1 and SCK2, respectively. T is the number of bits of the output signals IFO1 and IFO2 of the control interfaces 14 and 24.

  FIG. 7 is a diagram showing the FIFO 13. The FIFO 13 includes a memory 130, a write address counter 132, a POP counter 134, a frequency divider 136, and a read address counter 138.

  In the memory 130, the write data ADP is written to the memory array managed by the write address WADR in synchronization with the clock signal CKP of the write address counter 132. The memory 130 reads data FO1 from the memory array managed by the read address RADR in synchronization with the clock signal of the read address counter 138. The clock signal of the read address counter 138 is a clock signal obtained by dividing the IFCK1 output from the PLL 38 by the frequency divider 136.

  The write address counter 132 is a counter that counts up the clock number of the clock signal CKP when the write enable signal WEN is at the H level. The write address counter 132 associates the counted up numerical value with the write address WADR. Thus, the number of clocks of the clock signal CKP when the write enable signal WEN is at the H level is made to correspond to the address of the memory array managed by the write address WADR. The write enable signal WEN is output from the control unit 139 to the write address counter 132 and the memory 130.

  When the write address counter 132 counts a predetermined count, the POP counter 134 receives a POP signal that is an H level pulse signal from the write address counter 132. For example, the POP counter 134 receives the POP signal from the write address counter 132 when the write address counter 132 counts the clock signal CKP by two.

  The POP counter 134 is a counter that counts the POP signal. When the POP counter 134 counts the POP signal by a predetermined number, the POP counter 134 outputs an H level signal as the read enable signal REN to the read address counter 138 and the memory 130. Thereby, the rising timing of the write enable signal WEN and the rising timing of the read enable signal REN can be shifted by the number of clocks of the clock signal CKP. In general, the rising timing of both is shifted by 3 clocks or more.

  The frequency divider 136 outputs a clock signal obtained by dividing the clock signal IFCK1 of the control interface 14. The frequency divider 136 outputs the frequency-divided clock to the memory 130 and the read address counter 138. Note that the frequency of the frequency-divided clock signal and the clock signal CKP is the same.

  The read address counter 138 is a counter that counts up the number of clocks of the clock signal in synchronization with the clock signal output from the frequency divider 136 when the read enable signal REN is at the H level. The read address counter 138 associates the counted up numerical value with the read address RADR. Thus, when the read enable signal REN is at the H level, the number of clocks of the divided clock signal is made to correspond to the address of the memory array managed by the read address RADR.

  Since the rising timing of the write enable signal WEN and the rising timing of the read enable signal REN are shifted by several clocks, the relationship between the write address WADR and the read address RADR can always be uniquely determined. As a result, the FIFO 13 can synchronize input / output data even when the clock signal CKP input to the write address counter 132 and the clock signal input to the read address counter 138 are asynchronous.

  The FIFO 23 has the same configuration as the FIFO 13. However, in the FIFO 13, ADS is input to the memory 130 instead of ADP, CKS is input to the memory 130 and the write address counter 132 instead of CKP, and IFCK2 is input to the frequency divider 136 instead of IFCK1. Further, a digital signal FO 2 is output from the memory 130.

  The PLL 38 that generates the clock signal IFCK1 is cascade-connected to the PLL 34 that generates the clock signal CKP. The clock signal IFCK1 is generated in the PLL 38 based on the clock signal CKP of the PLL 34. In this case, the phase relationship between the clock signal CKP and the clock signal IFCK1 is not uniquely determined. Therefore, in order to uniquely determine the phase relationship between the clock signal CKP and the clock signal IFCK1, a FIFO 13 is required between the AD conversion unit 12 and the control interface 14. For the same reason, the FIFO 23 is required between the AD conversion unit 22 and the control interface 24. However, there is a problem that latencies between channels are different due to the influence of asynchronous synchronization in each of the FIFOs 13 and 23.

  In addition, when different clock signals IFCK1 and IFCK2 are used in each channel, the control interfaces 14 and 24 are also in an asynchronous relationship. In particular, when different F1 and F2 (octets / frame) are used in each channel, the clock signals IFCK1 and IFCK2 are different. Therefore, even if the control interfaces 14 and 24 receive the combined synchronization signal of the synchronization confirmation signals SYNC1_N and SYNC2_N as in Conventional Example 1, asynchronous synchronization is separately required between the control interfaces 14 and 24. Therefore, there is a problem that the timing for releasing synchronization is not uniform between channels.

  In Conventional Example 2, inter-channel synchronization cannot be realized due to the two problems described above. Note that inter-channel synchronization cannot be realized if any one of the problems is still unsolved.

  FIG. 8 is a timing chart after the synchronization cancellation in the transmission circuit 101. The arrow direction represents time. In addition to the signals described in FIG. 5, FO1 that is the output of the FIFO 13 and FO2 that is the output of the FIFO 23 are added. FIG. 8 is a timing chart when D = 4 (ratio of the frequency of the clock signal CKP to the frequency of the clock signal CKS) and T = 10 (T is the number of output bits of IFO1 and IFO2).

  (1) in the figure is a shift caused by asynchronous synchronization in each of the FIFOs 13 and 23. There is a shift in the start positions of IFO1 and IFO2 between channels. Further, (2) in the figure is a shift caused by the asynchronousness of the clock signals IFCK1 and IFCK2 of the control interfaces 14 and 24. There is a difference between the start position of the ILA state, the end position of the ILA state, and the start position of the DATA_ENC state between the channels.

  In the first aspect of the present invention, there is provided a transmission circuit that includes a plurality of channels that can be operated with different clocks, and that transmits transmission data from each channel to a reception circuit, based on the respective clocks in the plurality of channels. And a synchronization signal generation circuit for generating a synchronization signal of the same frequency synchronized with each other for each channel, and each channel receives a digital signal synchronized with a first clock determined for each channel and a synchronization signal as a channel. Receives a FIFO output in synchronization with the second clock determined every time, a control interface that outputs a digital signal output from the FIFO in accordance with the second clock, and a signal output by the control interface A transmission unit for transmitting to the circuit, and a control interface for each channel. Face, depending on the synchronization signal the FIFO output, provides a transmission circuit for starting the signal processing for the digital signal.

  According to a second aspect of the present invention, there is provided a transmission circuit that includes a plurality of channels that can be operated with different clocks, and that transmits transmission data from each channel to a reception circuit, based on the respective clocks in the plurality of channels. A synchronization signal generation circuit that generates a synchronization signal of the same frequency synchronized with each other for each channel, and each channel defines a digital signal synchronized with a first clock determined for each channel for each channel. A control interface that performs signal processing according to the second clock and outputs the signal; and a transmission unit that transmits a signal output from the control interface to the receiving circuit. A transmission circuit for initiating signal processing is provided.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 is a diagram showing a general transmission / reception circuit 300. FIG. It is a figure which shows the transmission circuit 100 as the prior art example 1. FIG. It is a figure which shows the control interface. It is a figure which shows the state machine conceptual diagram of the controller 140. FIG. FIG. 6 is a diagram illustrating a timing chart when the synchronization of the transmission circuit 100 is canceled. It is a figure which shows the transmission circuit 101 as a prior art example 2 which controls each channel by several PLL circuit. It is a figure which shows FIFO13. FIG. 6 is a diagram illustrating a timing chart after the synchronization is canceled in the transmission circuit 101. It is a figure which shows the transmission circuit 102 in 1st Embodiment. 4 is a diagram illustrating an operation timing chart of the synchronization signal generation circuit 40. FIG. 2 is a diagram illustrating a first FIFO 13 of a transmission circuit 102. FIG. 2 is a diagram illustrating a control interface 14 of a transmission circuit 102. FIG. FIG. 6 is a diagram illustrating a timing chart when the synchronization of the transmission circuit 102 is released. It is a figure which shows the transmission circuit 103 in 2nd Embodiment. FIG. 6 is a diagram illustrating a timing chart when the synchronization of the transmission circuit 103 is released.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

(Embodiment 1)
FIG. 9 is a diagram illustrating the transmission circuit 102 according to the first embodiment. The transmission circuit 102 is a part of the transmission / reception circuit 300 including the reception circuit 200 shown in FIG. The transmission circuit 102 is a transmission circuit that transmits transmission data from each channel to the reception circuit 200. The same members as those in FIGS. 2 and 6 are denoted by the same reference numerals. The transmission circuit 102 includes a first channel 10, a second channel 20, a clock interface 30, a PLL 34, a SYNC combine 36 as a synchronous coupling unit, PLL 38 and PLL 39 used for each channel, and a synchronization signal generation circuit (Local A Multi Frame Clock Generator) 40.

  In the transmission circuit 102, the first channel 10 and the second channel 20 can operate with different clocks. In this example, a clock signal CKP as a first clock defined in the first channel 10 and a clock signal CKS as a first clock defined in the second channel 20 are used. In addition, IFCK1 as the second clock defined in the first channel 10 and IFCK2 as the second clock defined in the second channel 20 are used.

  The clock signal CKP is input to the AD converter 12, the FIFO 13, the PLL 38, and the synchronization signal generation circuit 40. The clock signal CKS is input to the AD converter 22, the FIFO 23, the PLL 39, and the synchronization signal generation circuit 40. The clock signal IFCK1 is input to the FIFO 13 and the control interface 14. The clock signal IFCK2 is input to the FIFO 23 and the control interface 24.

  The SYNC combine 36 receives, for each channel, synchronization confirmation signals SYNC1_N and SYNC2_N that are output when the receiving circuit 200 is synchronized with the first channel 10 and the second channel 20. The SYNC combine 36 outputs a combined synchronization signal LMFC_REQ to the synchronization signal generation circuit 40 when receiving the synchronization confirmation signals SYNC1_N and SYNC2_N of the channels 10 and 20, respectively.

  The synchronization signal generation circuit 40 generates synchronization signals LMFCP and LMFCS having the same frequency synchronized with each other for each channel. The synchronization signal generation circuit 40 generates synchronization signals LMFCP and LMFCS based on the clock signals CKP and CKS in the first channel 10 and the second channel 20, respectively. A specific method for generating the synchronization signals LMFCP and LMFCS will be described in more detail with reference to FIG.

  The synchronization signal generation circuit 40 receives the combined synchronization signal LMFC_REQ from the SYNC combine 36, and generates the write enable signals WENP and WENS. Specifically, the synchronization signal generation circuit 40 changes the write enable signals WENP and WENS from the L level to the H level at the latest timing when the synchronization signals LMFCP and LMFCS rise after receiving the combined synchronization signal LMFC_REQ. Refer also to the description of FIG. 11 for the generation of the write enable signals WENP and WENS.

  When receiving the combined synchronization signal LMFC_REQ, the synchronization signal generation circuit 40 outputs to the FIFO 13 a write enable signal WENP that causes the digital signal ADP and the synchronization signal LMFCP to be written to the FIFO 13. Similarly, when the synchronization signal generation circuit 40 receives the combined synchronization signal LMFC_REQ, the synchronization signal generation circuit 40 outputs a write enable signal WENS for writing the digital signal ADS and the synchronization signal LMFCS to the FIFO 23 to the FIFO 13.

  The first channel 10 includes an AD conversion unit 12 as a plurality of AD converters, a FIFO 13, a control interface 14, and a serializer 16 as a transmission unit. Similarly, the second channel 20 includes an AD conversion unit 22, a FIFO 23, a control interface 24, and a serializer 26 as a transmission unit.

  The FIFO 13 outputs the digital signal ADP synchronized with the clock signal CKP and the synchronization signal LMFCP as digital signals FO1 and LMFC1 in synchronization with the clock signal IFCK1. Similarly, the FIFO 23 outputs the digital signal ADS synchronized with the clock signal CKS and the synchronization signal LMFCS as the digital signals FO2 and LMFC2 in synchronization with the clock signal IFCK2. Write enable signals WENP and WENS are also input to the FIFO 13 and the FIFO 23, respectively. The write enable signals WENP and WENS are signals having the same role as the write enable signal WEN described in FIG.

  The control interface 14 processes the digital signal FO1 output from the FIFO 13 according to the clock signal IFCK1 and outputs the signal to the serializer 16. Similarly, the control interface 24 processes the digital signal FO2 output from the FIFO 23 in accordance with the clock signal IFCK2 and outputs it to the serializer 26. Specifically, the control interfaces 14 and 24 operate with the clock signals IFCK1 and IFCK2, and output the digital signals FO1 and FO2 to the serializers 16 and 26. The control interfaces 14 and 24 will be described in more detail in FIG. The serializers 16 and 26 transmit digital signals FO1 and FO2 output from the control interfaces 14 and 24, respectively, to the reception circuit 200.

  FIG. 10 is a diagram illustrating an operation timing chart of the synchronization signal generation circuit 40. As described above, the synchronization signal generation circuit 40 receives the clock signals CKP and CKS from the PLL 34. The synchronization signal generation circuit 40 receives an H level enable signal CKEN from the PLL 34 when the PLL 34 locks the clock signals CKP and CKS. Then, the synchronization signal generation circuit 40 counts up the clock signals CKP and CKS from the timing when the enable signal CKEN becomes H level.

  The synchronization signal generation circuit 40 generates a synchronization signal LMFCP having a period P times the minimum period of the clock signal CKP. Further, the synchronization signal generation circuit 40 generates a synchronization signal LMFCS having a period P times the minimum period of the clock signal CKS. Note that P is a natural number. For example, since the synchronization signal generation circuit 40 counts the clock signal CKP by 16 to generate the synchronization signal LMFCP, the synchronization signal LMFCP is 16 times the cycle of the clock signal CKP. Further, since the synchronization signal generation circuit 40 counts the clock signal CKS by 4 to generate the synchronization signal LMFCS, the synchronization signal LMFCS is four times the cycle of the clock signal CKS.

  FIG. 11 is a diagram illustrating the first FIFO 13 of the transmission circuit 102. The FIFO 13 has basically the same configuration as the FIFO 13 in FIG. However, a write enable signal WENP is input to the write address counter 132 and the memory 130, a synchronization signal LMFCP, a digital signal ADP, and a clock signal CKP are input to the memory 130, and the memory 130 is a synchronization signal. The difference is that LMFC1 and FO1 are output.

  The FIFO 23 has the same configuration as the FIFO 13. However, in the FIFO 13, ADS is input to the memory 130 instead of ADP, CKS is input to the memory 130 and the write address counter 132 instead of CKP, LMFCS is input to the memory 130 instead of LMFCP, and WENP is replaced. WENS is input to the memory 130 and the write address counter 132, and IFCK2 is input to the frequency divider 136 instead of IFCK1. Further, a digital signal FO 2 is output from the memory 130.

  In this example, the write enable signals WENP and WENS are generated by the synchronization signal generation circuit 40 when the synchronization signal generation circuit 40 receives the combined synchronization signal LMFC_REQ. Here, the clock signal CKP of the write address counter 132 of the FIFO 13 and the clock signal CKS of the write address counter 132 of the FIFO 23 are in synchronization with each other. Further, the clock signal CKP and the synchronization signal LMFCP are also in a synchronous relationship, and the clock signal CKS and the synchronization signal LMFCS are also in a synchronous relationship. Therefore, the clock signals CKP and CKS and the synchronization signals LMFCP and LMFCS are in a synchronous relationship with each other.

  Further, the synchronization signal generation circuit 40 performs synchronization signal LMFCP within a range where the phase difference between the write enable signal WENP and the synchronization signal LMFCP in the first channel 10 is equal to or less than one cycle of the clock signal CKP in the first channel 10. The write enable signal WENP of the first channel 10 is output immediately before. Thus, the write address counter 132 in each channel can start counting at the same timing between channels. Therefore, in each channel, the write timing to the memory 130 and the read timing from the memory 130 match. Therefore, the problem that the latencies between channels are different due to the influence of asynchronous synchronization in each of the FIFOs 13 and 23 can be solved. In other words, the latencies due to the FIFOs 13 and 23 match between the channels.

  FIG. 12 is a diagram illustrating the control interface 14 of the transmission circuit 102. The control interface 14 has basically the same configuration as that shown in FIG. However, the point that the synchronization signal LMFC1 and the combined synchronization signal LMFC_REQ are input to the controller 150, the point that IFCK1 is input to the control interface 14, and the point that the digital signal FO1 is input to the frame-to-octet mapping unit 142 are the points. Different.

  The control interface 24 has the same configuration as the control interface 14. However, in the control interface 24, LMFC2 is input to the controller 150 instead of LMFC1, IFCK2 is input to the control interface 24 instead of IFCK1, and the digital signal FO2 is input to the frame-to-octet mapping unit 142 instead of the digital signal FO1. Entered.

  The control interface 14 starts signal processing for the digital signal FO1 in response to the synchronization signal LMFC1 output from the FIFO 13. Similarly, the control interface 24 starts signal processing for the digital signal FO2 in accordance with the synchronization signal LMFC2 output from the FIFO 23. Specifically, upon receiving the H level synchronization signal LMFC1 or LMFC2, the controller 150 cancels initialization of the internal state machine, octet counter, and frame counter. The synchronization signals LMFC1 and LMFC2 are synchronization signals corresponding to the aforementioned synchronization signals LMFCP and LMFCS. Since the synchronization signals LMFC1 and LMFC2 are synchronized between the channels, the control timing of the controller 150 between the channels can be aligned.

  The control interface 14 starts signal processing for the digital signal FO1 according to the synchronization signal LMFC1 output from the FIFO 13 on the condition that the combined synchronization signal LMFC_REQ is received. Similarly, the control interface 24 starts signal processing for the digital signal FO2 in accordance with the synchronization signal LMFC2 output from the FIFO 23 on the condition that the combined synchronization signal LMFC_REQ is received.

  Specifically, the controller 150 embeds the synchronization data K28.5 in the IFO1 or IFO2 in the digital signal when the combined synchronization signal LMFC_REQ is at the L level. In this case, the controller 150 maintains the SYNC state. On the other hand, when the controller 150 receives the H level synchronization signal LMFC_REQ and receives the H level synchronization signal LMFC1 or LMFC2, the SYNC state is canceled and the controller 150 transits to the ILA state. Further, the controller 150 transitions to the DATA_ENC state when the control time of the ILA state ends. As a result, the synchronization release timings coincide between the control interfaces 14 and 24 of each channel, so that the channels can be synchronized.

  FIG. 13 is a diagram illustrating a timing chart when the transmission circuit 102 releases synchronization. The arrow direction represents time. In addition to the signals described in FIG. 8, synchronization signals LMFCP and LMFCS, write enable signals WENP and WENS, and synchronization signals LMFC1 and LMFC2 are added. FIG. 13 is a timing chart when D = 4 (ratio of the frequency of the clock signal CKP to the frequency of the clock signal CKS) and T = 10 (T is the number of output bits of IFO1 and IFO2).

  Despite the asynchronous synchronization in each of the FIFOs 13 and 23, the latencies between the channels are the same in this example. Therefore, the data of the digital signals ADP and ADS (black portions) are output as IFO1 and IFO2 data (black portions) at the same timing. Further, in this example, the synchronization release timings coincide with each other even though the clock signals IFCK1 and IFCK2 of the control interfaces 14 and 24 are asynchronous. Therefore, the start timing and end timing of the counts of the ILA states (ILA_COUNT1 and ILA_COUNT2) match. As a result, the start position of the ILA state, the end position of the ILA state, and the start position of the DATA_ENC state coincide between the channels.

  FIG. 14 is a diagram illustrating the transmission circuit 103 according to the second embodiment. The same members as those in FIGS. 2, 6 and 9 are denoted by the same reference numerals. The transmission circuit 103 of this example uses logical product circuits 18 and 28 instead of the FIFOs 13 and 23 of the transmission circuit 102 in the first embodiment. With this change, the AD converters 12 and 22 output digital signals ADP and ADS to the control interfaces 14 and 24, respectively.

  The logical product circuit 18 receives the write enable signal WENP and the synchronous signal LMFCP from the synchronous signal generation circuit 40, and outputs the logical product of both signals to the control interface 14 as the synchronous signal LMFC1. For example, the AND circuit 18 receives the H level write enable signal WENP and the H level synchronization signal LMFCP, and outputs the H level synchronization signal LMFC1. Similarly, the AND circuit 28 receives the write enable signal WENS and the synchronization signal LMFCS from the synchronization signal generation circuit 40, and outputs the logical product of both signals to the control interface 24 as the synchronization signal LMFFC2.

  The control interface 14 synchronizes the digital signal ADP synchronized with the clock signal CKP, which is the first clock defined in the first channel 10, according to the clock signal IFCK 1, which is the second clock defined in the first channel 10. Signal processing. The control interface 14 outputs the processed signal to the serializer 16 as a digital signal IFO1. Similarly, the control interface 24 converts the digital signal ADS synchronized with the clock signal CKS, which is the first clock defined in the second channel 20, into the clock signal IFCK2, which is the second clock defined in the second channel 20. Depending on the signal processing. The control interface 24 outputs the processed signal to the serializer 26 as a digital signal IFO2. The serializers 6 and 26 as transmission units transmit the digital signals IFO 1 and IFO 2 output from the control interfaces 14 and 24 to the reception circuit 200.

  Synchronization signals LMFC1 and LMFC2 input to the control interfaces 14 and 24, respectively, are used to cancel initialization of the state machine, octet counter, and frame counter in the controller 150. The synchronization signals LMFC1 and LMFC2 are synchronization signals corresponding to the aforementioned synchronization signals LMFCP and LMFCS. Since the synchronization signals LMFCP and LMFCS are synchronized between the channels, the synchronization signals LMFFC1 and LMFC2 can align the control timing of the controller 150 between the channels. Since the configurations of the control interfaces 14 and 24 are the same as those in the first embodiment, the start position of the ILA state, the end position of the ILA state, and the start position of the DATA_ENC state match between the channels.

  In this example, by using the AND circuits 18 and 28, the synchronization between channels can be maintained, and the latency generated in the FIFO can be eliminated. Therefore, the latency generated in the first channels 10 and 20 can be reduced as compared with the first embodiment. Therefore, the operation of the transmission circuit 103 can be made faster than in the first embodiment. Further, the configuration of the transmission circuit 103 can be further simplified as compared with the case where the FIFOs 13 and 23 are used.

  FIG. 15 is a timing chart when the synchronization of the transmission circuit 103 is released. The arrow direction represents time. FIG. 15 is a timing chart when D = 4 (ratio of the frequency of the clock signal CKP to the frequency of the clock signal CKS) and T = 10 (T is the number of output bits of IFO1 and IFO2).

  In this example, since the FIFOs 13 and 23 are not used, the latency between channels is smaller than that in FIG. Specifically, the interval between the output timings of the data (black portions) of the digital signals ADP and ADS and the output timing of the data (black portions) of the digital signals IFO1 and IFO2 is smaller than that in FIG. Further, in this example, the synchronization release timings coincide with each other even though the clock signals IFCK1 and IFCK2 of the control interfaces 14 and 24 are asynchronous. Therefore, the start timing and end timing of the counts of the ILA states (ILA_COUNT1 and ILA_COUNT2) match. As a result, the start position of the ILA state, the end position of the ILA state, and the start position of the DATA_ENC state coincide between the channels.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the operation flow in the claims, the description, and the drawings is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  10 first channel, 12 AD conversion unit, 13 FIFO, 14 control interface, 16 serializer, 18 AND circuit, 20 second channel, 22 AD conversion unit, 23 FIFO, 24 control interface, 26 serializer, 28 logical product Circuit, 30 clock interface, 34 PLL, 36 SYNC combine, 38 PLL, 39 PLL, 40 synchronization signal generation circuit, 100 transmission circuit, 101 transmission circuit, 102 transmission circuit, 103 transmission circuit, 130 memory, 132 write address counter, 134 POP counter, 136 frequency divider, 138 read address counter, 139 control unit, 140 controller, 142 frame to octet mapping unit, 144 scrambler, 146 Character replacement unit, 145 initial lane alignment unit, 147 selector, 148 bit conversion unit, 150 controller, 200 reception circuit, 300 transmission / reception circuit

Claims (8)

A transmission circuit having a plurality of channels operable with different clocks, and transmitting transmission data from each channel to a reception circuit,
A synchronization signal generating circuit that generates, for each channel, synchronization signals of the same frequency synchronized with each other, based on respective clocks in the plurality of channels;
Each said channel is
A FIFO that outputs a digital signal synchronized with a first clock determined for each channel and the synchronization signal in synchronization with a second clock determined for each channel;
A control interface for processing and outputting a digital signal output from the FIFO in accordance with the second clock;
A transmission unit that transmits a signal output from the control interface to the reception circuit;
The control interface of each channel is a transmission circuit that starts signal processing on the digital signal in accordance with the synchronization signal output from the FIFO. The transmission circuit according to claim 1, wherein the synchronization signal generation circuit generates the synchronization signal having a period P times a minimum period of the plurality of first clocks (P is a natural number). Synchronous coupling that receives a synchronization confirmation signal output for each channel when the receiving circuit is synchronized with each channel and outputs a combined synchronization signal when the synchronization confirmation signal is received for all channels Further comprising
The transmission according to claim 2, wherein the control interface of each channel starts signal processing on the digital signal in accordance with the synchronization signal output from the FIFO on condition that the combined synchronization signal is received. circuit. 4. The transmission circuit according to claim 3, wherein the synchronization signal generation circuit outputs a write enable signal for writing the digital signal and the synchronization signal to the FIFO when the combined synchronization signal is received. . The synchronization signal generation circuit is configured so that the phase difference between the write enable signal and the synchronization signal in each channel is equal to or less than one cycle of the first clock in each channel, and the write of each channel is performed immediately before the synchronization signal. The transmission circuit according to claim 4, which outputs an enable signal. A transmission circuit having a plurality of channels operable with different clocks, and transmitting transmission data from each channel to a reception circuit,
A synchronization signal generating circuit that generates, for each channel, synchronization signals of the same frequency synchronized with each other, based on respective clocks in the plurality of channels;
Each said channel is
A control interface that outputs a digital signal synchronized with a first clock determined for each channel in accordance with a second clock determined for each channel;
A transmitter that transmits a signal output from the control interface to the receiver circuit;
The control interface of each channel is a transmission circuit that starts signal processing on the digital signal according to the synchronization signal. The transmission circuit according to claim 6, wherein the synchronization signal generation circuit generates the synchronization signal having a period P times a minimum period of the plurality of first clocks (P is a natural number).   A transmission / reception circuit comprising the transmission circuit and the reception circuit according to claim 1.

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