JP2015115374A - Silicon carbide semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device manufacturing method which can achieve high electromigration resistance of a surface electrode and stable predetermined electrical characteristics.SOLUTION: A silicon carbide semiconductor switching element manufacturing method comprises the steps of: first, forming an interlayer insulation film 7 so as to cover a MOS gate structure formed on an n-type silicon carbide wafer 1; subsequently forming first and second contact holes 8, 10 in the interlayer insulation film 7 to expose a conductive part of the MOS gate structure; subsequently forming a high melting point metal layer 11 on the interlayer insulation film 7 as a first layer of a surface electrode; subsequently forming an Al-Si layer 12 on the high melting point metal layer 11 as a second layer of he surface electrode; subsequently patterning the Al-Si layer 12 by first wet etching; and subsequently removing the high melting point metal layer 11 exposed on a pattern opening 14 by second wet etching to lift off an Si nodule 13 together with the high melting point metal layer 11.

Description

  The present invention relates to a method for manufacturing a silicon carbide semiconductor device.

  Silicon carbide (SiC) has a band gap and a breakdown electric field strength that greatly exceed silicon (Si). For this reason, it is expected as a semiconductor material that can replace a part of the elements of the semiconductor switching element with an element having a lower loss, or can realize a semiconductor switching element having a high withstand voltage exceeding 10 kV alone. A semiconductor switching element (hereinafter referred to as a silicon carbide semiconductor switching element) such as a MOSFET (insulated gate field effect transistor) using silicon carbide as a semiconductor material is an element excellent in high frequency / high temperature operation, Use at high current density is assumed. For this reason, an Al—Si alloy that is more excellent in electromigration resistance than pure aluminum (Al) having a purity of 99.00% or more is employed as the surface electrode material.

When an Al—Si alloy is used as the surface electrode material, Si in the surface electrode is in the shape of a bowl or a bump at the interface between the surface electrode and its lower layer (interlayer insulating film or electrode exposed in the contact hole of the interlayer insulating film) This precipitates as Si precipitates (Si nodules). Si nodules are used for wet etching for forming (patterning) a surface electrode into a predetermined wiring pattern (electrode pattern), such as phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), and acetic acid (CH ₃ COOH). Does not dissolve in chemicals containing (hereinafter referred to as phosphonitrate). For this reason, Si nodules remain in a state of being attached to an interlayer insulating film exposed between patterned surface electrodes (between wirings) or a state of being bitten into a surface layer of the interlayer insulating film (hereinafter simply referred to as adhesion). . When Si nodules are present between the wirings, the wirings may not be electrically insulated. For this reason, it is common to remove Si nodules remaining between the surface electrodes by dry etching (see, for example, Patent Document 1 below).

JP 2004-077982 A

  However, in the above-described silicon carbide semiconductor switching element, the Si atoms and C (carbon) atoms are present in the semiconductor material in a ratio of 1: 1, so that the gate is more than the semiconductor switching element using Si as the semiconductor material. It is known that the defect density in the insulating film increases and the stability of the electrical characteristics is impaired. Furthermore, in the technique shown in Patent Document 1 described above, when an Al—Si alloy is used as the surface electrode material, depending on the formation conditions of the gate insulating film, the element may be used during dry etching for removing Si nodules remaining on the element surface. When the surface is exposed to plasma, there is a problem that the on-voltage shifts from a predetermined value based on the design condition to the low pressure side by about 10% to 20%.

  Such a variation in on-voltage is presumed to be caused by an interaction between a defect in the gate insulating film and a plasma generated in the processing furnace in the dry etching of the Si nodule. On the other hand, when pure Al is used as the surface electrode material, it is not necessary to perform dry etching for removing Si nodules, and thus the present inventors have confirmed that the on-voltage can be avoided. Yes. However, when pure Al is used as the surface electrode material, there is a problem that the electromigration resistance of the surface electrode is lower than that when an Al—Si alloy is used as the surface electrode material, and the lifetime of the element is shortened.

  The present invention provides a method for manufacturing a silicon carbide semiconductor device in which the electromigration resistance of a surface electrode is high and predetermined electrical characteristics can be stably obtained in order to eliminate the above-described problems caused by the prior art. With the goal.

  In order to solve the above-described problems and achieve the object, the present inventor has made extensive studies, and as a result, titanium (Ti), zirconium (Zr) or hafnium (Hf) between the Al-Si layer and the interlayer insulating film. A thin metal layer made of a refractory metal such as) is provided, and the refractory metal layer exposed between the patterned surface electrodes is removed by wet etching so that it remains between the surface electrodes without performing dry etching. It has been found that Si nodules can be lifted off. The present invention has been made based on such knowledge.

  In order to solve the above-described problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following characteristics. First, the 1st formation process which forms a device structure on the surface of a semiconductor wafer which consists of silicon carbide is performed. Next, a second forming step is performed for forming an insulating film covering the device structure on the semiconductor wafer. Next, an exposure process is performed in which the insulating film is selectively removed to expose the conductive portions constituting the device structure. Next, a third forming step is performed in which a first metal layer made of a metal having a high melting point is formed on the insulating film in contact with the conductive portion. Next, a fourth forming step of forming a second metal layer made of aluminum and silicon on the first metal layer is performed. Next, a forming process for forming the second metal layer into a predetermined pattern is performed by first wet etching. Next, a removal step of removing the first metal layer exposed between the second metal layers formed by the forming step by a second wet etching is performed.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention as set forth in the invention described above, the first metal layer is made of at least one of titanium, zirconium, and hafnium.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention, the thickness of the first metal layer is the interface between the first metal layer and the second metal layer in the third forming step. It is characterized in that it is thicker than half the grain size of the silicon precipitate deposited on the substrate.

  In the method for manufacturing a silicon carbide semiconductor device according to the present invention as set forth in the invention described above, the thickness of the first metal layer is not less than 100 nm and not more than 200 nm.

  The method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the thickness of the second metal layer is larger than the thickness of the first metal layer.

  According to the method for manufacturing a silicon carbide semiconductor device according to the present invention, in the above-described invention, in the first formation step, the device structure has a gate insulating film that is thinner than the insulating film on the surface of the semiconductor wafer as the device structure. Forming a gate electrode through the substrate, and forming, as the device structure, an input electrode electrically insulated from the gate electrode on the surface of the semiconductor wafer, and in the exposing step, The gate electrode and the input electrode are exposed as a conductive portion.

  According to the above-described invention, the electromigration resistance of the surface electrode can be increased by using the metal layer containing aluminum and silicon as the surface electrode material. Even when a metal layer containing aluminum and silicon is used as the surface electrode material, it is possible to remove silicon deposits remaining on the element surface after patterning the surface electrode without using dry etching. It is possible to avoid the voltage from deviating from a predetermined value based on the design conditions.

  According to the method for manufacturing a silicon carbide semiconductor device of the present invention, it is possible to increase the electromigration resistance of the surface electrode and to obtain predetermined electrical characteristics stably.

It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment. It is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning embodiment.

  Exemplary embodiments of a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment)
A method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described by taking an example of manufacturing an n-channel MOSFET using silicon carbide as a semiconductor material. FIGS. 1-6 is sectional drawing which shows the state in the middle of manufacture of the silicon carbide semiconductor device concerning Embodiment. First, a predetermined device structure is formed on an n-type silicon carbide wafer 1 made of, for example, a single crystal. Specifically, n-type silicon carbide wafer 1 previously prepared by a method such as chemical cleaning or sacrificial oxidation is prepared. Next, the n ⁻ type drift layer 2 is grown on the front surface of the n-type silicon carbide wafer 1 by, for example, epitaxial growth. Next, the p-type well layer 3 is selectively formed on the surface layer of the n ⁻ -type drift layer 2 opposite to the n-type silicon carbide wafer 1 side, for example, by ion implantation.

Next, the n ⁺ type high concentration region 4 is selectively formed inside the p type well layer 3 by, for example, ion implantation. Next, a gate electrode (conductive portion) 6 is formed on the surface of the portion of the p-type well layer 3 sandwiched between the n ⁺ -type high concentration region 4 and the n ⁻ -type drift layer 2 via the gate insulating film 5. Form. Next, on the surface of the n ⁻ type drift layer 2 opposite to the n type silicon carbide wafer 1 side, from the p type well layer 3, the n ⁺ type high concentration region 4, the gate insulating film 5 and the gate electrode 6. An interlayer insulating film 7 is formed so as to cover (seal) a MOS gate (metal-oxide film-insulated gate made of semiconductor) structure. The state up to here is shown in FIG.

Next, the interlayer insulating film 7 is selectively removed to form a first contact hole 8, and the n ⁺ type high concentration region 4 is exposed in the first contact hole 8. Next, an ohmic electrode (conductive portion) 9 that is in ohmic contact with the n ⁺ type high concentration region 4 exposed in the first contact hole 8 is formed by a general method. As a material of the ohmic electrode 9, for example, a Ni alloy containing nickel (Ni) as a main component may be used. The composition of the Ni alloy, the ohmic sintering (heat treatment) conditions, and the like can be variously changed according to the design conditions. As a method of forming the first contact hole 8 in the interlayer insulating film 7, for example, dry etching may be used. The state up to this point is shown in FIG.

  Next, the interlayer insulating film 7 is selectively removed to form a second contact hole (gate contact hole) 10, and the gate electrode 6 is exposed in the second contact hole 10. As a method of forming the second contact hole 10 in the interlayer insulating film 7, for example, wet etching may be used. The state up to here is shown in FIG.

  Next, a refractory metal layer (first metal layer) 11 is formed (formed) on the interlayer insulating film 7. At this time, the refractory metal layer 11 is formed along the inner walls of the first and second contact holes so as to be in contact with the ohmic electrode 9 and the gate electrode 6 exposed in the first and second contact holes 8 and 10, respectively. As a method for forming the refractory metal layer 11, a general method such as sputtering may be used. The refractory metal layer 11 is the first layer of the surface electrode. The thickness of the refractory metal layer 11 is set to be thicker than half the average particle diameter (diameter) of a Si nodule 13 described later. The reason for making the thickness of the refractory metal layer 11 thicker than half the average particle diameter of the Si nodules 13 is that the thickness of the refractory metal layer 11 is equal to or less than the above conditions in the Si nodule removal step described later. This is because the refractory metal layer 11 in the region masked by the Si nodules 13 cannot be completely removed, and the Si nodules 13 may not be sufficiently separated from the surface of the interlayer insulating film 7. . In addition, the thickness of the refractory metal layer 11 is preferably as thin as possible in consideration of stability when patterning the refractory metal layer 11 by second wet etching described later, for example, 100 nm to 200 nm. It should be a degree.

  As an electrode material for the refractory metal layer 11, a metal having a relatively high melting point such as titanium (Ti), zirconium (Zr) or hafnium (Hf), or an alloy containing one or more of these metals is used. Good. Aluminum (Al) or nickel (Ni) generally used as the electrode material of the silicon carbide semiconductor switching element is not preferable as the material of the refractory metal layer 11. The reason is as follows. This is because aluminum has poor stability such as low electromigration resistance when used in a high temperature environment and a large current density. This is because nickel may diffuse into the interlayer insulating film 7 in a high temperature region and cause dielectric breakdown. That is, as the electrode material of the refractory metal layer 11, it is preferable to use a metal that has high stability when used in a high temperature environment and a large current density and is difficult to diffuse into the interlayer insulating film 7 in a high temperature region.

  Next, a metal layer containing aluminum (Al) and silicon (Si) (hereinafter referred to as an Al-Si layer (second metal layer)) on the refractory metal layer 11 so as to fill the first and second contact holes 8 and 10. And 12) is formed. Specifically, the Al—Si layer 12 may be an aluminum alloy layer containing, for example, about 1 wt% silicon. As a method for forming the Al—Si layer 12, a general method such as sputtering may be used. By forming the Al—Si layer 12 in this way, the Si in the Al—Si layer 12 is formed into a spherical or nodular Si precipitate (Si nodule) at the interface between the Al—Si layer 12 and the refractory metal layer 11. ) 13 to precipitate. The Al—Si layer 12 is the second layer of the surface electrode. That is, the surface electrode is formed by sequentially laminating the refractory metal layer 11 and the Al—Si layer 12. The state up to this point is shown in FIG.

Next, the Al—Si layer 12 is formed (patterned) into a predetermined wiring pattern by photolithography and first wet etching. By this patterning, the Al—Si wiring layer 12a in contact with the ohmic electrode 9 through the refractory metal layer 11 in the first contact hole 8 and the gate through the refractory metal layer 11 in the second contact hole 10 are obtained. An Al—Si wiring layer 12 b in contact with the electrode 6 is formed. The refractory metal layer 11 is exposed between the Al—Si wiring layers 12a and 12b (hereinafter referred to as a pattern opening 14). As a chemical solution for the first wet etching, for example, a chemical solution containing phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), acetic acid (CH ₃ COOH) and the like (phosphorous nitrate acetic acid) (components can be variously changed) is used. Also good. Si nodules 13 do not dissolve in most chemicals containing phosphonitrate acetic acid. For this reason, when the first wet etching is completed, the Si nodules 13 remain attached to the refractory metal layer 11 exposed at the pattern openings 14. That is, the Si nodule 13 is attached to the element surface. The state up to here is shown in FIG.

  By patterning the Al—Si layer 12 by the first wet etching, the throughput can be improved as compared with the case of patterning the Al—Si layer 12 by dry etching. Further, when the Al—Si layer 12 is patterned by dry etching, the on-voltage fluctuates, and there is a possibility that a predetermined on-voltage set based on the design condition cannot be maintained. Since the Al—Si layer 12 is patterned by the wet etching 1, it is possible to avoid the ON voltage from fluctuating.

Next, the refractory metal layer 11 is patterned by second wet etching using a chemical solution such as a mixed solution containing ammonia (NH ₃ ) and hydrogen peroxide (H ₂ O ₂ ) (components can be variously changed). Then, the refractory metal layer 11 exposed in the pattern opening 14 is removed. This second wet etching proceeds isotropically in the depth direction and in the direction parallel to the main surface of the substrate (hereinafter referred to as the lateral direction). For this reason, etching proceeds in the depth direction from the portion of the refractory metal layer 11 where the Si nodules 13 are not attached, and the width from the periphery of the Si nodules 13 is the same as the etching depth in the depth direction. In the direction, etching proceeds to a portion of the refractory metal layer 11 immediately below the Si nodule 13. Therefore, as described above, by making the thickness of the refractory metal layer 11 thicker than half the average grain size of the Si nodules 13, the etching in the depth direction is performed by the thickness of the refractory metal layer 11. At the time of advance, the portion immediately below the Si nodule 13 of the refractory metal layer 11 is removed with a width equal to or larger than the diameter of the Si nodule 13. That is, when the portion of the refractory metal layer 11 to which the Si nodules 13 are not attached is completely removed by etching proceeding in the depth direction, the portion of the refractory metal layer 11 immediately below the Si nodules 13 is also completely removed. Removed. In this way, by removing the portion where the Si nodules 13 are adhered (the refractory metal layer 11) inside the pattern openings 14, the Si nodules 13 remaining in the pattern openings 14 are peeled off (lifted off) from the element surface. And removed. The state up to this point is shown in FIG.

When there is a possibility that the planar pattern (wiring shape) of the Al—Si layer 12 may be significantly changed by the chemical used for the second wet etching, the Al—Si layer 12 is previously obtained by photolithography before the second wet etching. What is necessary is just to form the protective film (not shown) which covers. In the second wet etching, a chemical solution that does not contain fluoride such as ammonium fluoride (NH ₄ F) is preferably used. The reason is that the interlayer insulating film 7 under the refractory metal layer 11 is hardly etched at the time of the second wet etching, so that the thickness of the interlayer insulating film 7 is maintained at the thickness before the second wet etching. Because you can.

  Thereafter, after performing general steps after the formation of the wiring layer, such as forming a passivation protection film (not shown) on the front side of the wafer so as to cover the Al—Si wiring layers 12a and 12b, for example, The silicon carbide semiconductor device according to the embodiment is completed by cutting (dicing) the chip.

  As described above, according to the embodiment, by providing the refractory metal layer between the Al—Si layer and the interlayer insulating film, the Si nodules generated when the Al—Si layer is formed are Al—Si. It precipitates at the interface between the layer and the refractory metal layer and does not directly adhere to the interlayer insulating film below the refractory metal layer. In the conventional method, Si nodules are deposited at the interface between the Al-Si layer and the interlayer insulating film and adhere directly to the interlayer insulating film. The adhering Si nodules must be removed by dry etching, and it was necessary to design the element in consideration of fluctuations in the on-voltage. In contrast, according to the embodiment, since Si nodules adhere to the refractory metal layer, by removing the refractory metal layer exposed in the pattern opening by wet etching, the element can be obtained without performing dry etching. Si nodules remaining on the surface can be removed. Therefore, it is not necessary to design the device in consideration of the on-voltage variation, and the device design is facilitated. That is, according to the embodiment, the electromigration resistance of the surface electrode can be increased by using an Al—Si alloy as the surface electrode material, and the reliability of the element can be improved. Even when an Al—Si alloy is used as the surface electrode material, it is possible to avoid fluctuations in the on-voltage and improve electrical insulation between the wirings. The characteristics can be obtained stably, and the yield can be improved.

  In addition, when a dry etching process is included in the manufacturing process, since the dry etching process is generally a single wafer process, it is necessary to prepare a plurality of dry etchers in order to improve throughput. According to this, since the surface electrode patterning and the Si nodule removal are performed by a wet etching process capable of batch processing, the throughput can be greatly improved.

  In the above description, the present invention has been described by taking an n-channel MOSFET as an example. Is possible. The present invention can be applied to any structure of a horizontal semiconductor device having electrodes on one side of a substrate and a vertical semiconductor device having electrodes on both sides of a substrate. That is, when a horizontal semiconductor device is manufactured (manufactured) by applying the present invention, the gate electrode, input electrode, and output electrode wiring layers may be formed by patterning the surface electrode. When a vertical semiconductor device is manufactured by applying the present invention, a wiring layer for a gate electrode and an input electrode is formed by patterning the surface electrode, and a back electrode serving as an output electrode is formed on the back surface of the silicon carbide wafer. That's fine. Further, the present invention is similarly established even when the conductivity type is reversed.

  As described above, the method for manufacturing a silicon carbide semiconductor device according to the present invention is useful for a silicon carbide semiconductor device used for a switching element or the like.

1 n-type silicon carbide wafer 2 n ⁻ type drift layer 3 p type well layer 4 n ⁺ type high concentration region 5 gate insulating film 6 gate electrode 7 interlayer insulating film 8 first contact hole 9 ohmic electrode 10 second contact hole 11 high Melting point metal layer 12 Al-Si layer 13 Si nodule 14 Pattern opening of Al-Si layer

Claims (6)

A first forming step of forming a device structure on a surface of a semiconductor wafer made of silicon carbide;
A second forming step of forming an insulating film covering the device structure on the semiconductor wafer;
An exposure step of selectively removing the insulating film and exposing a conductive portion constituting the device structure;
A third forming step of forming a first metal layer made of a metal having a high melting point on the insulating film in contact with the conductive portion;
A fourth forming step of forming a second metal layer made of aluminum and silicon on the first metal layer;
A forming step of forming the second metal layer into a predetermined pattern by a first wet etching;
A removal step of removing the first metal layer exposed between the second metal layers formed by the forming step by a second wet etching;
The manufacturing method of the silicon carbide semiconductor device characterized by the above-mentioned.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the first metal layer is made of at least one of titanium, zirconium, and hafnium.   The thickness of the first metal layer is thicker than half the grain size of the silicon precipitate deposited at the interface between the first metal layer and the second metal layer in the third forming step. A method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2.   The thickness of the said 1st metal layer is 100 nm or more and 200 nm or less, The manufacturing method of the silicon carbide semiconductor device as described in any one of Claims 1-3 characterized by the above-mentioned.   The thickness of the said 2nd metal layer is thicker than the thickness of the said 1st metal layer, The manufacturing method of the silicon carbide semiconductor device as described in any one of Claims 1-4 characterized by the above-mentioned. In the first forming step,
As the device structure, forming a gate electrode on the surface of the semiconductor wafer through a gate insulating film thinner than the insulating film;
Forming the input electrode electrically insulated from the gate electrode on the surface of the semiconductor wafer as the device structure; and
6. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the exposing step, the gate electrode and the input electrode are exposed as the conductive portion.

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