JP2015114825A - Computer system and method for operating the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system capable of eliminating the problem that a BMC is restarted at an unintended timing due to a memory leak in the BMC to influence the operation of an operating system, and operating the system in a stable state.SOLUTION: A computer system comprises a firmware (BIOS) 170, a base management controller (BMC) 180, and a hardware control circuit 190 which restarts the base management controller (BMC). The base management controller (BMC) monitors free space in a memory. When the free space becomes less than or equal to a prescribed setting value, the base management controller (BMC) notifies the firmware (BIOS) of the free space information. When it receives the free space information from the base management controller (BMC) during a power-on self test period, the firmware (BIOS) determines whether to restart the base management controller (BMC).

Description

  The present invention relates to a computer system having a board management controller or a service processor incorporating firmware for monitoring the operation of the computer system, and an operation method thereof.

  A board management controller (BMC) has a power control for a computer system, a temperature and voltage monitoring function, a system operation monitoring function, and the like. In recent computer systems, not only that, but also the functions of the BMC such as system power control from a remote computer, remote media control and multitasking have become diversified and complicated, and the number of cases where the BMC itself stalls has increased. For this reason, in order to increase the reliability of the computer system, there is a computer system having a specification in which the BMC itself has a target WDT (Watch Dog Timer) by an external hardware control circuit.

  Thus, there is a need for a technique for restarting the system and operating it in a stable state.

  Japanese Patent Laid-Open No. 2004-228688 solves a problem with the operation of the computer system by restarting the BMC from the BIOS (Basic Input / Output System) when the command exchange becomes impossible during the POST (Power On Self Test). A possible technique is disclosed.

  Japanese Patent Application Laid-Open No. 2004-228867 discloses a technique for avoiding a memory leak by monitoring a storage area of a memory, requesting a restart of the apparatus, and releasing an unreleased area of the memory at a timing that does not affect the operation of the apparatus. Is disclosed. A memory leak is a phenomenon in which the amount of usable memory gradually decreases while a computer is operating. This occurs because a memory area occupied for processing by an OS (Operating System) or application software is left unreleased for some reason.

JP 2009-193492 A JP 2007-010357 A

  In the technique described in Patent Document 1, when the exchange of commands becomes impossible during POST, the system is restored by restarting the BMC from the BIOS. However, when a memory leak occurs in the BMC, it is not intended. There was a problem that the BMC was restarted by the opportunity, which affected the operation of the OS.

  In the technique described in Patent Literature 2, the analysis instrument itself is restarted in a timely state when a memory leak occurs in the memory of the analysis instrument itself. Specifically, when a restart request is made, the earliest analysis interval is found and the restart is executed, the memory is initialized, and the unreleased area is forcibly released. For this reason, there is a problem that if the analysis is timeless and takes time, or if the analysis has just begun, it takes a long time until the latest interval comes and normal operation takes time.

  An object of the present invention is to eliminate a situation in which the BMC restarts due to an unintended trigger due to a memory leak in the memory in the BMC, affecting the operation of the operating system, and to operate the system in a stable state. It is to provide a computer system that can.

  In order to solve the above problems, the present invention is a computer system having firmware and a board management controller, and includes a hardware control circuit that restarts the board management controller, and the board management controller includes an internal memory. The free space is monitored, and when the free space falls below the preset value, the firmware is notified of the free space information. The firmware receives information from the board management controller during the power-on self-test. In this case, it is determined whether to restart the board controller.

  Further, the present invention includes a step of restarting the board management controller using the hardware control circuit, and the board management controller monitors the free space in the internal memory, and the free space is less than a predetermined set value. A step of notifying the firmware of information on free space, and a step of determining whether to restart the board controller during the power-on self-test when the firmware receives information from the board management controller. It is characterized by having.

  According to the present invention, it is possible to eliminate a situation in which the BMC restarts due to an unintended trigger due to a memory leak in the memory in the BMC and affects the operation of the operating system, and to operate the system in a stable state. A computer system that can be provided is provided.

It is a block diagram which shows the structure of the computer system in embodiment of this invention. It is a flowchart which shows operation | movement of the computer system in embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment)
FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention. In FIG. 1, a mother board 100 shows its architecture. This architecture is for illustrative purposes only, and only one of the many possible architectures for a motherboard is shown.

  As shown in FIG. 1, the motherboard 100 includes a central processing unit (CPU) 110. The CPU 110 is connected via a processor bus 120 to a chip generally referred to as “north bridge” indicated by 130 in FIG. The north bridge 130 generally controls parts such as a memory unit and a graphic card that are desired to operate at high speed. In FIG. 1, communication between the memory 140 and the CPU 110 is managed. A plurality of memories 140 may be connected.

  Also in FIG. 1, a chip known as “South Bridge”, indicated at 150, is also connected to the North Bridge 130. The south bridge 150 controls parts that are generally slower than those performed by the north bridge 130.

  The slow part is, for example, a peripheral component interface (PCI) bus. The south bridge 150 can be connected to a memory unit including the BIOS 170 via a low pin count (LPC) bus 160. The BIOS is also referred to as firmware. North bridge 130 and south bridge 150 are often collectively referred to as the “chipset” of motherboard 100.

  Although omitted in this description, the mother board 100 includes various other input / output (I / O) devices and components for communicating with the outside.

  In FIG. 1, the BMC 180 is connected to the LPC bus 160. BMC is often referred to as firmware. The BMC 180 generally controls power, controls temperature and voltage as an interface between system management software and platform hardware. The BMC 180 includes an internal memory 181.

  Further, a hardware control circuit 190 for restarting the BMC 180 from the BIOS 170 is connected from the south bridge 150 through a GPIO (General Purpose Input / Output) 200, and a reset signal 210 for the BMC 180 is sent from the hardware control circuit 190 to the BMC 180. Connected. If the hardware control circuit 190 can be controlled from the BIOS 170, the present invention is not affected even if the connection is not from the south bridge 150. The memory leak information is notified from the BMC 180 to the BIOS 170 through the GPIO 220 connected to the south bridge 150.

  FIG. 2 is a flowchart showing the operation of the embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIG.

  When the BMC 180 receives a power-on instruction, the BMC 180 starts up the system by the power control function (S400), and the BIOS 170 starts POST (S300). When a memory leak occurs in the internal memory 181 in the BMC, the BMC 180 notifies the BIOS 170 through the GPIO 220 connected to the south bridge 150 (S410). The BMC 180 notifies the BIOS 170 of the value of the free memory capacity as memory leak information when the free memory capacity is below a predetermined threshold. The BMC itself is embedded firmware, and memory leak information (free capacity) can be acquired by an OS command of the embedded firmware.

  The BIOS 170 receives the memory leak information transmitted from the BMC in the POST task through the GPIO 220 (S310), and whether or not the memory leak is in a state where the obtained free memory value is below a predetermined threshold value. Judgment is made (S311). If there is no memory leak with the free capacity below the threshold, the POST task is continuously executed (S320). When all the tasks are completed, POST ends (S330). That the free capacity falls below the threshold means that the memory leak is so large as to hinder a predetermined BMC function.

  When the BIOS 170 determines that a memory leak that hinders the operation of the BMC has occurred (S311), the BIOS 170 instructs the hardware control circuit 190 to reset the BMC 180 via the south bridge 150 (S500). The hardware control circuit 190 restarts the BMC 180 by the reset signal 210 (S510). As a result, the BMC 180 is restored.

  As a result of the above, it is possible to operate the system in a stable state, eliminating the possibility that the BMC will restart due to a memory leak in the memory in the BMC and that will affect the operation of the operating system. It is.

  In this embodiment, since the BMC is restarted at the time of POST, the restart is difficult to occur during system operation. Therefore, more stable system operation can be performed.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, In the range which does not deviate from the summary, various deformation | transformation are possible. For example, the operation of the function for the BMC according to the embodiment to notify the BIOS of the memory leak information and the function for the BIOS to detect the memory leak information of the BMC is executed by other hardware, software, or a combination of both. It is also possible.

  The present invention can be used for a computer system having a board management controller or a service processor incorporating firmware for monitoring the operation of the computer system.

100 Motherboard 110 Central processing unit (CPU)
120 processor bus 130 north bridge 140 memory unit and memory controller 150 south bridge 160 low pin count (LPC) bus 170 BIOS
180 BMC
181 Internal memory 190 Hardware control circuit 200 GPIO
210 Reset signal 220 GPIO (for memory leak information notification)

Claims (8)

A computer system having firmware and a board management controller,
A hardware control circuit for restarting the board management controller;
The board management controller monitors the free space in the internal memory, and notifies the firmware of the free space information when the free space is below a predetermined set value.
The firmware determines whether or not to restart the board controller when receiving the information from the board management controller during a power-on self-test.   The firmware receives the information from the board management controller, and outputs a signal for restarting the board controller to the hardware control circuit when the board controller is restarted. The computer system according to claim 1.   The firmware restarts the board controller when it is determined that the free capacity of the memory of the board management controller is a capacity that hinders the operation of the board management controller. 3. The computer system according to 2.   The computer system according to any one of claims 1 to 3, wherein the firmware is a BIOS (Basic Input / Output System). Restarting the board management controller using the hardware control circuit;
The board management controller monitors the free space of an internal memory, and notifies the firmware of the free space information when the free space is below a predetermined set value;
The firmware determines whether to restart the board controller when receiving the information from the board management controller during a power-on self-test;
A method for operating a computer system, comprising:   When the firmware receives the information from the board management controller and restarts the board controller, the firmware has a step of outputting a signal for restarting the board controller to the hardware control circuit. 6. The method of operating a computer system according to claim 5, wherein:   The firmware includes a step of restarting the board controller when it is determined that the free space of the memory of the board management controller is hindering the operation of the board management controller. 7. A method for operating the computer system according to 6.   8. The method according to claim 5, wherein the firmware includes a step of restarting the board controller during a power-on self test.

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