JP2015103601A - Resistance change element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resistance change element in which high resistance ratio window, endurance and a stable electrode having less resistance fluctuation are achieved.SOLUTION: A resistance change element includes: a first electrode 11 and a second electrode 15; a resistance change layer 13 containing oxygen and a first metal; a resistance layer 14 which is arranged between the second electrode 15 and the resistance change layer 13, which includes oxygen and the second metal different from the first metal, and whose specific resistance is 1000 μ Ω cm or less; and a diffusion prevention layer 12 which is arranged between the first electrode 11 and the resistance change layer 13 and which has characteristics for preventing oxygen supplied from the resistance layer 14 to the resistance change layer 13 from being diffused to the first electrode 11.

Description

  The present invention relates to a resistance change element.

  2. Description of the Related Art A resistance change element that changes its resistance value in response to applying a voltage (flowing current) to itself is known. The resistance change element has a property that the resistance value reversibly changes when a voltage is applied, and can store data corresponding to the resistance value in a nonvolatile manner. Therefore, the resistance change element is used in a nonvolatile semiconductor memory device. ing.

For example, in Patent Document 1, a variable resistance element (resistance change) configured by sandwiching a resistance change layer and a low resistance layer (resistance layer) in contact with the second electrode between the first electrode and the second electrode. Device). This low resistance layer is an oxide (for example, HfO _x-δ ; δ> 0 containing the same metal element as the metal element included in the metal oxide constituting the resistance change layer (for example, HfO _x ; x <2). And the resistance is reduced so that the resistance value is lower than that of the resistance change layer. In the process of reducing the resistance, a process in which the low resistance layer is deficient in oxygen than the resistance change layer is performed. For example, a mixed gas of Ar and O ₂ is sputtered using a metal target (eg, Hf target). In the reactive sputtering method used in the above, the oxygen partial pressure ratio in the sputtering gas is lowered to make the low resistance layer oxygen deficient than the resistance change layer.

  The resistance change element described in Patent Document 1 transitions (sets) from a high resistance state to a low resistance state when a pulse is applied so that the first electrode has a negative voltage with respect to the second electrode. When a pulse in which the first electrode has a positive voltage is applied with reference to, the transition from the low resistance state to the high resistance state (reset). Here, in the resistance change of such a resistance change element, the resistance change layer is reduced in resistance by oxygen ions moving from the resistance change layer to the low resistance layer, while the oxygen ions extracted from the low resistance layer are reduced. It is considered that the resistance change layer is increased in resistance by being taken into the resistance change layer.

JP 2012-79930 A (FIG. 1)

  The following analysis is given by the inventor.

The variable resistance element described in Patent Document 1 has a problem that the conductivity of the low resistance layer changes due to the movement of oxygen ions when the resistance changes. In the variable resistance element described in Patent Document 1, when oxygen ions move for rewriting set / reset, oxygen ions move inevitably to the low resistance layers of adjacent memory cells. The low resistance layer is an oxide of the same metal element as the metal oxide constituting the resistance change layer. Therefore, even if the oxygen concentration is reduced (by increasing the oxygen deficiency concentration) than the resistance change layer, the low resistance layer has a low resistance. When oxygen ions enter and exit, it is inevitable that a certain change in conductivity occurs. In particular, the high risk of increasing the resistance when oxygen ions move into the low resistance layer is a big problem. In the worst case, the low resistance layer loses its role as an electrode conductor. Actually, when the specific resistance of the low resistance layer is calculated from the description in Patent Document 1, it is considerably high at 5 × 10 ³ Ω · cm.

  In addition, when oxygen ions invade into a substance intentionally imparting conductivity to an insulating oxide, it tends to proceed in the direction of oxidation, but difficult to proceed in the direction of reduction. In order to secure the read signal, it is desirable that the conductivity of the low resistance layer does not vary in such a set / reset operation. However, in the variable resistance element described in Patent Document 1, the conductivity of the low resistance layer varies. In particular, since the resistance is easily increased, the function as an electrode deteriorates while the switching cycle is repeated.

  Further, the variable resistance element described in Patent Document 1 also affects the endurance (number of rewrites). When such movement of oxygen ions occurs repeatedly, the discontinuous difference in oxygen amount or distribution that was initially in the resistance change layer and the low resistance layer is averaged, and the resistance ratio window gradually narrows, resulting in an endurance. Getting worse.

  Further, in the variable resistance element described in Patent Document 1, since it is a low resistance layer by modifying the material that is originally an insulator to reduce resistance, it is easily affected by heat and redox gas, and is variable. It is susceptible to changes in characteristics due to the semiconductor process after the resistance element is manufactured. In particular, among semiconductor processes, there is a process (for example, annealing) that gives strong oxidative damage, and such a process may increase the resistance of the low resistance layer.

  Furthermore, oxygen movement in the variable resistance element also occurs with respect to the first electrode. On the other hand, Patent Document 1 does not take any measures.

  The main subject of this invention is providing the variable resistance element which implement | achieves the stable electrode with a high resistance ratio window, endurance, and resistance variation few.

  In one aspect of the present invention, in a resistance change element, the first electrode and the second electrode, a resistance change layer containing oxygen and a first metal, and the second electrode and the resistance change layer are arranged. And a resistance layer that includes oxygen and a second metal different from the first metal and has a specific resistance of 1000 μΩ · cm or less, and is disposed between the first electrode and the resistance change layer, A diffusion prevention layer having a property of preventing diffusion of oxygen supplied from the resistance layer to the resistance change layer into the first electrode.

  According to the present invention, by providing the diffusion prevention layer 12 between the contact plug 11 serving as the lower electrode and the resistance change layer 13, oxygen remains in the resistance change layer 13 and is concentrated at a high concentration. The resistance ratio window is enlarged and the endurance can be increased. Further, according to the present invention, by providing the diffusion preventing layer 12, oxygen does not diffuse into the contact plug 11 serving as the lower electrode as compared with the prior art, so that the distribution of oxygen becomes narrower and the contact plug 11 serving as the lower electrode. The resistance variation can be reduced.

It is sectional drawing which showed typically an example of the structure of the memory cell containing the resistance change element which concerns on one Embodiment of this invention. It is sectional drawing which showed typically an example of the structure of the resistance change element which concerns on one Embodiment of this invention. It is the block diagram which showed typically an example of the circuit structure of the semiconductor memory device provided with the memory cell containing the resistance change element which concerns on one Embodiment of this invention. 1 is a circuit diagram schematically illustrating an example of a configuration of a memory cell array in a semiconductor memory device including a memory cell including a resistance change element according to an embodiment of the present invention.

  A variable resistance element according to an embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram schematically showing an example of a circuit configuration of a semiconductor memory device including a memory cell including a resistance change element according to an embodiment of the present invention.

  The semiconductor memory device 20 is a semiconductor chip provided with a memory circuit. The semiconductor memory device 20 includes a memory cell array 30 divided into a plurality of Banks 0 to 1 as a memory circuit, a row decoder 31 associated with each Bank 0 to 1, a sense amplifier 32, a write amplifier 33, a determination register 34, a data register 35, And a column decoder 36. Further, the semiconductor memory device 20 has a peripheral circuit formed around the memory circuit. The semiconductor memory device 20 includes a row address buffer 37, an array control circuit 38, a phase counter 39, a control logic circuit 40, a command register 41, a status register 42, a command detector 43, an I / O as peripheral circuits. An O control circuit 44, a column address buffer 45, an address register 46, and a transistor 47 are included. In the example of FIG. 3, two Banks 0 to 1 are provided, but the number of Banks is not particularly limited. Although not shown, external power supply voltages VDD and VSS are supplied to the semiconductor memory device 20 from the outside.

  The memory cell array 30 is a circuit in which a plurality of memory cells MC are arranged in the row direction and the column direction. The memory cell array 30 includes a plurality of word lines WL extending in one direction and arranged in the other direction (a direction perpendicular to one direction) and a plurality of bit lines BL extending in the other direction and arranged in one direction. And a plurality of memory cells MC provided in the vicinity of each intersection of the word line WL and the bit line BL. The word line WL is electrically connected to the row decoder 31. Each bit line BL is electrically connected to the sense amplifier 32. Details of the memory cell array 30 and the memory cell MC will be described later.

  The row decoder 31 activates a corresponding word line WL based on signals from the array control circuit 38 and the row address buffer 37, and selects a row (row) address in the memory cell array 30 via the word line WL. It is.

  The sense amplifier 32 is a circuit that amplifies the potential of data read from the memory cell array 30 via the bit line BL based on a signal from the array control circuit 38. The sense amplifier 32 outputs the potential-amplified data to the data register 35 and the determination register 34.

  The write amplifier 33 is a circuit that amplifies the potential of data from the data register 35 based on a signal from the array control circuit 38. The write amplifier 33 outputs the potential amplified data to the memory cell array 30 and the determination register 34 via the selected bit line BL.

  The determination register 34 is a register that determines whether a pass or a fail (verify operation) by comparing write data in the write amplifier 33 and read data in the sense amplifier 32 based on a signal from the array control circuit 38. is there. When the determination register 34 detects a failure, rewrite to the memory cell array 30 is performed, and the rewrite and read loops are repeated until all cells pass.

  The data register 35 is a register that holds data. The data register 35 exchanges data with the I / O control circuit 44. The data register 35 holds data from the I / O control circuit 44 or the sense amplifier 32. The data register 35 outputs the held data to the write amplifier 33 based on a signal from the array control circuit 38 at the time of writing. The data register 35 outputs the held data to the I / O control circuit 44 based on a signal from the array control circuit 38 at the time of reading.

  The column decoder 36 is a circuit that selects a column address in the memory cell array 30 via the bit line BL based on signals from the array control circuit 38 and the column address buffer 45.

  The row address buffer 37 is a buffer that holds a row address among the addresses from the address register 46. The row address buffer 37 outputs the held row address to the row decoder 31.

  Based on signals from the control logic circuit 40 and the phase counter 39, the array control circuit 38 operates the row decoder 31, the sense amplifier 32, the write amplifier 33, the determination register 34, the data register 35, and the column decoder 36, respectively. Is a circuit for controlling The array control circuit 38 supplies a word line selection signal to the row decoder 31, and supplies a bit line selection signal to the column decoder 36, and the sense amplifier 32, the write amplifier 33, the determination register 34, and the data register 35 are supplied. Various control signals are supplied.

  The phase counter 39 is a counter for controlling the phase to be accessed in the array control circuit 38.

  The control logic circuit 40 is a logic circuit that outputs various control signals to peripheral circuits. The control logic circuit 40 outputs various control signals to the array control circuit 38, the status register 42, and the transistor 47 based on signals from the command detector 43 and the command register 41. The control logic circuit 40 exchanges signals with the array control circuit 38.

  The command register 41 is a register that holds a command from the I / O control circuit 44. The command register 41 outputs the held command toward the control logic circuit 40.

  The status register 42 is a register that holds a status signal from the control logic circuit 40. The status register 42 outputs the held status signal to the I / O control circuit 44. Here, the status signal is information indicating a state such as a write pass or a failure.

  The command detector 43 is a circuit to which commands (chip enable / CE, command latch enable CLE, address latch enable ALE, write enable / WE, read enable / RE, / WP) are input.

  Here, / CE is a device selection signal. For example, when it is High in the read state, the standby mode is set.

  CLE is a signal for controlling the command to be taken into the command register 41 in the device. By setting CLE to High when / WE rises and falls, data on the I / O terminals (I / O1 to I / O8) is taken into the command register 41 as commands.

  ALE is a signal for controlling the address and data taken into the address register 46 and the data register 35 in the device. By setting ALE to High when / WE rises and falls, data on the I / O terminals (I / O1 to I / O8) is taken into the address register 46 as address data. Further, by setting ALE to Low, data on the I / O terminals (I / O1 to I / O8) is taken into the data register 35 as input data.

  Further, / WE is a write signal for taking data from the IO terminals (I / O1 to I / O8) into the device.

  / RE is a signal for outputting data (serial output).

  / WP is a control signal for protecting data by prohibiting write and erase operations. Normally, / WP = High, and / WP = Low when the power is turned off and the like.

  The I / O control circuit 44 is a circuit that controls input / output of commands, addresses, and data. The I / O control circuit 44 exchanges commands, addresses, and data to the outside via the I / O terminals (I / O1 to I / O8). The I / O control circuit 44 outputs the input command toward the command register 41. The I / O control circuit 44 outputs the input address to the address register 46. The I / O control circuit 44 exchanges data with the data register 35. The I / O control circuit 44 controls the input / output of commands, addresses, and data based on signals from the command detector 43 and the status register 42.

  Here, I / O 1 to 8 are terminals (ports) for inputting and outputting addresses, commands, and data.

  The column address buffer 45 is a buffer that holds a column address among the addresses from the address register 46. The column address buffer 45 outputs the held column address to the column decoder 36.

  The address register 46 is a register that holds an address from the I / O control circuit 44. The address register 46 outputs the row address among the held addresses to the row address buffer 37. The address register 46 outputs the column address among the held addresses toward the column address buffer 45.

  The transistor 47 is an nMOS transistor having an open drain configuration. The gate of the transistor 47 is connected to the control logic circuit 40. The source of the transistor 47 is connected to the ground. The drain of the transistor 47 is connected to the output terminal of the internal state notification signal RY / BY. The gate of the transistor 47 is set to a high potential during the execution of operations such as a program / erase / read operation. The gate of the transistor 47 is turned on (conductive) and becomes RY / BY = Low (Busy). When the operation is completed, the potential is set to Low, RY / BY is pulled up to the power supply potential, and RY / BY = High (Ready). )

  Here, RY / BY is a signal for notifying the outside of the internal state of the device.

  FIG. 4 is a circuit diagram schematically showing an example of the configuration of the memory cell array in the semiconductor memory device including the memory cell including the resistance change element according to the embodiment of the present invention.

  The memory cell array (30 in FIG. 3) includes a plurality of word lines (WL in FIG. 3, WL0 to WL5 in FIG. 4) extending in one direction and arranged in the other direction (direction perpendicular to one direction) and the other A plurality of bit lines (BL in FIG. 3 and BL0 to BL2 in FIG. 4) extending in one direction and arranged in one direction, and a plurality of memory cells MC provided in the vicinity of each intersection of the word lines and bit lines Have. The word lines WL0 to WL5 are controlled by a row decoder (31 in FIG. 3). The bit lines BL0 to BL2 are controlled by a column decoder (36 in FIG. 3). The memory cell MC has one MOS transistor 19, the source of the MOS transistor 19 is electrically connected to the ground via a common source line (not shown), and the gate of the MOS transistor 19 corresponds to the corresponding word line WL0. Are electrically connected to WL5, and the drain of the MOS transistor 19 is electrically connected to the corresponding bit lines BL0 to BL2 via the resistance change element 21.

  FIG. 1 is a cross-sectional view schematically showing an example of a configuration of a memory cell including a resistance change element according to an embodiment of the present invention.

  The memory cell (MC in FIGS. 3 and 4) includes a MOS transistor 19 serving as a selection element and a resistance change element 21 serving as a recording element. The memory cell has a p-type semiconductor substrate 1 (for example, a p-type silicon substrate). The semiconductor substrate 1 has a groove 1a having a predetermined depth. The groove 1a is formed in a mesh shape when viewed from the direction perpendicular to the main surface. An STI (Shallow Trench Isolation) type insulating film 2 (for example, a silicon oxide film) is buried in the trench 1a. A word line 4 (for example, polysilicon; for example, polysilicon) serving as the gate of the MOS transistor 19 is provided on a portion of the semiconductor substrate 1 serving as a channel region of the MOS transistor 19 via a gate insulating film 3 (for example, silicon oxide film). WL, WL0 to WL5 in FIG. 4). Sidewall insulating films 5 (for example, silicon oxide films) are formed on both sides of the side surfaces of the word lines 4 and the gate insulating film 3. N-type diffusion regions 6 a and 6 b (for example, phosphorus ion diffusion regions) serving as the source / drain of the MOS transistor 19 are formed on both sides of the semiconductor substrate 1 in the portion serving as the channel region of the MOS transistor 19.

  On the MOS transistor 19 and the insulating film 2, an interlayer insulating film 7 (for example, a silicon oxide film) is formed. In the interlayer insulating film 7, a pilot hole communicating with the diffusion region 6 a is formed, and a contact plug 8 (for example, tungsten) is embedded in the pilot hole. A source line 9 (for example, copper) electrically connected to the contact plug 8 is formed at a predetermined position on the interlayer insulating film 7 including the contact plug 8. The source line 9 is electrically connected to the ground.

An interlayer insulating film 10 (for example, a silicon oxide film) is formed on the interlayer insulating film 7 including the source line 9. In the interlayer insulating film 10 and the interlayer insulating film 7, a pilot hole leading to the diffusion region 6b is formed, and a contact plug 11 (for example, TiN) is embedded in the pilot hole. In a predetermined position on the interlayer insulating film 10 including the contact plug 11, a diffusion prevention layer 12 (for example, Si ₃ N ₄ ), a resistance change layer 13 (for example, HfO _x ), a resistance layer 14 (for example, for example) MoO ₂ ) and the upper electrode 15 (for example, Ta) are laminated in this order. The contact plug 11, the diffusion prevention layer 12, the resistance change layer 13, the resistance layer 14, and the upper electrode 15 become the resistance change element 21. The detailed configuration of the resistance change element 21 will be described later.

  An interlayer insulating film 16 (for example, a silicon oxide film) is formed on the interlayer insulating film 10 including the resistance change element 21. A pilot hole communicating with the upper electrode 15 is formed in the interlayer insulating film 16, and a contact plug 17 (for example, TiN) is embedded in the pilot hole. A bit line 18 (for example, copper) electrically connected to the contact plug 17 is formed at a predetermined position on the interlayer insulating film 16 including the contact plug 17. The bit line 18 is electrically connected to a column decoder (36 in FIG. 3).

  FIG. 2 is a cross-sectional view schematically showing an example of the configuration of the variable resistance element according to the embodiment of the present invention.

  The resistance change element 21 has a configuration in which the resistance change layer 13 is sandwiched between two electrodes (a contact plug 11 serving as a lower electrode and an upper electrode 15). In the variable resistance element 21, a diffusion prevention layer 12 that prevents diffusion of oxygen from the variable resistance layer 13 to the contact plug 11 is interposed between the variable resistance layer 13 and the contact plug 11. In the resistance change element 21, a resistance layer 14 made of a metal oxide having a conductivity of 1000 μΩ · cm or less is interposed between the resistance change layer 13 and the upper electrode 15.

  For the contact plug 11 serving as the lower electrode, for example, TiN which is a conductive film often used in a semiconductor device can be used.

  The diffusion prevention layer 12 is disposed between the contact plug 11 serving as the lower electrode and the resistance change layer 13, and is joined to each of the contact plug 11 and the resistance change layer 13. The diffusion prevention layer 12 functions as an oxygen stopper that suppresses the diffusion of oxygen from the resistance change layer 13 to the contact plug 11 serving as the lower electrode. For the diffusion preventing layer 12, a material having an oxygen barrier property against oxygen in the resistance change layer 13 can be used, and a material that does not contain oxygen or hardly accept oxygen can be used. Since such a material is often an insulator, in such a case, an ultrathin film of about 1 nm (0.5 nm to 1.5 nm) is used. Then, since electrons tunnel, current can flow. As a result, oxygen does not flow into and out of the contact plug 11 serving as the lower electrode, and electrons pass. This is particularly important at reset. The fact that oxygen flows out to the contact plug 11 serving as the lower electrode at the time of reset means that a part of oxygen is released from the resistance change layer 13 and means that the reset resistance does not increase.

For the diffusion prevention layer 12, a nitride film can be used, for example, a nitride film (for example, Si ₃ N ₄ , AlN, BN, etc.) having a stronger covalent bond than TiN of the contact plug 11 serving as the lower electrode. But it is possible). In addition, a completely oxidized oxide can be used for the diffusion preventing layer 12, and for example, a covalent oxide film (for example, a multilayer such as SiO ₂ , Al ₂ O _3, etc.) is desirable. A completely oxidized oxide film is difficult to accept new oxygen ions and has a strong bond between atoms, so that it is difficult to give oxygen ions to the resistance change layer 13. In addition, an oxynitride film can be used for the diffusion preventing layer 12, and for example, a covalent oxynitride film (for example, a multilayer such as SiON, AlON, SiAlON, etc.) is desirable. For example, Si ₃ N ₄ (energy band gap of about 5 eV), AlN (about 6 eV), BN (about 6 eV), SiO ₂ (about 9 eV), or the like can be used. The film thickness of the diffusion preventing layer 12 can be about 1 nm (0.5 nm or more and 1.5 nm or less).

The resistance change layer 13 is disposed between the diffusion prevention layer 12 and the resistance layer 14 and is joined to each of the diffusion prevention layer 12 and the resistance layer 14. The resistance change layer 13 is made of a material containing oxygen and metal, and for example, HfO _x (x <2) can be used. The resistance change layer 13 can produce HfO _x (x <2) that is deficient in oxygen (has oxygen vacancies) by using only Ar sputtering gas for the HfO ₂ target. The film thickness of the resistance change layer 13 is 1 nm or more and 10 nm or less, preferably 2 nm or more and 3 nm or less. If it exceeds 10 nm, the forming voltage is too high, and if it is less than 1 nm, it tends to be out of the composition range where the resistivity is constant.

  The resistance layer 14 is disposed between the resistance change layer 13 and the upper electrode 15 and is joined to each of the resistance change layer 13 and the upper electrode 15. A metal oxide having a conductivity of 1000 μΩ · cm or less can be used for the resistance layer 14, and a metal oxide having a conductivity of 100 μΩ · cm or less is preferable. There are materials having high conductivity even in metal oxides, and such metal oxides are relatively stable with respect to increase and decrease of oxygen and are suitable for the resistance layer 14. In addition, such a metal oxide has a merit that it has sufficient resistance against inflow of oxygen from the resistance change layer 13 and oxygen distribution performance to the resistance change layer 13, and the resistance layer 14 functions as an oxygen reservoir. Suitable for In particular, it is important that the resistance layer 14 does not increase in resistance even when oxygen is injected during the set operation. That is, even if oxygen is injected into the upper electrode 15 side in the resistance change operation, the resistance layer 14 does not lose its role as an electrode because it contains a large amount of oxygen from the beginning, and (2) a large amount of oxygen Therefore, the change in conductivity with respect to the change in the amount of oxygen is extremely small, and (3) it functions as a sufficient oxygen distribution source when oxygen moves to the resistance change layer 13.

For the resistance layer 14, for example, RuO ₂ or IrO ₂ used as an electrode of a ferroelectric material can be used. Perovskite oxide ferroelectrics deteriorate due to the loss of oxygen when electrode inversion is repeated, while materials such as RuO ₂ and IrO ₂ appropriately supplement oxygen to suppress deterioration. The specific resistance of RuO ₂ , IrO _2, etc. is 100 μΩ · cm or less, which is orders of magnitude lower than 5 × 10 ³ Ω · cm of the low resistance layer of Patent Document 1, and the change in conductivity with respect to oxygen fluctuations Is small. In addition, RuO ₂ , IrO _{2 and the} like have high thermal stability and diffusion barrier properties, and their characteristics do not change even after a semiconductor process. However, RuO ₂ , IrO _{2 and the} like are also expensive materials. For the resistance layer 14, for example, VO ₂ , CoO ₂ , MoO ₂ , WO ₂ or the like can be used as an inexpensive material. Materials such as VO ₂ , CoO ₂ , MoO ₂ , and WO ₂ have a specific resistance of 100 to 1000 μΩ · cm, which is slightly higher than that of RuO ₂ , IrO _{2, and the} like. Is much lower. As a material, MoO ₂ is the easiest to handle. MoO _{2 is} also stable for semiconductor processes at 500 ° C. or lower. MoO ₂ can be formed by RF (radio frequency) sputtering in a Ar + O ₂ gas atmosphere on a Mo target by sputtering. The film thickness of the resistance layer 14 is 1 nm or more and 10 nm or less, preferably 2 nm or more and 3 nm or less. If the thickness exceeds 10 nm, the composition of the resistance change layer 13 is likely to be affected. If the thickness is less than 1 nm, oxygen tends to deviate from the constant composition range when oxygen enters from the resistance change layer 13.

  For the upper electrode 15, for example, Ta can be used. For the upper electrode 15, for example, a Ta target can be formed by DC (Direct Current) sputtering. The film thickness of the upper electrode 15 is 15 nm or more and 25 nm or less.

  The resistance change element 21 as described above transitions (sets) from the high-resistance state to the low-resistance state when a pulse that is a negative voltage is applied to the contact plug 11 that is the lower electrode with reference to the upper electrode 15. When a pulse having a positive voltage is applied to the contact plug 11 serving as the lower electrode with reference to 15, the transition is made from the low resistance state to the high resistance state (reset). Such a resistance change is a phenomenon in which at least an oxygen element is entangled, and is generated by an increase or decrease of oxygen with respect to the resistance change layer 13. For example, in the case where the resistance change layer 13 is an n-type metal oxide, the conductivity is increased by the release of oxygen, and the insulation is improved by the implantation of oxygen. The increase / decrease in oxygen occurs when negative ions of oxygen move by applying a voltage to both electrodes 11, 15 of the resistance change element 21. Therefore, some oxygen ions move to the upper electrode 15 side during setting, and move to the contact plug 11 side serving as the lower electrode during resetting.

  The manufacturing method of the semiconductor memory device (20 in FIG. 3) can be the same manufacturing method as that of the prior art for portions other than the diffusion prevention layer 12 and the resistance layer 14 in the resistance change element 21. Further, for the shape processing of the resistance change element 21, the diffusion prevention layer 12, the resistance change layer 13, the resistance layer 14, and the upper electrode 15 were continuously formed on the surface where the contact plug 11 serving as the lower electrode is exposed. Thereafter, a structure in which the contact plug 11, the diffusion prevention layer 12, the resistance change layer 13, the resistance layer 14, and the upper electrode 15 are electrically connected as shown in FIG. 1 is formed by photolithography and processing technology in a semiconductor process. Can do. The diffusion prevention layer 12 can be formed by a CVD (Chemical Vapor Deposition) method or a PVD (Physical Vapor Deposition) method. The resistance layer 14 can be formed by RF (Radio Frequency) sputtering.

  According to the embodiment, by providing the diffusion prevention layer 12 between the contact plug 11 serving as the lower electrode and the resistance change layer 13, oxygen remains in the resistance change layer 13 and is concentrated at a high concentration. The resistance ratio window is enlarged and the endurance can be increased. In addition, according to the embodiment, by providing the diffusion prevention layer 12, oxygen does not diffuse into the contact plug 11 serving as the lower electrode as compared with the prior art, so that the distribution of oxygen becomes narrower and the contact plug 11 serving as the lower electrode. The resistance variation can be reduced. Furthermore, according to the first embodiment, a sufficient margin for the set / reset operation is possible, and the yield and performance of the chip can be increased.

  Note that, in the present application, where reference numerals are attached to the drawings, these are only for the purpose of helping understanding, and are not intended to be limited to the illustrated embodiments.

(Appendix)
In one aspect of the present invention, in a resistance change element, the first electrode and the second electrode, a resistance change layer containing oxygen and a first metal, and the second electrode and the resistance change layer are arranged. And a resistance layer that includes oxygen and a second metal different from the first metal and has a specific resistance of 1000 μΩ · cm or less, and is disposed between the first electrode and the resistance change layer, A diffusion prevention layer having a property of preventing diffusion of oxygen supplied from the resistance layer to the resistance change layer into the first electrode.

  In the variable resistance element according to the aspect of the invention, it is preferable that the diffusion preventing layer is a nitride film, an oxide film, or an oxynitride film having a stronger covalent bond than the material of the first electrode. The strength of the covalent bond may be determined, for example, by measuring the difference in electronegativity between different elements constituting the film. When there are three or more constituent elements, the largest difference among the electronegativity differences in all combinations of the two elements may be used as a measure of the strength of the covalent bond. The smaller the difference in electronegativity, the higher the covalent bond.

In the resistance change element of the present invention, it is preferable that the diffusion prevention layer is made of one or more materials of Si ₃ N ₄ , AlN, BN, SiO ₂ , Al ₂ O ₃ , SiON, AlON, and SiAlON. .

  In the resistance change element of the present invention, it is preferable that the resistance layer is a metal oxide film that functions as an oxygen distribution source with respect to the resistance change layer.

In the resistance change element of the present invention, it is preferable that the resistance layer is made of one or more materials of RuO ₂ , IrO ₂ , VO ₂ , CoO ₂ , MoO ₂ , and WO ₂ .

  It should be noted that the embodiments or examples can be changed or adjusted within the scope of the entire disclosure (including claims and drawings) of the present invention and based on the basic technical concept. Various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are included within the scope of the claims of the present invention. Is possible. That is, the present invention naturally includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea. Further, regarding numerical values and numerical ranges described in the present application, it is considered that any intermediate value, lower numerical value, and small range are described even if not specified.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a Groove 2 Insulating film 3 Gate insulating film 4 Word line 5 Side wall insulating film 6a, 6b Diffusion area 7 Interlayer insulating film 8 Contact plug 9 Source line 10 Interlayer insulating film 11 Contact plug (lower electrode, first electrode)
12 Diffusion Prevention Layer 13 Resistance Change Layer 14 Resistance Layer 15 Upper Electrode (Second Electrode)
16 Interlayer insulating film 17 Contact plug 18 Bit line 19 MOS transistor 20 Semiconductor memory device 21 Resistance change element 30 Memory cell array 31 Row decoder 32 Sense amplifier 33 Write amplifier 34 Decision register 35 Data register 36 Column decoder 37 Row address buffer 38 Array control circuit 39 Phase counter 40 Control logic circuit 41 Command register 42 Status register 43 Command detector 44 I / O control circuit 45 Column address buffer 46 Address register 47 Transistor WL, WL0 to WL5 Word line BL, BL0 to BL2 Bit line MC Memory cell

Claims (5)

A first electrode and a second electrode;
A resistance change layer including oxygen and a first metal;
A resistance layer disposed between the second electrode and the resistance change layer, including a second metal different from oxygen and the first metal, and having a specific resistance of 1000 μΩ · cm or less;
A diffusion preventing layer disposed between the first electrode and the resistance change layer and having a property of preventing diffusion of oxygen supplied from the resistance layer to the resistance change layer into the first electrode;
A variable resistance element comprising:   The resistance change element according to claim 1, wherein the diffusion prevention layer is a nitride film, an oxide film, or an oxynitride film having a stronger covalent bond than the material of the first electrode. The resistance change according to claim 2, wherein the diffusion prevention layer is made of one or more materials of Si ₃ N ₄ , AlN, BN, SiO ₂ , Al ₂ O ₃ , SiON, AlON, and SiAlON. element.   4. The variable resistance element according to claim 1, wherein the resistance layer is a metal oxide film that functions as an oxygen distribution source for the variable resistance layer. 5. The variable resistance element according to claim 4, wherein the resistance layer is made of one or more materials of RuO ₂ , IrO ₂ , VO ₂ , CoO ₂ , MoO ₂ , and WO ₂ .

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