JP2015103593A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is unlikely to cause mechanical and electrical damages even when being subjected to a heat treatment such as reflow, and achieves easy positioning in packaging; and provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device 100 comprises: a semiconductor chip 101; an insulation layer 104 provided on a principal surface 101a of the semiconductor chip 101; a wiring layer; an overcoat layer 106; a wiring pattern 105A including a connection pad provided in the wiring layer, for achieving connection with an external circuit; a base pattern 105M provided in the wiring layer; an opening 106-1 as a first opening formed at a position on the overcoat layer 106, which overlaps the connection pad and an opening 106-2 as a second opening formed at a position on the overcoat layer 106, which overlaps the base pattern 105M; a solder bump 107A as a solder terminal formed by filling the opening 106-1; and a solder part 108 for alignment formed by filling the opening 106-2.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

As a semiconductor device, a so-called chip size semiconductor device is known in which connection portions (bumps) for electrical connection with a circuit board are formed on a main surface of a semiconductor chip.
Even such a chip-sized semiconductor device requires marking such as product identification and manufacturing lot number.
For example, Patent Document 1 discloses a semiconductor device including a wiring pattern provided by patterning a metal layer covering a low elastic modulus layer formed on a main surface of a semiconductor chip, and a marking. It is also shown that the marking is at least one of a mark indicating the attribute of the semiconductor device, a mark indicating the wiring pattern number, and an alignment mark for aligning the semiconductor device.

Japanese Patent No. 3378880

In the semiconductor device of Patent Document 1, since the marking is provided on the main surface of the semiconductor chip, when providing a protective layer that protects the main surface, in order to make the marking identifiable, for example, a protective layer is provided. It is conceivable to provide an opening in a portion overlapping the marking by patterning.
However, due to the difference in physical properties between the low elastic modulus layer and the protective layer, the protective layer may crack around the opening due to the influence of heat or the like when the semiconductor device is mounted on the circuit board. In addition, if the crack of the protective layer reaches the low elastic modulus layer around the opening, moisture and the like enter the main surface of the semiconductor chip from the cracked portion, resulting in reduced reliability. There was a problem that related problems might occur.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  [Application Example] A semiconductor device according to this application example includes a semiconductor chip, an insulating layer covering a main surface of the semiconductor chip, an overcoat layer covering the insulating layer, and between the insulating layer and the overcoat layer. A wiring pattern provided in the wiring layer, a wiring pattern provided in the wiring layer and including a connection pad for connection to an external circuit, a ground pattern provided in the wiring layer, and the connection pad in the overcoat layer A solder terminal formed by filling the first opening disposed at the overlapping position, and an alignment terminal formed by filling the second opening disposed at the position overlapping the base pattern of the overcoat layer And a solder part.

  According to this application example, the base pattern provided in the wiring layer on the insulating layer is exposed in the second opening of the overcoat layer, and the second opening is filled with the solder part, and the base pattern, the solder part, To form an alignment mark. Therefore, since the second opening is filled with the solder portion, the visibility of the alignment mark is improved as compared with the case where the base pattern exposed in the second opening is used as the alignment mark. In addition, since the second opening is filled with the solder part and is not opened, cracks occur around the second opening of the overcoat layer due to the difference in physical properties of the insulating layer and the overcoat layer. Can be reduced. Therefore, it is possible to reduce the occurrence of problems such as the cracks in the overcoat layer reaching the insulating layer and moisture and the like entering the main surface of the semiconductor chip from the cracks to deteriorate the insulation. That is, it is possible to provide a semiconductor device that can be easily aligned at the time of mounting and has excellent reliability quality.

In the semiconductor device according to the application example, the insulating layer and the overcoat layer are formed using a resin material, and the breaking strength of the insulating layer is larger than the breaking strength of the overcoat layer. And
According to this structure, it can reduce more that the crack of an overcoat layer reaches an insulating layer.

In the semiconductor device according to the application example, the insulating layer includes a first resin layer and a second resin layer having different strength at break, and the first resin layer, the second resin layer, The wiring layer and the overcoat layer are formed in this order, and the strength at break satisfies the relationship of the overcoat layer <the first resin layer <the second resin layer.
According to this structure, it can reduce that the crack of an overcoat layer reaches the insulating layer which consists of a resin layer. In addition, since the insulating layer includes the first resin layer and the second resin layer, the first resin layer is less likely to crack compared to the case where the insulating layer is formed of a single resin layer. .

In the semiconductor device according to the application example, it is preferable that the insulating layer is formed using a polyimide resin.
According to this configuration, high insulation can be realized by covering the main surface of the semiconductor chip with the polyimide resin.

In the semiconductor device according to the application example, it is preferable that a size of the first opening is larger than a size of the second opening.
According to this configuration, for example, the first opening and the second opening are filled with the solder paste, heated to form the solder terminal in the first opening, and the alignment for the second opening. Even if the solder portion is formed, the height of the solder portion on the main surface of the semiconductor chip does not exceed the height of the solder terminal, so that the solder terminal and the circuit board are reliably joined at the time of mounting.

In the semiconductor device according to the application example, the wiring layer includes a plurality of wiring patterns, and the base pattern is provided in the vicinity of a specific wiring pattern among the plurality of wiring patterns. And
According to this configuration, the solder portion can be used as an alignment mark of the semiconductor device, and the relative alignment between the plurality of wiring patterns and the circuit board can be reliably performed.

In the semiconductor device according to the application example, it is preferable that the base pattern is electrically independent in the wiring layer.
According to this configuration, when a semiconductor device is mounted on, for example, a circuit board, even if the solder portion bonded to the base pattern is in contact with an electronic component mounted on the circuit board or a wiring connected to the electronic component, etc. It is possible to provide a semiconductor device that does not cause a defect.

  [Application Example] A method of manufacturing a semiconductor device according to this application example is a method of manufacturing a semiconductor device having a semiconductor chip and a solder terminal provided on the main surface of the semiconductor chip for connection to an external circuit. A step of forming an insulating layer that covers the main surface; a step of forming a wiring layer on the insulating layer; a wiring pattern that patterns the wiring layer and leads to the solder terminals; and an electrically independent base Forming a pattern, forming an overcoat layer covering the wiring pattern and the base pattern, and patterning the overcoat layer to form a first opening at a position overlapping the connection pad And a step of forming a second opening at a position overlapping the base pattern, a step of filling the first opening and the second opening with solder, and heating the solder Te, thereby forming the solder terminal to said first opening, characterized in that it comprises a step of forming a solder portion for alignment with the second opening.

  According to this application example, the base pattern formed in the wiring layer on the insulating layer is exposed in the second opening of the overcoat layer, and the solder portion is formed in the second opening to form the base pattern and the solder. An alignment mark is formed by joining the portions. Therefore, since the second opening is filled with the solder portion, the visibility of the alignment mark is improved as compared with the case where the base pattern exposed in the second opening is used as the alignment mark. In addition, since the solder portion is formed in the second opening and the second opening is not opened, the second opening of the overcoat layer is caused by the difference in physical properties between the insulating layer and the overcoat layer. The occurrence of cracks around the part can be reduced. Therefore, it is possible to reduce the occurrence of problems such as the cracks in the overcoat layer reaching the insulating layer and moisture and the like entering the main surface of the semiconductor chip from the cracks to deteriorate the insulation. That is, it is possible to manufacture a semiconductor device that can be easily aligned at the time of mounting and has excellent reliability quality.

In the method of manufacturing a semiconductor device according to the application example, in the step of forming the insulating layer, the insulating layer is formed by applying a solution containing a photosensitive polyimide resin to the main surface and drying. In the step of forming the overcoat layer, the overcoat layer having a breaking strength lower than that of the insulating layer is formed.
According to this method, even if a crack is generated around the second opening of the overcoat layer, the crack hardly reaches the insulating layer. Further, since the insulating layer is formed of a photosensitive polyimide resin, the insulating layer can be easily patterned and a semiconductor device having excellent insulating performance can be manufactured.

In the method of manufacturing a semiconductor device according to the application example, in the step of forming the first opening and the second opening, the second opening that is smaller than the size of the first opening is formed. The step of forming and filling the first opening and the second opening with solder preferably fills the first opening and the second opening by using a solder paste by a printing method. .
According to this method, the solder paste filling the first opening and the second opening is heated to form a solder terminal in the first opening, and a high height on the main surface is formed in the second opening. It is possible to form a solder portion whose length is lower than that of the solder terminal. That is, it is possible to manufacture a semiconductor device capable of reliably joining the solder terminal and the circuit board without causing the solder portion as the alignment mark to become an obstacle during mounting.

In the method of manufacturing a semiconductor device according to the application example, in the step of forming the first opening and the second opening, the second opening larger than the size of the first opening is formed. In the step of forming and filling the first opening and the second opening with solder, it is preferable that a solder ball is disposed in the first opening and the second opening.
According to this method, the solder ball is heated to form a solder terminal in the first opening, and a solder portion having a height on the main surface lower than that of the solder terminal is formed in the second opening. it can. That is, it is possible to manufacture a semiconductor device capable of reliably joining the solder terminal and the circuit board without causing the solder portion as the alignment mark to become an obstacle during mounting.

In the method for manufacturing a semiconductor device according to the application example described above, in the step of forming the base pattern, it is preferable that the wiring layer is patterned to form the base pattern that is electrically independent.
According to this method, even when a semiconductor device is mounted on, for example, a circuit board, even if the solder portion in contact with the base pattern is in contact with an electronic component mounted on the circuit board or a wiring connected to the electronic component. A semiconductor device that does not cause a defect can be manufactured.

(A) is a schematic perspective view which shows the structure of the semiconductor device of 1st Embodiment, (b) is a schematic sectional drawing which shows the mounting state of the semiconductor device of 1st Embodiment with respect to a circuit board. FIG. 2 is a schematic plan view showing the arrangement of each component on the main surface side of the semiconductor device of the first embodiment. FIG. 3 is a schematic cross-sectional view showing the structure of the semiconductor device of the first embodiment taken along line A-A ′ of FIG. 2. FIG. 3 is a schematic cross-sectional view showing the structure of the semiconductor device of the first embodiment taken along line B-B ′ of FIG. 2. 3 is a flowchart showing a method for manufacturing the semiconductor device of the first embodiment. (A)-(e) is a schematic sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. (F)-(j) is a schematic sectional drawing which shows the manufacturing method of the semiconductor device of 1st Embodiment. (A) And (b) is a schematic sectional drawing which shows the manufacturing method of the semiconductor device of 2nd Embodiment. (A) And (b) is a schematic sectional drawing which shows the structure of the semiconductor device of a modification. The schematic plan view which shows a semiconductor wafer.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

(First embodiment)
<Semiconductor device>
The semiconductor device of this embodiment will be described with reference to FIGS. 1A is a schematic perspective view showing a configuration of a semiconductor device, FIG. 1B is a schematic cross-sectional view showing a mounting state of the semiconductor device on a circuit board, and FIG. 2 is an arrangement of each configuration on the main surface side of the semiconductor device. FIG. 3 is a schematic cross-sectional view showing the structure of the semiconductor device taken along the line AA ′ in FIG. 2, and FIG. 4 shows the structure of the semiconductor device taken along the line BB ′ in FIG. It is a schematic sectional drawing.

As shown in FIG. 1A, the semiconductor device 100 of this embodiment includes a semiconductor chip 101 having an electric circuit formed on the main surface 101a and a plurality (6) of solder terminals provided on the main surface 101a side. ) Solder bumps 107A to 107F and a solder portion 108 as an alignment mark.
The semiconductor chip 101 is made of a semiconductor substrate such as silicon having a thickness of 300 μm to 750 μm, for example, and is a quadrangle with a side length of, for example, about several mm to about 10 mm.
The solder bumps 107A to 107F are substantially hemispherical, and are connection portions that make electrical connection between an electric circuit formed on the main surface 101a and an external circuit. A plurality of (six) solder bumps 107A to 107F are collectively referred to as solder bumps 107.
An overcoat layer 106 is formed so as to cover the main surface 101 a excluding the solder bump 107 and the solder portion 108. The overcoat layer 106 is a protective layer for preventing mechanical damage such as scratches from being generated on the main surface 101a or intrusion of moisture or the like to impair electrical performance. As will be described in detail later, the overcoat layer 106 is formed so as to cover the main surface 101 a except for the outer edge portion of the semiconductor chip 101.

As shown in FIG. 1B, the semiconductor device 100 is positioned on the circuit board 180 so that the solder bumps 107 are in contact with the connection lands 181 provided on one surface of the circuit board 180, for example. One surface of the circuit board 180 is covered with, for example, an insulating solder resist 182 so that the connection land 181 is exposed. The circuit board 180 on which the semiconductor device 100 is positioned is subjected to a heat treatment such as reflow, so that the solder bump 107 is melted and joined to the connection land 181.
As described above, when the semiconductor device 100 is mounted on the circuit board 180, the solder bump 107 and the solder portion 108 are imaged and recognized by, for example, an imaging device, so that the semiconductor device 100 is properly mounted on the circuit board 180. It can be positioned at a position. The circuit board 180 is not limited to being a single-sided mounting board, and may be a double-sided mounting board. In addition, electronic components other than the semiconductor device 100 may be mounted on the circuit board 180. Therefore, the heat treatment such as reflow is not limited to once but may be performed a plurality of times.

  Next, each configuration and arrangement on the main surface side of the semiconductor device 100 will be described with reference to FIG. On the main surface 101 a of the semiconductor device 100, a plurality of solder bumps 107 are arranged symmetrically about a center line along the short side or the long side in plan view of the semiconductor chip 101. In the present embodiment, two of the six solder bumps 107 are located on the center line along the short side of the semiconductor chip 101. Three solder bumps 107 are arranged in three rows at equal intervals in the short side direction of the semiconductor chip 101. In addition, two rows of three solder bumps 107 are arranged at equal intervals in the long side direction of the semiconductor chip 101. The size (diameter) of the solder bump 107 in plan view is, for example, 200 μm to 250 μm.

  A plurality (six) of electrodes 102 connected to an electric circuit formed on the semiconductor chip 101 are provided. In addition, a plurality (six) of wiring patterns 105A to 105F that connect each of the electrodes 102 and the solder bump 107 are provided. The wiring pattern 105A connects the solder bump 107A and the corresponding electrode 102. Similarly, the other wiring patterns 105B to 105F connect the solder bumps 107 indicated by the same alphabet with the same reference numerals to the corresponding electrodes 102. The plurality of wiring patterns 105A to 105F are collectively referred to as a wiring pattern 105.

  The end of the wiring pattern 105 on the solder bump 107 side has an arc shape (round shape) corresponding to the circular solder bump 107 in plan view. The arc-shaped portion corresponds to the connection pad in the present invention.

Each of the plurality of solder bumps 107 is given position information corresponding to the electrode 102 connected through the wiring pattern 105. In the present embodiment, the solder bumps 107A, the solder bumps 107B, the solder bumps 107C, the solder bumps 107D, the solder bumps 107E, and the solder bumps 107F are arranged in this order in the clockwise direction with respect to the center of the main surface 101a of the semiconductor chip 101. .
The solder portion 108 as an alignment mark is provided in the vicinity of one corner portion of the four corner portions of the semiconductor chip 101. Further, in order to indicate positional information of the plurality of solder bumps 107 arranged in line symmetry on the main surface 101a, it is provided in the vicinity of a specific solder bump 107A. The solder part 108 only needs to have a size that can be recognized by the imaging device as described above. The solder part 108 in the present embodiment is substantially hemispherical, and the size (diameter) in plan view is For example, 50 μm.

  The arrangement of the electrode 102, the wiring pattern 105, the solder bump 107, and the solder portion 108 on the main surface 101a is not limited to this. Corresponding to the configuration of the electric circuit formed on the semiconductor chip 101, a necessary number of electrodes 102, wiring patterns 105, and solder bumps 107 are arranged. Further, the number of solder portions 108 is not limited to one, and a plurality of solder portions 108 may be arranged. Furthermore, the plurality of solder portions 108 need not have the same size (diameter).

Next, the structure of the semiconductor device 100 will be described with reference to FIGS.
As shown in FIG. 3, an electrode 102 is formed on a main surface 101a of a semiconductor chip 101 using a low-resistance electrode material such as aluminum. An insulating film 103 made of an inorganic insulating material such as silicon oxide is formed so as to cover the main surface 101a on which the electrode 102 is formed. The insulating film 103 has a thickness in the range of, for example, 0.1 μm to 1.5 μm, and an opening is formed in a portion overlapping the electrode 102 by photolithography. The insulating film 103 is patterned so as not to reach the outer edge of the semiconductor chip 101.

  An insulating layer 104 is further formed to cover the main surface 101a on which the insulating film 103 is formed. The insulating layer 104 can be formed using a photosensitive resin material. The insulating layer 104 in this embodiment is formed using a photosensitive polyimide resin, and can insulate the main surface 101a of the semiconductor chip 101 with high insulating properties. The insulating layer 104 includes a first resin layer 104-1 that covers the insulating film 103 and a second resin layer 104-2 that is formed by being stacked on the first resin layer 104-1. The first resin layer 104-1 and the second resin layer 104-2 have an opening in a portion overlapping with the electrode 102 in a plan view, and are formed in a region overlapping with the solder bump 107. The thickness of the 1st resin layer 104-1 is about 5 micrometers, and the thickness of the 2nd resin layer 104-2 is thicker than the 1st resin layer 104-1, and is about 9 micrometers.

  In addition, the first resin layer 104-1 and the second resin layer 104-2 are made of polyimide resin, but the second resin layer 104- is more than the first resin layer 104-1, depending on how it is formed. No. 2 has higher (larger) breaking strength as a physical property. Specifically, the breaking strength of the first resin layer 104-1 is approximately 120 MPa, and the breaking strength of the second resin layer 104-2 is approximately 160 MPa.

  A wiring pattern 105 (in the figure, wiring patterns 105C and 105D) is formed on the second resin layer 104-2. The material configuration of the wiring pattern 105 is not particularly limited. In the present embodiment, the first layer 105-1 in which a layer made of TiW (titanium / tungsten) and a layer made of Cu (copper) are stacked is provided. And a second layer 105-2 made of Cu (copper) formed by being laminated on the first layer 105-1. The thickness of the TiW layer in the first layer 105-1 is approximately 100 nm, and the thickness of the Cu layer is approximately 300 nm. That is, the thickness of the first layer 105-1 is approximately 400 nm. On the other hand, the thickness of the second layer 105-2 is approximately 8 μm. The wiring pattern 105 is formed so as to fill an opening formed on the electrode 102 in the insulating film 103 and the insulating layer 104, and is electrically connected to the electrode 102.

  An overcoat layer 106 is formed so as to cover the main surface 101a on which the wiring pattern 105 is formed. The overcoat layer 106 can be formed using a photosensitive solder resist (resin material). The overcoat layer 106 in this embodiment is formed using a photosensitive phenol resin, and the thickness thereof is 8 μm to 10 μm. In the overcoat layer 106, an opening 106-1 is formed in a portion of the wiring pattern 105 that overlaps the above-described connection pad by photolithography. The strength at break of the overcoat layer 106 covering the insulating layer 104 is smaller than the strength at break of the first resin layer 104-1 and the second resin layer 104-2 constituting the insulating layer 104. Specifically, the strength at break of the overcoat layer 106 in this embodiment is approximately 90 MPa. Therefore, the relationship between the breaking strengths of the first resin layer 104-1, the second resin layer 104-2, and the overcoat layer 106 provided on the main surface 101a of the semiconductor chip 101 is as follows: overcoat layer 106 <first The order of the resin layer 104-1 <the second resin layer 104-2. When attention is paid to the elongation at break as a physical property, the first resin layer 104-1 is approximately 36%, the second resin layer 104-2 is approximately 83%, and the overcoat layer 106 is 6%. It has become the same tendency. Further, focusing on the linear expansion coefficient as a physical property, the first resin layer 104-1 is approximately 54 ppm / ° C., the second resin layer 104-2 is approximately 46 ppm / ° C., and the overcoat layer 106 is approximately 55 ppm / ° C. And there is not much difference between each other.

  Solder bumps 107 (solder bumps 107C and 107D in the figure) as solder terminals are formed so as to fill the openings 106-1 formed in the overcoat layer 106, and bonded to the connection pads of the wiring pattern 105. ing.

  Next, alignment marks of the semiconductor device 100 will be described with reference to FIG. As shown in FIG. 4, in the same layer as the wiring layer provided with the wiring pattern 105 (wiring pattern 105A in the figure), a base pattern 105M is formed on the insulating layer 104 electrically independently. That is, the base pattern 105M includes a first layer 105-1 composed of a TiW layer and a Cu layer, and a second layer 105-2 composed of Cu. Being electrically independent means that it is not electrically connected to the wiring connected to the internal circuit of the semiconductor device 100. By making the base pattern 105M electrically independent, the solder portion 108 bonded to the base pattern 105M is also electrically independent. Therefore, even if the semiconductor device 100 is mounted on the circuit board 180 described above, for example, even if the solder part 108 contacts the electronic component mounted on the circuit board 180 or the wiring connected to the electronic component, the semiconductor device 100 is electrically short-circuited. The problem does not occur. As described above, the base pattern 105M is preferably formed electrically independently. However, for example, the base pattern 105M may be electrically connected to a common wiring such as GND in the internal circuit of the semiconductor device 100.

  In the overcoat layer 106, an opening 106-2 is formed in a portion overlapping with the base pattern 105M by a photolithography method. The solder part 108 is formed so as to fill the opening 106-2 and is joined to the base pattern 105M. The first resin layer 104-1 in the insulating layer 104 is formed so as to cover not only the solder bump 107 (the solder bump 107A in the drawing) but also the solder portion 108 in a plan view. Yes.

The opening 106-1 formed in the overcoat layer 106 corresponds to the first opening of the present invention, and the opening 106-2 corresponds to the second opening of the present invention. The planar shapes of the opening 106-1 and the opening 106-2 are each circular. The size (diameter) of the opening 106-1 in plan view is larger than the size (diameter) of the opening 106-2.
A detailed method for forming these structures on the main surface 101 a of the semiconductor chip 101 will be described in the following method for manufacturing the semiconductor device 100.

<Method for Manufacturing Semiconductor Device>
The manufacturing method of the semiconductor device of this embodiment will be described with reference to FIGS. FIG. 5 is a flowchart showing a method for manufacturing a semiconductor device, and FIGS. 6A to 6E and 7F to 7J are schematic cross-sectional views showing a method for manufacturing a semiconductor device. 6 (a) to 6 (e) and FIGS. 7 (f), (g), and (j) are schematic cross-sectional views corresponding to FIG. 3, and FIGS. 7 (h) and (i) are illustrated in FIG. It is a corresponding schematic sectional drawing.

  As shown in FIG. 5, the manufacturing method of the semiconductor device 100 of this embodiment includes a first resin layer forming step (step S1), a second resin layer forming step (step S2), and a wiring layer forming step (step S3). ), Wiring pattern forming step (step S4), overcoat layer (OC layer) forming step (step S5), overcoat layer (OC layer) patterning step (step S6), and solder terminal forming step (step S7). ). As a method for forming the electric circuit or the electrode 102 connected to the electric circuit on the main surface 101a of the semiconductor chip 101 and a method for forming the insulating film 103 covering the main surface 101a, known methods can be employed. Therefore, here, the steps related to the present invention will be described.

  In step S <b> 1 of FIG. 5, as shown in FIG. 6A, the first resin layer 104-1 is formed on the main surface 101 a of the semiconductor chip 101 so as to cover the insulating film 103. As a specific forming method, first, a photosensitive resin layer is formed by applying a solution containing a photosensitive polyimide resin to the main surface 101a by, for example, spin coating, drying and baking. And the 1st resin layer 104-1 which has an opening part in the part which overlaps with the electrode 102 is formed by exposing and developing the said photosensitive resin layer. The first resin layer 104-1 is patterned so that the formation region does not reach the outer edge of the semiconductor chip 101. As described above, the thickness of the first resin layer 104-1 is approximately 5 μm. Then, the process proceeds to step S2.

  In step S2 of FIG. 5, as shown in FIG. 6B, the second resin layer 104-2 is formed so as to cover the first resin layer 104-1. As a specific forming method, similar to the first resin layer 104-1, a solution containing a photosensitive polyimide resin is applied to the main surface 101a by, for example, a spin coating method, and is dried and baked, for example. A resin layer is formed. Then, by exposing and developing the photosensitive resin layer, a second resin layer 104-2 having an opening in a portion overlapping with the electrode 102 is formed. The second resin layer 104-2 is patterned so that the formation region does not reach the outer edge of the semiconductor chip 101. The thickness of the second resin layer 104-2 is approximately 9 μm as described above. Thereby, the insulating layer 104 composed of the first resin layer 104-1 and the second resin layer 104-2 is completed. Then, the process proceeds to step S3.

In step S3 of FIG. 5, first, as shown in FIG. 6C, the first layer 105-1 constituting the wiring layer is formed on the second resin layer 104-2. As a specific forming method, a film is formed by continuously sputtering TiW and Cu by a sputtering method. As described above, the thickness of TiW is approximately 100 nm, and the thickness of Cu is approximately 300 nm. The first layer 105-1 is electrically connected to the electrode 102 by covering the inside of the opening formed in the insulating layer 104.
Next, the second layer 105-2 is formed over the first layer 105-1 formed in advance. Specifically, a photosensitive resin layer that covers the first layer 105-1 is formed. Then, the photosensitive resin layer is exposed and developed so that a portion where the second layer 105-2 is formed is opened. Subsequently, by using the first layer 105-1 as an electrode and forming a Cu film by an electrolytic plating method, the second resin layer 105 in contact with the first layer 105-1 is removed by removing the photosensitive resin layer. -2 is formed by a lift-off method. As described above, the thickness of the second layer 105-2 is approximately 8 μm. Since the wiring layer is mainly composed of Cu having a thickness of 8 μm, it is possible to form the wiring pattern 105 having a small electric resistance by patterning the wiring layer. Then, the process proceeds to step S4.

  In step S4 of FIG. 5, as shown in FIG. 6E, the wiring layer is patterned to form a wiring pattern 105 (wiring patterns 105A to 105F in the drawing). Although not shown in FIG. 6E, the wiring layer is patterned to form the wiring pattern 105, and at the same time, an electrically independent ground pattern 105M is formed in the vicinity of the specific wiring pattern 105A. As a specific formation method, the first layer 105-1 and the second layer 105-2 in the wiring layer have different material configurations, and therefore the first layer is formed using the second layer 105-2 patterned by the lift-off method as a mask. Etch 105-1. Examples of the etching method include a wet etching method. Specifically, for example, a ferric chloride solution is used for etching the Cu layer of the first layer 105-1, and a hydrogen peroxide aqueous solution is used for etching the TiW layer of the first layer 105-1, for example. It is done. Since the second layer 105-2 as a mask is formed thick by electrolytic plating, the second layer 105-2 may be slightly etched when the Cu layer of the first layer 105-1 is etched. Absent. In addition, since the first layer 105-1 containing TiW is formed first on the electrode 102 made of aluminum, the first layer 105-1 is etched using the second layer 105-2 made of Cu as a mask. At this time, it is difficult to affect the connection portion with the electrode 102 by etching. That is, the connection reliability in the wiring pattern 105 can be improved. The wiring layer etching method is not limited to wet etching, and dry etching may be used. Then, the process proceeds to step S5.

  In step S5 of FIG. 5, as shown in FIG. 7F, an overcoat layer 106 that covers the wiring pattern 105 (wiring patterns 105A to 105F in the drawing) is formed. As a specific forming method, there is a method of forming the overcoat layer 106 by applying a solution containing a photosensitive phenol resin by, for example, a spin coating method, drying and baking. As described above, the thickness of the overcoat layer 106 is 8 μm to 10 μm. That is, the thickness is sufficient to cover the insulating layer 104, the wiring pattern 105, and the base pattern 105M formed on the main surface 101a of the semiconductor chip 101. Then, the process proceeds to step S6.

  In step S6 of FIG. 5, the overcoat layer 106 is patterned by photolithography. Thus, as shown in FIG. 7G, an opening 106-1 is formed in the portion of the overcoat layer 106 that overlaps the connection pad of the wiring pattern 105. Although not shown in FIG. 7G, an opening 106-2 is formed in the portion of the overcoat layer 106 that overlaps the base pattern 105M at the same time. The size of the opening 106-1 is larger than the size of the opening 106-2. Then, the process proceeds to step S7.

In step S7 of FIG. 5, solder bumps 107 as solder terminals are formed in the openings 106-1 of the overcoat layer 106, and solder portions 108 are formed in the openings 106-2. Specifically, first, as shown in FIG. 7H, a solder paste 70 is applied by, for example, a printing method so as to fill the opening 106-1 and the opening 106-2, respectively. Then, the applied solder paste 70 is heated and melted and cooled, so that the solder bumps 107 (solder in the figure) are filled with the openings 106-1 and bonded to the wiring pattern 105 (wiring pattern 105A in the figure). Bumps 107A) are formed. Similarly, the solder part 108 is formed by filling the opening 106-2 and joining the base pattern 105M. As described above, since the size of the opening 106-1 is larger than the size of the opening 106-2, the coating amount of the solder paste 70 filling the opening 106-1 is larger than the coating amount filling the opening 106-2. And increase. Therefore, after cooling, the height h1 of the solder bump 107A is larger than the height h2 of the solder portion 108, as shown in FIG. 7 (i). Similarly, as shown in FIG. 7 (j), the height at which the openings 106-1 formed corresponding to the other wiring patterns 105B to 105F are filled and joined to the other wiring patterns 105B to 105F is high. The h1 solder bumps 107B to 107F are formed.
In addition, the opening shape in planar view of the opening part 106-1 and the opening part 106-2 is not limited to circular. Therefore, when the opening shape is a polygon such as a hexagon or an octagon, the “size” of the opening 106-1 and the opening 106-2 is the length of the diagonal line of the opening in a plan view, that is, The maximum diameter of the opening in plan view. The same applies when only the opening shape of the opening 106-2 is not circular.

The effects of the first embodiment are as follows.
(1) According to the semiconductor device 100 and the manufacturing method thereof, the solder part 108 as an alignment mark fills the opening 106-2 formed in the overcoat layer 106 with the solder paste 70 and heats and melts it. It is formed by being bonded to the base pattern 105M. Further, the overcoat layer 106 has a lower breaking strength than the first resin layer 104-1 and the second resin layer 104-2 constituting the lower insulating layer 104. Therefore, compared to the case where the opening 106-2 is opened without being filled with the solder part 108, when heat such as reflow is applied, due to the difference in physical properties between the insulating layer 104 and the overcoat layer 106, Even if stress is applied to the overcoat layer 106, since the opening 106-2 is filled with the solder part 108, the stress applied to the vicinity of the opening 106-2 is dispersed, and the overcoat layer is formed in the vicinity of the opening 106-2. The occurrence of cracks in 106 can be reduced. In addition, it can be prevented that cracks of the overcoat layer 106 progress to reach the insulating layer 104, and moisture and the like enter the main surface 101a from the crack portion to deteriorate the insulating properties. That is, it is possible to provide the semiconductor device 100 having an electrically excellent reliability quality.
(2) Since the solder portion 108 as an alignment mark provided on the main surface 101a side of the semiconductor chip 101 is formed so as to protrude from the surface of the overcoat layer 106, the base pattern is provided without providing the solder portion 108. Compared to the case where 105M is used as an alignment mark, it is easier to recognize a specific solder bump 107A and the solder portion 108 as an alignment mark at the same time. Specifically, since the difference in distance between the solder bump 107A and the solder portion 108 in the height direction is smaller than when imaging the solder bump 107A and the base pattern 105M using an imaging device, it is possible to adjust the focus. The time required is short. In other words, it is possible to simultaneously image the solder bump 107A and the solder portion 108 even with an imaging device with a shallow depth of focus.
(3) The insulating layer 104 includes the first resin layer 104-1 and the second resin layer 104-2 having a higher breaking strength than the first resin layer 104-1. Therefore, compared with the case where the insulating layer 104 has a single structure, cracks caused by thermal stress are unlikely to reach the first resin layer 104-1.
(4) The height h2 of the solder portion 108 as an alignment mark is lower than the height h1 of the solder bump 107 provided on the main surface 101a side. Therefore, when the semiconductor device 100 is mounted on the circuit board 180, for example, the solder portion 108 does not become an obstacle to mounting.

(Second Embodiment)
<Other semiconductor devices and manufacturing methods thereof>
Next, the semiconductor device of the second embodiment and the manufacturing method thereof will be described with reference to FIG. 8A and 8B are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device of the second embodiment. The semiconductor device of the second embodiment is different from the semiconductor device 100 of the first embodiment in that the size of the solder portion 108 in plan view is different, specifically, larger. Therefore, the same components as those of the semiconductor device 100 are denoted by the same reference numerals and detailed description thereof is omitted. 8A and 8B are schematic cross-sectional views corresponding to FIG. 4 of the first embodiment.

  As shown in FIG. 8A, in the semiconductor device 150 of this embodiment, the size of the opening 106-2 formed in the overcoat layer 106 corresponding to the base pattern 105M is the wiring pattern 105 (FIG. Among them, the size is larger than the size of the opening 106-1 formed corresponding to the wiring pattern 105A). Then, in the step of forming the solder terminals, as shown in FIG. 8A, the solder balls 70B are disposed in the opening 106-1 and the opening 106-2, respectively. The disposed solder balls 70B are heated, melted, and cooled to form solder bumps 107A filling the openings 106-1 and bonded to the wiring pattern 105A, and filling the openings 106-2 to form the base pattern 105M. A solder portion 108 is formed as an alignment mark joined to the substrate. Even if the size of the solder ball 70B is the same, the opening 106-2 is larger than the opening 106-1, so that the height h2 of the formed solder 108 is lower than the height h1 of the solder bump 107A.

According to the semiconductor device 150 and the manufacturing method thereof according to the second embodiment, the following effects are obtained in addition to the effects (1) to (3) of the first embodiment.
(5) Compared with the semiconductor device 100 of the first embodiment, since the size of the solder part 108 in plan view is increased, the visibility of the solder part 108 as an alignment mark is improved. In addition, even if the opening 106-2 is enlarged, the solder ball 70B is disposed, and the solder part 108 is formed by heating, melting, and cooling, so that the solder part does not become an obstacle in mounting the semiconductor device 150. The height h2 of 108 can be adjusted.

  The present invention is not limited to the above-described embodiments, and various modifications can be made as appropriate without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. A method for manufacturing a semiconductor device is also included in the technical scope of the present invention. Various modifications other than the above embodiment are conceivable. Hereinafter, a modification will be described.

(Modification 1) The configuration of the insulating layer 104 in the semiconductor device 100 or the semiconductor device 150 is not limited to including the first resin layer 104-1 and the second resin layer 104-2. 9A and 9B are schematic cross-sectional views showing the structure of a semiconductor device according to a modification. FIG. 9A corresponds to FIG. 3 of the first embodiment, and FIG. 9B corresponds to FIG. 4 of the first embodiment.
As shown in FIGS. 9A and 9B, in the semiconductor device 170 of the modified example, the insulating layer 104A covering the main surface 101a of the semiconductor chip 101 is made of a single material and a layer configuration. Therefore, the manufacturing process can be simplified according to the first embodiment. Even in this case, the breaking strength of the insulating layer 104A is preferably larger than the breaking strength of the overcoat layer 106.

  The manufacture of the chip-sized semiconductor device 100 is normally performed in a clean room in which the size and number of particles (foreign matter) during the manufacturing process are controlled. The degree of cleanliness in the process of forming the electric circuit, the electrode 102, and the insulating film 103 on the semiconductor chip 101 is much better than the degree of cleanliness in the process of forming the wiring pattern 105, the overcoat layer 106, and the solder bump 107 (foreign matter) Is required). Therefore, a process prior to the process of forming the wiring pattern 105 may be referred to as a pre-process, and a process after the process of forming the wiring pattern 105 may be referred to as a post-process. When the semiconductor chip 101 being manufactured is transported between clean rooms or factories or companies having different cleanliness, in the semiconductor device 100 of the first embodiment, the first resin layer 104-1 is formed in the previous step to form the main surface. It is possible to manufacture the semiconductor device 100 with a high yield by preventing the mechanical or electrical damage during the transportation by transferring to the subsequent process while protecting the 101a and forming the second resin layer 104-2 in the subsequent process. it is conceivable that.

  (Modification 2) The semiconductor device to which the present invention is applicable is not limited to the chip size. FIG. 10 is a schematic plan view showing a semiconductor wafer. As shown in FIG. 10, a semiconductor device 100 to which the present invention is applied can be manufactured using a semiconductor wafer 100W. The semiconductor device 100 (semiconductor chip 101) is manufactured in a state in which a plurality of layouts are designed on the basis of an orientation flat in which the outer edge of the semiconductor wafer 100W is partially cut away. When the semiconductor wafer 100W is cut using a cutting method such as a dicing method or a laser cutting method after the series of manufacturing steps described above is completed, the individual semiconductor devices 100 can be taken out. That is, the semiconductor wafer 100W is also included in the technical scope of the present invention.

  Further, the outer shape of the chip-sized semiconductor device 100 is adjusted by cutting the semiconductor wafer 100W. If the insulating film 103 formed using an inorganic insulating material, and the insulating layer 104 or the overcoat layer 106 formed using a resin material are formed over the entire surface of the semiconductor wafer 100W, cracks or peeling may occur in the cross section during cutting. Is likely to occur. Then, moisture or the like easily enters the main surface 101a from the cracked or peeled portion, so that the insulating film 103, the insulating layer 104, and the overcoat layer 106 in the semiconductor device 100 are selectively used in a region that avoids the outer edge of the semiconductor chip 101. (Refer to FIG. 1 or FIG. 2).

  DESCRIPTION OF SYMBOLS 70 ... Solder paste, 70B ... Solder ball, 100, 150, 170 ... Semiconductor device, 101 ... Semiconductor chip, 101a ... Main surface of semiconductor chip, 104 ... Insulating layer, 104-1 ... First resin layer, 104-2 ... Second resin layer, 105, 105A, 105B, 105C, 105D, 105E, 105F ... wiring pattern, 105M ... base pattern, 106-1 ... opening as first opening, 106-2 ... second opening 107, 107A, 107B, 107C, 107D, 107E, 107F ... solder bumps as solder terminals, 108 ... solder parts.

Claims (12)

A semiconductor chip;
An insulating layer covering the main surface of the semiconductor chip;
An overcoat layer covering the insulating layer;
A wiring layer provided between the insulating layer and the overcoat layer;
A wiring pattern provided on the wiring layer and including a connection pad for connection to an external circuit;
A base pattern provided in the wiring layer;
A solder terminal formed by filling a first opening disposed at a position overlapping the connection pad of the overcoat layer;
A semiconductor device comprising: an alignment solder portion formed by filling a second opening disposed at a position overlapping the base pattern of the overcoat layer. The insulating layer and the overcoat layer are formed using a resin material,
The semiconductor device according to claim 1, wherein the breaking strength of the insulating layer is larger than the breaking strength of the overcoat layer. The insulating layer includes a first resin layer and a second resin layer having different strength at break,
On the main surface, the first resin layer, the second resin layer, the wiring layer, the overcoat layer are formed in this order.
3. The semiconductor device according to claim 2, wherein the strength at break satisfies the relationship of the overcoat layer <the first resin layer <the second resin layer. 4.   The semiconductor device according to claim 2, wherein the insulating layer is formed using a polyimide resin.   The semiconductor device according to claim 1, wherein a size of the first opening is larger than a size of the second opening. The wiring layer is provided with a plurality of the wiring patterns,
The semiconductor device according to claim 1, wherein the base pattern is provided in the vicinity of a specific wiring pattern among the plurality of wiring patterns.   The semiconductor device according to claim 1, wherein the base pattern is electrically independent in the wiring layer. A method for manufacturing a semiconductor device, comprising: a semiconductor chip; and a solder terminal provided on a main surface of the semiconductor chip for connection to an external circuit,
Forming an insulating layer covering the main surface;
Forming a wiring layer on the insulating layer;
Patterning the wiring layer to form a wiring pattern connected to the solder terminal and a base pattern;
Forming an overcoat layer covering the wiring pattern and the base pattern;
Patterning the overcoat layer to form a first opening at a position overlapping the solder terminal, and forming a second opening at a position overlapping the base pattern;
Filling the first opening and the second opening with solder;
And heating the solder to form the solder terminal in the first opening and forming an alignment solder in the second opening. Production method. In the step of forming the insulating layer, the insulating layer is formed by applying a solution containing a photosensitive polyimide resin to the main surface and drying.
9. The method of manufacturing a semiconductor device according to claim 8, wherein, in the step of forming the overcoat layer, the overcoat layer having a breaking strength lower than that of the insulating layer is formed. In the step of forming the first opening and the second opening, the second opening smaller than the size of the first opening is formed,
The step of filling the first opening and the second opening with solder fills the first opening and the second opening using a solder paste by a printing method. Item 10. A method for manufacturing a semiconductor device according to Item 8 or 9. In the step of forming the first opening and the second opening, the second opening larger than the size of the first opening is formed,
9. The step of filling the first opening and the second opening with solder includes disposing solder balls in the first opening and the second opening. A method for manufacturing a semiconductor device according to claim 9.   12. The method of manufacturing a semiconductor device according to claim 8, wherein in the step of forming the base pattern, the wiring layer is patterned to form the electrically independent base pattern. .

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