JP2015095816A - Δσda modulator and δσad modulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a complex multi-band-pass DA modulator.SOLUTION: A complex multi-band-pass DA modulator has a first DA converter 11 and a second DA converter 12, a first converter control unit 13, a second converter control unit 14, an input selection unit 15, and an output selection unit 16. The first converter control unit 13 sequentially selects, while using N pointers, segment elements of the first DA converter 11 by a low-pass element rotation algorithm. The second converter control unit 14 sequentially selects, while using N pointers, segment elements of the second DA converter 12 by a high-pass element rotation algorithm. The input selection unit 15 and the output selection unit 16 alternately select, every N signals, the signal to be inputted and outputted to and from the first DA converter 11 and second DA converter 12.

Description

  The present invention relates to a ΔΣ DA modulator and a ΔΣ AD modulator.

  Application of a ΔΣ modulator using a multiband pass filter to an RF receiver circuit of a communication system such as a mobile phone or a wireless LAN is under study. Patent Document 1 and Non-Patent Document 1 describe a ΔΣ modulator having a plurality of segment elements and a DA converter provided with a weighting pointer so that an input digital signal is sequentially supplied to the plurality of segment elements. ing. With this DA converter, it is possible to efficiently remove non-linear noise resulting from the characteristics of the multi-bit DAC.

  In addition, it has been studied to apply a complex bandpass ΔΣ AD converter to the RF receiving circuit. Patent Document 2 and Non-Patent Documents 2 and 3 describe a DA modulator comprising a first DA converter and a second DA converter, multiplexer means, first logic circuit means and second logic circuit means. . In this modulator, the multiplexer means alternately inputs / outputs the first digital signal and the second digital signal at a predetermined cycle in accordance with a predetermined clock so as to obtain a DA converted analog signal. Control. Further, the first logic circuit means and the second logic circuit means are provided in front of the first DA converter and the second DA converter, respectively. The first logic circuit means and the second logic circuit means use the high-pass element rotation method for the first digital signal, and realize the complex digital filter using the low-pass element rotation method for the second digital signal. The first logic circuit means and the second logic circuit means implement the complex analog filter. In this DA converter, the nonlinearity of the first DA converter and the second DA converter can be substantially noise-shaped.

Special table 2007-066431 JP 2006-13705 A

Atsushi Motozawa, Hiroyuki Sugawara, Yoshio Yamada, Haruo Kobayashi, Takanori Komuro, Satoshi Umbrella, “Multiband Pass ΔΣ Modulator Technology and its Applications”, IEICE Journal C vol. J90-C, no.2, pp.143-158 (February 2007). H. San, H. Kobayashi, S. Kawakami, N. Kuroiwa, `` A Noise-Shaping Algorithm of Multi-bit DAC Nonlinearities in Complex Bandpass Δ ΣAD Modulators '', IEICE Trans. On Fundamentals, E87-A, no. 4, pp.792-800 (April. 2004). H. San, A. Hagiwara, A. Motozawa, H. Kobayashi `` DWA Algorithms for Multibit Complex Bandpass ΔΣAD Modulators of Arbitrary Signal Band '', IEEJ International Analog VLSI Workshop, Hangzhou, China (Nov. 2006).

  In order to further reduce power consumption, it is desired that each of the AD modulator and the DA modulator be realized by a multi-bit ΔΣ modulator. When the AD modulator is realized by a multi-bit ΔΣ modulator, the slew rate requirement of the amplifier is eased, and the power consumption of the amplifier can be reduced. Also, when realized with a DA modulator multi-bit ΔΣ modulator, the quantization noise is reduced, thereby reducing the requirement for an analog filter disposed at the subsequent stage of the DA modulator. However, a complex multiband pass DA modulator that DA-modulates a complex digital signal with multibits has not been realized.

  Accordingly, an object of the present invention is to provide a complex multiband pass DA modulator that DA-modulates a complex digital signal with multi-bits.

  In order to achieve the above object, a ΔΣ DA modulator according to the present invention DA-converts a first digital signal into a first analog signal, and also makes a second digital signal orthogonal to the first digital signal orthogonal to the first analog signal. A ΔΣ DA modulator that performs DA conversion to a second analog signal, each of which has a plurality of segment elements, and controls the first DA converter and the second DA converter that convert a digital signal into an analog signal, and the first DA converter A first converter control unit, a second converter control unit for controlling the second DA converter, and a second digital signal input to the second converter control unit when a first digital signal is input to the first converter control unit. An input selection unit that inputs a signal and inputs the first digital signal to the second converter control unit when the second digital signal is input to the first converter control unit, and a first analog signal from the first DA converter An output selection unit that outputs a second analog signal from the second DA converter when outputting, and outputs a first analog signal from the second DA converter when outputting the second analog signal from the first DA converter. The input selection unit alternately inputs the first digital signal and the second digital signal to the first converter control unit and the second converter control unit for every N number that is an integer of 2 or more, and the output selection unit Alternately outputs the first analog signal and the second analog signal from the first converter control unit and the second converter control unit every N units, and the first converter control unit receives the N digital inputs Each of the signals has N pointers corresponding to each of the signals. Using the N pointers, the segment elements of the first DA converter are sequentially selected by the low-pass element rotation algorithm, and the second converter controller is input. N The digital signal has N pointers corresponding to each of the digital signals, and the segment elements of the second DA converter are sequentially selected by the high-pass element rotation algorithm using the N pointers.

  Further, in the ΔΣ DA modulator according to the present invention, the first converter control unit includes a first DAC first pointer to a first DAC number which are N pointers each indicating any one of a plurality of segment elements of the first DA converter. Each time a digital signal is input, the first DA converter sequentially uses the first DAC first pointer to the first DAC Nth pointer, and each of the second converter control units performs the second DA conversion. The second DAC first pointer to the second DAC Nth pointer, which are N pointers indicating any one of the plurality of segment elements of the device, and the second DA converter receives the second DAC every time a digital signal is input. It is preferable to sequentially use the first pointer to the second DAC Nth pointer.

  Further, in the ΔΣ DA modulator according to the present invention, the first converter control unit determines the number of segment elements to be selected based on the input digital signal, and the first DA converter indicated by the first DAC Nth pointer. It is preferable to select the determined number of segment elements located in the forward direction of the segment element, and change the segment element of the first DA converter indicated by the first DAC N-th pointer based on the selected segment element.

  Further, in the ΔΣ DA modulator according to the present invention, the first DA converter has M segment elements from the first segment element to the Mth segment element, and the first converter control unit extends to the Mth segment element. It is preferable that the first segment element is then selected when sequentially selected in the forward direction.

  Furthermore, in the ΔΣ DA modulator according to the present invention, the second converter control unit determines the number of segment elements to be selected based on the input digital signal, and the second DA converter indicated by the second DAC Nth pointer. The determined number of segment elements located in the forward direction or the reverse direction of the segment element are selected, the segment element of the second DA converter indicated by the second DAC Nth pointer is changed based on the selected segment element, and the second When the converter control unit selects a segment element positioned in the forward direction of the segment element indicated by the second DAC Nth pointer, the next DA converter indicated by the second DAC Nth pointer is used when the second DAC Nth pointer is used next time. The segment element located in the opposite direction of the segment element is selected, and the second converter control unit selects the segment indicated by the second DAC Nth pointer. When a segment element located in the reverse direction of the second element is selected, the next time the second DAC Nth pointer is used, the segment element located in the forward direction of the segment element of the second DA converter indicated by the second DAC Nth pointer is selected. It is preferable to select.

  Further, in the ΔΣDA modulator according to the present invention, the second DA converter has M segment elements from the first segment element to the Mth segment element, and the second converter control unit extends to the Mth segment element. When selecting sequentially in the forward direction, the first segment element is selected when further selecting in the forward direction, and when selecting further in the reverse direction up to the first segment element, the Mth segment is selected when further selecting in the reverse direction. It is preferable to select an element.

  In order to achieve the above object, a ΔΣ AD modulator according to the present invention AD-modulates a first analog signal to a first digital signal and a second analog signal orthogonal to the first analog signal orthogonal to the first digital signal. A ΔΣ AD modulator that AD-modulates a second digital signal, DA-modulating the first digital signal to a first feedback signal, and DA-modulating the second digital signal to a second feedback signal; A first subtractor for subtracting the first feedback signal from the analog signal; a second subtractor for subtracting the second feedback signal from the second analog signal; and a complex for filtering the output signals of the first subtractor and the second subtractor. A multi-band pass filter and a signal that has been filtered by the complex multi-band pass filter are AD converted to a first digital signal. An AD converter, and a second AD converter that AD converts the signal filtered by the complex multi-bandpass filter into a second digital signal, and each of the first DA modulator and the second DA modulator includes the above-described ΔΣDA modulator. It is either of these.

  With the DA modulator according to the present invention, it is possible to provide a complex multiband pass DA modulator that DA-modulates a complex digital signal with multi-bits.

(A) is a circuit diagram of a segment current cell type DA converter, and (b) is a circuit diagram in which elements of the segment current cell type DA converter shown in (a) are arranged in a ring shape. (A) is a figure which shows a low-pass element rotation algorithm schematically, (b) is a figure which shows an example of the power spectrum of the DA converter which uses a low-pass element rotation algorithm. (A) is a figure which shows a high-pass element rotation algorithm schematically, (b) is a figure which shows an example of the power spectrum of the DA converter which uses a high-pass element rotation algorithm. (A) is a circuit block diagram of a complex bandpass ΔΣDA modulator, (b) is an internal circuit diagram of the complex resonator shown in (a), and (c) is a power of the complex resonator shown in (b). It is a figure which shows an example of a spectrum. (A) is a circuit block diagram of a secondary complex bandpass ΔΣDA modulator, and (b) is a diagram showing an example of a power spectrum of the secondary complex bandpass ΔΣDA modulator shown in (a). (A) is a circuit block diagram of another example of the complex bandpass ΔΣDA modulator, (b) is a diagram showing an operation algorithm of the DA converter shown in (a), and (c) is (a). FIG. 3 is a circuit block diagram showing a specific circuit configuration of the complex bandpass ΔΣ AD modulator shown in FIG. (A) is a circuit block diagram of an example of a multi-band pass ΔΣ AD modulator, (b) is a diagram showing an example of a power spectrum of the multi-band pass ΔΣ AD modulator shown in (a), and (c) is a multi-band pass ΔΣ AD modulator. It is a circuit block diagram of the other example of a band pass ΔΣ AD modulator, and (d) is a diagram showing an example of a power spectrum of the multiband pass ΔΣ AD modulator shown in (c). (A) is a circuit block diagram of an example of a secondary multiband pass ΔΣDA modulator, (b) is a diagram showing a signal band center frequency of the secondary multibandpass ΔΣDA modulator shown in (a), c) is a diagram showing an example of a low-pass element rotation algorithm used in the secondary multiband pass ΔΣDA modulator shown in (a), and (d) is a secondary multiband pass ΔΣDA modulator shown in (a). (E) is a figure which shows the other example of the power spectrum of the secondary multiband path | pass (DELTA) ΣDA modulator shown to (a). (A) is a circuit block diagram of another example of a secondary multiband pass ΔΣDA modulator, and (b) is a diagram showing a signal band center frequency of the secondary multibandpass ΔΣDA modulator shown in (a). (C) is a figure which shows an example of the high-pass element rotation algorithm used with the secondary multiband pass delta-sigma DA modulator shown to (a), (d) is the figure which shows secondary secondary bandpass delta-sigma DA shown to (a). It is a figure which shows an example of the power spectrum of a modulator, (e) is a figure which shows the other example of the power spectrum of the secondary multiband path | pass (DELTA) ΣDA modulator shown to (a). (A) is a circuit block diagram of a secondary complex multiband pass ΔΣDA modulator, and (b) is a diagram showing a signal band in which the noise of the secondary complex multibandpass ΔΣDA modulator shown in (a) is substantially zero. (C) is an equivalent circuit of the second-order complex multiband pass ΔΣDA modulator shown in (a). 1 is a circuit block diagram of a complex multiband pass ΔΣ modulator according to a first embodiment. FIG. FIG. 12 is a diagram illustrating an operation algorithm of the complex multiband pass ΔΣ modulator illustrated in FIG. 11. FIG. 12 is a circuit block diagram showing a specific circuit configuration of the complex multiband pass ΔΣ modulator shown in FIG. 11. (A) is a figure which shows an example of the power spectrum of the complex multiband pass delta-sigma modulator shown in FIG. 11, (b) is the simulation result of the SNDR value with respect to OSR of the complex multiband pass delta-sigma modulator shown in FIG. FIG. FIG. 6 is a circuit block diagram of a complex multiband pass ΔΣ modulator according to a second embodiment. FIG. 16 is a diagram showing an operation algorithm of the complex multiband pass ΔΣ modulator shown in FIG. 15. FIG. 16 is a circuit block diagram showing a specific circuit configuration of the complex multiband pass ΔΣ modulator shown in FIG. 15. (A) is a figure which shows an example of the power spectrum of the complex multiband pass delta-sigma modulator shown in FIG. 15, (b) is the simulation result of the SNDR value with respect to OSR of the complex multiband pass delta-sigma modulator shown in FIG. FIG. FIG. 6 is a circuit block diagram of a complex multiband pass ΔΣ modulator according to a third embodiment. It is a figure explaining the characteristic of the complex multiband pass delta-sigma modulator concerning an embodiment.

  A DA modulator and an AD modulator according to the present invention will be described below with reference to the drawings. However, it should be noted that the technical scope of the present invention is not limited to these embodiments, and extends to equivalents to the invention described in the claims.

  Prior to describing the DA modulator and AD modulator according to the present invention, techniques related to the DA modulator and AD modulator according to the present invention will be described.

  First, a low-pass element rotation algorithm that is a first algorithm of a DWA (Data-Weighted-Averaging) algorithm for a ΔΣ AD modulator and a high-pass element rotation algorithm that is a second algorithm will be described.

  1A is a circuit diagram of a segment current cell type DA converter, and FIG. 1B is a circuit diagram in which elements of the segment current cell type DA converter shown in FIG. 1A are arranged in a ring shape. is there.

The segment current cell type DA converter 300 includes a first current source CS0 to an eighth current source CS7, and a first switch S0 to an eighth switch S7 connected in series to the current source. The first current source CS0 to the eighth current source CS7 are desirably current sources that flow currents having the same magnitude, but when they are mounted on a semiconductor device, the first current source CS7 to the eighth current source CS7 may vary depending on the manufacturing process. The magnitudes of the currents of the source CS0 to the eighth current source CS7 are different. In the example shown in FIG. 1A, the current magnitude of the first current source CS0 is I + e ₀ , the current magnitude of the second current source CS1 is I + e ₁ , and the current magnitude of the eighth current source CS7 is The magnitude is I + e ₇ . In FIG. 1A, e _{0 to} e ₇ are mismatch values, which indicate the nonlinearity of the DA converter.

When current sources are used in order from the first current source CS0 according to the digital signal input to the segment current cell type DA converter 300, the magnitudes of the current values of the first current source CS0 to the eighth current source CS7 are different. To do. For example, since the first current source CS0 and the second current source CS1 are turned on when a digital signal indicating “2” is input, the magnitude of the output current is 2I + (e ₀ + e ₁ ). Further, since the first current source CS0 to the fourth current source CS3 are turned on when a digital signal indicating “4” is input, the magnitude of the output current is 4I + (e ₀ + e ₁ + e ₂ + e ₃ ). Since noise is generated due to the difference in output current depending on the input digital signal, the characteristics deteriorate, and the power spectrum of the segment current cell DA converter 300 becomes flat.

  The segment current cell type DA converter 310 includes a first current source CS0 to an eighth current source CS7 arranged in a ring shape. In the segment current cell type DA converter 310, one of the first current source CS0 to the eighth current source CS7 can be selected in the forward direction or the reverse direction. When any one of the first current source CS0 to the eighth current source CS7 is selected in the forward direction, the first switch S0 to the eighth switch S7 are sequentially turned on, and the first current source CS0 to the eighth current source CS7 are sequentially turned on. select. When selecting any one of the first current source CS0 to the eighth current source CS7 in the reverse direction, the eighth switch S7 to the first switch S0 are sequentially turned on, and the eighth switch S7 to the first switch S0 are sequentially selected. .

  FIG. 2A is a diagram schematically showing a low-pass element rotation algorithm, and FIG. 2B is a diagram showing an example of a power spectrum of a DA converter using the low-pass element rotation algorithm.

  In the low-pass element rotation algorithm, the current source used according to the previously inputted digital signal is stored, and then the current source used according to the inputted digital signal is sequentially selected in the same direction. In the example shown in FIG. 2A, first, when a digital signal indicating “4” is input, the first current source CS0 to the fourth current source CS3 are used. Next, when a digital signal indicating “3” is input, three current sources are sequentially selected in the same direction, and the fifth current source CS4 to the seventh current source CS6 are used. Next, when a digital signal indicating “2” is input, two current sources are sequentially selected in the same direction, and the eighth current source CS7 and the first current source CS0 are used. This is because the first current source CS0 to the eighth current source CS7 are arranged in a ring shape as shown in FIG. 1B, and the eighth current source CS7 and the first current source CS0 are adjacent to each other. Next, when a digital signal indicating “6” is input, six current sources are sequentially selected in the forward direction, and the second current source CS1 to the seventh current source CS6 are used. As described above, in the low-pass element rotation algorithm, by sequentially selecting the current sources to be used in the forward direction, the mismatch between the first current source CS0 to the eighth current source CS7 is as shown in FIG. First-order noise shaping is performed.

  FIG. 3A is a diagram schematically illustrating a high-pass element rotation algorithm, and FIG. 3B is a diagram illustrating an example of a power spectrum of a DA converter using the high-pass element rotation algorithm.

  In the high-pass element rotation algorithm, the current source used in accordance with the previously input digital signal is stored, and then the current source to be used is determined in turn in the opposite direction in accordance with the input digital signal. To do. In the example shown in FIG. 3A, first, when a digital signal indicating “4” is input, the first current source CS0 to the fourth current source CS3 are used. Next, when a digital signal indicating “3” is input, three current sources are sequentially selected in the reverse direction, and the second current source CS1 to the fourth current source CS3 are used. Next, when a digital signal indicating “2” is input, two current sources are sequentially selected in the forward direction, and the second current source CS1 to the third current source CS2 are used. Next, when a digital signal indicating “6” is input, six current sources are sequentially selected in the reverse direction, and the first current source CS0 to the third current source CS2 and the sixth current sources CS5 to eighth. A current source CS7 is used. This is because the first current source CS0 to the eighth current source CS7 are arranged in a ring shape as shown in FIG. 1B, and the first current source CS0 and the eighth current source CS7 are adjacent to each other. As described above, in the high-pass element rotation algorithm, the current sources to be used are alternately selected in the opposite direction sequentially, so that the first current source CS0 to the eighth current source CS7 are connected as shown in FIG. The mismatch is first-order noise shaped.

  4A is a circuit block diagram of the complex bandpass ΔΣDA modulator, FIG. 4B is an internal circuit diagram of the complex resonator shown in FIG. 4A, and FIG. 4C is FIG. It is a figure which shows an example of the power spectrum of the complex resonator shown to (b).

ここで、Ｉ_inは入力信号の同相成分であり、Ｑ_inは入力信号の直交成分であり、Ｉ_outは出力信号の同相成分であり、Ｑ_outは出力信号の直交成分である。また、Ｈ（ｚ）は複素共振器４０１の伝達関数であり、Ｅ_iはノイズの同相成分であり、Ｅ_qはノイズの直交成分である。式（１）において、信号伝達関数ＳＴＦ（ｚ）及びノイズ伝達関数ＮＴＦ（ｚ）はそれぞれ、

で示される。また、複素共振器４０１の伝達関数Ｈ（ｚ）は、

で示される。複素共振器４０１の伝達関数Ｈ（ｚ）が大きくなると、信号伝達関数ＳＴＦ（ｚ）は１に漸近し、ノイズ伝達関数ＮＴＦ（ｚ）は略ゼロになり、複素バンドパスΔΣＤＡ変調器４００の出力信号のノイズを略ゼロにすることができる。 The input / output relationship of the complex bandpass ΔΣDA modulator 400 is shown as follows.

Here, I _in is the in-phase component of the input signal, Q _in is the quadrature component of the input signal, I _out is the in-phase component of the output signal, and Q _out is the quadrature component of the output signal. H (z) is a transfer function of the complex resonator 401, E _i is an in-phase component of noise, and E _q is an orthogonal component of noise. In equation (1), the signal transfer function STF (z) and the noise transfer function NTF (z) are respectively

Indicated by The transfer function H (z) of the complex resonator 401 is

Indicated by When the transfer function H (z) of the complex resonator 401 is increased, the signal transfer function STF (z) is asymptotic to 1, the noise transfer function NTF (z) is substantially zero, and the output of the complex bandpass ΔΣDA modulator 400 The noise of the signal can be made substantially zero.

  FIG. 5A is a circuit block diagram of the second-order complex bandpass ΔΣDA modulator, and FIG. 5B is a diagram showing an example of the power spectrum of the second-order complex bandpass ΔΣDA modulator shown in FIG. It is.

  The second-order complex bandpass ΔΣDA modulator 410 has two complex resonators 411 and 412 connected in series. With such a configuration, the second-order complex bandpass ΔΣDA modulator 410 can increase the sampling frequency, and has an SNR (Signal-to-to-Signal) than the complex bandpass ΔΣDA modulator 400 due to the oversampling effect. The noise ratio is improved.

  FIG. 6A is a circuit block diagram of another example of the complex bandpass ΔΣDA modulator, and FIG. 6B is a diagram showing an operation algorithm of the DA converter shown in FIG. FIG. 6C is a circuit block diagram showing a specific circuit configuration of the complex bandpass ΔΣ AD modulator shown in FIG.

The complex bandpass ΔΣ DA modulator 500 includes a first DA converter 501, a second DA converter 502, a first pointer 511, a second pointer 512, a first input switch 521 to a fourth input switch 524, and a first output. A switch 531 to a fourth output switch 534. The complex bandpass ΔΣDA modulator 500 converts the first digital signal I _in into a first analog signal I _out and converts the second digital signal Q _in into a second analog signal Q _out .

  As shown in FIG. 1B, the first DA converter 501 includes a first current source CS0 to an eighth current source CS7 arranged in a ring shape, and an input digital signal is converted into an analog signal by a low-pass element rotation algorithm. Are converted sequentially. In the second DA converter 502, as shown in FIG. 1B, the first current source CS0 to the eighth current source CS7 are arranged in a ring shape, and the input digital signal is converted into an analog signal by a high-pass element rotation algorithm. Are converted sequentially. The first pointer 511 stores the current source used according to the digital signal previously input to the first DA converter 501, and the second pointer 512 corresponds to the digital signal previously input to the second DA converter 502. Memorize the current source used.

First input switch 521 to the fourth input switch 524 inputs the second digital signal Q _in the first 2DA converter 502 when the first 1DA converter 501 inputs the first digital signal I _in. In this case, the first input switch 521 and the second input switch 522 are turned on, and the third input switch 523 and the fourth input switch 524 are turned off. The first input switch 521 to the fourth input switch 524 inputs the second digital signal Q _in the first 1DA converter 501 when the first 2DA converter 502 inputs the first digital signal I _in. In this case, the first input switch 521 and the second input switch 522 are turned off, and the third input switch 523 and the fourth input switch 524 are turned on. First input switch 521 to the fourth input switch 524 each time the first digital signal I _in and the second digital signal Q _in is inputted, switches the input signal alternately.

The first output switch 531 to the fourth output switch 534 output the second analog signal Q _out from the second DA converter 502 when outputting the first analog signal I _out from the first DA converter 501. In this case, the first output switch 531 and the second output switch 532 are turned on, and the third output switch 533 and the fourth output switch 534 are turned off. The first output switch 531 to the fourth output switch 534 output the second analog signal Q _out from the first DA converter 501 when the first analog signal I _out is output from the second DA converter 502. In this case, the first output switch 531 and the second output switch 532 are turned off, and the third output switch 533 and the fourth output switch 534 are turned on. The first input switch 521 to the fourth input switch 524 alternately switch the output signal each time the first analog signal I _out and the second analog signal Q _out are output.

With reference to FIG. 6B, an operation algorithm of the complex bandpass ΔΣDA modulator 500 will be described. First, “4 + 3j” is input to the complex bandpass ΔΣDA modulator 500. The first input switch 521 to the fourth input switch 524 input “4” as the first digital signal I _in to the first DA converter 501 and “3” as the second digital signal Q _in to the second DA converter 502. input. The 1DA converter 501 converts the first digital signal I _in using a first current source CS0~ fourth current source CS3 indicating "4" into an analog signal. The 2DA converter 502 converts the second digital signal Q _in using a first current source CS0~ third current source CS2 indicating "3" into an analog signal. The first pointer 511 stores the fourth current source CS3, and the second pointer 512 stores the third current source CS2. The first output switch 531 to the fourth output switch 534 output the analog signal indicating “4” converted by the first DA converter 501 as the first analog signal I _out and “3” converted by the second DA converter 502. _Is output as the second analog signal _Qout .

Next, “2 + 5j” is input to the complex bandpass ΔΣDA modulator 500. The first input switch 521 to the fourth input switch 524 input “2” as the first digital signal I _in to the second DA converter 502 and “5” as the second digital signal Q _in to the first DA converter 501. input. The first DA converter 501 uses the first current source CS0 and the fifth current source CS4 to the eighth current source CS7 which are five current sources in the forward direction from the fourth current source CS3 stored in the first pointer 511. Then, the second digital signal I _in indicating “5” is converted into an analog signal. The second DA converter 502 uses the second current source CS1 to the third current source CS2 which are two current sources in the reverse direction from the third current source CS2 stored in the second pointer 512 to set “2”. converting the second digital signal Q _in indicating the analog signal. The first pointer 511 stores the first current source CS1, and the second pointer 512 stores the second current source CS1. The first output switch 531 to the fourth output switch 534 output an analog signal indicating “2” converted by the second DA converter 502 as the first analog signal I _out and “5” converted by the first DA converter 501. _Is output as the second analog signal _Qout .

The complex band-pass ΔΣDA modulator 500, the 1DA converter 501 and a first digital signal I _in and the second digital signal Q _in each of the first 2DA converter 502, a first input switch to alternately input 521 The fourth input switch 524 is controlled to operate. The first DA converter 501 is controlled to apply a low-pass element rotation algorithm, while the second DA converter 502 is controlled to apply a high-pass element rotation algorithm. By adopting such a configuration, the complex bandpass ΔΣ DA modulator 500 can noise-shape noise generated by the non-linearity of the first DA converter 501 and the second DA converter 502.

A complex bandpass ΔΣDA modulator 550 showing a specific circuit configuration of the complex bandpass ΔΣDA modulator 500 includes a first DA converter 501, a second DA converter 502, a first converter control unit 551, and a second conversion. A device controller 552. Complex bandpass ΔΣDA modulator 550 further includes an input selection unit 553 and an output selection unit 554. The first converter control unit 551 sequentially selects a plurality of segment elements of the first DA converter 501 by a low-pass element rotation algorithm according to the input digital signal. The second converter control unit 552 sequentially selects a plurality of segment elements of the second DA converter 502 by a high-pass element rotation algorithm according to the input digital signal. The input selection unit 553 implements the functions of the first input switch 521 to the fourth input switch 524. That is, the input selection unit 553 inputs the second digital signal Q _in the second transducer control unit 552 when the first transducer control unit 551 inputs the first digital signal I _in. Further, the input selection unit 553 inputs the second digital signal Q _in the first transducer control unit 551 when the second transducer control unit 552 inputs the first digital signal I _in. Input selection unit 553, each time the first digital signal I _in and the second digital signal Q _in is inputted, switches the input signal alternately. The output selection unit 554 implements the functions of the first output switch 531 to the fourth output switch 534. The output selection unit 554 outputs the second analog signal Q _out to the second DA converter 502 when outputting the first analog signal I _out from the first DA converter 501. The output selection unit 554 outputs the second analog signal Q _out from the first DA converter 501 when outputting the first analog signal I _out from the second DA converter 502. The output selection unit 554 switches the output signal alternately each time the first analog signal I _out and the second analog signal Q _out are output.

  FIG. 7A is a circuit block diagram illustrating an example of a multiband pass ΔΣ AD modulator, and FIG. 7B is a diagram illustrating an example of a power spectrum of the multiband pass ΔΣ AD modulator illustrated in FIG. . FIG. 7C is a circuit block diagram of another example of the multiband pass ΔΣ AD modulator, and FIG. 7D is an example of the power spectrum of the multiband pass ΔΣ AD modulator shown in FIG. FIG.

であり、マルチバンドパスΔΣＡＤ変調器６００の出力信号Ｙ（ｚ）は、

で示され、マルチバンドパスΔΣＡＤ変調器６００の信号伝達関数ＳＴＦ（ｚ）及びノイズ伝達関数ＮＴＦ（ｚ）はそれぞれ、

で示される。マルチバンドパスΔΣＡＤ変調器６００の信号伝達関数ＳＴＦ（ｚ）が「１」であり、ノイズ伝達関数ＮＴＦ（ｚ）が「０」である複数の信号帯域中心周波数ｆ_nはサンプリング周波数ｆ_sを用いて、図７（ｂ）に示すように、

となる。 The multiband pass ΔΣ AD modulator 600 includes a filter 601, an AD converter 602, and a DA converter 603. The transfer function H (z) of the filter 601 is

The output signal Y (z) of the multiband pass ΔΣ AD modulator 600 is

The signal transfer function STF (z) and noise transfer function NTF (z) of the multiband pass ΔΣ AD modulator 600 are

Indicated by The sampling frequency f _s is used as the plurality of signal band center frequencies f _n in which the signal transfer function STF (z) of the multiband pass ΔΣ AD modulator 600 is “1” and the noise transfer function NTF (z) is “0”. As shown in FIG.

It becomes.

であり、マルチバンドパスΔΣＡＤ変調器６１０の出力信号Ｙ（ｚ）は、

で示され、マルチバンドパスΔΣＡＤ変調器６１０の信号伝達関数ＳＴＦ（ｚ）及びノイズ伝達関数ＮＴＦ（ｚ）はそれぞれ、

で示される。信号伝達関数ＳＴＦ（ｚ）が「１」であり、ノイズ伝達関数ＮＴＦ（ｚ）が「０」である複数の信号帯域中心周波数ｆ_nはサンプリング周波数ｆ_sを用いて、図７（ｄ）に示すように、

となる。 The multiband pass ΔΣ AD modulator 610 includes a filter 611, an AD converter 612, and a DA converter 613. The transfer function H (z) of the filter 611 is

The output signal Y (z) of the multiband pass ΔΣ AD modulator 610 is

The signal transfer function STF (z) and the noise transfer function NTF (z) of the multiband pass ΔΣ AD modulator 610 are

Indicated by A plurality of signal band center frequencies f _n having a signal transfer function STF (z) of “1” and a noise transfer function NTF (z) of “0” are represented in FIG. 7D by using the sampling frequency f _s . As shown

It becomes.

  FIG. 8A is a circuit block diagram of an example of a secondary multiband pass ΔΣDA modulator, and FIG. 8B shows the signal band center frequency of the secondary multiband pass ΔΣDA modulator shown in FIG. FIG. FIG. 8C is a diagram showing an example of a low-pass element rotation algorithm used in the second-order multiband pass ΔΣ DA modulator shown in FIG. 8D is a diagram illustrating an example of the power spectrum of the secondary multiband path ΔΣDA modulator illustrated in FIG. 8A, and FIG. 8E is the secondary multiband path illustrated in FIG. 8A. It is a figure which shows the other example of the power spectrum of a delta-sigma DA modulator.

で示される。 The secondary multiband pass ΔΣ DA modulator 700 includes filters 701 and 702 and a DA converter 703. The DA converter 703 is a segment current cell type DA converter in which elements are arranged in a ring shape as shown in FIG. The output signal A _out of the secondary multiband pass ΔΣDA modulator 700 is

Indicated by

  With reference to FIG. 8C, the low-pass element rotation algorithm used in the second-order multiband pass ΔΣDA modulator corresponding to N = 4, that is, the fourth-order filter will be described. The DA converter 703 has first to fourth pointers, and each of the first to fourth pointers executes a low-pass element rotation algorithm in accordance with the input digital signal.

  First, when a digital signal indicating “4” is input, the first current source CS0 to the fourth current source CS3 are used, and the fourth current source CS3 is stored in the first pointer. Next, when a digital signal indicating “3” is input, the three current sources are sequentially selected, the first current source CS0 to the third current source CS2 are used, and the third current source CS2 is set to the second current source CS2. The pointer memorizes it. Next, when a digital signal indicating “2” is input, the two current sources are sequentially selected, the first current source CS0 and the second current source CS2 are used, and the second current source CS1 is changed to the first current source CS1. 3 pointers are stored. Next, when a digital signal indicating “2” is input, the two current sources are sequentially selected, the first current source CS0 and the second current source CS2 are used, and the second current source CS1 is changed to the first current source CS1. 4 pointers are stored.

  Next, when a digital signal indicating “6” is input, the fifth current source CS4 to the second current are six current sources that are located in the forward direction of the fourth current source CS3 stored in the first pointer. The source CS1 is used and the first pointer stores the second current source CS1. Next, when a digital signal indicating “1” is input, the fourth current source CS3 which is one current source located in the forward direction of the third current source CS2 stored in the second pointer is used, The second pointer stores the fourth current source CS3. Next, when a digital signal indicating “7” is input, the third current source CS2 to the first current are seven current sources positioned in the forward direction of the second current source CS1 stored in the third pointer. The source CS0 is used, and the first pointer stores the first current source CS0. Next, when a digital signal indicating “5” is input, the third current source CS2 to the seventh current are five current sources located in the forward direction of the second current source CS1 stored in the fourth pointer. The source CS6 is used and the fourth pointer stores the seventh current source CS6.

  FIG. 9A is a circuit block diagram of another example of the secondary multiband pass ΔΣDA modulator, and FIG. 9B is a signal band center of the secondary multibandpass ΔΣDA modulator shown in FIG. 9A. It is a figure which shows a frequency. FIG. 9C is a diagram showing an example of a high-pass element rotation algorithm used in the secondary multiband pass ΔΣ DA modulator shown in FIG. 9D is a diagram showing an example of the power spectrum of the secondary multiband path ΔΣDA modulator shown in FIG. 9A, and FIG. 9E is the secondary multiband path shown in FIG. 9A. It is a figure which shows the other example of the power spectrum of a delta-sigma DA modulator.

で示される。 The secondary multiband pass ΔΣ DA modulator 710 includes filters 711 and 712 and a DA converter 713. The DA converter 713 is a segment current cell type DA converter in which elements are arranged in a ring shape as shown in FIG. The output signal A _out of the secondary multiband pass ΔΣDA modulator 710 is

Indicated by

  With reference to FIG. 9C, a high-pass element rotation algorithm used in the second-order multiband pass ΔΣDA modulator corresponding to N = 4, that is, a fourth-order filter will be described. The DA converter 713 has first to fourth pointers, and each of the first to fourth pointers executes a high-pass element rotation algorithm in accordance with the input digital signal.

  First, when a digital signal indicating “4” is input, the first current source CS0 to the fourth current source CS3 are used, and the fourth current source CS3 is stored in the first pointer. Next, when a digital signal indicating “3” is input, the three current sources are sequentially selected, the first current source CS0 to the third current source CS2 are used, and the third current source CS2 is set to the second current source CS2. The pointer memorizes it. Next, when a digital signal indicating “2” is input, the two current sources are sequentially selected, the first current source CS0 and the second current source CS2 are used, and the second current source CS1 is changed to the first current source CS1. 3 pointers are stored. Next, when a digital signal indicating “2” is input, the two current sources are sequentially selected, the first current source CS0 and the second current source CS2 are used, and the second current source CS1 is changed to the first current source CS1. 4 pointers are stored.

  Next, when a digital signal indicating “6” is input, the first current source CS0 to the fourth current are six current sources located in the reverse direction from the fourth current source CS3 stored in the first pointer. The source CS3 and the seventh current source CS6 to the eighth current source CS7 are used. The first pointer stores the sixth current source CS5. Next, when a digital signal indicating “1” is input, the third current source CS2 which is one current source located in the reverse direction from the third current source CS2 stored in the second pointer is used, The second pointer stores the third current source CS2. Next, when a digital signal indicating “7” is input, the first current source CS0 to the second current are seven current sources located in the reverse direction from the second current source CS1 stored in the third pointer. The source CS1 and the fourth current source CS3 to the eighth current source CS7 are used. Then, the fourth pointer stores the fourth current source CS3. Next, when a digital signal indicating “5” is input, the first current source CS0 to the second current are five current sources located in the reverse direction from the second current source CS1 stored in the fourth pointer. The source CS1 and the sixth current source CS5 to the eighth current source CS7 are used. The fourth pointer stores the sixth current source CS5.

  The complex bandpass ΔΣ AD modulator described with reference to FIGS. 4 to 6 uses a first-order complex filter. In addition, the multiband pass ΔΣ AD modulator described with reference to FIGS. 7 to 9 filters an actual signal with an Nth-order filter, and does not use a complex filter. Based on these ΔΣ AD modulators, the inventors of the present invention invented a complex multiband pass ΔΣ AD modulator and a DWA algorithm applied to the complex multiband pass ΔΣ AD modulator.

  FIG. 10A is a circuit block diagram of a second-order complex multiband pass ΔΣDA modulator, and FIG. 10B shows that the noise of the second-order complex multibandpass ΔΣDA modulator shown in FIG. It is a figure which shows the signal band which becomes. FIG. 10C is an equivalent circuit of the second-order complex multiband pass ΔΣDA modulator shown in FIG.

で示される。ここで、Ｉ_inは入力信号の同相成分であり、Ｑ_inは入力信号の直交成分であり、Ｉ_outは出力信号の同相成分であり、Ｑ_outは出力信号の直交成分である。また、Ｅ_Iは量子化ノイズの同相成分であり、Ｅ_Qは量子化ノイズの直交成分であり、δ_IはＤＡ変換器のノイズの同相成分であり、δ_QはＤＡ変換器のノイズの直交成分である。 The output signal (I _out + jQ _out ) of the secondary ΔΣ DA modulator 100 is

Indicated by Here, I _in is the in-phase component of the input signal, Q _in is the quadrature component of the input signal, I _out is the in-phase component of the output signal, and Q _out is the quadrature component of the output signal. E _I is the in-phase component of the quantization noise, E _Q is the quadrature component of the quantization noise, δ _I is the in-phase component of the DA converter noise, and δ _Q is the quadrature of the DA converter noise. It is an ingredient.

The equivalent circuit 101 of the second-order ΔΣ DA modulator 100 includes a first DA converter 11, a second DA converter 12, a complex resonator 102, and a complex notch 103. In the equivalent circuit 101 of the second-order ΔΣ DA modulator 100, the in-phase component δ _I of the DA converter noise and the quadrature component δ _Q of the DA converter noise affect the complex notch 103. The equivalent circuit 101 of the second-order ΔΣ DA modulator 100 cannot be realized because the digital signals input to the first DA converter 11 and the second DA converter 12 may be infinite.

  FIG. 11 is a circuit block diagram of the complex multiband pass ΔΣ modulator according to the first embodiment.

  The ΔΣ DA modulator 1 includes a first DA converter 11, a second DA converter 12, a first DAC first pointer 21, a first DAC second pointer 22, a second DAC first pointer 31, and a second DAC second pointer 32. And have. The ΔΣ DA modulator 1 further includes a first input switch 41 to a fourth input switch 44 and a first output switch 51 to a fourth output switch 54.

  The first DA converter 11 has the same function and configuration as the first DA converter 501 described with reference to FIG. 6, and the second DA converter 12 is the same as the second DA converter 502 described with reference to FIG. It has various functions and configurations. That is, in the first DA converter 11, as shown in FIG. 1B, the first current source CS0 to the eighth current source CS7 are arranged in a ring shape, and the input digital signal is converted by a low-pass element rotation algorithm. Convert to analog signal sequentially. In the second DA converter 12, the first current source CS0 to the eighth current source CS7 are arranged in a ring shape as shown in FIG. 1B, and the input digital signal is converted into an analog signal by a high-pass element rotation algorithm. Are converted sequentially.

  Each of the first DAC first pointer 21 and the first DAC second pointer 22 stores a current source used in accordance with the digital signal previously input to the first DA converter 11. Each of the second DAC first pointer 31 and the second DAC second pointer 32 stores a current source used in accordance with the digital signal previously input to the second DA converter 12.

First input switch 41 to a fourth input switch 44 inputs the second digital signal Q _in the first 2DA transducer 12 when the first 1DA converter 11 inputs the first digital signal I _in. In this case, the first input switch 41 and the second input switch 42 are turned on, and the third input switch 43 and the fourth input switch 44 are turned off. The first input switch 41 to a fourth input switch 44 inputs the second digital signal Q _in the first 1DA converter 11 when the first 2DA converter 12 inputs the first digital signal I _in. In this case, the first input switch 41 and the second input switch 42 are turned off, and the third input switch 43 and the fourth input switch 44 are turned on. First input switch 41 to a fourth input switch 44 is, each time the first digital signal I _in and the second digital signal Q _in is 2 to input, switches the input signal alternately. That is, the first input switch 41 to the fourth input switch 44 input two first digital signals I _in to the first DA converter 11 and input two second digital signals Q _in to the second DA converter 12. When input, the switching operation is executed. After executing the switching operation, the first input switch 41 to the fourth input switch 44 input the two first digital signals I _in to the second DA converter 12 and input the two second digital signals Q _in to the second. The signal is input to the 1DA converter 11 and the switching operation is executed again.

The first output switch 51 to the fourth output switch 54 output the second analog signal Q _out from the second DA converter 12 when outputting the first analog signal I _out from the first DA converter 11. In this case, the first output switch 51 and the second input switch 52 are turned on, and the third output switch 53 and the fourth output switch 54 are turned off. The first output switch 51 to the fourth output switch 54 output the second analog signal Q _out from the first DA converter 11 when outputting the first analog signal I _out from the second DA converter 12. In this case, the first output switch 51 and the second input switch 52 are turned off, and the third output switch 53 and the fourth output switch 54 are turned on. The first output switch 51 to the fourth output switch 54 alternately switch the output signals every time two pairs of the first analog signal I _out and the second analog signal Q _out are output. That is, the first output switch 51 to the fourth output switch 54 output the two first analog signals I _out from the first DA converter 11 and the two second analog signals Q _out from the second DA converter 12. When output, the switching operation is executed. After executing the switching operation, the first output switch 51 to the fourth output switch 54 output the two first analog signals I _out from the second DA converter 12 and the two second analog signals Q _out to the second output. The data is output from the 1DA converter 11, and the switching operation is executed again.

  FIG. 12 is a diagram illustrating an operation algorithm of the ΔΣ DA modulator 1.

First, “4 + 2j” is input to the ΔΣDA modulator 1. The first input switch 41 to the fourth input switch 44 input “4” as the first digital signal I _in to the first DA converter 11 and “2” as the second digital signal Q _in to the second DA converter 12. input. The 1DA converter 11 converts the first digital signal I _in using a first current source CS0~ fourth current source CS3 indicating "4" into an analog signal. The 2DA converter 12 converts the second digital signal Q _in using a first current source CS0~ second current source CS1 indicating "2" to the analog signal. The first DAC first pointer 21 stores the fourth current source CS3, and the second DAC first pointer 31 stores the second current source CS1. The first output switch 51 to the fourth output switch 54 output an analog signal indicating “4” converted by the first DA converter 11 as the first analog signal I _out and “2” converted by the second DA converter 12. _Is output as the second analog signal _Qout .

Next, “3 + 2j” is input to the ΔΣDA modulator 1. The first input switch 41 to the fourth input switch 44 input “3” as the first digital signal I _in to the first DA converter 11 and “2” as the second digital signal Q _in to the second DA converter 12. input. The first DA converter 11 converts the first digital signal I _in indicating “3” into an analog signal using the first current source CS0 to the third current source CS2. The 2DA converter 12 converts the second digital signal Q _in using a first current source CS0~ second current source CS1 indicating "2" to the analog signal. The first DAC second pointer 22 stores the third current source CS2, and the second DAC second pointer 32 stores the second current source CS1. The first output switch 51 to the fourth output switch 54 output an analog signal indicating “3” converted by the first DA converter 11 as the first analog signal I _out and “2” converted by the second DA converter 12. _Is output as the second analog signal _Qout .

Next, “2 + 6j” is input to the ΔΣ DA modulator 1. The first input switch 41 to the fourth input switch 44 input “2” as the first digital signal I _in to the second DA converter 12 and “6” as the second digital signal Q _in to the first DA converter 11. input. The first DA converter 11 includes a first current source CS0 to a second current source CS1 and a fifth current source CS4 to an eighth current source located in the forward direction from the fourth current source CS3 stored in the first DAC first pointer 21. The second digital signal I _in indicating “6” is converted into an analog signal using CS7. The second DA converter 12 uses the first current source CS1 to the second current source CS1 that are two current sources in the reverse direction from the second current source CS1 stored in the second DAC first pointer 31 to “2”. the second digital signal Q _in indicating a "into an analog signal. The first DAC first pointer 21 stores the second current source CS1, and the second DAC first pointer 31 stores the first current source CS0. The first output switch 51 to the fourth output switch 54 output the analog signal indicating “2” converted by the second DA converter 12 as the first analog signal I _out and “6” converted by the first DA converter 11. _Is output as the second analog signal _Qout .

Next, “2 + 1j” is input to the ΔΣ DA modulator 1. The first input switch 41 to the fourth input switch 44 input “2” as the first digital signal I _in to the second DA converter 12, and “1” as the second digital signal Q _in to the first DA converter 11. input. The 1DA converter 11, the 1DAC fourth current source CS3 second digital signal I _in the analog signal indicating "1" by using the position from the third current source CS2 in the forward direction stored in the second pointer 22 Convert to The second DA converter 12 uses the first current source CS <b> 1 to the second current source CS <b> 1 that are two current sources in the reverse direction from the second current source CS <b> 1 stored in the second DAC second pointer 32. the second digital signal Q _in indicating a "into an analog signal. The first DAC second pointer 22 stores the fourth current source CS3, and the second DAC second pointer 32 stores the first current source CS0. The first output switch 51 to the fourth output switch 54 output an analog signal indicating “2” converted by the second DA converter 12 as the first analog signal I _out and “1” converted by the first DA converter 11. _Is output as the second analog signal _Qout .

A first digital signal I _in and the second digital signal Q _in each and the 1DA converter 11 to a 2DA transducer 12, operates the first input switch 41 to a fourth input switch 44 so as to alternately input two pairs To control. Further, the first 1DA converter 11 to the analog signal converted by the first 2DA converter 12 as Hendai 1 digital signals I _in and the second digital signal Q _in, so as to alternately output two pairs the first output switch 51 Control the fourth output switch 54 to operate. The 1DA converter 11, converting the first digital signal I _in the two analog signals, and converts the second digital signal Q _in the two analog signals. The 2DA converter 12, when the first 1DA converter 11 converts the first digital signal I _in the analog signal and converts the second digital signal Q _in the analog signal. Further, the 2DA converter 12, when the first 1DA converter 11 converts the second digital signal Q _in the analog signal and converts the first digital signal I _in the analog signal.

  FIG. 13 is a circuit block diagram showing a specific circuit configuration of the ΔΣ DA modulator 1.

  The ΔΣ DA modulator 1 includes a first DA converter 11, a second DA converter 12, a first converter control unit 13, a second converter control unit 14, an input selection unit 15, and an output selection unit 16. Have.

The first converter control unit 13 uses the first DAC first pointer 21 and the first DAC second pointer 22 to generate a plurality of segment elements of the first DA converter 11 using a low-pass element rotation algorithm according to an input digital signal. Are selected in sequence. The second converter control unit 14 uses the second DAC first pointer 31 and the second DAC second pointer 32 to perform a plurality of segment elements of the second DA converter 502 by a high-pass element rotation algorithm according to the input digital signal. Are selected in sequence. The input selection unit 15 realizes the functions of the first input switch 41 to the fourth input switch 44. That is, the input selecting section 15 inputs the second digital signal Q _in the first 2DA transducer 12 when the first 1DA converter 11 inputs the first digital signal I _in. The input selector 15 inputs the second digital signal Q _in the first 1DA converter 11 when the first 2DA converter 12 inputs the first digital signal I _in. Input selector 15, each time the first digital signal I _in and the second digital signal Q _in is 2 to input, switches the input signal alternately. The output selection unit 16 realizes the functions of the first output switch 51 to the fourth output switch 54. The output selection unit 16 outputs the second analog signal Q _out to the second DA converter 12 when outputting the first analog signal I _out from the first DA converter 11. The output selection unit 16 outputs the second analog signal Q _out from the first DA converter 11 when outputting the first analog signal I _out from the second DA converter 12. The output selection unit 16 switches the output signal alternately each time two pairs of the first analog signal I _out and the second analog signal Q _out are output.

  FIG. 14A is a diagram illustrating an example of the power spectrum of the ΔΣDA modulator 1. FIG. 14B is a diagram showing a simulation result of a value of SNDR (Signal-to-noise and distortion ratio) with respect to the OSR (Over sampling Ratio) of the ΔΣ DA modulator 1. In FIG. 14B, squares indicate cases where the DWA algorithm is not applied, and diamonds indicate simulation results of the ΔΣDA modulator 1 to which the DWA algorithm is applied.

  As shown in FIG. 14A, the ΔΣ DA modulator 1 has reduced noise in the signal band. Further, as shown in FIG. 14B, the ΔΣDA modulator 1 can obtain a better SNDR than the case where the DWA algorithm is not applied.

  FIG. 15 is a circuit block diagram of a complex multiband pass ΔΣ modulator according to the second embodiment.

  The ΔΣ DA modulator 2 includes a first DA converter 11, a second DA converter 12, a first DAC first pointer 21 to a first DAC fourth pointer 24, and a second DAC first pointer 31 to a second DAC fourth pointer 34. Have. The ΔΣ DA modulator 1 further includes a first input switch 61 to a fourth input switch 64 and a first output switch 71 to a fourth output switch 74. The ΔΣDA modulator 2 is different from the ΔΣDA modulator 1 in that it includes a first DAC third pointer 23 and a first DAC fourth pointer 24 in addition to the first DAC first pointer 21 and the first DAC second pointer 22. . The ΔΣDA modulator 2 includes a second DAC third pointer 33 and a second DAC fourth pointer 34 in addition to the second DAC first pointer 31 and the second DAC second pointer 32. Furthermore, it is different. The ΔΣDA modulator 2 is further different from the ΔΣDA modulator 1 in that the first input switch 61 to the fourth input switch 64 are arranged instead of the first input switch 41 to the fourth input switch 44. Further, the ΔΣDA modulator 2 is further different from the ΔΣDA modulator 1 in that the first output switch 71 to the fourth output switch 74 are arranged instead of the first output switch 51 to the fourth output switch 54.

  The first DAC third pointer 23 and the first DAC fourth pointer 24 each store a current source used according to the digital signal previously input to the first DA converter 11. Each of the second DAC third pointer 33 and the second DAC fourth pointer 34 stores a current source used according to the digital signal previously input to the second DA converter 12.

The first input switch 61 to the fourth input switch 64 are different from the first input switch 41 to the fourth input switch 44 in the cycle of alternately switching input signals. First input switch 61 to the fourth input switch 64 is not in every first digital signal I _in and the second digital signal Q _in is 2 versus input, the first digital signal I _in and the second digital signal Q _in The input signal is alternately switched every time four pairs are input. That is, the first input switch 61 to the fourth input switch 64 input the four first digital signals I _in to the first DA converter 11 and the four second digital signals Q _in to the second DA converter 12. When input, the switching operation is executed. After executing the switching operation, the first input switch 61 to the fourth input switch 64 input the four first digital signals I _in to the second DA converter 12 and the four second digital signals Q _in to the first. The signal is input to the 1DA converter 11 and the switching operation is executed again.

The first output switch 71 to the fourth output switch 74 are different from the first output switch 51 to the fourth output switch 54 in the cycle of alternately switching input signals. The first output switch 71 to the fourth output switch 74 alternately switch the output signals every time four pairs of the first analog signal I _out and the second analog signal Q _out are output. That is, the first output switch 71 to the fourth output switch 74 output the four first analog signals I _out from the first DA converter 11 and the four second analog signals Q _out from the second DA converter 12. When output, the switching operation is executed. After executing the switching operation, the first output switch 71 to the fourth output switch 74 output the four first analog signals I _out from the second DA converter 12 and the four second analog signals Q _out to the second output. The data is output from the 1DA converter 11, and the switching operation is executed again.

  FIG. 16 is a diagram illustrating an operation algorithm of the ΔΣ DA modulator 2.

In the ΔΣ DA modulator 2, first input switches 41 to 41 are configured to alternately input four pairs of the first digital signal I _in and the second digital signal Q _in to the first DA converter 11 and the second DA converter 12, respectively. The fourth input switch 44 is controlled to operate. Further, the first 1DA converter 11 to the analog signal converted by the first 2DA converter 12 as Hendai 1 digital signals I _in and the second digital signal Q _in, so as to alternately output every four pairs first output switch 51 Control the fourth output switch 54 to operate. The 1DA converter 11 converts the four first digital signal I _in is converted into an analog signal, the four second digital signal Q _in the analog signal. The 2DA converter 12, when the first 1DA converter 11 converts the first digital signal I _in the analog signal and converts the second digital signal Q _in the analog signal. Further, the 2DA converter 12, when the first 1DA converter 11 converts the second digital signal Q _in the analog signal and converts the first digital signal I _in the analog signal.

  FIG. 17 is a circuit block diagram showing a specific circuit configuration of the ΔΣDA modulator 2.

  The ΔΣ DA modulator 1 includes a first DA converter 11, a second DA converter 12, a first converter control unit 17, a second converter control unit 18, an input selection unit 19, and an output selection unit 20. Have.

The first converter control unit 17 uses the four pointers to sequentially select a plurality of segment elements of the first DA converter 11 by a low-pass element rotation algorithm according to the input digital signal. The second converter control unit 18 uses the four pointers to sequentially select a plurality of segment elements of the second DA converter 502 by a high-pass element rotation algorithm according to the input digital signal. The input selection unit 19 realizes the functions of the first input switch 61 to the fourth input switch 64. That is, the input selecting section 19 inputs the second digital signal Q _in the first 2DA transducer 12 when the first 1DA converter 11 inputs the first digital signal I _in. The input selector 15 inputs the second digital signal Q _in the first 1DA converter 11 when the first 2DA converter 12 inputs the first digital signal I _in. Input selection unit 19, each time the first digital signal I _in and the second digital signal Q _in is 4 vs. input, switches the input signal alternately. The output selection unit 20 realizes the functions of the first output switch 71 to the fourth output switch 74. The output selection unit 20 outputs the second analog signal Q _out to the second DA converter 12 when outputting the first analog signal I _out from the first DA converter 11. The output selection unit 20 outputs the second analog signal Q _out from the first DA converter 11 when outputting the first analog signal I _out from the second DA converter 12. The output selection unit 20 alternately switches the output signal every time four pairs of the first analog signal I _out and the second analog signal Q _out are output.

  FIG. 18A is a diagram illustrating an example of the power spectrum of the ΔΣ DA modulator 2, and FIG. 18B is a diagram illustrating an example of the power spectrum of the ΔΣ DA modulator to which the DWA algorithm is not applied. FIG. 18C is a diagram illustrating a simulation result of a value of SNDR (Signal-to-noise and distortion ratio) with respect to the OSR (Over sampling Ratio) of the ΔΣ DA modulator 2. In FIG. 18 (c), squares indicate cases where the DWA algorithm is not applied, and diamonds indicate simulation results of the ΔΣDA modulator 1 to which the DWA algorithm is applied.

  As shown in FIG. 18A, the ΔΣDA modulator 2 has reduced noise in the signal band. On the other hand, as shown in FIG. 18B, in the ΔΣDA modulator to which the DWA algorithm is not applied, a lot of noise is generated in the signal band. As shown in FIG. 18C, the ΔΣDA modulator 1 can obtain a good SNDR compared to the case where the DWA algorithm is not applied.

  FIG. 19 is a circuit block diagram of a complex multiband pass ΔΣ modulator according to the third embodiment.

  The ΔΣ AD modulator 200 includes a ΔΣ DA modulator 201, a first AD converter 211, a second AD converter 212, a first subtractor 221, a second subtractor 222, and a complex multiband pass filter 230.

The ΔΣDA modulator 201 has the same configuration and function as the ΔΣDA modulator 1 or 2. The ΔΣ DA modulator 201 DA-modulates the first digital signal I _out and outputs it as a first feedback signal to the first subtractor 221, and DA-modulates the second digital signal Q _out and outputs the second feedback signal as a second feedback signal. 2 is output to the subtracter 222. The 1AD converter 211 AD converts the signal complex multi-band pass filter 230 has filtered first digital signals I _out, the second 2AD transducer 212 signals the complex multi-band pass filter 230 has filtered the second digital signal Q AD conversion to _out . The first subtractor 221 subtracts the first feedback signal output from the ΔΣDA modulator 201 from the first analog signal I _in, the second feedback signal a second subtractor 222 output from ΔΣDA modulator 201 second It is subtracted from the analog signal Q _in.

  The complex multiband pass filter 230 is a filter having an Nth order signal band. When the ΔΣ DA modulator 1 is used as the ΔΣ DA modulator 201, a filter having a secondary signal band is used as the complex multiband pass filter 230. When the ΔΣDA modulator 2 is used as the ΔΣDA modulator 201, a filter having a fourth-order signal band is used as the complex multiband pass filter 230.

In the ΔΣ DA modulator 1, the first converter control unit 13 uses the two pointers corresponding to each of the two input digital signals to change the segment elements of the first DA converter 11 by a low-pass element rotation algorithm. Select sequentially. Further, the second converter control unit 14 sequentially selects the segment elements of the second DA converter 12 by the high-pass element rotation algorithm using the two pointers corresponding to the two input digital signals. The input selector 15 alternately selects the first digital signal I _in and the second digital signal Q _in every two, and the output selector 16 selects the first analog signal I _out and the second analog signal Q _out . Are alternately selected every two.

In the ΔΣ DA modulator 2, the first converter control unit 17 uses the four pointers corresponding to each of the four input digital signals to perform segmentation of the first DA converter 11 using a low-pass element rotation algorithm. Elements are selected sequentially. Further, the second converter control unit 18 sequentially selects the segment elements of the second DA converter 12 by the high-pass element rotation algorithm using the four pointers corresponding to the four input digital signals. The input selection unit 19 alternately selects the first digital signal I _in and the second digital signal Q _in every four, and the output selection unit 20 outputs the first analog signal I _out and the second analog signal Q _out . Are alternately selected every four.

  Each of the ΔΣ DA modulators 1 and 2 has such a configuration, thereby enabling complex multiband pass ΔΣ modulation and reducing the performance required for the analog filter disposed at the subsequent stage of the ΔΣ DA modulator 1. Can do.

As shown in FIG. 10B, the signal band of the ΔΣ DA modulator 1 is f _n / f _s = −3 / 8 and 1/8, and the signal band of the ΔΣ DA modulator 2 is f _n / f _s = −. 7/16, -3/16, 1/16 and 5/16. The ΔΣDA modulators 1 and 2 have different absolute values in the positive and negative signal bands. On the other hand, as shown in FIGS. 8B and 9B, the signal band of the secondary multiband pass ΔΣDA modulator 700 is f _n / f _s = ± 1/2, and the secondary multiband pass ΔΣDA. The signal band of the modulator 710 is f _n / f _s = ¼, and the absolute value is the same in the positive and negative signal bands. In the ΔΣ DA modulators 1 and 2, the absolute values are different between the positive and negative signal bands, and the signal band can be used effectively. In addition, the ΔΣDA modulators 1 and 2 can realize a good noise spread in the vicinity of the signal band.

  Further, as shown in FIG. 20, in the ΔΣDA modulators 1 and 2, since the absolute value of the power spectrum can be reduced by using multi-bit, the cutoff characteristic required for the analog filter disposed in the subsequent stage. Is reduced.

  In the ΔΣ DA modulator 1, two signals are input / output to / from the first DA converter 11 and the second DA converter 12, and in the ΔΣ DA modulator 2, the signals are input / output to the first DA converter 11 and the second DA converter 12. Switch four by four. However, the ΔΣ DA modulator may be configured to alternately switch the signals input to and output from the first DA converter 11 and the second DA converter 12 every N which is an integer of 2 or more.

  When the signals input / output to / from the first DA converter 11 and the second DA converter 12 are alternately switched every N, the first converter control unit 13 and the second converter control unit 14 N pointers corresponding to each of the N digital signals are configured.

  Each of the first DA converter 11 and the second DA converter 12 has a structure in which the first current source CS0 to the eighth current source CS7 are arranged in a ring shape as shown in FIG. Instead of CS0 to eighth current source CS7, a voltage drive type structure having eight voltage sources may be used. Further, the number of current sources or voltage sources can be selected as appropriate according to the accuracy of the DA converter.

  The first converter control units 13 and 17 select one or more current sources in the forward direction from current sources adjacent to each other in the forward direction of the current sources indicated by the first DAC first pointer 21 to the first DAC fourth pointer 24. . However, the first converter control units 13 and 17 may be configured to select one or more current sources in the forward direction, including the current sources indicated by the first DAC first pointer 21 to the first DAC fourth pointer 24, respectively. .

  The second converter control units 14 and 18 select one or a plurality of current sources including the current sources indicated by the second DAC first pointer 31 to the second DAC fourth pointer 34 in the forward direction or the reverse direction. However, the second converter control units 14 and 18 select one or a plurality of current sources from current sources adjacent to each other in the forward direction or the reverse direction of the current sources indicated by the first DAC first pointer 21 to the first DAC fourth pointer 24, respectively. A configuration may be selected.

1, 2, 201 ΔΣ DA modulator 11 First DA converter 12 Second DA converter 13, 17 First converter control unit 14, 18 Fourth converter control unit 15, 19 Input selection unit 16, 20 Output selection unit 21- 24 1st DAC 1st pointer-1st DAC 4th pointer 31-34 2nd DAC 1st pointer-2nd DAC 4th pointer 41-44, 61-64 1st input switch-4th input switch 51-54, 71-74 1st 1 output switch to 4th output switch 200 ΔΣ AD modulator 211 1st AD converter 212 2nd AD converter 230 complex multiband pass filter

Claims (7)

A ΔΣDA modulator that DA-modulates a first digital signal to a first analog signal and DA-modulates a second digital signal orthogonal to the first digital signal to a second analog signal orthogonal to the first analog signal; ,
A first DA converter and a second DA converter each having a plurality of segment elements and converting a digital signal into an analog signal;
A first converter control unit for controlling the first DA converter;
A second converter control unit for controlling the second DA converter;
When the first digital signal is input to the first converter controller, the second digital signal is input to the second converter controller, and the second digital signal is input to the first converter controller. An input selection unit for inputting the first digital signal to the second converter control unit,
The second DA signal is output from the second DA converter when the first analog signal is output from the first DA converter, and the second DA signal is output when the second analog signal is output from the first DA converter. An output selection unit that outputs the first analog signal from a converter;
The input selection unit alternately inputs the first digital signal and the second digital signal to the first converter control unit and the second converter control unit every N that is an integer of 2 or more,
The output selection unit alternately outputs the first analog signal and the second analog signal from the first converter control unit and the second converter control unit every N times,
The first converter control unit has N pointers corresponding to each of the N digital signals to be input, and the first DA converter using a low-pass element rotation algorithm using the N pointers Select the segment elements in order,
The second converter control unit has N pointers corresponding to each of the N digital signals to be input, and the second DA converter using a high-pass element rotation algorithm using the N pointers Sequentially select the segment elements of
A ΔΣDA modulator characterized by that. The first converter control unit includes a first DAC first pointer to a first DAC Nth pointer, each of which is an N number of pointers indicating a plurality of segment elements of the first DA converter. The converter sequentially uses the first DAC first pointer to the first DAC Nth pointer each time a digital signal is input,
The second converter control unit includes a second DAC first pointer to a second DAC Nth pointer, each of which is an N number of pointers indicating a plurality of segment elements of the second DA converter. 2. The ΔΣ DA modulator according to claim 1, wherein the converter sequentially uses the second DAC first pointer to the second DAC Nth pointer each time a digital signal is input. The first converter controller is
Based on the input digital signal, determine the number of segment elements to select,
Selecting the determined number of segment elements located in the forward direction of the segment elements of the first DA converter indicated by the first DAC Nth pointer;
The ΔΣ DA modulator according to claim 2, wherein a segment element of the first DA converter indicated by the first DAC Nth pointer is changed based on the selected segment element. The first DA converter has M segment elements from a first segment element to an Mth segment element,
4. The ΔΣ DA modulator according to claim 3, wherein the first converter control unit selects the first segment element next when the first converter control unit sequentially selects the first segment element in the forward direction. 5. The second converter controller is
Based on the input digital signal, determine the number of segment elements to select,
Selecting the determined number of segment elements located in the forward or reverse direction of the segment elements of the second DA converter indicated by the second DAC N pointer;
The segment element of the second DA converter indicated by the second DAC N pointer is changed based on the selected segment element,
When the second converter controller selects a segment element located in the forward direction of the segment element indicated by the second DAC N pointer, the second DAC N pointer is used when the second DAC N pointer is used next time. A segment element located in the opposite direction of the segment element of the second DA converter indicated by
When the second converter control unit selects a segment element located in a direction opposite to the segment element indicated by the second DAC N pointer, the second DAC N pointer is used when the second DAC N pointer is used next time. The delta-sigma DA modulator as described in any one of Claims 2-4 which selects the segment element located in the forward direction of the segment element of the said 2nd DA converter which shows. The second DA converter has M segment elements from a first segment element to an Mth segment element,
When the second converter control unit sequentially selects the M segment element in the forward direction, the second converter control unit selects the first segment element and further selects the first segment element in the reverse direction. 6. The ΔΣ DA modulator according to claim 5, wherein the M-th segment element is selected when further selecting in the reverse direction when sequentially selected. A ΔΣ AD modulator that AD-modulates a first analog signal into a first digital signal and AD-modulates a second analog signal orthogonal to the first analog signal into a second digital signal orthogonal to the first digital signal; ,
A DA modulator that DA-modulates the first digital signal into a first feedback signal and DA-modulates the second digital signal into a second feedback signal;
A first subtractor for subtracting the first feedback signal from the first analog signal;
A second subtracter for subtracting the second feedback signal from the second analog signal;
A complex multi-band pass filter for filtering output signals of the first subtractor and the second subtractor;
A first AD converter that AD converts the signal filtered by the complex multi-bandpass filter into the first digital signal;
A second AD converter that AD converts the signal filtered by the complex multi-bandpass filter into the second digital signal;
The DA modulator is a ΔΣ DA modulator according to any one of claims 1 to 6.
A ΔΣ AD modulator characterized by the above.

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