JP2015095473A - Electronic component module - Google Patents

Electronic component module Download PDF

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JP2015095473A
JP2015095473A JP2013232123A JP2013232123A JP2015095473A JP 2015095473 A JP2015095473 A JP 2015095473A JP 2013232123 A JP2013232123 A JP 2013232123A JP 2013232123 A JP2013232123 A JP 2013232123A JP 2015095473 A JP2015095473 A JP 2015095473A
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recess
electronic component
conductive member
component module
copper plate
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稔 篠原
Minoru Shinohara
稔 篠原
中村　直樹
Naoki Nakamura
直樹 中村
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Aisin Corp
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Aisin Seiki Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To provide an electronic component module in which contact failure is hard to occur even when thermal shock is applied thereto.SOLUTION: An electronic component module 1 includes: an element 10; a conductive member 20 brazed to the element 10; and a placement surface 30 which is opposed to the element 10 out of the surface having the conductive member 20 and has a recess 60 opened to the side of the element 10. On the placement surface 30 which is the surface to which the element 10 in a copper plate 21 is soldered, a groove-shaped hollow opened toward the placement surface 30 is formed.

Description

本発明は、樹脂内に素子が封入された電子部品モジュールに関する。   The present invention relates to an electronic component module in which an element is enclosed in a resin.

従来、回路素子を樹脂内に封止した半導体モジュールが利用されてきた。この種の技術として下記に出展を示す特許文献１及び２に記載のものがある。   Conventionally, a semiconductor module in which a circuit element is sealed in a resin has been used. As this type of technology, there are those described in Patent Documents 1 and 2 that exhibit the following.

特許文献１に記載の半導体モジュールは、回路素子を搭載するための回路パターンが形成されたリードフレームと、回路素子及びリードフレームの回路素子搭載面を覆い、且つ、リードフレームの回路素子非搭載面である下面と同じ高さの下面を有する成形樹脂と、リードフレームの回路素子非搭載面である下面及び成形樹脂の下面を覆うように溶射されるセラミックス絶縁層と、を備えて構成される。   The semiconductor module described in Patent Document 1 covers a lead frame on which a circuit pattern for mounting circuit elements is formed, a circuit element and a circuit element mounting surface of the lead frame, and a circuit element non-mounting surface of the lead frame. And a ceramic insulating layer that is sprayed so as to cover the lower surface of the lead frame that is not mounted on the circuit element and the lower surface of the molding resin.

特許文献２に記載の半導体モジュールは、電気絶縁性且つ熱伝導性を有する絶縁層と、当該絶縁層の一面に設けられた金属製のリードフレームとを備えている。リードフレームには素子搭載部がパターニングされ、当該素子搭載部に発熱する回路素子が搭載される。絶縁層の一方の面の側はリードフレーム及び回路素子が樹脂によって封止され、絶縁層の他方の面の側は樹脂から露出させて放熱を行うように構成される。   The semiconductor module described in Patent Document 2 includes an insulating layer having electrical insulation and thermal conductivity, and a metal lead frame provided on one surface of the insulating layer. An element mounting portion is patterned on the lead frame, and a circuit element that generates heat is mounted on the element mounting portion. The lead frame and the circuit element are sealed with resin on one side of the insulating layer, and the other side of the insulating layer is exposed from the resin for heat dissipation.

特開２００５−００５６３８号公報JP-A-2005-005638 特開２０１１−０９１２５９号公報JP 2011-091259 A

特許文献１及び２に記載の技術は、半田を用いて回路素子を銅板やアルミニウム板に接合している。これにより、回路素子と銅板やアルミニウム板とを電気的に接合しつつ、銅板やアルミニウム板の裏面から放熱を行っている。しかしながら、回路素子と銅板やアルミニウム板の基板とは熱膨張係数に差があるので、熱衝撃により半田にクラックが生じることがある。このようなクラックは回路素子の接触不良の原因となってしまう。   In the techniques described in Patent Documents 1 and 2, circuit elements are joined to a copper plate or an aluminum plate using solder. Thereby, heat is radiated from the back surface of the copper plate or the aluminum plate while electrically joining the circuit element and the copper plate or the aluminum plate. However, since there is a difference in thermal expansion coefficient between the circuit element and the copper plate or aluminum plate substrate, cracks may occur in the solder due to thermal shock. Such cracks cause poor contact of circuit elements.

本発明の目的は、上記問題に鑑み、熱衝撃が加わった場合でも接触不良が生じ難い電子部品モジュールを提供することにある。   In view of the above problems, an object of the present invention is to provide an electronic component module that is unlikely to cause poor contact even when a thermal shock is applied.

上記目的を達成するための本発明に係る電子部品モジュールの特徴構成は、素子と、前記素子とろう付けされる導電性部材と、前記導電性部材の有する面のうち前記素子に対向し、前記素子の側に開口する凹部を有する載置面と、を備えている点にある。   In order to achieve the above object, the electronic component module according to the present invention is characterized by an element, a conductive member brazed to the element, a surface of the conductive member facing the element, And a mounting surface having a recess opening on the element side.

このような特徴構成とすれば、載置面に凹部が設けられているので、導電性部材に熱衝撃が加わった場合であっても、導電性部材の面方向の膨張及び収縮を抑制することができる。このため、導電性部材と素子とをろう付けした部分に生じる応力を低減することができるので、ろう付け部分の損傷を防止できる。したがって、素子の接触不良を生じ難くすることが可能となる。   With such a characteristic configuration, since the concave portion is provided on the mounting surface, the expansion and contraction in the surface direction of the conductive member can be suppressed even when a thermal shock is applied to the conductive member. Can do. For this reason, since the stress which arises in the part which brazed the electroconductive member and the element can be reduced, damage to a brazing part can be prevented. Therefore, it becomes possible to make it difficult to cause poor contact of the elements.

また、前記導電性部材における前記凹部が形成された面の裏側の面に、前記素子に対向する面の凹部とは異なるパターンの凹部が形成されていると好適である。   In addition, it is preferable that a concave portion having a pattern different from the concave portion of the surface facing the element is formed on the back surface of the conductive member in which the concave portion is formed.

このような構成とすれば、導電性部材の表面に加え、裏面の熱衝撃による膨張及び収縮も低減することができる。このため、導電性部材全体に亘って熱衝撃による応力の発生を抑えることが可能となる。したがって、素子の接触不良を更に生じ難くすることが可能となる。   With such a configuration, in addition to the surface of the conductive member, expansion and contraction due to thermal shock on the back surface can also be reduced. For this reason, it becomes possible to suppress generation | occurrence | production of the stress by a thermal shock over the whole electroconductive member. Therefore, it is possible to further reduce the contact failure of the element.

また、前記導電性部材は前記素子が実装される基板であると好適である。   The conductive member is preferably a substrate on which the element is mounted.

このような構成とすれば、基板と素子との固着強度を高めることに利用できる。したがって、製品の信頼性を高めることが可能となる。   Such a configuration can be used to increase the fixing strength between the substrate and the element. Therefore, it becomes possible to improve the reliability of the product.

また、前記載置面の凹部は、絶縁体で埋め戻されていると好適である。   Moreover, it is preferable that the concave portion of the mounting surface is backfilled with an insulator.

このような構成とすれば、載置面を平坦にすることができる。したがって、素子を載置面に安定した状態で搭載することが可能となる。   With such a configuration, the placement surface can be flattened. Therefore, the element can be mounted on the mounting surface in a stable state.

また、前記導電性部材は、前記絶縁体で埋め戻された前記凹部を含む前記載置面に導電被膜が形成されていると好適である。   In addition, it is preferable that the conductive member has a conductive film formed on the mounting surface including the concave portion backfilled with the insulator.

このような構成とすれば、素子を導電被膜上に搭載することができる。したがって、載置面に搭載する素子と載置される面との接触面積を増加することができるので、ろう付けによる固着強度を高めることが可能となる。   With such a configuration, the element can be mounted on the conductive film. Accordingly, the contact area between the element mounted on the mounting surface and the mounting surface can be increased, so that the fixing strength by brazing can be increased.

電子部品モジュールの表側の斜視図である。It is a perspective view of the front side of an electronic component module. 電子部品モジュールが有する素子の接続形態を示す回路図である。It is a circuit diagram which shows the connection form of the element which an electronic component module has. 電子部品モジュールの各部の断面図である。It is sectional drawing of each part of an electronic component module. 基板の表側の斜視図である。It is a perspective view of the front side of a board | substrate. 基板の裏側の斜視図である。It is a perspective view of the back side of a board | substrate. 電子部品モジュールの製造方法を示す図である。It is a figure which shows the manufacturing method of an electronic component module. 電子部品モジュールの製造方法を示す図である。It is a figure which shows the manufacturing method of an electronic component module. その他の実施形態に係る凹部のパターンを示す図である。It is a figure which shows the pattern of the recessed part which concerns on other embodiment. その他の実施形態に係る凹部のパターンを示す図である。It is a figure which shows the pattern of the recessed part which concerns on other embodiment. その他の実施形態に係る凹部のパターンを示す図である。It is a figure which shows the pattern of the recessed part which concerns on other embodiment. その他の実施形態に係る導電性部材を示す図である。It is a figure which shows the electroconductive member which concerns on other embodiment.

本発明に係る電子部品モジュールは、熱衝撃が加わった場合でも素子が接触不良を起こさないように構成される。以下、本実施形態の電子部品モジュール１について、詳細に説明する。図１には電子部品モジュール１の表側の斜視図が示される。   The electronic component module according to the present invention is configured so that the element does not cause poor contact even when a thermal shock is applied. Hereinafter, the electronic component module 1 of the present embodiment will be described in detail. FIG. 1 is a perspective view of the front side of the electronic component module 1.

本実施形態の電子部品モジュール１は、図１に示されるように本体部２とリード端子３とを有して構成される。本体部２は直方体状に形成される。本体部２は、後述するモールド部４０に相当し、当該モールド部４０には複数の素子１０が内包される。リード端子３は本体部２に内包される素子１０の回路構成に応じた本数だけ備えられ、夫々のリード端子３は本体部２が有する面のうち、互いに対向する２つの面から延出して設けられる。このような電子部品モジュール１は、基板に設けられた貫通孔に挿通できるようにリード端子３が所定の形状にフォーミングされ、所謂基板挿入型の部品（ＤＩＰ部品）として構成される。なお、本体部２の形状は直方体状であるが、特に限定されるものではない。   As shown in FIG. 1, the electronic component module 1 of this embodiment includes a main body 2 and lead terminals 3. The main body 2 is formed in a rectangular parallelepiped shape. The main body portion 2 corresponds to a mold portion 40 described later, and a plurality of elements 10 are included in the mold portion 40. The lead terminals 3 are provided in the number corresponding to the circuit configuration of the element 10 included in the main body 2, and each lead terminal 3 is provided to extend from two surfaces facing each other among the surfaces of the main body 2. It is done. Such an electronic component module 1 is formed as a so-called substrate insertion type component (DIP component) by forming the lead terminal 3 into a predetermined shape so that it can be inserted into a through hole provided in the substrate. In addition, although the shape of the main-body part 2 is a rectangular parallelepiped shape, it is not specifically limited.

本実施形態では、モールド部４０にはＨブリッジ回路５０が内包される。このようなＨブリッジ回路５０が図２に示される。Ｈブリッジ回路５０は２つの出力端子（Ｕ相端子及びＶ相端子）を有し、出力電流の流れを、一方の出力端子から他方の出力端子への流れ、又は他方の出力端子から一方の出力端子への流れに切り替える回路である。Ｈブリッジ回路５０は、複数のスイッチング素子を有して構成される。スイッチング素子には、ＦＥＴ（field effect transistor）やＩＧＢＴ（insulated gate bipolar transistor）等を用いることができる。本実施形態では、図２に示されるように、スイッチング素子としてＦＥＴ５１が用いられる。したがって、本発明に係る素子１０は本実施形態ではＦＥＴ５１が相当する。   In the present embodiment, an H bridge circuit 50 is included in the mold part 40. Such an H-bridge circuit 50 is shown in FIG. The H-bridge circuit 50 has two output terminals (U-phase terminal and V-phase terminal), and the output current flows from one output terminal to the other output terminal or from the other output terminal to one output. It is a circuit that switches to the flow to the terminal. The H bridge circuit 50 includes a plurality of switching elements. As the switching element, a field effect transistor (FET), an insulated gate bipolar transistor (IGBT), or the like can be used. In the present embodiment, as shown in FIG. 2, an FET 51 is used as a switching element. Therefore, the element 10 according to the present invention corresponds to the FET 51 in this embodiment.

Ｈブリッジ回路５０は、図２に示されるように直流電源の正極に接続される正電源ラインＰと、直流電源の負極に接続される負電源ラインＮ（例えば接地電位）との間に設けられる。正電源ラインＰと負電源ラインＮとの間には、ハイサイドのＦＥＴ５１ＨとローサイドのＦＥＴ５１Ｌとが直列に接続されたアーム部５２が、２組（５２Ａ、５２Ｂ）設けられる。すなわち、夫々のアーム部５２Ａ、５２Ｂは、正電源ラインＰと負電源ラインＮとの間で並列に接続される。本実施形態では、ＦＥＴ５１はＰ型ＦＥＴが用いられる。   As shown in FIG. 2, the H bridge circuit 50 is provided between a positive power supply line P connected to the positive electrode of the DC power supply and a negative power supply line N (for example, ground potential) connected to the negative electrode of the DC power supply. . Between the positive power supply line P and the negative power supply line N, two sets (52A, 52B) of arm portions 52 in which a high-side FET 51H and a low-side FET 51L are connected in series are provided. That is, the respective arm portions 52A and 52B are connected in parallel between the positive power supply line P and the negative power supply line N. In the present embodiment, the FET 51 is a P-type FET.

このようなＨブリッジ回路５０は単相モータのＵ相、Ｖ相に対応するステータコイルの夫々に通電するのに利用される。具体的には、アーム部５２ＡにおけるハイサイドのＦＥＴ５１ＨとローサイドのＦＥＴ５１Ｌとの中点（Ｕ相端子）が単相モータのＵ相のステータコイルに接続される。また、アーム部５２ＢにおけるハイサイドのＦＥＴ５１ＨとローサイドのＦＥＴ５１Ｌとの中点（Ｖ相端子）が単相モータのＶ相のステータコイルに接続される。   Such an H-bridge circuit 50 is used to energize the stator coils corresponding to the U-phase and V-phase of the single-phase motor. Specifically, the midpoint (U-phase terminal) of the high-side FET 51H and the low-side FET 51L in the arm portion 52A is connected to the U-phase stator coil of the single-phase motor. Further, the midpoint (V-phase terminal) of the high-side FET 51H and the low-side FET 51L in the arm portion 52B is connected to the V-phase stator coil of the single-phase motor.

各アーム部５２Ａ、５２ＢのハイサイドのＦＥＴ５１Ｈのソース端子Ｓは正電源ラインＰに接続され、ドレイン端子Ｄは夫々のアーム部５２Ａ、５２ＢのローサイドのＦＥＴ５１Ｌのソース端子Ｓに接続される。また、各アーム部５２Ａ、５２ＢのローサイドのＦＥＴ５１Ｌのドレイン端子Ｄは、負電源ラインＮに接続される。図２には図示しないが、各ＦＥＴ５１のソース端子Ｓ及びドレイン端子Ｄの間にはダイオードが設けられる。このダイオードは、カソード端子がソース端子Ｓに接続され、アノード端子がドレイン端子Ｄに接続される。   The source terminal S of the high-side FET 51H of each arm part 52A, 52B is connected to the positive power supply line P, and the drain terminal D is connected to the source terminal S of the low-side FET 51L of each arm part 52A, 52B. The drain terminal D of the low-side FET 51L of each arm portion 52A, 52B is connected to the negative power supply line N. Although not shown in FIG. 2, a diode is provided between the source terminal S and the drain terminal D of each FET 51. The diode has a cathode terminal connected to the source terminal S and an anode terminal connected to the drain terminal D.

ここで、同一のアーム部５２においてハイサイドのＦＥＴ５１ＨとローサイドのＦＥＴ５１Ｌとが同時にオン状態（導通状態）となると、正電源ラインＰと負電源ラインＮとが短絡状態となるので、ＦＥＴ５１ＨとＦＥＴ５１Ｌとは相補的にオン状態となるように制御される。このような制御は、ＦＥＴ５１ＨとＦＥＴ５１Ｌとの夫々のゲート端子Ｇに制御信号が入力され実現される。   Here, when the high-side FET 51H and the low-side FET 51L are simultaneously turned on (conductive state) in the same arm portion 52, the positive power supply line P and the negative power supply line N are short-circuited, so that the FET 51H and FET 51L Are controlled to be complementarily turned on. Such control is realized by inputting control signals to the gate terminals G of the FETs 51H and 51L.

次に、このようなＦＥＴ５１の部品配置について図３を用いて説明する。図３（ａ）は、図１のIIIa−IIIa線における断面図であり、図３（ｂ）は図３（ａ）のIIIb−IIIb線における断面図である。電子部品モジュール１は、素子１０と、導電性部材２０と、載置面３０と、モールド部４０とを備えて構成される。   Next, the arrangement of parts of the FET 51 will be described with reference to FIG. 3A is a cross-sectional view taken along line IIIa-IIIa in FIG. 1, and FIG. 3B is a cross-sectional view taken along line IIIb-IIIb in FIG. The electronic component module 1 includes an element 10, a conductive member 20, a placement surface 30, and a mold part 40.

素子１０は、例えば半田付け等のろう付けを行うことが可能な電極を有する電子部品である。本実施形態ではＨブリッジ回路５０を構成するＦＥＴ５１が相当する。   The element 10 is an electronic component having electrodes that can be brazed, for example, by soldering. In the present embodiment, the FET 51 constituting the H bridge circuit 50 corresponds.

導電性部材２０は、素子１０とろう付けされる。本実施形態では、導電性部材２０は、素子１０が実装される基板である。具体的には銅板２１が相当する。銅板２１は所定の厚さを有する板状であれば良い。ろう付けとは、接着部材を用いて部品を基材に接着することをいい、例えば半田付けが相当する。基材は、本実施形態では銅板２１である。このため、素子１０は銅板２１に半田付けされる。   The conductive member 20 is brazed to the element 10. In the present embodiment, the conductive member 20 is a substrate on which the element 10 is mounted. Specifically, the copper plate 21 corresponds. The copper plate 21 may be a plate shape having a predetermined thickness. Brazing refers to bonding a component to a substrate using an adhesive member, and corresponds to soldering, for example. A base material is the copper plate 21 in this embodiment. For this reason, the element 10 is soldered to the copper plate 21.

載置面３０は、導電性部材２０の有する面のうち素子１０に対向し、素子１０の側に開口する凹部６０を有する。導電性部材２０の有する面のうち素子１０に対向する面とは、本実施形態では銅板２１における素子１０が半田付けされる面である。凹部６０とは、半田付けされる面に対して窪んでいる部位である。このような凹部６０は、銅板２１を貫通することなく切削加工により形成される。本実施形態では、凹部６０は溝状に形成される。素子１０の側に開口するとは、銅板２１における素子１０が半田付けされる面に開口していることを意味する。したがって、銅板２１における素子１０が半田付けされる面である載置面３０には、当該載置面３０に向けて開口する溝状の窪みが形成される。   The mounting surface 30 has a recess 60 that faces the element 10 in the surface of the conductive member 20 and opens on the element 10 side. The surface facing the element 10 among the surfaces of the conductive member 20 is a surface to which the element 10 in the copper plate 21 is soldered in the present embodiment. The recess 60 is a portion that is recessed with respect to the surface to be soldered. Such a recess 60 is formed by cutting without penetrating the copper plate 21. In the present embodiment, the recess 60 is formed in a groove shape. Opening to the element 10 side means opening to the surface of the copper plate 21 to which the element 10 is soldered. Therefore, a groove-shaped depression that opens toward the mounting surface 30 is formed on the mounting surface 30 on which the element 10 of the copper plate 21 is soldered.

図４には本実施形態に係る銅板２１の表側からの斜視図が示される。図５には本実施形態に係る銅板２１の裏側からの斜視図が示される。図４及び図５に示されるように、本実施形態の凹部６０は所定の間隔を有する溝で形成される。このため、本実施形態では凹部６０は銅板２１上に碁盤の目のように形成される。凹部６０は、銅板２１を完全に貫通せずに底部を有し、例えば銅板２１の半分の厚さに等しい深さで形成される。   FIG. 4 is a perspective view from the front side of the copper plate 21 according to the present embodiment. FIG. 5 shows a perspective view from the back side of the copper plate 21 according to the present embodiment. As shown in FIGS. 4 and 5, the recess 60 of the present embodiment is formed by a groove having a predetermined interval. For this reason, in this embodiment, the recessed part 60 is formed on the copper plate 21 like a grid. The recess 60 does not completely penetrate the copper plate 21 and has a bottom, and is formed with a depth equal to, for example, half the thickness of the copper plate 21.

また、本実施形態では、図４及び図５に示されるように、導電性部材２０における凹部６０が形成された面の裏側の面に、素子１０に対向する面の凹部６０とは異なるパターンの凹部６１が形成される。導電性部材２０における凹部６０が形成された面とは、銅板２１の凹部６０が形成された面であり、素子１０が載置される載置面３０となる面である。このような面の裏側の面に凹部６１が形成される。本実施形態では、凹部６１も凹部６０と同様に銅板２１を貫通せず、底部を有する溝で形成される。凹部６０とは異なるパターンの凹部６１とは、凹部６０と凹部６１との夫々の形状が異なっている状態、或いは形状が同じであっても銅板２１における位置が異なっている様態を意味する。したがって、図４及び図５に示されるように、銅板２１を厚さ方向に見て、凹部６０と凹部６１とが交差することはあっても良い。   In the present embodiment, as shown in FIGS. 4 and 5, the conductive member 20 has a pattern on the back side of the surface where the recess 60 is formed, which is different from the recess 60 on the surface facing the element 10. A recess 61 is formed. The surface of the conductive member 20 on which the recess 60 is formed is the surface on which the recess 60 of the copper plate 21 is formed, and is the surface that becomes the mounting surface 30 on which the element 10 is mounted. A recess 61 is formed on the back surface of such a surface. In the present embodiment, the concave portion 61 is also formed of a groove having a bottom portion without penetrating the copper plate 21 like the concave portion 60. The concave portion 61 having a pattern different from the concave portion 60 means a state in which the concave portion 60 and the concave portion 61 have different shapes, or a state in which the positions on the copper plate 21 are different even if the shapes are the same. Therefore, as shown in FIGS. 4 and 5, the concave portion 60 and the concave portion 61 may intersect each other when the copper plate 21 is viewed in the thickness direction.

図３（ｂ）に戻り、載置面３０の凹部６０は、絶縁体８０で埋め戻されている。載置面３０の凹部６０とは、銅板２１における素子１０が載置される側の面に形成された溝である。絶縁体８０とは、例えば樹脂やゴム部材が相当する。もちろん、セラミック等であっても良い。埋め戻されているとは、凹部６０が当該凹部６０が形成されていない面と均一な面となるように埋められていることをいう。したがって、凹部６０が絶縁体８０で埋め戻された載置面３０は平坦な面となる。本実施形態では、このような溝が絶縁体８０で埋め戻されている。   Returning to FIG. 3B, the recess 60 of the mounting surface 30 is backfilled with an insulator 80. The recess 60 of the mounting surface 30 is a groove formed on the surface of the copper plate 21 on the side where the element 10 is mounted. The insulator 80 corresponds to, for example, a resin or a rubber member. Of course, ceramic or the like may be used. The term “refilled” means that the concave portion 60 is buried so as to be uniform with the surface where the concave portion 60 is not formed. Therefore, the mounting surface 30 in which the recess 60 is backfilled with the insulator 80 is a flat surface. In the present embodiment, such a groove is backfilled with the insulator 80.

これにより、例えば絶縁体８０が導電性部材２０よりも柔らかい部材である場合に、導電性部材２０が熱衝撃により膨張又は収縮しても絶縁体８０が、膨張や収縮に係る応力を吸収することができる。したがって、導電性部材２０と素子１０との間のろう付けされた部分（半田部分）が剥離したり損傷したりすることを防止できる。一方、例えば絶縁体８０が導電性部材２０よりも固い部材である場合には、導電性部材２０が熱衝撃により膨張又は収縮すると絶縁体８０の間毎に導電性部材２０が膨張又は収縮するので、導電性部材２０全体での応力を低減することができる。したがって、導電性部材２０と素子１０との間のろう付けされた部分（半田部分）が剥離したり損傷したりすることを防止できる。このように、導電性部材２０に凹部６０を設け、当該凹部６０を異種の材料で埋め戻すことによりろう付けした部分の信頼性を向上することが可能となる。   Thereby, for example, when the insulator 80 is a softer member than the conductive member 20, even if the conductive member 20 expands or contracts due to a thermal shock, the insulator 80 absorbs stress related to expansion or contraction. Can do. Therefore, it is possible to prevent the brazed portion (solder portion) between the conductive member 20 and the element 10 from being peeled off or damaged. On the other hand, for example, when the insulator 80 is harder than the conductive member 20, the conductive member 20 expands or contracts between the insulators 80 when the conductive member 20 expands or contracts due to thermal shock. The stress in the entire conductive member 20 can be reduced. Therefore, it is possible to prevent the brazed portion (solder portion) between the conductive member 20 and the element 10 from being peeled off or damaged. As described above, it is possible to improve the reliability of the brazed portion by providing the conductive member 20 with the recess 60 and backfilling the recess 60 with a different material.

ここで、導電性部材２０は、絶縁体８０で埋め戻された凹部６０を含む載置面３０に導電被膜８１が形成されている。また、本実施形態では導電被膜８１は、凹部６０の側壁部７２にも形成される。導電被膜上に素子１０をろう付けすることができ、当該導電被膜８１を介して素子１０を導電性部材２０の載置面３０に載置することが可能となる。したがって、凹部６０が形成された状態のまま素子１０を載置する場合に比べて、素子１０とのろう付けに寄与する面積が増加することができるので、ろう付けの固着強度を高めることが可能となる。   Here, in the conductive member 20, a conductive film 81 is formed on the mounting surface 30 including the recess 60 backfilled with the insulator 80. In the present embodiment, the conductive coating 81 is also formed on the side wall 72 of the recess 60. The element 10 can be brazed on the conductive film, and the element 10 can be mounted on the mounting surface 30 of the conductive member 20 via the conductive film 81. Therefore, the area contributing to brazing with the element 10 can be increased as compared with the case where the element 10 is placed in a state where the recess 60 is formed, so that the fixing strength of brazing can be increased. It becomes.

次に、電子部品モジュール１の製造方法について説明する。まず、図６（ａ）に示されるように、銅板２１の表側の面に凹部６０を形成し、裏側の面に凹部６１を形成する。この際、凹部６０と凹部６１とは互いに異なるパターンで形成される。次に、図６（ｂ）に示されるように、銅板２１の凹部６０が形成された側の面に絶縁体８０が載置（堆積）され、更にこの絶縁体８０上に導体８２が載置（堆積）される。このような導体８２／絶縁体８０／銅板２１の積層構造物を上下方向から加熱しながら押圧し、凹部６０に絶縁体８０を充填し、凹部６０が埋め戻される。   Next, a method for manufacturing the electronic component module 1 will be described. First, as shown in FIG. 6A, the recess 60 is formed on the front surface of the copper plate 21, and the recess 61 is formed on the back surface. At this time, the recess 60 and the recess 61 are formed in different patterns. Next, as shown in FIG. 6B, the insulator 80 is placed (deposited) on the surface of the copper plate 21 on which the concave portion 60 is formed, and the conductor 82 is placed on the insulator 80. (Deposition). Such a laminated structure of the conductor 82 / insulator 80 / copper plate 21 is pressed while being heated from above and below to fill the recess 60 with the insulator 80, and the recess 60 is backfilled.

図６（ｃ）に示されるように、電子部品モジュール１に内包する回路構成に応じて、導体８２をパターンニングする。パターンニング後、ＦＥＴ５１を載置する部位を、導体８２の側から銅板２１が露出するように切削加工を施し、凹部７０を形成する。この場合、図６（ｄ）に示されるようにエンドミル９９を用いて切削しても良いし、レーザにより切削しても良い。なお、上述のように凹部６０には絶縁体８０が充填されるので、凹部７０の底部７１では銅板２１と絶縁体８０とが露出される。   As shown in FIG. 6C, the conductor 82 is patterned according to the circuit configuration included in the electronic component module 1. After patterning, the recess 51 is formed by cutting the part on which the FET 51 is placed so that the copper plate 21 is exposed from the conductor 82 side. In this case, cutting may be performed using an end mill 99 as shown in FIG. Since the recess 60 is filled with the insulator 80 as described above, the copper plate 21 and the insulator 80 are exposed at the bottom 71 of the recess 70.

次に、図７（ａ）に示されるように、凹部７０の底部７１及び側壁部７２に導電被膜８１が形成される。これにより、凹部７０の底部７１に形成された導電被膜８１と、導体８２とが側壁部７２の導電被膜８１を介して電気的に接続される。   Next, as shown in FIG. 7A, a conductive film 81 is formed on the bottom 71 and the side wall 72 of the recess 70. As a result, the conductive coating 81 formed on the bottom 71 of the recess 70 and the conductor 82 are electrically connected via the conductive coating 81 on the side wall 72.

次に、図７（ｂ）に示されるように、底部７１の導電被膜８１上にＦＥＴ５１を載置する。この際、ＦＥＴ５１の裏面のドレイン端子Ｄと導電被膜８１とを例えば半田付けにより電気的に接続する。そして、ＦＥＴ５１のゲート端子Ｇ及びソース端子Ｓの夫々を、導体８２上の所定の位置とワイヤ９５で接続する。   Next, as shown in FIG. 7B, the FET 51 is placed on the conductive film 81 on the bottom 71. At this time, the drain terminal D on the back surface of the FET 51 and the conductive film 81 are electrically connected by, for example, soldering. Then, each of the gate terminal G and the source terminal S of the FET 51 is connected to a predetermined position on the conductor 82 by a wire 95.

また、図７（ｃ）に示されるように、導体８２の所定の位置にリード端子３がろう付けされる。図７（ｄ）に示されるように、リード端子３を延出させた状態でモールド部４０を構成する。この場合、銅板２１の裏面がモールド部４０から露出するように形成する。これにより、銅板２１の放熱性を高めることができる。このようにして電子部品モジュール１が製造される。なお、この際、銅板２１の裏面の凹部６１にはモールド部４０が注入されても良い。   Further, as shown in FIG. 7C, the lead terminal 3 is brazed to a predetermined position of the conductor 82. As shown in FIG. 7D, the mold part 40 is configured with the lead terminals 3 extended. In this case, the back surface of the copper plate 21 is formed so as to be exposed from the mold part 40. Thereby, the heat dissipation of the copper plate 21 can be improved. In this way, the electronic component module 1 is manufactured. At this time, the mold part 40 may be injected into the recess 61 on the back surface of the copper plate 21.

〔その他の実施形態〕
上記実施形態では、銅板２１に形成される凹部６０及び凹部６１が溝であるとして説明した。しかしながら、本発明の適用範囲はこれに限定されるものではない。例えば、図８に示されるように、凹部６０及び凹部６１を円柱状の窪みで形成することも可能である。もちろん、凹部６０及び凹部６１を多角形の窪みで形成することも可能である。 [Other Embodiments]
In the said embodiment, the recessed part 60 and the recessed part 61 which are formed in the copper plate 21 demonstrated as a groove | channel. However, the scope of application of the present invention is not limited to this. For example, as shown in FIG. 8, it is also possible to form the recess 60 and the recess 61 with a cylindrical recess. Of course, it is also possible to form the recessed part 60 and the recessed part 61 by a polygonal hollow.

上記実施形態では、銅板２１に形成された凹部６０及び凹部６１が、夫々銅板２１における互いに対向する側面に亘って形成されているように図示した。しかしながら、本発明の適用範囲はこれに限定されるものではない。図９に示されるように、凹部６０及び凹部６１の夫々が、銅板２１の側面（縁部）に到達しないように形成することも可能である。   In the said embodiment, it illustrated in figure that the recessed part 60 and the recessed part 61 which were formed in the copper plate 21 were formed over the mutually opposing side surface in the copper plate 21, respectively. However, the scope of application of the present invention is not limited to this. As shown in FIG. 9, each of the recess 60 and the recess 61 can be formed so as not to reach the side surface (edge) of the copper plate 21.

上記実施形態では、凹部６０と凹部６１とが、夫々同じ形状で形成されているように図示した。しかしながら、本発明の適用範囲はこれに限定されるものではない。すなわち、凹部６０と凹部６１とを異なる形状で形成することも可能である。例えば図１０に示されるように、凹部６０を円柱状に形成し、凹部６１を多角柱状に形成することも可能である。もちろん、凹部６０を多角柱状に形成し、凹部６１を円柱状に形成することも可能である。   In the said embodiment, it illustrated in figure that the recessed part 60 and the recessed part 61 were each formed in the same shape. However, the scope of application of the present invention is not limited to this. That is, it is possible to form the recess 60 and the recess 61 in different shapes. For example, as shown in FIG. 10, it is possible to form the recess 60 in a columnar shape and form the recess 61 in a polygonal column shape. Of course, it is also possible to form the recess 60 in a polygonal column and form the recess 61 in a columnar shape.

上記実施形態では、素子１０がＦＥＴ５１であるとして説明した。しかしながら、本発明の適用範囲はこれに限定されるものではない。素子１０としてＦＥＴ５１以外の電子部品を適用することも可能である。また、素子１０は半導体部品以外の部品を適用することも可能である。   In the above embodiment, the element 10 is described as the FET 51. However, the scope of application of the present invention is not limited to this. It is also possible to apply an electronic component other than the FET 51 as the element 10. In addition, the element 10 can be a component other than a semiconductor component.

上記実施形態では、銅板２１の表側の面に凹部６０が形成され、裏側の面に凹部６１が形成されるとして説明した。しかしながら、本発明の適用範囲はこれに限定されるものではない。銅板２１の表側の面にのみ凹部６０を形成し、裏側の面に凹部６１を形成しないように構成することも可能である。   In the said embodiment, the recessed part 60 was formed in the surface of the copper plate 21, and the recessed part 61 was formed in the surface of a back side. However, the scope of application of the present invention is not limited to this. It is possible to form the recess 60 only on the front surface of the copper plate 21 and not to form the recess 61 on the back surface.

上記実施形態では、導電性部材２０は素子１０が実装される基板、すなわち銅板２１であるとして説明した。しかしながら、本発明の適用範囲は限定されるものではない。上述したワイヤボンディングに代えて、素子１０がリード端子３や電極パッド７４と例えばクリップボンドにより接続される場合には、当該クリップボンドに用いられるリード８６も導電性部材２０であると考え、図１１に示されるように、リード８６が有する面のうち素子１０に対向する面に、凹部６０を構成することも可能である。このようなリード８６と素子１０とをクリップボンドにより接続することで、素子１０とリード８６との間のろう付けされた部分（例えば半田部）に熱衝撃が加わった場合でも応力を緩和することができる。したがって、素子１０とリード８６との接合信頼性を高めることが可能となる。なお、凹部６０が形成された裏面には、図１１に示されるように凹部６１を形成しても良い。   In the said embodiment, the electroconductive member 20 demonstrated as the board | substrate with which the element 10 is mounted, ie, the copper plate 21, and was demonstrated. However, the application range of the present invention is not limited. When the element 10 is connected to the lead terminal 3 and the electrode pad 74 by, for example, clip bonding instead of the wire bonding described above, the lead 86 used for the clip bonding is also considered to be the conductive member 20, and FIG. As shown in FIG. 6, the recess 60 can be formed on the surface of the lead 86 that faces the element 10. By connecting the lead 86 and the element 10 by clip bonding, the stress can be relieved even when a thermal shock is applied to a brazed portion (for example, a solder portion) between the element 10 and the lead 86. Can do. Therefore, it is possible to improve the bonding reliability between the element 10 and the lead 86. In addition, you may form the recessed part 61 as FIG. 11 shows in the back surface in which the recessed part 60 was formed.

上記実施形態では、載置面３０の凹部６０が絶縁体８０で埋め戻されているとして説明した。しかしながら、本発明の適用範囲はこれに限定されるものではない。凹部６０を絶縁体８０で埋めずに構成することも可能である。また、凹部６０を導電体で埋め戻しすることも当然に可能である。   In the embodiment described above, it has been described that the recess 60 of the placement surface 30 is backfilled with the insulator 80. However, the scope of application of the present invention is not limited to this. It is also possible to configure the recess 60 without filling it with the insulator 80. In addition, it is naturally possible to backfill the recess 60 with a conductor.

上記実施形態では、導電性部材２０は、絶縁体８０で埋め戻された凹部６０を含む載置面３０に導電被膜８１が形成されているとして説明した。しかしながら、本発明の適用範囲はこれに限定されるものではない。載置面３０に導電被膜８１を形成せずに、直接、導電性部材２０に素子１０をろう付けする構成とすることも可能である。   In the above embodiment, the conductive member 20 has been described on the assumption that the conductive film 81 is formed on the placement surface 30 including the recess 60 backfilled with the insulator 80. However, the scope of application of the present invention is not limited to this. A configuration in which the element 10 is brazed directly to the conductive member 20 without forming the conductive film 81 on the mounting surface 30 is also possible.

本発明は、樹脂内に素子が封入された電子部品モジュールに用いることが可能である。   The present invention can be used for an electronic component module in which an element is enclosed in a resin.

１:電子部品モジュール
１０：素子
２０：導電性部材
３０：載置面
６０：凹部
６１：凹部
８０：絶縁体
８１：導電被膜 1: Electronic component module 10: Element 20: Conductive member 30: Placement surface 60: Recess 61: Recess 80: Insulator 81: Conductive coating

Claims (5)

素子と、
前記素子とろう付けされる導電性部材と、
前記導電性部材の有する面のうち前記素子に対向し、前記素子の側に開口する凹部を有する載置面と、
を有する電子部品モジュール。 Elements,
A conductive member brazed to the element;
A mounting surface having a recess facing the element and opening on the element side of the surface of the conductive member;
An electronic component module. 前記導電性部材における前記凹部が形成された面の裏側の面に、前記素子に対向する面の凹部とは異なるパターンの凹部が形成されている請求項１に記載の電子部品モジュール。   2. The electronic component module according to claim 1, wherein a recess having a pattern different from a recess on a surface facing the element is formed on a surface on a back side of the surface on which the recess is formed in the conductive member. 前記導電性部材は前記素子が実装される基板である請求項１又は２に記載の電子部品モジュール。   The electronic component module according to claim 1, wherein the conductive member is a substrate on which the element is mounted. 前記載置面の凹部は、絶縁体で埋め戻されている請求項１から３のいずれ一項に記載の電子部品モジュール。   The electronic component module according to claim 1, wherein the concave portion of the placement surface is backfilled with an insulator. 前記導電性部材は、前記絶縁体で埋め戻された前記凹部を含む前記載置面に導電被膜が形成されている請求項４に記載の電子部品モジュール。   5. The electronic component module according to claim 4, wherein the conductive member has a conductive film formed on the placement surface including the concave portion backfilled with the insulator. 6.
JP2013232123A 2013-11-08 2013-11-08 Electronic component module Pending JP2015095473A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5967686A (en) * 1982-10-12 1984-04-17 イビデン株式会社 Printed circuit board and method of producing same
JP2001267478A (en) * 2000-03-17 2001-09-28 Hitachi Chem Co Ltd Semiconductor device and method for manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5967686A (en) * 1982-10-12 1984-04-17 イビデン株式会社 Printed circuit board and method of producing same
JP2001267478A (en) * 2000-03-17 2001-09-28 Hitachi Chem Co Ltd Semiconductor device and method for manufacturing the same

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