JP2015092140A - Semiconductor module inspection method and semiconductor system - Google Patents

Semiconductor module inspection method and semiconductor system Download PDF

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JP2015092140A
JP2015092140A JP2013231640A JP2013231640A JP2015092140A JP 2015092140 A JP2015092140 A JP 2015092140A JP 2013231640 A JP2013231640 A JP 2013231640A JP 2013231640 A JP2013231640 A JP 2013231640A JP 2015092140 A JP2015092140 A JP 2015092140A
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semiconductor module
semiconductor
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parasitic resistance
capacitance
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JP6432126B2 (en
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西口　哲也
Tetsuya Nishiguchi
哲也 西口
山田　真一
Shinichi Yamada
真一 山田
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Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths

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Abstract

PROBLEM TO BE SOLVED: To evaluate the state of a junction of a semiconductor module at short time.SOLUTION: In a semiconductor module inspection method, a capacitance between any terminals of a P terminal 6, N terminal 7, and AC terminal 8 which connect a circuit constituted of semiconductor chips 2-5 with external circuits, and parasite resistance that parasites in series to the capacitance are measured; and the degree of deterioration in junctions (junctions at solder layer 12, 14, and 16, and wires 13 and 15) of a semiconductor module 1 on the basis of secular changes of the measured capacitance and/or parasite resistance is evaluated. In addition, a cooler terminal 11a is provided in a cooler 11 which is provided in a base 10 of the semiconductor module 1 via a grease layer 17; a capacitance between the cooler terminal 11a and any terminal of the P terminal 6, N terminal 7, and AC terminal 8, and parasite resistance parasitic in series to the capacitance are measured; and the degree of deterioration in the grease layer 17 between the base 10 and cooler 11 is evaluated on the basis of the measured capacitance and/or parasite resistance.

Description

本発明は、半導体モジュールの接合部の状態を検出する半導体モジュールの検査方法及び半導体システムに関する。   The present invention relates to a semiconductor module inspection method and a semiconductor system for detecting a state of a joint portion of a semiconductor module.

代表的な絶縁形パワー半導体モジュールとして、例えば、インバータ等の電力変換装置に用いられるＩＧＢＴ（Insulated Gate Bipolar Transistor：絶縁ゲートバイポーラトランジスタ）モジュールがある。このＩＧＢＴモジュールに代表される「絶縁形パワー半導体モジュール」若しくは「Isolated power semiconductor devices」は、それぞれＪＥＣ−２４０７−２００７、ＩＥＣ６０７４７−１５にて規格が制定されている。   As a typical insulated power semiconductor module, for example, there is an IGBT (Insulated Gate Bipolar Transistor) module used in a power converter such as an inverter. Standards for “insulated power semiconductor modules” or “Isolated power semiconductor devices” represented by this IGBT module are established in JEC-2407-2007 and IEC60747-15, respectively.

一般的に、ＩＧＢＴやダイオード等の半導体素子は、半導体素子の下面に設けられた電極層を介してＤＢＣ（Direct Bond Copper）基板の銅回路箔上にはんだ付けされ、半導体モジュールを構成する（例えば、非特許文献１）。ＤＢＣ基板は、放熱性を向上させるために、はんだを介して銅ベース上に設けられる。なお、ＤＢＣ基板は、セラミックス等の絶縁板に銅回路箔を直接接合したものである。   Generally, a semiconductor element such as an IGBT or a diode is soldered onto a copper circuit foil of a DBC (Direct Bond Copper) substrate via an electrode layer provided on the lower surface of the semiconductor element to constitute a semiconductor module (for example, Non-Patent Document 1). The DBC substrate is provided on the copper base via solder in order to improve heat dissipation. The DBC substrate is obtained by directly bonding a copper circuit foil to an insulating plate such as ceramics.

半導体素子の上面に設けられる電極層には、超音波ボンディング等の方法によりアルミワイヤが接続される。このアルミワイヤは、例えば、ＤＢＣ基板上の銅回路箔に結線される。そして、ＤＢＣ基板の銅回路箔から外部へ接続するための銅端子（リードフレームやブスバー）は、銅回路箔とはんだ付けや超音波ボンディング等により接続される。この周りは（スーパー）エンジニアリングプラスチックのケースで囲まれ、その中を電気絶縁のためのシリコーンゲルが充填される。   An aluminum wire is connected to the electrode layer provided on the upper surface of the semiconductor element by a method such as ultrasonic bonding. This aluminum wire is connected to, for example, a copper circuit foil on a DBC substrate. A copper terminal (lead frame or bus bar) for connecting to the outside from the copper circuit foil of the DBC substrate is connected to the copper circuit foil by soldering, ultrasonic bonding or the like. This area is surrounded by a (super) engineering plastic case, which is filled with silicone gel for electrical insulation.

はんだを用いた絶縁形パワー半導体モジュールの課題としては、ＲｏＨＳ（Restriction of Hazardous Substances）に対応するためのはんだの鉛フリー化に対応するという課題と、温度サイクルやパワーサイクル等の信頼性を向上するという課題の２つの課題がある。   Issues with insulated power semiconductor modules that use solder include the issue of responding to lead-free soldering to meet RoHS (Restriction of Hazardous Substances), and improving the reliability of temperature cycles, power cycles, etc. There are two issues:

はんだの鉛フリー化の課題に対しては、従来のはんだ材料に置換する材料である、金属系高温はんだ（Ｂｉ，Ｚｎ，Ａｕ）、化合物系高温はんだ（Ｓｎ−Ｃｕ）若しくは低温焼結金属（Ａｇナノペースト）等が提案されている（例えば、特許文献１）。   To solve the problem of lead-free soldering, metal-based high-temperature solder (Bi, Zn, Au), compound-based high-temperature solder (Sn—Cu), or low-temperature sintered metal (materials to replace conventional solder materials) Ag nanopaste) and the like have been proposed (for example, Patent Document 1).

また、温度サイクルやパワーサイクル等の信頼性を向上する課題に対しては、半導体モジュールを構成する各部材（半導体、金属、セラミックス等）の熱膨張の違いにより生じる課題を解決する必要がある。例えば、ＤＢＣ基板−銅ベース間、ＤＢＣ基板−銅端子間において、銅とセラミックスの熱膨張係数の差から、部材間に設けられたはんだにせん断応力が働き、はんだに亀裂が生じるおそれがある。その結果、熱抵抗が増大したり、端子が剥離したりするおそれが生じることとなる。さらに、半導体素子−ＤＢＣ基板間のはんだにも同様の理由により亀裂が生じるおそれがある。条件によっては、半導体素子上のアルミワイヤの接続部でも、アルミニウムと半導体素子との熱膨張係数の差から生じるせん断応力により、アルミワイヤが疲労破断することも考えられる。   Further, for the problem of improving the reliability such as the temperature cycle and the power cycle, it is necessary to solve the problem caused by the difference in thermal expansion of each member (semiconductor, metal, ceramics, etc.) constituting the semiconductor module. For example, between the DBC substrate and the copper base and between the DBC substrate and the copper terminal, shear stress acts on the solder provided between the members due to the difference in thermal expansion coefficient between copper and ceramics, and the solder may be cracked. As a result, the thermal resistance may increase or the terminal may be peeled off. Furthermore, the solder between the semiconductor element and the DBC substrate may be cracked for the same reason. Depending on the conditions, even at the connection portion of the aluminum wire on the semiconductor element, the aluminum wire may be fatigued and fractured due to the shear stress generated from the difference in thermal expansion coefficient between the aluminum and the semiconductor element.

そこで、半導体モジュールの接合部（例えば、はんだ接合部、超音波接合部、溶接部、接着剤による接合部）の信頼性が、高温放置試験、サーマル（熱）サイクル負荷試験、あるいはパワーサイクル負荷（通電負荷）試験等により評価されている。これらの試験では、一定時間経過後（サイクル後）の半導体素子とモジュールケースとの間の熱抵抗の変化を計測する方法、はんだ接合部内のボイドをＸ線や超音波等で可視化する方法、あるいは接合部の電気特性の変動を評価する方法等により接合部の信頼性の評価が行われる。   Therefore, the reliability of the joint part of the semiconductor module (for example, solder joint part, ultrasonic joint part, welded part, joint part by adhesive) is determined as a high temperature standing test, thermal cycle load test, or power cycle load ( (Electrical load) is evaluated by tests. In these tests, a method of measuring the change in thermal resistance between the semiconductor element and the module case after a certain time (after the cycle), a method of visualizing voids in the solder joints with X-rays, ultrasonic waves, or the like, or The reliability of the joint is evaluated by a method for evaluating the variation in the electrical characteristics of the joint.

特開２０１０−９３２８９号公報JP 2010-93289 A 国際公開第２０１１／１２１７２５号International Publication No. 2011-121725

電気学会高性能高機能パワーデバイス・パワーＩＣ調査専門委員会、「パワーデバイス・パワーＩＣハンドブック」、コロナ社、１９９６年７月、ｐ２８９、ｐ３３６IEEJ Technical Committee on High Performance and High Performance Power Devices and Power ICs, “Power Device and Power IC Handbook”, Corona, July 1996, p289, p336 森睦宏，関康和、「大容量ＩＧＢＴの最近の進歩」、電気学会誌、社団法人電気学会、１９９８年５月、Ｖｏｌ．１１８（５）、ｐｐ．２７４−２７７Hiroshi Mori, Yasukazu Seki, “Recent Advances in Large Capacity IGBTs”, The Institute of Electrical Engineers of Japan, The Institute of Electrical Engineers of Japan, May 1998, Vol. 118 (5), pp. 274-277

しかしながら、半導体モジュール内の劣化する可能性のある接合箇所は多数あり、これらを同時に短時間で行うことは困難となるおそれがある。また、劣化する可能性のある接合箇所を同時に検出する場合は、計測設備が高価となるおそれがある。   However, there are many joint portions in the semiconductor module that may be deteriorated, and it may be difficult to carry out these simultaneously in a short time. Moreover, when detecting the joint location which may deteriorate, measuring equipment may become expensive.

図１に、半導体モジュール１の断面構造を示す。半導体モジュール１底辺のベース１０には、サーマルグリース１７を介して冷却器１１が接合されている。半導体モジュール１に対して、熱サイクルあるいはパワーサイクル（通電サイクル）負荷を加えたり、実動作環境で動作させたりした場合、劣化するおそれのある接合部は、（１）半導体チップ２〜５表面上のワイヤ１３，１５接合部、（２）半導体チップ２〜５下のはんだ層１２，１４、（３）絶縁基板９下のはんだ層１６、及び（４）半導体モジュール１のベース１０と冷却器１１の接合面に存在するグリース層１７が主に想定される。   FIG. 1 shows a cross-sectional structure of the semiconductor module 1. A cooler 11 is joined to the base 10 at the bottom of the semiconductor module 1 via a thermal grease 17. When a thermal cycle or power cycle (energization cycle) load is applied to the semiconductor module 1 or when the semiconductor module 1 is operated in an actual operating environment, the junction that may be deteriorated is (1) on the surface of the semiconductor chips 2 to 5 (2) Solder layers 12 and 14 under the semiconductor chips 2 to 5, (3) Solder layer 16 under the insulating substrate 9, and (4) Base 10 and cooler 11 of the semiconductor module 1 The grease layer 17 present on the joint surface is mainly assumed.

例えば、熱抵抗を評価する方法で、個々の接合の劣化を評価する場合、冷却器１１の温度、ベース１０の温度、絶縁基板９の温度及び半導体チップ２〜５のいずれか温度と、最低４箇所の温度を計測する必要がある。これら各箇所に熱電対等の接触式温度センサを省スペースで取り付けることは困難であるため、これらすべての温度を計測することは一般的に困難である。一方、半導体チップ２〜５の温度のみを計測するのであれば、オンチップセンサで計測することができる。オンチップセンサは、例えば、半導体素子（ＩＧＢＴやダイオード）の静特性（オン抵抗）が温度に依存することを利用して、一定の電流を通電したときに半導体素子で発生する電圧降下に基づいて温度を計測する計測器である。すなわち、半導体チップ２〜５から冷却器１１のトータルの熱抵抗（冷却器１１−半導体チップ２〜５間の熱抵抗）は、現技術で計測することができる。   For example, when evaluating deterioration of individual junctions by a method of evaluating thermal resistance, the temperature of the cooler 11, the temperature of the base 10, the temperature of the insulating substrate 9, and any one of the semiconductor chips 2 to 5 and at least 4 It is necessary to measure the temperature at the location. Since it is difficult to attach a contact temperature sensor such as a thermocouple to each of these locations in a space-saving manner, it is generally difficult to measure all these temperatures. On the other hand, if only the temperature of the semiconductor chips 2 to 5 is measured, it can be measured by an on-chip sensor. An on-chip sensor is based on a voltage drop generated in a semiconductor element when a constant current is applied by utilizing the fact that the static characteristics (on resistance) of the semiconductor element (IGBT or diode) depends on temperature, for example. It is a measuring instrument that measures temperature. That is, the total thermal resistance from the semiconductor chips 2 to 5 to the cooler 11 (heat resistance between the cooler 11 and the semiconductor chips 2 to 5) can be measured with the current technology.

また、Ｘ線や超音波等によりはんだ層１２，１４，１６の接合部を計測し、熱負荷によるボイド率の変動による損傷を評価することができる。しかし、Ｘ線や超音波等の測定には、前処理が必要である（例えば、超音波探査測定は水中で計測するため、半導体モジュール１の防水処理が必要となる）。また、半導体チップ２〜５下のはんだ層１２，１４と絶縁基板９の下のはんだ層１６といった個々のはんだ層１２，１４，１６の像を十分な解像度で分離して取得するには、特定の方向からＸ線を照射する必要がある。これらの理由により、接合部をＸ線や超音波により測定するためには、技術と経験が必要となる場合がある。   Moreover, the junction part of the solder layers 12, 14, and 16 can be measured by X-rays, ultrasonic waves, etc., and the damage by the fluctuation | variation of the void ratio by a thermal load can be evaluated. However, pre-processing is required for measurement of X-rays, ultrasonic waves, and the like (for example, since the ultrasonic exploration measurement is performed in water, the semiconductor module 1 needs to be waterproofed). In addition, in order to separate and acquire images of the individual solder layers 12, 14, 16 such as the solder layers 12, 14 below the semiconductor chips 2-5 and the solder layer 16 below the insulating substrate 9 with sufficient resolution, it is necessary to specify It is necessary to irradiate X-rays from the direction. For these reasons, techniques and experience may be required to measure the joint by X-rays or ultrasonic waves.

また、電気特性（静特性やスイッチング特性等）の変動ではんだ層１２，１４を評価する試験は、その場で簡便に測定を行うことができるが、通電箇所の接合状態しか把握することができない。つまり、絶縁基板９下のはんだ層１６やグリース層１７の疲労を評価することが困難となるおそれがある。さらに、はんだ層１２，１４のボイド率がかなり増大した状態や、はんだ層１２，１４が剥がれた状態、あるいははんだ層１２，１４層内に亀裂がかなり進展した状態にならないと、はんだ層１２，１４の異常を電気特性の変動としてとらえることができない場合が少なくない。つまり、初期のはんだ層１２，１４の劣化、すなわち、はんだ層１２，１４の低疲労時の劣化を把握することが困難となるおそれがある。   In addition, the test for evaluating the solder layers 12 and 14 based on fluctuations in electrical characteristics (static characteristics, switching characteristics, etc.) can be easily measured on the spot, but can only grasp the joining state of the energized location. . That is, it may be difficult to evaluate the fatigue of the solder layer 16 and the grease layer 17 under the insulating substrate 9. Further, if the void ratio of the solder layers 12 and 14 is considerably increased, the solder layers 12 and 14 are peeled off, or the cracks are not sufficiently developed in the solder layers 12 and 14, the solder layers 12 and 14 In many cases, the 14 abnormalities cannot be regarded as fluctuations in electrical characteristics. That is, it may be difficult to grasp the initial deterioration of the solder layers 12 and 14, that is, the deterioration of the solder layers 12 and 14 at the time of low fatigue.

これらの理由により、従来、半導体モジュール１の接合部の評価（試験）は、これら３種の評価手法を組み合わせて、あるいはその他の評価手法も併用して、各接合部の疲労程度（信頼性）を評価している。   For these reasons, conventionally, the evaluation (test) of the joint portion of the semiconductor module 1 is a combination of these three kinds of evaluation methods or in combination with other evaluation methods, and the degree of fatigue of each joint portion (reliability). Is evaluated.

上記事情に鑑み、本発明は、半導体モジュールの接合部の状態を短時間で評価することに貢献する技術を提供することを目的とする。   In view of the above circumstances, an object of the present invention is to provide a technique that contributes to evaluating the state of a joint portion of a semiconductor module in a short time.

上記目的を達成する本発明の半導体モジュールの検査方法の一態様は、半導体素子と、前記半導体素子で構成される回路と、該回路と外部の回路とを接続する複数の電極端子と、を有する半導体モジュールの接合部の検査方法であって、前記電極端子間の寄生抵抗を計測し、各電極端子間で計測された寄生抵抗の経時変化を比較して、前記半導体モジュールの接合部の状態を検出することを特徴としている。   One aspect of the inspection method of a semiconductor module of the present invention that achieves the above object includes a semiconductor element, a circuit constituted by the semiconductor element, and a plurality of electrode terminals that connect the circuit and an external circuit. A method for inspecting a junction portion of a semiconductor module, wherein the parasitic resistance between the electrode terminals is measured, and the time-dependent change of the parasitic resistance measured between the electrode terminals is compared to determine the state of the junction portion of the semiconductor module. It is characterized by detecting.

また、上記目的を達成する本発明の半導体モジュールの検査方法の他の態様は、上記半導体モジュールの検査方法において、前記半導体素子の温度を計測し、各電極端子間で計測された寄生抵抗の経時変化と、前記半導体素子の温度の相関性に基づいて、前記半導体モジュールの接合部の異常が発生した箇所を特定することを特徴としている。   According to another aspect of the semiconductor module inspection method of the present invention for achieving the above object, in the semiconductor module inspection method, the temperature of the semiconductor element is measured, and the time of the parasitic resistance measured between the electrode terminals is measured. Based on the correlation between the change and the temperature of the semiconductor element, the location where the abnormality of the junction of the semiconductor module occurs is specified.

また、上記目的を達成する本発明の半導体モジュールの検査方法の他の態様は、半導体素子と、前記半導体素子で構成される回路と、該回路と外部の回路とを接続する複数の電極端子と、前記半導体素子を冷却する冷却器と、を有する半導体モジュールの接合部の検査方法であって、前記電極端子のいずれかと前記冷却器との間の静電容量と、該静電容量に対して直列に寄生する寄生抵抗と、を計測し、計測された静電容量の経時変化または計測された静電容量及び寄生抵抗の経時変化に基づいて、前記半導体モジュールの接合部の状態を検出することを特徴としている。   In another aspect of the semiconductor module inspection method of the present invention that achieves the above object, a semiconductor element, a circuit composed of the semiconductor element, and a plurality of electrode terminals that connect the circuit to an external circuit are provided. A method of inspecting a junction portion of a semiconductor module having a cooler that cools the semiconductor element, the capacitance between any of the electrode terminals and the cooler, and the capacitance And measuring the parasitic resistance that is parasitic in series and detecting the state of the junction of the semiconductor module based on the time-dependent change in the measured capacitance or the time-dependent change in the measured capacitance and parasitic resistance. It is characterized by.

また、上記目的を達成する本発明の半導体モジュールの検査方法の他の態様は、上記半導体モジュールの検査方法において、予め正常時における前記電極端子間の寄生抵抗を異なる測定周波数で計測しておき、検査対象となる半導体モジュールの電極端子間の寄生抵抗を測定周波数を変化させて計測し、計測された寄生抵抗と、該寄生抵抗が計測された測定周波数と同じ測定周波数で計測された正常時の寄生抵抗と、を比較して、前記半導体モジュールの接合部の状態を検出することを特徴としている。   In another aspect of the semiconductor module inspection method of the present invention that achieves the above object, in the semiconductor module inspection method, the parasitic resistance between the electrode terminals in a normal state is previously measured at different measurement frequencies. The parasitic resistance between the electrode terminals of the semiconductor module to be inspected is measured by changing the measurement frequency, and the measured parasitic resistance is measured at the same measurement frequency as the measured frequency. The parasitic resistance is compared to detect the state of the junction of the semiconductor module.

また、上記目的を達成する本発明の半導体システムの一態様は、半導体素子と、前記半導体素子で構成される回路と、該回路と外部の回路とを接続する複数の電極端子と、前記電極端子間の寄生抵抗を計測する計測手段と、各電極端子間で計測された寄生抵抗の経時変化を比較して、前記半導体モジュールの接合部の状態を検出する制御手段と、を有する
ことを特徴としている。 Another embodiment of the semiconductor system of the present invention that achieves the above object is to provide a semiconductor element, a circuit composed of the semiconductor element, a plurality of electrode terminals that connect the circuit and an external circuit, and the electrode terminal. Measuring means for measuring the parasitic resistance between, and control means for detecting the state of the junction part of the semiconductor module by comparing the time-dependent changes in the parasitic resistance measured between the respective electrode terminals. Yes.

また、上記目的を達成する本発明の半導体システムの他の態様は、半導体素子と、前記半導体素子で構成される回路と、該回路と外部の回路とを接続する複数の電極端子と、前記半導体素子を冷却する冷却器と、前記電極端子のいずれかと前記冷却器との間の静電容量と、該静電容量に対して直列に寄生する寄生抵抗とを計測する計測手段と、計測された静電容量の経時変化または計測された静電容量及び寄生抵抗の経時変化に基づいて、前記半導体モジュールの接合部の状態を検出する制御手段と、を有することを特徴としている。   According to another aspect of the semiconductor system of the present invention for achieving the above object, a semiconductor element, a circuit constituted by the semiconductor element, a plurality of electrode terminals connecting the circuit and an external circuit, and the semiconductor A cooling device that cools the device, a measuring unit that measures a capacitance between one of the electrode terminals and the cooling device, and a parasitic resistance that is parasitic in series with the capacitance, and was measured. And control means for detecting the state of the junction of the semiconductor module based on a change in capacitance with time or a change in measured capacitance and parasitic resistance with time.

以上の発明によれば、半導体モジュールの接合部の状態を短時間で評価することに貢献することができる。   According to the above invention, it can contribute to evaluating the state of the junction part of a semiconductor module in a short time.

本発明の実施形態に係る半導体モジュールの要部断面図である。It is principal part sectional drawing of the semiconductor module which concerns on embodiment of this invention. 図１に示された半導体モジュールの等価回路を示す図である。It is a figure which shows the equivalent circuit of the semiconductor module shown by FIG. Ｐ端子（若しくはＮ端子、ＡＣ端子）と冷却器端子との静電容量の時間変化を示す図である。It is a figure which shows the time change of the electrostatic capacitance of a P terminal (or N terminal, AC terminal) and a cooler terminal. 端子間の寄生抵抗の時間変化を示す図である。It is a figure which shows the time change of the parasitic resistance between terminals. 端子間の寄生抵抗と測定周波数との関係を示す図である。It is a figure which shows the relationship between the parasitic resistance between terminals, and a measurement frequency. 圧接型の半導体モジュールの要部断面図である。It is principal part sectional drawing of a pressure-contact type semiconductor module.

本発明の半導体モジュールの検査方法及び半導体システムについて、図面を参照して詳細に説明する。なお、図１，６に示す半導体モジュールの断面図は、本発明の実施形態に係る半導体モジュールを模式的に示したものであり、図面上の寸法比と実際の寸法比とは必ずしも一致するものではない。   A semiconductor module inspection method and a semiconductor system according to the present invention will be described in detail with reference to the drawings. The cross-sectional views of the semiconductor module shown in FIGS. 1 and 6 schematically show the semiconductor module according to the embodiment of the present invention, and the dimensional ratio on the drawings and the actual dimensional ratio do not necessarily match. is not.

まず、図１に示す半導体モジュール（２ｉｎ１モジュール）の接合部の検査を行う例を示して、本発明の実施形態に係る半導体モジュールの検査方法について説明する。   First, an inspection method for a semiconductor module according to an embodiment of the present invention will be described by showing an example in which a joint portion of the semiconductor module (2 in 1 module) shown in FIG. 1 is inspected.

図１に示す半導体モジュール１は、半導体チップ２〜５、主端子（Ｐ端子６、Ｎ端子７、ＡＣ端子８）、絶縁基板９、ベース１０、冷却器１１とを備える。   A semiconductor module 1 shown in FIG. 1 includes semiconductor chips 2 to 5, main terminals (P terminal 6, N terminal 7, AC terminal 8), an insulating substrate 9, a base 10, and a cooler 11.

半導体チップ２〜５は、例えば、ＩＧＢＴやＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）等のスイッチング素子と、このスイッチング素子に逆並列に接続されるＦＷＤ（Free Wheeling Diode）とにより構成される。半導体チップ２〜５の上面及び下面には、それぞれ主端子６〜８のいずれかと接続される図示省略の電極層が形成されている。なお、実施形態の説明では、便宜上、上面及び下面とするが、上下方向は、本発明をなんら限定するものではない。   The semiconductor chips 2 to 5 are configured by, for example, switching elements such as IGBTs and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and FWDs (Free Wheeling Diodes) connected in reverse parallel to the switching elements. On the upper and lower surfaces of the semiconductor chips 2 to 5, electrode layers (not shown) connected to any of the main terminals 6 to 8 are formed. In the description of the embodiment, for convenience, the upper surface and the lower surface are used, but the vertical direction does not limit the present invention.

Ｐ端子６は、絶縁基板９の回路箔９ａ上に設けられる。回路箔９ａには、それぞれはんだ層１２を介して半導体チップ２，３が設けられており、半導体チップ２，３が、はんだ層１２及び回路箔９ａを介してＰ端子６と接続される。半導体チップ２，３の上面の電極層には、ワイヤ１３の一端が超音波接合等により接合され、ワイヤ１３の他端は、回路箔９ａを介して（若しくは、直接）ＡＣ端子８に接合される。   The P terminal 6 is provided on the circuit foil 9 a of the insulating substrate 9. The circuit foil 9a is provided with semiconductor chips 2 and 3 via solder layers 12, respectively, and the semiconductor chips 2 and 3 are connected to the P terminal 6 via the solder layer 12 and the circuit foil 9a. One end of the wire 13 is bonded to the electrode layers on the upper surfaces of the semiconductor chips 2 and 3 by ultrasonic bonding or the like, and the other end of the wire 13 is bonded to the AC terminal 8 via the circuit foil 9a (or directly). The

ＡＣ端子８は、絶縁基板９の回路箔９ａ上に設けられる。回路箔９ａには、それぞれはんだ層１４を介して半導体チップ４，５が設けられており、半導体チップ４，５が、はんだ層１４及び回路箔９ａを介してＡＣ端子８と接続される。半導体チップ４，５の上面の電極層には、ワイヤ１５の一端が超音波接合やはんだ付け等により接合され、ワイヤ１５の他端はＮ端子７に接合される。   The AC terminal 8 is provided on the circuit foil 9 a of the insulating substrate 9. Semiconductor foils 4 and 5 are provided on the circuit foil 9a via solder layers 14, respectively, and the semiconductor chips 4 and 5 are connected to the AC terminal 8 via the solder layer 14 and circuit foil 9a. One end of the wire 15 is bonded to the electrode layers on the upper surfaces of the semiconductor chips 4 and 5 by ultrasonic bonding or soldering, and the other end of the wire 15 is bonded to the N terminal 7.

絶縁基板９は、例えば、ＤＢＣ基板等であり、その上面には回路箔９ａにより回路が形成されている。   The insulating substrate 9 is, for example, a DBC substrate or the like, and a circuit is formed on its upper surface by a circuit foil 9a.

ベース１０は、半導体モジュール１の放熱性を向上させるために絶縁基板９の下にはんだ層１６を介して設けられる。ベース１０は、熱伝導性の高い材料（例えば、銅等）により構成される。   The base 10 is provided under the insulating substrate 9 via the solder layer 16 in order to improve the heat dissipation of the semiconductor module 1. The base 10 is made of a material having high thermal conductivity (for example, copper).

冷却器１１は、ベース１０の下にグリース層１７を介して設けられ、半導体チップ２〜５で発生した熱を外部に放出する。冷却器１１には、冷却器端子１１ａ（プローブ）が設けられ、冷却器端子１１ａと主端子６〜８と間の静電容量やこの静電容量に直列に寄生する寄生抵抗が計測される。各端子（主端子６〜８や冷却器端子１１ａ）間の静電容量及びこの静電容量に直列に寄生する寄生抵抗は、ＬＣＲメータ若しくはインピーダンス・アナライザ等のインピーダンス計測器により計測される。   The cooler 11 is provided under the base 10 via a grease layer 17 and releases heat generated in the semiconductor chips 2 to 5 to the outside. The cooler 11 is provided with a cooler terminal 11a (probe), and a capacitance between the cooler terminal 11a and the main terminals 6 to 8 and a parasitic resistance parasitic in series with the capacitance are measured. The capacitance between the terminals (main terminals 6 to 8 and the cooler terminal 11a) and the parasitic resistance parasitic in series with the capacitance are measured by an impedance measuring instrument such as an LCR meter or an impedance analyzer.

なお、本発明の半導体システムは、半導体モジュール１と、半導体モジュール１の各主端子６〜８間または各主端子６〜８と冷却器端子１１ａ間の静電容量及び寄生抵抗を計測するインピーダンス計測器（図示省略）と、インピーダンス計測器の計測値の経時変化を評価する（または表示させる）制御部（図示省略）と、により構成される。   In addition, the semiconductor system of this invention is the impedance measurement which measures the electrostatic capacitance and parasitic resistance between the semiconductor module 1 and each main terminal 6-8 of the semiconductor module 1, or between each main terminal 6-8 and the cooler terminal 11a. And a control unit (not shown) for evaluating (or displaying) a change with time of the measurement value of the impedance measuring instrument.

図２は、図１に示した半導体モジュール１の等価回路を示す図である。   FIG. 2 is a diagram showing an equivalent circuit of the semiconductor module 1 shown in FIG.

この等価回路の静電容量成分は、半導体チップ２〜５の静電容量（上アーム側の半導体チップ２，３の静電容量Ｃ1、下アーム側の半導体チップ４，５の静電容量Ｃ2）、絶縁基板９の静電容量（Ｐ端子６面とベース１０間の静電容量Ｃ3、ＡＣ端子８面とベース１０間の静電容量Ｃ4及びＮ端子７面とベース１０間の静電容量Ｃ5）、グリース層１７の静電容量Ｃ6の６箇所に存在する。なお、図１に示した半導体モジュール１では図示省略しているが、Ｎ端子７の下部には、Ｐ端子６やＡＣ端子８と同様に、回路箔９ａや絶縁基板９が存在しており、静電容量Ｃ5は、この図示していないＮ端子７の下部の絶縁基板９の静電容量を示す。 The capacitance component of the equivalent circuit is the capacitance of the semiconductor chips 2 to 5 (capacitance C 1 of the semiconductor chips 2 and 3 on the upper arm side, and capacitance C 1 of the semiconductor chips 4 and 5 on the lower arm side). 2 ) Capacitance of the insulating substrate 9 (capacitance C 3 between the surface of the P terminal 6 and the base 10, capacitance C 4 between the surface of the AC terminal 8 and the base 10, and between the surface of the N terminal 7 and the base 10. The electrostatic capacity C 5 ) and the electrostatic capacity C 6 of the grease layer 17 exist at six locations. Although not shown in the semiconductor module 1 shown in FIG. 1, a circuit foil 9 a and an insulating substrate 9 exist in the lower part of the N terminal 7 like the P terminal 6 and the AC terminal 8. The electrostatic capacity C 5 indicates the electrostatic capacity of the insulating substrate 9 below the N terminal 7 (not shown).

一方、この等価回路の静電容量成分に対して直列に寄生する寄生抵抗として、上アーム側の半導体チップ２，３の下に設けられるはんだ層１２の損傷を反映する寄生抵抗ｒ1、上アーム側の半導体チップ２，３の上面電極層とワイヤ１３の接合状態を反映する寄生抵抗ｒ2、下アーム側の半導体チップ４，５の下に設けられるはんだ層１４の損傷を反映する寄生抵抗ｒ3、下アーム側の半導体チップ４，５の上面電極層とワイヤ１５の接合状態を反映する寄生抵抗ｒ4が存在する。また、主端子６〜８と冷却器端子１１ａとの間には、それぞれ絶縁基板９下のはんだ層１６の損傷を反映する寄生抵抗ｒ5，ｒ6，ｒ7が存在する。 On the other hand, the parasitic resistance r 1 reflecting the damage of the solder layer 12 provided below the semiconductor chips 2 and 3 on the upper arm side as the parasitic resistance parasitic in series with the capacitance component of the equivalent circuit, the upper arm Parasitic resistance r 2 reflecting the bonding state of the upper surface electrode layer of the semiconductor chip 2, 3 on the side and the wire 13, and parasitic resistance r reflecting damage of the solder layer 14 provided under the semiconductor chip 4, 5 on the lower arm side 3 , there is a parasitic resistance r 4 reflecting the bonding state between the upper electrode layer of the semiconductor chip 4, 5 on the lower arm side and the wire 15. In addition, parasitic resistances r 5 , r 6 , and r 7 that reflect damage to the solder layer 16 under the insulating substrate 9 exist between the main terminals 6 to 8 and the cooler terminal 11a, respectively.

次に、本発明の実施形態に係る半導体モジュール１の検査方法及び半導体システムにより、具体的な損傷個所を特定する方法について詳細に説明する。   Next, a detailed description will be given of a method for identifying a specific damaged portion by the semiconductor module 1 inspection method and semiconductor system according to the embodiment of the present invention.

実施形態に係る半導体モジュール１の検査方法及び半導体システムでは、Ｐ端子６−Ｎ端子７間、Ｐ端子６−ＡＣ端子８間、Ｎ端子７−ＡＣ端子８間、Ｐ端子６−冷却器端子１１ａ間、Ｎ端子７−冷却器端子１１ａ間、ＡＣ端子８−冷却器端子１１ａ間、の６つの端子間の静電容量とこの静電容量に直列に寄生する寄生抵抗とを、ＬＣＲメータ若しくはインピーダンス・アナライザ等のインピーダンス計測器を用いて計測する。   In the inspection method and semiconductor system of the semiconductor module 1 according to the embodiment, between the P terminal 6 and the N terminal 7, between the P terminal 6 and the AC terminal 8, between the N terminal 7 and the AC terminal 8, the P terminal 6 and the cooler terminal 11a. Between the N terminal 7 and the cooler terminal 11a, between the AC terminal 8 and the cooler terminal 11a, and the parasitic resistance that is parasitic in series with the electrostatic capacity, an LCR meter or impedance・ Measure using an impedance measuring instrument such as an analyzer.

静電容量及び寄生抵抗の計測は、表皮効果が支配的となる周波数（例えば、１００ｋＨｚより高い周波数で行う。測定周波数を上げるほど、電流は各部材の表面または界面（例えば、はんだ下の配線層とはんだ層の界面）を経由して流れるため、寄生抵抗の計測値は、はんだ層表面の電気抵抗、表面のマクロな凹凸、合金層形成等による材料の抵抗率の変化を反映することとなる。   Capacitance and parasitic resistance are measured at a frequency at which the skin effect is dominant (for example, a frequency higher than 100 kHz. The higher the measurement frequency, the more current flows on the surface or interface of each member (for example, the wiring layer under the solder). The measured value of the parasitic resistance reflects the change in the resistivity of the material due to the electrical resistance of the solder layer surface, macro unevenness of the surface, alloy layer formation, etc. .

さらに、半導体チップ２〜５に、図示省略のオンチップセンサ（温度により特性が変化するセンサ、例えば、ダイオード）を設け、半導体チップ２〜５の温度を計測する。なお、オンチップセンサは、半導体チップ２〜５の内部または半導体チップ２〜５の近傍に設けてもよい。   Furthermore, on-chip sensors (not shown) (sensors whose characteristics change with temperature, for example, diodes) are provided on the semiconductor chips 2 to 5, and the temperatures of the semiconductor chips 2 to 5 are measured. The on-chip sensor may be provided inside the semiconductor chips 2 to 5 or in the vicinity of the semiconductor chips 2 to 5.

［グリース層１７の検査］
グリース層１７の劣化（損傷）は、例えば、図３に示すように、Ｐ端子６（またはＮ端子７、ＡＣ端子８）と冷却器端子１１ａ間の静電容量を常時モニタ（或いは定期的にモニタ）し、初期に計測された静電容量からの低下度合いにより把握することができる。 [Inspection of grease layer 17]
For example, as shown in FIG. 3, the grease layer 17 is deteriorated (damaged) by constantly monitoring the capacitance between the P terminal 6 (or N terminal 7 and AC terminal 8) and the cooler terminal 11a (or periodically). Monitor) and can be grasped by the degree of decrease from the capacitance measured initially.

グリース層１７内でのボイド（空隙）が発生したり、グリース抜け（ポンプアウト）が生じたりすると、グリース層１７の静電容量が低下する。したがって、Ｐ端子６−冷却器端子１１ａ間、Ｎ端子７−冷却器端子１１ａ間、及びＡＣ端子８−冷却器端子１１ａ間の静電容量と寄生抵抗を計測し、各端子間で計測された寄生抵抗のいずれにも変化がなく、各端子間で計測された静電容量の低下が確認された場合、グリース層１７の劣化が起こったと判断することができる。つまり、各端子間で計測された寄生抵抗の変化がないことで、はんだ層１６やワイヤ１５の接合部における劣化が起こっていないと判断することができるので、各端子間で計測された静電容量の低下が、グリース層１７の劣化を反映していると判断できる。   If a void (gap) is generated in the grease layer 17 or grease is removed (pumped out), the capacitance of the grease layer 17 decreases. Therefore, the capacitance and parasitic resistance between the P terminal 6 and the cooler terminal 11a, between the N terminal 7 and the cooler terminal 11a, and between the AC terminal 8 and the cooler terminal 11a were measured and measured between the terminals. If there is no change in any of the parasitic resistances and a decrease in the capacitance measured between the terminals is confirmed, it can be determined that the grease layer 17 has deteriorated. That is, since there is no change in the parasitic resistance measured between the terminals, it can be determined that the solder layer 16 and the joint of the wire 15 are not deteriorated. It can be determined that the decrease in the capacity reflects the deterioration of the grease layer 17.

［はんだ層１２，１４，１６の検査（劣化位置の特定）］
はんだ層１２，１４，１６の劣化（損傷）箇所は、例えば、図４に示すように、各端子６〜８，１１ａ間で計測される寄生抵抗（静電容量に対して直列に寄生する寄生抵抗）をモニタしておき、初期に計測された寄生抵抗からの増加の度合いに基づいて把握する。 [Inspection of solder layers 12, 14, 16 (determination of deterioration position)]
For example, as shown in FIG. 4, the deterioration (damage) portion of the solder layers 12, 14, 16 is a parasitic resistance measured between the terminals 6-8, 11a (parasitism in series with respect to the capacitance). Resistance) is monitored and grasped based on the degree of increase from the parasitic resistance measured in the initial stage.

図４に示す例では、Ｐ端子６−Ｎ端子７間と、Ｐ端子６−ＡＣ端子８間の寄生抵抗が増大し、その他端子間の寄生抵抗が増大していない。この場合、上アーム側の半導体チップ２，３の下に設けられるはんだ層１２の損傷、あるいは上アーム側の半導体チップ２，３の上面電極層とワイヤ１３の接合部の損傷が疑われる。   In the example shown in FIG. 4, the parasitic resistance between the P terminal 6 and the N terminal 7 and between the P terminal 6 and the AC terminal 8 is increased, and the parasitic resistance between the other terminals is not increased. In this case, damage to the solder layer 12 provided under the semiconductor chips 2 and 3 on the upper arm side, or damage to the joint between the upper electrode layer of the semiconductor chips 2 and 3 on the upper arm side and the wire 13 is suspected.

はんだ層１２の損傷は、ワイヤ１３の接合部の損傷と比較して、半導体チップ２，３の温度との相関が高い。よって、オンチップセンサ（図示せず）で半導体チップ２，３の温度を計測し、半導体チップ２，３の温度上昇が確認できなかった場合、主としてワイヤ１３の接合部の損傷がおきていると判断できる。   The damage of the solder layer 12 has a higher correlation with the temperature of the semiconductor chips 2 and 3 than the damage of the joint portion of the wire 13. Therefore, when the temperature of the semiconductor chips 2 and 3 is measured by an on-chip sensor (not shown) and the temperature rise of the semiconductor chips 2 and 3 cannot be confirmed, the joint portion of the wire 13 is mainly damaged. I can judge.

なお、半導体チップ２〜５下のはんだ層１２，１４や絶縁基板９の下はんだ層１６の剥がれが一定以上進行すると、図３に示したグリース層１７の静電容量の経時変化と同様に、はんだ層１２，１４，１６の剥がれが、各端子６〜８，１１ａ間の静電容量の低下として検出される。よって、各端子６〜８，１１ａ間の寄生抵抗の増大だけでなく、各端子６〜８，１１ａ間の静電容量の低下の検出をはんだ層１２，１４，１６の劣化指標として用いることができる。   When the peeling of the solder layers 12 and 14 below the semiconductor chips 2 to 5 and the lower solder layer 16 of the insulating substrate 9 proceeds to a certain level or more, as with the change with time of the capacitance of the grease layer 17 shown in FIG. The peeling of the solder layers 12, 14, 16 is detected as a decrease in the capacitance between the terminals 6-8, 11a. Therefore, not only the increase in the parasitic resistance between the terminals 6 to 8 and 11 a but also the detection of the decrease in the capacitance between the terminals 6 to 8 and 11 a can be used as a deterioration index of the solder layers 12, 14 and 16. it can.

［はんだ層１２，１４，１６の検査（深さ方向の特定）］
はんだ層１２，１４，１６の深さ方向の劣化は、例えば、図５に示すように、各端子６〜８，１１ａ間の寄生抵抗を測定周波数を変えて計測し、各測定周波数で計測された寄生抵抗と、接合正常時に各測定周波数で計測された寄生抵抗（例えば、初期に各測定周波数で計測された寄生抵抗）とを、比較することで把握する。 [Inspection of solder layers 12, 14, 16 (specification of depth direction)]
Degradation in the depth direction of the solder layers 12, 14, and 16 is measured at each measurement frequency by measuring the parasitic resistance between the terminals 6 to 8 and 11a by changing the measurement frequency, for example, as shown in FIG. By comparing the parasitic resistance measured with the parasitic resistance measured at each measurement frequency when the junction is normal (for example, the parasitic resistance measured at each measurement frequency in the initial stage).

図５に示すように、正常な接合形成時には、表皮効果が始まる周波数域（例えば、１００ｋＨｚ以上）で測定周波数の増大とともに線形に寄生抵抗が増大する。これに対して、表面からある深さ内ではんだ層１２，１４，１６の剥がれ（接触電気抵抗の増大）、亀裂進展、若しくは変質（合金層の形成）が起こった場合、その深さ以内で電流が流れる測定周波数で計測した寄生抵抗に変極点（周波数と寄生抵抗の関係における傾きの増大）が発生する。この傾きの変化が発生した測定周波数に基づいて、損傷領域（表面からの深さ）を類推することができる。   As shown in FIG. 5, at the time of normal junction formation, the parasitic resistance increases linearly with the increase of the measurement frequency in the frequency range where the skin effect starts (for example, 100 kHz or more). On the other hand, if the solder layers 12, 14, and 16 are peeled (increased contact electric resistance), crack progress, or alteration (formation of alloy layer) occurs within a certain depth from the surface, within that depth An inflection point (increase in slope in the relationship between frequency and parasitic resistance) occurs in the parasitic resistance measured at the measurement frequency through which the current flows. The damaged area (depth from the surface) can be inferred based on the measurement frequency at which this change in inclination occurs.

以上のような本発明の実施形態に係る半導体モジュール１の検査方法及び半導体システムによれば、主端子６〜８間（若しくは主端子６〜８と冷却器端子１１ａ間）の静電容量やこの静電容量に対して直列に寄生する寄生抵抗を、特定の測定周波数あるいは測定周波数を変化させて計測することで、損傷が発生した接合箇所を簡易的に検出することができる。また、主端子６〜８間（若しくは主端子６〜８と冷却器端子１１ａ間）の静電容量及びこの静電容量に対して直列に寄生する寄生抵抗の経時変化を評価することで、半導体チップ２〜５下のはんだ層１２，１４、半導体チップ２〜５上のワイヤ１３，１５接合部、グリース層１７、絶縁基板９下のはんだ層１６等の各接合の損傷具合を切り分けて評価することができる。   According to the inspection method and the semiconductor system of the semiconductor module 1 according to the embodiment of the present invention as described above, the capacitance between the main terminals 6 to 8 (or between the main terminals 6 to 8 and the cooler terminal 11a) By measuring the parasitic resistance that is parasitic in series with the capacitance by changing the specific measurement frequency or the measurement frequency, it is possible to easily detect the joint portion where the damage has occurred. Further, by evaluating the change in the capacitance between the main terminals 6 to 8 (or between the main terminals 6 to 8 and the cooler terminal 11a) and the parasitic resistance parasitic in series with the capacitance, the semiconductor The damage levels of each joint such as the solder layers 12 and 14 under the chips 2 to 5, the wires 13 and 15 joints on the semiconductor chips 2 to 5, the grease layer 17 and the solder layer 16 under the insulating substrate 9 are separated and evaluated. be able to.

また、本発明の実施形態に係る半導体モジュール１の検査方法及び半導体システムによれば、その場で、特別な事前処理等なしに、短時間に、半導体モジュール１の信頼性の評価や疲労度の評価を行うことができる。つまり、半導体モジュール１の信頼性試験中あるいは実動作中にオンライン若しくはオフラインで（定期的に）端子間の静電容量や寄生抵抗を計測して半導体モジュール１の接合部を評価することができる。つまり、半導体モジュール１の接合部の信頼性を監視したり、検査したりすることができる。   Moreover, according to the inspection method and the semiconductor system of the semiconductor module 1 according to the embodiment of the present invention, the reliability evaluation and the fatigue degree of the semiconductor module 1 can be performed in a short time in a short time without special pre-processing. Evaluation can be made. That is, the junction of the semiconductor module 1 can be evaluated by measuring the capacitance and parasitic resistance between terminals online or offline (periodically) during the reliability test or actual operation of the semiconductor module 1. That is, the reliability of the joint portion of the semiconductor module 1 can be monitored or inspected.

また、半導体チップ２〜５の温度の計測値あるいは周囲環境と半導体チップ２〜５間の熱抵抗の評価と組み合わせることで、より正確に接合の不良箇所を同定することができる。   Further, by combining the measurement value of the temperature of the semiconductor chips 2 to 5 or the evaluation of the thermal resistance between the surrounding environment and the semiconductor chips 2 to 5, it is possible to more accurately identify the bonding failure location.

また、各端子６〜８，１１ａ間の静電容量及び寄生抵抗を測定周波数を変えて（例えば、１００ｋＨｚ〜１０ＭＨｚ）計測し、各端子６〜８，１１ａ間の寄生抵抗成分等を評価することで、損傷、亀裂、あるいは変質（合金層の形成等）が表面からどの程度の深さの領域まで発生しているかを予測することができる。つまり、不良発生の空間的な位置を具体的に類推することができる。はんだ層１２，１４，１６の劣化（亀裂発生等）は、表面や界面から発生することが知られており、測定周波数をかえることによる寄生抵抗の変化をモニタ、正常接合形成時と比較することで、損傷発生位置の表面からの深さを類推することができる。   Further, the capacitance and parasitic resistance between the terminals 6 to 8 and 11a are measured by changing the measurement frequency (for example, 100 kHz to 10 MHz), and the parasitic resistance component between the terminals 6 to 8 and 11a is evaluated. Thus, it is possible to predict to what extent the damage, crack, or alteration (formation of alloy layer, etc.) has occurred from the surface. That is, it is possible to specifically estimate the spatial position where the defect occurs. Degradation (cracking etc.) of the solder layers 12, 14, 16 is known to occur from the surface or interface, and the change in the parasitic resistance due to changing the measurement frequency is monitored and compared with the normal junction formation. Thus, the depth from the surface of the damage occurrence position can be analogized.

本発明の実施形態に係る半導体モジュール１の検査方法及び半導体システムによれば、ダメージレスの簡易的な評価で、任意の使用条件における接合のウィークポイントの把握が可能となる。よって、半導体モジュール１の使い方の改善（制御、冷却）、半導体モジュール１の使用材料、構成、構造の対策を考案するスピードが速くなり、半導体モジュール１の開発工程を加速させることができる。   According to the inspection method and semiconductor system of the semiconductor module 1 according to the embodiment of the present invention, it is possible to grasp the weak point of the junction under an arbitrary use condition by simple evaluation without damage. Therefore, improvement of how to use the semiconductor module 1 (control, cooling), speed of devising countermeasures for the materials, configuration, and structure of the semiconductor module 1 are increased, and the development process of the semiconductor module 1 can be accelerated.

以上、本発明の半導体モジュールの検査方法及び半導体システムについて、具体例を示して詳細に説明したが、本発明の半導体モジュールの検査方法及び半導体システムは、上述した実施形態に限らず、本発明の特徴を損なわない範囲で適宜設計変更が可能である。   The semiconductor module inspection method and semiconductor system of the present invention have been described in detail with specific examples. However, the semiconductor module inspection method and semiconductor system of the present invention are not limited to the above-described embodiments, and Design changes can be made as appropriate without departing from the characteristics.

例えば、スイッチングデバイスを検査する場合には、制御端子と各端子（主端子（Ｐ端子、Ｎ端子またはＡＣ端子若しくは冷却器端子）間の静電容量や寄生抵抗を計測することで、実施形態に係る半導体モジュール１の検査方法と同様の方法で、制御用ワイヤ内の接合の損傷（信頼性）も評価することができる。   For example, when a switching device is inspected, the capacitance and parasitic resistance between the control terminal and each terminal (main terminal (P terminal, N terminal, AC terminal, or cooler terminal)) are measured. The damage (reliability) of the joint in the control wire can be evaluated by the same method as the inspection method of the semiconductor module 1.

また、半導体チップの温度の計測は、オンチップセンサに限定されるものではなく、例えば、熱電対や放射温度計を用いて計測することもできる。   Further, the measurement of the temperature of the semiconductor chip is not limited to the on-chip sensor, and for example, it can be measured using a thermocouple or a radiation thermometer.

また、実施形態の説明では、２ｉｎ１の半導体モジュール１を例として説明しているが、半導体モジュールの回路構成は、適宜使用態様に応じて設計変更が可能であり、半導体チップの数や種類等は任意に設定可能である。   In the description of the embodiment, the 2-in-1 semiconductor module 1 is described as an example. However, the circuit configuration of the semiconductor module can be appropriately changed in accordance with the usage mode. It can be set arbitrarily.

また、図６に示すように、半導体チップ１８，１９の上下に冷却器２０，２１を設け、冷却器２０，２１をボルト２２とナット２３で締結して、主端子２４，２５を半導体チップ１８，１９に圧接する圧接型の半導体モジュール２６の検査を行う場合に、本発明の半導体モジュールの検査方法を適用することもできる。この場合、上下の冷却器２０，２１にそれぞれ冷却器端子（図示省略）を設け、各冷却器端子と主端子２４，２５（若しくは制御端子２７）との間の静電容量とこの静電容量に直列に寄生する寄生抵抗とを計測することで、実施形態の半導体モジュールの検査方法及び半導体システムと同様に、各接合部を評価することができる。   Further, as shown in FIG. 6, coolers 20 and 21 are provided above and below the semiconductor chips 18 and 19, the coolers 20 and 21 are fastened with bolts 22 and nuts 23, and the main terminals 24 and 25 are connected to the semiconductor chips 18. , 19, the semiconductor module inspection method of the present invention can also be applied. In this case, each of the upper and lower coolers 20 and 21 is provided with a cooler terminal (not shown), and the capacitance between each cooler terminal and the main terminals 24 and 25 (or the control terminal 27) and this capacitance. By measuring the parasitic resistance parasitic in series with each other, each junction can be evaluated as in the semiconductor module inspection method and semiconductor system of the embodiment.

１，２６…半導体モジュール
２〜５，１８，１９…半導体チップ（半導体素子）
６…Ｐ端子（電極端子）
７…Ｎ端子（電極端子）
８…ＡＣ端子（電極端子）
９…絶縁基板
９ａ…回路箔
１０…ベース
１１，２０，２１…冷却器
１１ａ…冷却器端子
２４，２５…主端子
２７…制御端子 1, 26 ... Semiconductor modules 2 to 5, 18, 19 ... Semiconductor chips (semiconductor elements)
6 ... P terminal (electrode terminal)
7. N terminal (electrode terminal)
8 ... AC terminal (electrode terminal)
DESCRIPTION OF SYMBOLS 9 ... Insulating substrate 9a ... Circuit foil 10 ... Base 11, 20, 21 ... Cooler 11a ... Cooler terminal 24, 25 ... Main terminal 27 ... Control terminal

Claims (6)

半導体素子と、前記半導体素子で構成される回路と、該回路と外部の回路とを接続する複数の電極端子と、を有する半導体モジュールの接合部の検査方法であって、
前記電極端子間の寄生抵抗を計測し、
各電極端子間で計測された寄生抵抗の経時変化を比較して、前記半導体モジュールの接合部の状態を検出する
ことを特徴とする半導体モジュールの検査方法。 A method for inspecting a junction part of a semiconductor module comprising a semiconductor element, a circuit constituted by the semiconductor element, and a plurality of electrode terminals connecting the circuit and an external circuit,
Measure the parasitic resistance between the electrode terminals,
A method for inspecting a semiconductor module, comprising comparing a time-dependent change in parasitic resistance measured between each electrode terminal and detecting a state of a junction of the semiconductor module. 前記半導体素子の温度を計測し、各電極端子間で計測された寄生抵抗の経時変化と、前記半導体素子の温度の相関性に基づいて、前記半導体モジュールの接合部の異常が発生した箇所を特定する
ことを特徴とする請求項１に記載の半導体モジュールの検査方法。 Measure the temperature of the semiconductor element, and identify the location where the abnormality of the junction part of the semiconductor module occurred based on the correlation between the time-dependent change of the parasitic resistance measured between each electrode terminal and the temperature of the semiconductor element The method for inspecting a semiconductor module according to claim 1. 半導体素子と、前記半導体素子で構成される回路と、該回路と外部の回路とを接続する複数の電極端子と、前記半導体素子を冷却する冷却器と、を有する半導体モジュールの接合部の検査方法であって、
前記電極端子のいずれかと前記冷却器との間の静電容量と、該静電容量に対して直列に寄生する寄生抵抗と、を計測し、
計測された静電容量の経時変化または計測された静電容量及び寄生抵抗の経時変化に基づいて、前記半導体モジュールの接合部の状態を検出する
ことを特徴とする半導体モジュールの検査方法。 A method for inspecting a junction part of a semiconductor module, comprising: a semiconductor element; a circuit composed of the semiconductor element; a plurality of electrode terminals that connect the circuit to an external circuit; and a cooler that cools the semiconductor element. Because
A capacitance between any of the electrode terminals and the cooler, and a parasitic resistance parasitic in series with the capacitance;
A method for inspecting a semiconductor module, comprising: detecting a state of a junction portion of the semiconductor module based on a change with time of measured capacitance or a change with time of measured capacitance and parasitic resistance. 予め正常時における前記電極端子間の寄生抵抗を異なる測定周波数で計測しておき、
検査対象となる半導体モジュールの電極端子間の寄生抵抗を測定周波数を変化させて計測し、
計測された寄生抵抗と、該寄生抵抗が計測された測定周波数と同じ測定周波数で計測された正常時の寄生抵抗と、を比較して、前記半導体モジュールの接合部の状態を検出する
ことを特徴とする請求項１から請求項３のいずれか１項に記載の半導体モジュールの検査方法。 Preliminarily measure the parasitic resistance between the electrode terminals at normal times at different measurement frequencies,
Measure the parasitic resistance between the electrode terminals of the semiconductor module to be inspected by changing the measurement frequency,
Comparing the measured parasitic resistance with a normal parasitic resistance measured at the same measurement frequency as the measurement frequency of the parasitic resistance, and detecting the state of the junction of the semiconductor module A method for inspecting a semiconductor module according to any one of claims 1 to 3. 半導体素子と、
前記半導体素子で構成される回路と、
該回路と外部の回路とを接続する複数の電極端子と、
前記電極端子間の寄生抵抗を計測する計測手段と、
各電極端子間で計測された寄生抵抗の経時変化を比較して、前記半導体モジュールの接合部の状態を検出する制御手段と、を有する
ことを特徴とする半導体システム。 A semiconductor element;
A circuit composed of the semiconductor element;
A plurality of electrode terminals connecting the circuit and an external circuit;
Measuring means for measuring the parasitic resistance between the electrode terminals;
And a control means for detecting a state of a joint portion of the semiconductor module by comparing a time-dependent change in parasitic resistance measured between the electrode terminals. 半導体素子と、
前記半導体素子で構成される回路と、
該回路と外部の回路とを接続する複数の電極端子と、
前記半導体素子を冷却する冷却器と、
前記電極端子のいずれかと前記冷却器との間の静電容量と、該静電容量に対して直列に寄生する寄生抵抗とを計測する計測手段と、
計測された静電容量の経時変化または計測された静電容量及び寄生抵抗の経時変化に基づいて、前記半導体モジュールの接合部の状態を検出する制御手段と、を有する
ことを特徴とする半導体システム。 A semiconductor element;
A circuit composed of the semiconductor element;
A plurality of electrode terminals connecting the circuit and an external circuit;
A cooler for cooling the semiconductor element;
A measuring means for measuring a capacitance between any of the electrode terminals and the cooler, and a parasitic resistance parasitic in series with the capacitance;
Control means for detecting a state of a junction portion of the semiconductor module based on a time-dependent change of the measured capacitance or a time-dependent change of the measured capacitance and parasitic resistance. .
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