JP2015088850A - Signal detection circuit, optical receiver, base station device and signal detection method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal detection circuit and the like capable of detecting signal input at high speed in the head of a packet signal and detecting signal interruption at high speed in the end of the packet signal.SOLUTION: A DC voltage is removed from a differential signal that a preamplifier circuit 140 outputs, and a predetermined bias voltage between differentials is given, thereby producing a differential signal for detection. On the basis of the differential signal for detection, a reset signal generation circuit 115 generates an internal reset signal. A flip-flop circuit 117 inputs the differential signal for detection to an input terminal, inputs the internal reset signal to a reset terminal and outputs a packet detection signal. The reset signal generation part 115 remains a voltage in the case where the differential signal for detection is converted into a single-phase signal, and generates the internal reset signal that is an exclusive OR of a result of comparing the retained voltage value with two predetermined threshold voltages which are different from each other.

Description

  The present invention relates to a signal detection circuit, an optical receiver, a master station apparatus, and a signal detection method for detecting signal input and signal interruption.

  In recent access networks, a one-to-many optical communication system called a PON (Passive Optical Network) system is widely used.

  In the one-to-multiple optical communication system, time division multiplexing is applied to uplink communication from a slave station device to a master station device, and an uplink signal received by the master station device is transmitted from each slave station device. A burst-shaped packet signal is time-division multiplexed at intervals. Here, the master station device includes a signal detection circuit that performs signal detection for each packet signal in order to determine whether or not a packet signal is received. However, it is required to increase the response speed.

  The conventional signal detection circuit branches the output of the preamplifier circuit, inputs one to the differential amplifier, removes the DC voltage due to the series capacitance on the other, and then adds a DC voltage difference between the differentials to create an SR flip-flop By inputting the signal into the network, the head of the packet signal is identified at high speed, and the input of the burst packet signal is detected (for example, Patent Document 1).

  The optical receiving circuit described in Patent Literature 1 is described as receiving the reset signal from the outside after the end of the packet signal, thereby releasing the latched state of the SR flip-flop circuit and performing signal disconnection detection. However, this optical receiver circuit cannot detect a signal interruption unless it can receive a reset signal from the outside, and cannot detect subsequent signal input.

  On the other hand, there are systems in which it is difficult to input a reset signal due to a limitation on the number of interface pins between the optical receiver circuit and the control circuit in the master station device. As a conventional circuit capable of detecting a burst-like packet signal even in such a system that does not receive a reset signal from the outside, there is a configuration including an analog holding circuit that holds the output voltage of the preamplifier circuit (for example, Patent Documents). 2).

  The optical signal break detection circuit described in Patent Document 2 uses a capacitor of an analog holding circuit and a resistor capable of discharging a charge stored in the capacitor to charge and discharge the output of the preamplifier circuit. It is described that signal input detection can be performed when a packet signal is received, and signal disconnection can be detected when there is no signal.

JP 2009-44228 A JP 2011-166659 A

  The SR flip-flop circuit in the signal detection circuit provided in the optical receiving circuit described in Patent Document 1 is held in a state where the signal at the head portion of the packet is detected, and can be detected at a high speed. Until the reset from is input, the SR flip-flop circuit holds the state.

  When the reset is input to the SR flip-flop circuit, the holding state is released, the state is changed to the signal cut state, and the data waiting state is entered. At this time, since the signal detection circuit maintains the signal input detection state from the end of the packet until the next reset signal is input, there is a possibility that the master station apparatus erroneously detects the signal.

  In addition, the optical signal break detection circuit described in Patent Document 2 has a constant charge / discharge rate determined by the capacitance and resistance value of the analog holding circuit, so that the CID (Consecutive Identity Digit) signal in the burst signal is There is a possibility that signal interruption is erroneously detected when the same sign signal is continuous. It has been difficult to avoid erroneous detection due to a CID signal or the like and to increase the signal detection speed at the head of the packet signal.

  The present invention has been made in view of the above circumstances, such as a signal detection circuit capable of detecting a signal input at a high speed at the beginning of a packet signal and detecting a signal break at a high speed at the end of the packet signal. The purpose is to provide.

  In order to achieve the above object, the signal detection circuit of the present invention includes a DC voltage removing unit that removes a DC voltage from an input differential signal including a bursty packet signal, and a signal from which the DC voltage is removed by the DC voltage removing unit. A bias voltage application unit that generates a differential signal for detection by applying a bias voltage between predetermined differentials, and a reset that generates an internal reset signal after the beginning and end of the packet signal based on the differential signal for detection The signal generation unit holds the state indicating the packet signal input based on the detection differential signal, and releases the holding based on the internal reset signal, thereby generating a packet detection signal indicating the signal input and signal disconnection of the packet signal. A packet detection signal generation unit to be generated. The reset signal generation unit determines in advance a differential single-phase conversion circuit that converts a detection differential signal into a single-phase signal, a voltage holding circuit that holds the voltage of the single-phase signal, and a voltage that the voltage holding circuit holds. And a voltage comparison circuit for generating an internal reset signal based on the result of comparison with the threshold voltage.

  According to the present invention, it is possible to detect a signal input at a high speed at the beginning of a packet signal and to detect a signal break at a high speed when the packet signal ends.

It is a block diagram which shows the structure of the optical communication system which concerns on embodiment. It is a figure which shows the circuit structure of an optical receiver. FIG. 3 is a diagram illustrating a circuit configuration of a packet signal detection circuit according to the first embodiment. FIG. 4 is a diagram illustrating a timing chart of signals of respective units in the optical receiver according to the first embodiment. FIG. 4 is a diagram illustrating a circuit configuration of a packet signal detection circuit according to a second embodiment. FIG. 10 is a diagram illustrating a timing chart of signals of respective units in the optical receiver according to the second embodiment. FIG. 6 is a diagram illustrating a circuit configuration of a packet signal detection circuit according to a third embodiment.

Embodiment 1 FIG.
Embodiments of the present invention will be described in detail with reference to the drawings.

  The optical communication system 1 according to the present embodiment is a PON (Passive Optical Network) system adopting a one-to-many optical communication format. As shown in FIG. 1, the optical communication system 1 includes one OLT (Optical Line Terminal: optical subscriber line terminating device) 10 that is a master station device and an ONU (Optical Network Unit) that is a plurality of slave stations. Optical network device) 20 and an optical star coupler 30 for passively branching and joining optical signals. All the ONUs 20 are connected to the OLT 10 via one or more optical star couplers 30 and optical fibers 32.

  The OLT 10 includes an optical receiver 11, an optical transmitter 12, a wavelength multiplexing coupler 13, and a transmission control unit 14. The wavelength multiplexing coupler 13 is for outputting a downstream signal and an upstream signal having different optical wavelengths in a predetermined direction. The optical signal output from the ONU 20 and transmitted through the optical fiber 32 is output to the optical receiver 11 side, and the optical signal output from the optical transmitter 12 is output to the optical fiber 32 side to which the ONU 20 is connected. .

  The transmission control unit 14 generates a modulation signal based on a baseband signal input from an external network 40 such as the Internet and inputs the modulation signal to the optical transmitter 12. The optical transmitter 12 modulates light emitted from a light emitting element such as a semiconductor laser with a modulation signal input from the transmission control unit 14. The modulated optical signal is output as a downstream signal via the wavelength multiplexing coupler 13, transmitted through the optical fiber 32, and received by each ONU 20.

  The upstream optical signal transmitted from the ONU 20 and transmitted through the optical fiber 32 is input to the optical receiver 11 via the wavelength multiplexing coupler 13. The optical receiver 11 photoelectrically converts the input optical signal, demodulates the received optical signal into a received signal, and outputs the received signal to the transmission control unit 14. In addition to the received signal, the optical receiver 11 outputs a detection signal indicating the result of detecting the signal input or signal disconnection of the packet signal to the transmission control unit 14.

  The transmission control unit 14 converts the input received signal into a baseband signal and outputs it to the external network 40. Further, the transmission control unit 14 detects a code indicating the end of the packet from the input received signal, generates an external reset signal based on the code, and outputs the external reset signal to the optical receiver 11.

  Here, the optical signal transmitted from each ONU 20 is a burst-like packet signal, and a plurality of packet signals from each ONU 20 are time-division multiplexed, and intermittently connected optical signals are input to the OLT 10. Is done.

  As shown in FIG. 2, the optical receiver 11 of the OLT 10 includes a light receiving element 130 that outputs a current signal corresponding to the received optical signal, and a preamplifier circuit that converts the current signal output from the light receiving element 130 into a voltage signal. (Displayed as TIA (Trance-impedance-Amplifier) 140) in the figure, and a main amplifier circuit (LIA (Limiting Amplifier) in the figure) that outputs a reception signal obtained by amplifying the voltage signal output from the preamplifier circuit 140 to substantially the same amplitude. And 150).

  The main amplifier circuit 150 differentially amplifies the packet signal input from the preamplifier circuit 140, and an output buffer that shapes the output of the main amplifier 111 into a differential signal of a predetermined level and outputs it as a received signal. 112.

  The main amplifier circuit 150 is preset to a DC voltage removing unit 113 that removes a DC voltage from a signal obtained by branching a part of the output of the main amplifier 111, and a signal from which the DC voltage is removed by the DC voltage removing unit 113. A bias voltage application unit 114 that generates a differential signal for detection by applying a bias voltage between the differentials. In addition, a reset signal generation unit 115 to which a part of the detection differential signal is input is provided, and an internal reset signal is output at the beginning and end of the packet signal based on the input signal.

  Further, the main amplifier circuit 150 includes a logical sum circuit 116 that outputs a logical sum of an internal reset signal output from the reset signal generation unit 115 and an external reset signal input from the outside via a reset input terminal, and a bias voltage application unit. And a flip-flop circuit 117 that outputs a packet detection signal (SD: Signal Detect) indicating the presence / absence of a packet signal based on the detection differential signal output from 114 and the reset signal output from the OR circuit 116.

  Among these configurations, the DC voltage removal unit 113, the bias voltage application unit 114, the reset signal generation unit 115, the OR circuit 116, and the flip-flop circuit 117 detect signal input and signal interruption of the packet signal. It functions as the signal detection circuit 110.

  The main amplifier 111 is a low-noise high-frequency differential amplifier. The DC voltage removing unit 113 includes a capacitor that allows only high frequency components to pass therethrough. The bias voltage application unit 114 includes a power supply and a plurality of resistors, and applies a predetermined bias voltage by dividing the power supply voltage by resistance.

  The flip-flop circuit 117 is an arbitrary reset input type flip-flop circuit, and includes, for example, a D flip-flop circuit or an SR flip-flop circuit. FIG. 2 shows the case of a D flip-flop circuit. The detection differential signal output from the bias voltage application unit 114 is input to the differential clock terminal, and the reset signal output from the OR circuit 116 is input to the reset terminal. The flip-flop circuit 117 holds the signal input at the rising timing of the detection differential signal, and releases the hold at the reset signal input timing to indicate whether or not the packet signal is detected. SD (Signal Detect) is output.

  As shown in FIG. 3, the reset signal generation unit 115 includes a differential single-phase conversion buffer 1151 that converts the detection differential signal output from the bias voltage application unit 114 into a single-phase signal, and a transistor for the emitter follower circuit 1150. 1152, current source 1153, capacitor 1154 holding the output voltage of the emitter follower circuit 1150, comparators 1155 and 1156 for comparing the output voltage of the emitter follower circuit 1150 with different threshold voltages, and outputs of the comparators 1155 and 1156 The exclusive OR circuit 1157 for performing the exclusive OR of the above.

  The operation related to signal detection of the optical receiver 11 configured as described above will be described with reference to the timing chart of FIG.

  FIG. 4 shows the response of each signal when an optical signal including a burst packet optical signal as shown in FIG. 4A is input to the light receiving element 130. FIG. 4A shows a packet optical signal of “10” alternating. Such a packet optical signal is photoelectrically converted by the light receiving element 130, and the photocurrent output from the light receiving element 130 is current-voltage converted by the preamplifier circuit 140.

  As shown in FIG. 4B, the signal output from the preamplifier circuit 140 and input to the main amplifier circuit 150 is output from the preamplifier circuit 140 in the no-signal section before the packet signal is input. It is a signal containing noise. In the packet signal input section, a differential signal composed of a normal phase input and a reverse phase input based on the pattern of the packet optical signal is input to the main amplifier circuit 150.

  In the main amplifier circuit 150, the input differential signal is differentially amplified by the main amplifier 111. A part of the signal amplified by the main amplifier 111 is branched as a differential signal for detection. The DC voltage is removed from the detection differential signal by the capacitor of the DC voltage removing unit 113, and a predetermined differential bias voltage is applied by the bias voltage applying unit 114 to be input to the flip-flop circuit 117.

  Here, as shown in FIG. 4C, the input signal of the flip-flop circuit 117 is input to avoid malfunction due to the output noise of the preamplifier circuit 140 and the noise generated / amplified by the main amplifier 111. It is necessary to make the signal to noise ratio (SNR) equal to or greater than a predetermined value. That is, the capacitance value of the capacitor of the DC voltage removal unit 113 and the resistance value of the bias voltage application unit 114 are set so as to generate a differential signal for detection that is not affected by noise of each circuit. The capacitance value of the capacitor of the DC voltage removal unit 113 and the resistance value of the bias voltage application unit 114 are such that the voltage range of the input signal of the flip-flop circuit 117 is within the voltage range in which each circuit in the subsequent stage can operate and the packet optical signal It is set to be equal to or lower than a certain difference voltage so that it can be identified as a differential signal during reception.

  The detection differential signal input to the reset signal generation unit 115 is converted into a single-phase signal by the differential single-phase conversion buffer 1151 in the input stage. Thereafter, the emitter follower circuit 1150 (transistor 1152 and current source 1153) accumulates electric charge in the capacitor 1154 during the input of the “1” signal, and the electric charge accumulated in the capacitor 1154 by the current source 1153 is discharged during the input of the “0” signal. Is done. Here, when the “1” signal is input, the emitter current of the transistor 1152 for the emitter follower circuit 1150 increases as compared to when the “0” signal is input. Therefore, as shown in FIG. The output voltage Vout of the follower circuit 1150 increases rapidly. On the other hand, during the input of the “0” signal, Vout decreases linearly with time at a speed of (I / C) from the current value I of the current source 1153 of the emitter follower circuit 1150 and the capacitance C of the capacitor 1154.

  The exclusive OR of the result of comparing the output voltage Vout of the emitter follower circuit 1150 with the threshold voltage V1 by the comparator 1155 and the result of comparing the output voltage Vout of the emitter follower circuit 1150 with the threshold voltage V2 by the comparator 1156 Output from the circuit 1157. Here, V2 <V1, and V2 is set to be higher than the noise level of the emitter follower, and V1 is set to be lower than the minimum value of the output signal of the emitter follower when the packet signal is input. As a result, the reset signal generator 115 outputs an internal reset signal that becomes Hi when V2 ≦ Vout ≦ V1, as shown in FIG. That is, as shown in FIG. 4E, the internal reset signal is output at the beginning of the packet and at the end of the packet.

  The internal reset signal has a length of the CID signal in order to prevent the reset signal from being erroneously output even when the same sign continuous signal is input like a CID (Consecutive Identity Digit) signal having a length of about 72 bits. It has the above time width (for example, about 5 ns to 30 ns). The current value, capacitor capacity, and threshold voltages V1 and V2 of the emitter follower circuit 1150 are determined so as to have this time width.

  An external reset signal as shown in FIG. 4F is input to the main amplifier circuit 150. The OR circuit 116 outputs a reset signal that is a logical sum of the internal reset signal output from the reset signal generation unit 115 and the external reset signal input from the outside.

  The differential signal for detection as shown in FIG. 4C is input to the flip-flop circuit 117 at the differential clock terminal. When the preamble signal of the next packet signal (for example, “10” alternating signal) is input to the differential clock terminal after the reset signal is input, the flip-flop circuit 117 holds (latches) the Data input connected to the constant voltage source. And High is output. Further, when a reset signal is input to the reset input (transition from Low to High), the flip-flop circuit 117 releases the held Data input voltage value (sets to Low). As a result, a packet detection signal (SD output signal: FIG. 4 (g)) that becomes High near the beginning of the packet signal and becomes Low near the end of the packet signal is output. Can respond at high speed.

  Here, since the OR circuit 116 outputs a logical sum of the internal reset signal and the external reset, even if the guard time between packets is short and the internal reset signal is not generated, the vicinity of the head of the packet during the guard time is generated. A reset signal is input from the outside. Even when the internal reset signal has a reset width at which the flip-flop circuit 117 does not operate, the reset signal based on the external reset signal is input to the flip-flop circuit 117. As described above, when detecting a signal interruption based on the external reset signal, the current value of the emitter follower circuit 1150, the capacitance value of the capacitor, the threshold value so that the internal reset signal is generated after an appropriate time after the end of the packet. The voltages V1 and V2 may be determined. Thus, the flip-flop circuit 117 can reliably output a packet detection signal indicating a signal interruption after the end of the packet, and can also reliably output a packet detection signal indicating a signal input of the next packet.

  As described above, according to the present embodiment, a DC voltage is removed from a received differential signal, a predetermined differential bias voltage is applied to generate a detection differential signal, and detection is performed. Based on the differential signal for reset, the reset signal generator 115 generates an internal reset signal, inputs the differential signal for detection to the input terminal of the flip-flop circuit 117, inputs the internal reset signal to the reset terminal, and The detection signal is output. The reset signal generation unit 115 holds the voltage when the detection differential signal is converted into a single-phase signal, and excludes the result of comparing the held voltage value with two different predetermined threshold voltages. An internal reset signal that is a logical OR is generated. As a result, it is possible to detect a signal input at a high speed at the beginning of the packet signal and to detect a signal break at a high speed at the end of the packet signal.

Embodiment 2. FIG.
Embodiments of the present invention will be described in detail with reference to the drawings.

  The configurations of the optical communication system 1 and the optical receiver 11 according to the present embodiment are the same as those of the first embodiment. The reset signal generator 125 provided in place of the reset signal generator 115 in the main amplifier circuit 150 of the first embodiment receives a DC voltage from the differential signal input to the main amplifier circuit 150, as in the first embodiment. Although it has a function of generating an internal reset signal based on a detection differential signal obtained by removing and applying a bias voltage, the internal configuration is different from that of the first embodiment. The reset signal generation unit 125 according to the present embodiment will be described with reference to FIG.

  As shown in FIG. 5, the reset signal generation unit 125 removes the DC voltage from the DC voltage removal unit 113 and converts the detection differential signal to which the bias voltage is applied by the bias voltage application unit 114 into a single-phase signal. The output of the dynamic single-phase conversion buffer 1151 and the output of the differential single-phase conversion buffer 1151 are branched into two, and the transistor 1252 for the first emitter-follower circuit 1250, the current source 1253, and the first emitter are inputted. A capacitor 1254 that holds the output voltage of the follower circuit 1250, a transistor 1262 for the second emitter follower circuit 1260 that inputs the other of the branched signal, a current source 1263, and an output voltage for the second emitter follower circuit 1260 And the emitter follower circuits 1250 and 1260 with the same threshold voltage. Comparators 1155 and 1156 for comparing the output voltage, and an exclusive OR circuit 1157 for performing an exclusive logical sum of the outputs of the comparators 1155 and 1156. Here, the current values of the current sources 1253 and 1263 of the two emitter follower circuits 1250 and 1260 are different from each other, or the capacitance values of the capacitors 1254 and 1264 are different from each other.

  The operation related to signal detection of the optical receiver 11 configured as described above will be described with reference to the timing chart of FIG.

  FIG. 6 shows the response of each signal when an optical signal including a burst packet optical signal as shown in FIG. 6A is input to the light receiving element 130. FIG. 6A shows a packet optical signal of “10” alternating.

  As shown in FIG. 6B, the signal output from the preamplifier circuit 140 and input to the main amplifier circuit 150 is an input signal of the main amplifier circuit 150 in the non-signal period before the packet signal is input. The signal including the output noise of the preamplifier circuit 140 is input. Further, a differential signal composed of a normal phase input and a reverse phase input based on the pattern of the packet optical signal is input to the packet signal input section.

  In the main amplifier circuit 150, the input differential signal is differentially amplified by the main amplifier 111. From the signal amplified by the main amplifier 111, the DC voltage is removed by the capacitor of the DC voltage removing unit 113, and a predetermined differential bias voltage is applied by the bias voltage applying unit 114, so that a differential signal for detection is detected. Is input to the reset signal generator 115 and the flip-flop circuit 117 (FIG. 6C).

  The detection differential signal input to the reset signal generation unit 115 is converted into a single-phase signal by the differential single-phase conversion buffer 1151 in the input unit. The single-phase signal is divided into two branches, one of which is charged by the first emitter follower circuit 1250 (transistor 1252 and current source 1253) to accumulate electric charge in the capacitor 1254 during the “1” signal input, and the current source 1253 during the “0” signal input. As a result, the charge accumulated in the capacitor 1254 is discharged. Here, when the “1” signal is input, the emitter current of the transistor 1252 for the first emitter follower circuit 1250 increases as compared with the time when the “0” signal is input. Therefore, as shown in FIG. Sometimes the output voltage Vout1 of the first emitter follower circuit 1250 increases rapidly. On the other hand, during the input of the “0” signal, Vout1 decreases linearly with respect to time at a speed of (I / C) from the current value I of the current source 1253 of the first emitter follower circuit 1250 and the capacitance C of the capacitor 1254.

  The other one of the single-phase signals is accumulated in the capacitor 1264 during the “1” signal input by the second emitter follower circuit 1260 (transistor 1262 and current source 1263), and the capacitor 1264 by the current source 1263 during the “0” signal input. The electric charge accumulated in is discharged (FIG. 6E). Here, since the drive current of the current source or the capacitance value of the capacitor is different from that of the first emitter follower circuit 1250, the changing speed of the output voltage Vout2 is different.

  The exclusive OR of the results of comparing the output voltages Vout1 and Vout2 of the emitter follower circuits 1250 and 1260 with the threshold voltage V1 by the comparators 1155 and 1156 is output from the exclusive OR circuit 1157. V1 is set to be higher than the noise level of the emitter follower and lower than the minimum value of the output signal of the emitter follower at the time of packet signal input. As a result, the reset signal generator 125 outputs an internal reset signal at the beginning of the packet and at the end of the packet, as shown in FIG.

  The internal reset signal changes the output voltages Vout1 and Vout2 of the emitter follower circuits 1250 and 1260 at different changing speeds, so that the internal reset signal has an appropriate time width (for example, about 5 ns to 30 ns) at the end of the packet and the end of the packet. A reset signal can be generated. In addition, in order to prevent a reset signal from being erroneously output even when the same sign continuous signal is input, such as a CID (Consecutive Identity Digit) signal having a length of about 72 bits, a time longer than the length of the CID signal. The current value, capacitor capacity, and threshold voltage V1 of each emitter follower circuit 1250, 1260 are determined so as to have a width.

  The main amplifier circuit 150 receives an external reset signal similar to that shown in FIG. The OR circuit 116 outputs a reset signal that is a logical sum of the internal reset signal output from the internal reset signal generation unit 115 and the external reset signal input from the outside.

  A differential signal for detection as shown in FIG. 6C is input to the flip-flop circuit 117 at the differential clock terminal. When the preamble signal of the next packet signal (for example, “10” alternating signal) is input to the differential clock terminal after the reset signal is input, the flip-flop circuit 117 holds (latches) the Data input connected to the constant voltage source. And High is output. Further, when the reset signal is input to the reset input (transition from Low to High), the flip-flop circuit 117 releases the held Data input voltage value (sets to Low). As a result, a packet detection signal (SD output signal: FIG. 6 (g)) that becomes High near the beginning of the packet signal and becomes Low near the end of the packet signal is output. Can respond at high speed.

  In the second embodiment, the second emitter follower circuit 1260 is increased by one as compared with the first embodiment, so that the circuit scale increases. However, as a parameter that determines the operation speed of the reset signal generation circuit, Since the drive current of the emitter follower circuit 1260 and the capacitance of the capacitor increase, there is an advantage that the degree of freedom in parameter determination increases.

  As described above, according to the present embodiment, the reset signal generation unit 125 splits the single-phase signal converted from the detection differential signal into two branches, and one of them is provided at the output of the first emitter follower circuit 1250. The voltage is held by the capacitor 1254, the other is held by the capacitor 1264 provided at the output of the second emitter follower circuit 1260, and the exclusive OR of the results of comparing the two held voltage values with a predetermined threshold voltage An internal reset signal is generated. As a result, it is possible to detect a signal input at a high speed at the beginning of the packet signal, to detect a signal break at a high speed at the end of the packet signal, and to optimize the time width of the reset signal.

Embodiment 3 FIG.
Embodiments of the present invention will be described in detail with reference to the drawings.

  The configurations of the optical communication system 1 and the optical receiver 11 according to the present embodiment are the same as those of the first embodiment. The reset signal generation unit 135 provided in place of the reset signal generation unit 115 in the main amplifier circuit 150 of the first embodiment is similar to the first and second embodiments in that the differential signal input to the main amplifier circuit 150 is DC-converted. Although it has a function of generating an internal reset signal based on a differential signal for detection obtained by removing a voltage and applying a bias voltage, the internal configuration is different from those of the first and second embodiments. The reset signal generation unit 135 according to the present embodiment will be described with reference to FIG.

  As shown in FIG. 7, the reset signal generation unit 135 removes the DC voltage by the DC voltage removal unit 113 and converts the detection differential signal to which the bias voltage is applied by the bias voltage application unit 114 into a single-phase signal. The output of the dynamic single-phase conversion buffer 1151 and the output of the differential single-phase conversion buffer 1151 are branched into two, and the transistor 1352 for the first emitter follower circuit 1350 that inputs one of the branched signals, the current source 1353, and the first emitter A capacitor 1354 that holds the output voltage of the follower circuit 1350, a transistor 1362 for the second emitter follower circuit 1360 that inputs the other of the branched signal, a current source 1363, and an output voltage of the second emitter follower circuit 1360 are held. Capacitor 1364 and each emitter follower circuit 1350, 1360 with different threshold voltages Comparators 1155 and 1156 for comparing the output voltage, and an exclusive OR circuit 1157 for performing an exclusive logical sum of the outputs of the comparators 1155 and 1156. Here, the current values of the current sources 1353 and 1363 of the two emitter follower circuits 1350 and 1360 are different from each other, and the capacitance values of the capacitors 1354 and 1364 are also different from each other.

  The operation related to signal detection of the optical receiver 11 configured as described above is the same as that of the second embodiment, and the drive currents of the two emitter follower circuits 1350 and 1360 and the capacitances of the capacitors 1354 and 1364 are set to different values. In addition, by setting the threshold voltages of the two comparators 1155 and 1156 to different values, the reset signal generation circuit 135 can select the timing and time width of the internal reset signal generation more flexibly.

  As described above, according to the present embodiment, the reset signal generation unit 135 branches the single-phase signal converted from the detection differential signal into two, and one of them is provided at the output of the first emitter follower circuit 1350. The voltage is held by the capacitor 1354, the other is held by the capacitor 1364 provided at the output of the second emitter follower circuit 1360, and the exclusive OR of the results of comparing the two held voltage values with a predetermined threshold voltage An internal reset signal is generated. As a result, it is possible to detect a signal input at a high speed at the beginning of the packet signal and to detect a signal break at a high speed at the end of the packet signal, and to optimize the time width and timing of the reset signal.

  As described above, the present invention removes the DC voltage from the input differential signal, applies a predetermined differential bias voltage to generate a detection differential signal, and generates an internal signal based on the detection differential signal. A packet detection signal that generates a reset signal, holds the state indicating the input of the packet signal based on the differential signal for detection, and releases the holding based on the internal reset signal to indicate the signal input and signal disconnection of the packet signal It was decided to generate. The internal reset signal is generated based on a result of converting the detection differential signal into a single-phase signal, holding the voltage of the single-phase signal, and comparing the held voltage with a predetermined threshold voltage. It was. As a result, it is possible to detect a signal input at a high speed at the beginning of the packet signal and to detect a signal break at a high speed at the end of the packet signal.

  In addition, this invention is not limited to the said embodiment, Of course, the various change in the range which does not deviate from the summary of this invention is possible.

  For example, in the above embodiment, the main amplifier 111 is provided in the input section of the main amplifier circuit 150. However, the main amplifier 111 may be in front of the output buffer 112. In this case, the input of the main amplifier circuit 150 may be provided. The differential signal is branched into two at one part, and one is connected to the main amplifier 111 and the other is connected to the DC voltage removing part 113.

  The output buffer 112 of the main amplifier circuit 150 is configured to amplify the signal of the preamplifier circuit 140 and output it as it is. However, in order not to transmit noise to the next stage circuit, the flip-flop circuit 117 is used. The buffer may be a buffer that performs a squelch operation using the packet detection signal (SD signal) generated in step S2. In this case, the output buffer 112 has a select function that operates according to the SD signal.

  In the above embodiment, the signal obtained by converting the photocurrent output from the light receiving element 130 into a voltage signal is input to the preamplifier circuit 140 and the main amplifier circuit 150. However, the present invention is not limited to this. The present invention can be applied to a circuit that detects a packet signal from an arbitrary differential signal including a bursty packet signal.

  1 optical communication system, 10 OLT, 20 ONU, 30 optical star coupler, 32 optical fiber, 40 external network, 11 optical receiver, 110 signal detection circuit, 130 light receiving element, 140 preamplifier circuit, 150 main amplifier circuit, 111 Main amplifier, 112 output buffer, 113 DC voltage removing unit, 114 bias voltage applying unit, 115, 125, 135 reset signal generating unit, 116 OR circuit, 117 flip-flop circuit, 1150 emitter follower circuit, 1151 differential single phase conversion Buffer, 1152, 1252, 1262, 1352, 1362 Transistor, 1153, 1253, 1263, 1353, 1363 Current source, 1154, 1254, 1264, 1354, 1364 Capacitor, 1155, 1156 Comparator, 1 157 Exclusive OR circuit, 1250, 1350 1st emitter follower circuit, 1260, 1360 2nd emitter follower circuit

Claims (10)

A DC voltage removing unit for removing a DC voltage from an input differential signal including a bursty packet signal;
A bias voltage applying unit that generates a differential signal for detection by applying a predetermined differential bias voltage to the signal from which the DC voltage has been removed by the DC voltage removing unit;
A reset signal generating unit that generates an internal reset signal after the beginning and end of the packet signal based on the differential signal for detection;
A packet detection signal indicating a signal input of the packet signal and a signal disconnection is generated by holding the state indicating the input of the packet signal based on the differential signal for detection and releasing the holding based on the internal reset signal. A packet detection signal generator that
The reset signal generation unit holds a differential single-phase conversion circuit that converts the differential signal for detection into a single-phase signal, a voltage holding circuit that holds the voltage of the single-phase signal, and the voltage holding circuit holds A voltage comparison circuit that generates the internal reset signal based on a comparison result between a voltage and a predetermined threshold voltage,
A signal detection circuit. The packet detection signal generation unit releases the holding based on a logical sum of an external reset signal input from the outside and the internal reset signal.
The signal detection circuit according to claim 1. The packet detection signal generation unit is a reset input type D flip-flop circuit that inputs the detection differential signal to a clock input terminal and inputs a logical sum of the internal reset signal and the external reset signal to a reset input terminal. ,
The signal detection circuit according to claim 2. The packet detection signal generation unit is an SR flip-flop circuit that inputs the detection differential signal to a set input terminal and inputs a logical sum of the internal reset signal and the external reset signal to a reset input terminal.
The signal detection circuit according to claim 2. The voltage holding circuit includes an emitter follower circuit and a capacitor for holding a voltage connected in parallel with a current source of the emitter follower circuit.
5. The signal detection circuit according to claim 1, wherein The voltage comparison circuit includes two comparators having different threshold voltages, and the internal reset signal is an output of the two comparators when a voltage held by the voltage holding circuit is input to the two comparators. Is the exclusive OR of
The signal detection circuit according to claim 1, wherein the signal detection circuit includes: The voltage holding circuit includes two emitter follower circuits and two capacitors for holding a voltage connected in parallel with a current source of each emitter follower circuit,
The drive currents of the current sources of the two emitter follower circuits or the capacitance values of the capacitors are different from each other,
The voltage comparison circuit includes two comparators having a predetermined threshold voltage, and the internal reset signal is the two comparators when the voltages held by the two capacitors are input to the two comparators. Is the exclusive OR of the outputs of
5. The signal detection circuit according to claim 1, wherein A light receiving element that converts a burst optical packet signal into a current signal;
A preamplifier circuit for converting a current signal output from the light receiving element into a voltage signal;
A main amplifier circuit that amplifies the voltage signal output by the preamplifier circuit,
The main amplifier circuit includes the signal detection circuit according to any one of claims 1 to 7.
An optical receiver.   A master station apparatus comprising the optical receiver according to claim 8. A signal detection method for detecting signal input and signal interruption of a bursty packet signal,
A DC voltage removing step of removing a DC voltage from the input differential signal including the packet signal;
A bias application step of generating a differential signal for detection by applying a predetermined differential bias voltage to the signal from which the DC voltage has been removed in the DC voltage removal step;
A reset signal generating step for generating an internal reset signal after the beginning and end of the packet signal based on the detection differential signal;
A packet detection signal indicating a signal input and signal disconnection of the packet signal by holding a state indicating the input of the packet signal based on the differential signal for detection and releasing the holding based on the internal reset signal. A packet detection signal generation step to generate,
The reset signal generation step holds the differential single-phase conversion step for converting the detection differential signal into a single-phase signal, the voltage holding step for holding the voltage of the single-phase signal, and the voltage holding step. A voltage comparison step of generating the internal reset signal based on a comparison result between a voltage and a predetermined threshold voltage,
And a signal detection method.

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